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1 /*
2 * MIPS-specific CSRs.
3 *
4 * Copyright (c) 2025 MIPS
5 *
6 * SPDX-License-Identifier: GPL-2.0-or-later
7 *
8 */
9
10 #include "qemu/osdep.h"
11 #include "cpu.h"
12 #include "cpu_vendorid.h"
13 #include "target/riscv/tcg/csr.h"
14
15 /* Static MIPS CSR state storage */
16 static struct {
17 uint64_t tvec;
18 uint64_t config[12];
19 uint64_t pmacfg[16];
20 } mips_csr_state;
21
22 /* MIPS CSR */
23 #define CSR_MIPSTVEC 0x7c0
24 #define CSR_MIPSCONFIG0 0x7d0
25 #define CSR_MIPSCONFIG1 0x7d1
26 #define CSR_MIPSCONFIG2 0x7d2
27 #define CSR_MIPSCONFIG3 0x7d3
28 #define CSR_MIPSCONFIG4 0x7d4
29 #define CSR_MIPSCONFIG5 0x7d5
30 #define CSR_MIPSCONFIG6 0x7d6
31 #define CSR_MIPSCONFIG7 0x7d7
32 #define CSR_MIPSCONFIG8 0x7d8
33 #define CSR_MIPSCONFIG9 0x7d9
34 #define CSR_MIPSCONFIG10 0x7da
35 #define CSR_MIPSCONFIG11 0x7db
36 #define CSR_MIPSPMACFG0 0x7e0
37 #define CSR_MIPSPMACFG1 0x7e1
38 #define CSR_MIPSPMACFG2 0x7e2
39 #define CSR_MIPSPMACFG3 0x7e3
40 #define CSR_MIPSPMACFG4 0x7e4
41 #define CSR_MIPSPMACFG5 0x7e5
42 #define CSR_MIPSPMACFG6 0x7e6
43 #define CSR_MIPSPMACFG7 0x7e7
44 #define CSR_MIPSPMACFG8 0x7e8
45 #define CSR_MIPSPMACFG9 0x7e9
46 #define CSR_MIPSPMACFG10 0x7ea
47 #define CSR_MIPSPMACFG11 0x7eb
48 #define CSR_MIPSPMACFG12 0x7ec
49 #define CSR_MIPSPMACFG13 0x7ed
50 #define CSR_MIPSPMACFG14 0x7ee
51 #define CSR_MIPSPMACFG15 0x7ef
52
53 static RISCVException any(CPURISCVState *env, int csrno)
54 {
55 return RISCV_EXCP_NONE;
56 }
57
58 static RISCVException read_mipstvec(CPURISCVState *env, int csrno,
59 target_ulong *val)
60 {
61 *val = mips_csr_state.tvec;
62 return RISCV_EXCP_NONE;
63 }
64
65 static RISCVException write_mipstvec(CPURISCVState *env, int csrno,
66 target_ulong val, uintptr_t ra)
67 {
68 mips_csr_state.tvec = val;
69 return RISCV_EXCP_NONE;
70 }
71
72 static RISCVException read_mipsconfig(CPURISCVState *env, int csrno,
73 target_ulong *val)
74 {
75 *val = mips_csr_state.config[csrno - CSR_MIPSCONFIG0];
76 return RISCV_EXCP_NONE;
77 }
78
79 static RISCVException write_mipsconfig(CPURISCVState *env, int csrno,
80 target_ulong val, uintptr_t ra)
81 {
82 mips_csr_state.config[csrno - CSR_MIPSCONFIG0] = val;
83 return RISCV_EXCP_NONE;
84 }
85
86 static RISCVException read_mipspmacfg(CPURISCVState *env, int csrno,
87 target_ulong *val)
88 {
89 *val = mips_csr_state.pmacfg[csrno - CSR_MIPSPMACFG0];
90 return RISCV_EXCP_NONE;
91 }
92
93 static RISCVException write_mipspmacfg(CPURISCVState *env, int csrno,
94 target_ulong val, uintptr_t ra)
95 {
96 mips_csr_state.pmacfg[csrno - CSR_MIPSPMACFG0] = val;
97 return RISCV_EXCP_NONE;
98 }
99
100 const RISCVCSR mips_csr_list[] = {
101 {
102 .csrno = CSR_MIPSTVEC,
103 .csr_ops = { "mipstvec", any, read_mipstvec, write_mipstvec }
104 },
105 {
106 .csrno = CSR_MIPSCONFIG0,
107 .csr_ops = { "mipsconfig0", any, read_mipsconfig, write_mipsconfig }
108 },
109 {
110 .csrno = CSR_MIPSCONFIG1,
111 .csr_ops = { "mipsconfig1", any, read_mipsconfig, write_mipsconfig }
112 },
113 {
114 .csrno = CSR_MIPSCONFIG2,
115 .csr_ops = { "mipsconfig2", any, read_mipsconfig, write_mipsconfig }
116 },
117 {
118 .csrno = CSR_MIPSCONFIG3,
119 .csr_ops = { "mipsconfig3", any, read_mipsconfig, write_mipsconfig }
120 },
121 {
122 .csrno = CSR_MIPSCONFIG4,
123 .csr_ops = { "mipsconfig4", any, read_mipsconfig, write_mipsconfig }
124 },
125 {
126 .csrno = CSR_MIPSCONFIG5,
127 .csr_ops = { "mipsconfig5", any, read_mipsconfig, write_mipsconfig }
128 },
129 {
130 .csrno = CSR_MIPSCONFIG6,
131 .csr_ops = { "mipsconfig6", any, read_mipsconfig, write_mipsconfig }
132 },
133 {
134 .csrno = CSR_MIPSCONFIG7,
135 .csr_ops = { "mipsconfig7", any, read_mipsconfig, write_mipsconfig }
136 },
137 {
138 .csrno = CSR_MIPSCONFIG8,
139 .csr_ops = { "mipsconfig8", any, read_mipsconfig, write_mipsconfig }
140 },
141 {
142 .csrno = CSR_MIPSCONFIG9,
143 .csr_ops = { "mipsconfig9", any, read_mipsconfig, write_mipsconfig }
144 },
145 {
146 .csrno = CSR_MIPSCONFIG10,
147 .csr_ops = { "mipsconfig10", any, read_mipsconfig, write_mipsconfig }
148 },
149 {
150 .csrno = CSR_MIPSCONFIG11,
151 .csr_ops = { "mipsconfig11", any, read_mipsconfig, write_mipsconfig }
152 },
153 {
154 .csrno = CSR_MIPSPMACFG0,
155 .csr_ops = { "mipspmacfg0", any, read_mipspmacfg, write_mipspmacfg }
156 },
157 {
158 .csrno = CSR_MIPSPMACFG1,
159 .csr_ops = { "mipspmacfg1", any, read_mipspmacfg, write_mipspmacfg }
160 },
161 {
162 .csrno = CSR_MIPSPMACFG2,
163 .csr_ops = { "mipspmacfg2", any, read_mipspmacfg, write_mipspmacfg }
164 },
165 {
166 .csrno = CSR_MIPSPMACFG3,
167 .csr_ops = { "mipspmacfg3", any, read_mipspmacfg, write_mipspmacfg }
168 },
169 {
170 .csrno = CSR_MIPSPMACFG4,
171 .csr_ops = { "mipspmacfg4", any, read_mipspmacfg, write_mipspmacfg }
172 },
173 {
174 .csrno = CSR_MIPSPMACFG5,
175 .csr_ops = { "mipspmacfg5", any, read_mipspmacfg, write_mipspmacfg }
176 },
177 {
178 .csrno = CSR_MIPSPMACFG6,
179 .csr_ops = { "mipspmacfg6", any, read_mipspmacfg, write_mipspmacfg }
180 },
181 {
182 .csrno = CSR_MIPSPMACFG7,
183 .csr_ops = { "mipspmacfg7", any, read_mipspmacfg, write_mipspmacfg }
184 },
185 {
186 .csrno = CSR_MIPSPMACFG8,
187 .csr_ops = { "mipspmacfg8", any, read_mipspmacfg, write_mipspmacfg }
188 },
189 {
190 .csrno = CSR_MIPSPMACFG9,
191 .csr_ops = { "mipspmacfg9", any, read_mipspmacfg, write_mipspmacfg }
192 },
193 {
194 .csrno = CSR_MIPSPMACFG10,
195 .csr_ops = { "mipspmacfg10", any, read_mipspmacfg, write_mipspmacfg }
196 },
197 {
198 .csrno = CSR_MIPSPMACFG11,
199 .csr_ops = { "mipspmacfg11", any, read_mipspmacfg, write_mipspmacfg }
200 },
201 {
202 .csrno = CSR_MIPSPMACFG12,
203 .csr_ops = { "mipspmacfg12", any, read_mipspmacfg, write_mipspmacfg }
204 },
205 {
206 .csrno = CSR_MIPSPMACFG13,
207 .csr_ops = { "mipspmacfg13", any, read_mipspmacfg, write_mipspmacfg }
208 },
209 {
210 .csrno = CSR_MIPSPMACFG14,
211 .csr_ops = { "mipspmacfg14", any, read_mipspmacfg, write_mipspmacfg }
212 },
213 {
214 .csrno = CSR_MIPSPMACFG15,
215 .csr_ops = { "mipspmacfg15", any, read_mipspmacfg, write_mipspmacfg }
216 },
217 { },
218 };