| 1 | /* |
| 2 | * RISC-V Emulation Helpers for QEMU. |
| 3 | * |
| 4 | * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu |
| 5 | * Copyright (c) 2017-2018 SiFive, Inc. |
| 6 | * Copyright (c) 2022 VRULL GmbH |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify it |
| 9 | * under the terms and conditions of the GNU General Public License, |
| 10 | * version 2 or later, as published by the Free Software Foundation. |
| 11 | * |
| 12 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 15 | * more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License along with |
| 18 | * this program. If not, see <http://www.gnu.org/licenses/>. |
| 19 | */ |
| 20 | |
| 21 | #include "qemu/osdep.h" |
| 22 | #include "cpu.h" |
| 23 | #include "target/riscv/tcg/csr.h" |
| 24 | #ifndef CONFIG_USER_ONLY |
| 25 | #include "pmu.h" |
| 26 | #endif |
| 27 | #include "internals.h" |
| 28 | #include "exec/cputlb.h" |
| 29 | #include "accel/tcg/cpu-ldst.h" |
| 30 | #include "accel/tcg/cpu-loop.h" |
| 31 | #include "accel/tcg/probe.h" |
| 32 | #include "exec/helper-proto.h" |
| 33 | #include "exec/tlb-flags.h" |
| 34 | #include "trace.h" |
| 35 | |
| 36 | /* Exceptions processing helpers */ |
| 37 | G_NORETURN void riscv_raise_exception(CPURISCVState *env, |
| 38 | RISCVException exception, |
| 39 | uintptr_t pc) |
| 40 | { |
| 41 | CPUState *cs = env_cpu(env); |
| 42 | |
| 43 | trace_riscv_exception(exception, |
| 44 | riscv_cpu_get_trap_name(exception, false), |
| 45 | env->pc); |
| 46 | |
| 47 | cs->exception_index = exception; |
| 48 | cpu_loop_exit_restore(cs, pc); |
| 49 | } |
| 50 | |
| 51 | void helper_raise_exception(CPURISCVState *env, uint32_t exception) |
| 52 | { |
| 53 | #ifndef CONFIG_USER_ONLY |
| 54 | riscv_pmu_decr_instret(env); |
| 55 | #endif |
| 56 | riscv_raise_exception(env, exception, 0); |
| 57 | } |
| 58 | |
| 59 | target_ulong helper_csrr(CPURISCVState *env, int csr) |
| 60 | { |
| 61 | /* |
| 62 | * The seed CSR must be accessed with a read-write instruction. A |
| 63 | * read-only instruction such as CSRRS/CSRRC with rs1=x0 or CSRRSI/ |
| 64 | * CSRRCI with uimm=0 will raise an illegal instruction exception. |
| 65 | */ |
| 66 | if (csr == CSR_SEED) { |
| 67 | riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); |
| 68 | } |
| 69 | |
| 70 | target_ulong val = 0; |
| 71 | RISCVException ret = riscv_csrr(env, csr, &val); |
| 72 | |
| 73 | if (ret != RISCV_EXCP_NONE) { |
| 74 | riscv_raise_exception(env, ret, GETPC()); |
| 75 | } |
| 76 | return val; |
| 77 | } |
| 78 | |
| 79 | void helper_csrw(CPURISCVState *env, int csr, target_ulong src) |
| 80 | { |
| 81 | target_ulong mask = env->xl == MXL_RV32 ? UINT32_MAX : (target_ulong)-1; |
| 82 | RISCVException ret = riscv_csrrw(env, csr, NULL, src, mask, GETPC()); |
| 83 | |
| 84 | if (ret != RISCV_EXCP_NONE) { |
| 85 | riscv_raise_exception(env, ret, GETPC()); |
| 86 | } |
| 87 | } |
| 88 | |
| 89 | target_ulong helper_csrrw(CPURISCVState *env, int csr, |
| 90 | target_ulong src, target_ulong write_mask) |
| 91 | { |
| 92 | target_ulong val = 0; |
| 93 | RISCVException ret = riscv_csrrw(env, csr, &val, src, write_mask, GETPC()); |
| 94 | |
| 95 | if (ret != RISCV_EXCP_NONE) { |
| 96 | riscv_raise_exception(env, ret, GETPC()); |
| 97 | } |
| 98 | return val; |
| 99 | } |
| 100 | |
| 101 | target_ulong helper_csrr_i128(CPURISCVState *env, int csr) |
| 102 | { |
| 103 | Int128 rv = int128_zero(); |
| 104 | RISCVException ret = riscv_csrr_i128(env, csr, &rv); |
| 105 | |
| 106 | if (ret != RISCV_EXCP_NONE) { |
| 107 | riscv_raise_exception(env, ret, GETPC()); |
| 108 | } |
| 109 | |
| 110 | env->retxh = int128_gethi(rv); |
| 111 | return int128_getlo(rv); |
| 112 | } |
| 113 | |
| 114 | void helper_csrw_i128(CPURISCVState *env, int csr, |
| 115 | target_ulong srcl, target_ulong srch) |
| 116 | { |
| 117 | RISCVException ret = riscv_csrrw_i128(env, csr, NULL, |
| 118 | int128_make128(srcl, srch), |
| 119 | UINT128_MAX, GETPC()); |
| 120 | |
| 121 | if (ret != RISCV_EXCP_NONE) { |
| 122 | riscv_raise_exception(env, ret, GETPC()); |
| 123 | } |
| 124 | } |
| 125 | |
| 126 | target_ulong helper_csrrw_i128(CPURISCVState *env, int csr, |
| 127 | target_ulong srcl, target_ulong srch, |
| 128 | target_ulong maskl, target_ulong maskh) |
| 129 | { |
| 130 | Int128 rv = int128_zero(); |
| 131 | RISCVException ret = riscv_csrrw_i128(env, csr, &rv, |
| 132 | int128_make128(srcl, srch), |
| 133 | int128_make128(maskl, maskh), |
| 134 | GETPC()); |
| 135 | |
| 136 | if (ret != RISCV_EXCP_NONE) { |
| 137 | riscv_raise_exception(env, ret, GETPC()); |
| 138 | } |
| 139 | |
| 140 | env->retxh = int128_gethi(rv); |
| 141 | return int128_getlo(rv); |
| 142 | } |
| 143 | |
| 144 | |
| 145 | /* |
| 146 | * check_zicbo_envcfg |
| 147 | * |
| 148 | * Raise virtual exceptions and illegal instruction exceptions for |
| 149 | * Zicbo[mz] instructions based on the settings of [mhs]envcfg as |
| 150 | * specified in section 2.5.1 of the CMO specification. |
| 151 | */ |
| 152 | static void check_zicbo_envcfg(CPURISCVState *env, target_ulong envbits, |
| 153 | uintptr_t ra) |
| 154 | { |
| 155 | #if defined(CONFIG_USER_ONLY) |
| 156 | /* |
| 157 | * linux-user: the machine-level envcfg fields are not part of the |
| 158 | * user-mode environment; only the user-mode view of the enabling |
| 159 | * bits (senvcfg, as initialized for the guest) applies. |
| 160 | */ |
| 161 | if (!get_field(env->senvcfg, envbits)) { |
| 162 | riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, ra); |
| 163 | } |
| 164 | #else |
| 165 | if ((env->priv < PRV_M) && !get_field(env->menvcfg, envbits)) { |
| 166 | riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, ra); |
| 167 | } |
| 168 | |
| 169 | if (env->virt_enabled && |
| 170 | (((env->priv <= PRV_S) && !get_field(env->henvcfg, envbits)) || |
| 171 | ((env->priv < PRV_S) && !get_field(env->senvcfg, envbits)))) { |
| 172 | riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, ra); |
| 173 | } |
| 174 | |
| 175 | if ((env->priv < PRV_S) && !get_field(env->senvcfg, envbits)) { |
| 176 | riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, ra); |
| 177 | } |
| 178 | #endif |
| 179 | } |
| 180 | |
| 181 | void helper_cbo_zero(CPURISCVState *env, target_ulong address) |
| 182 | { |
| 183 | RISCVCPU *cpu = env_archcpu(env); |
| 184 | uint16_t cbozlen = cpu->cfg.cboz_blocksize; |
| 185 | int mmu_idx = riscv_env_mmu_index(env, false); |
| 186 | uintptr_t ra = GETPC(); |
| 187 | void *mem; |
| 188 | |
| 189 | check_zicbo_envcfg(env, MENVCFG_CBZE, ra); |
| 190 | |
| 191 | /* Mask off low-bits to align-down to the cache-block. */ |
| 192 | address &= ~(cbozlen - 1); |
| 193 | |
| 194 | /* |
| 195 | * cbo.zero requires MMU_DATA_STORE access. Do a probe_write() |
| 196 | * to raise any exceptions, including PMP. |
| 197 | */ |
| 198 | mem = probe_write(env, address, cbozlen, mmu_idx, ra); |
| 199 | |
| 200 | if (likely(mem)) { |
| 201 | memset(mem, 0, cbozlen); |
| 202 | } else { |
| 203 | /* |
| 204 | * This means that we're dealing with an I/O page. Section 4.2 |
| 205 | * of cmobase v1.0.1 says: |
| 206 | * |
| 207 | * "Cache-block zero instructions store zeros independently |
| 208 | * of whether data from the underlying memory locations are |
| 209 | * cacheable." |
| 210 | * |
| 211 | * Write zeros in address + cbozlen regardless of not being |
| 212 | * a RAM page. |
| 213 | */ |
| 214 | for (int i = 0; i < cbozlen; i++) { |
| 215 | cpu_stb_mmuidx_ra(env, address + i, 0, mmu_idx, ra); |
| 216 | } |
| 217 | } |
| 218 | } |
| 219 | |
| 220 | /* |
| 221 | * check_zicbom_access |
| 222 | * |
| 223 | * Check access permissions (LOAD, STORE or FETCH as specified in |
| 224 | * section 2.5.2 of the CMO specification) for Zicbom, raising |
| 225 | * either store page-fault (non-virtualized) or store guest-page |
| 226 | * fault (virtualized). |
| 227 | */ |
| 228 | static void check_zicbom_access(CPURISCVState *env, |
| 229 | target_ulong address, |
| 230 | uintptr_t ra) |
| 231 | { |
| 232 | RISCVCPU *cpu = env_archcpu(env); |
| 233 | int mmu_idx = riscv_env_mmu_index(env, false); |
| 234 | uint16_t cbomlen = cpu->cfg.cbom_blocksize; |
| 235 | void *phost; |
| 236 | int ret; |
| 237 | |
| 238 | /* Mask off low-bits to align-down to the cache-block. */ |
| 239 | address &= ~(cbomlen - 1); |
| 240 | |
| 241 | /* |
| 242 | * Section 2.5.2 of cmobase v1.0.1: |
| 243 | * |
| 244 | * "A cache-block management instruction is permitted to |
| 245 | * access the specified cache block whenever a load instruction |
| 246 | * or store instruction is permitted to access the corresponding |
| 247 | * physical addresses. If neither a load instruction nor store |
| 248 | * instruction is permitted to access the physical addresses, |
| 249 | * but an instruction fetch is permitted to access the physical |
| 250 | * addresses, whether a cache-block management instruction is |
| 251 | * permitted to access the cache block is UNSPECIFIED." |
| 252 | */ |
| 253 | ret = probe_access_flags(env, address, cbomlen, MMU_DATA_LOAD, |
| 254 | mmu_idx, true, &phost, ra); |
| 255 | if (ret != TLB_INVALID_MASK) { |
| 256 | /* Success: readable */ |
| 257 | return; |
| 258 | } |
| 259 | |
| 260 | /* |
| 261 | * Since not readable, must be writable. On failure, store |
| 262 | * fault/store guest amo fault will be raised by |
| 263 | * riscv_cpu_tlb_fill(). PMP exceptions will be caught |
| 264 | * there as well. |
| 265 | */ |
| 266 | probe_write(env, address, cbomlen, mmu_idx, ra); |
| 267 | } |
| 268 | |
| 269 | void helper_cbo_clean_flush(CPURISCVState *env, target_ulong address) |
| 270 | { |
| 271 | uintptr_t ra = GETPC(); |
| 272 | check_zicbo_envcfg(env, MENVCFG_CBCFE, ra); |
| 273 | check_zicbom_access(env, address, ra); |
| 274 | |
| 275 | /* We don't emulate the cache-hierarchy, so we're done. */ |
| 276 | } |
| 277 | |
| 278 | void helper_cbo_inval(CPURISCVState *env, target_ulong address) |
| 279 | { |
| 280 | uintptr_t ra = GETPC(); |
| 281 | check_zicbo_envcfg(env, MENVCFG_CBIE, ra); |
| 282 | check_zicbom_access(env, address, ra); |
| 283 | |
| 284 | /* We don't emulate the cache-hierarchy, so we're done. */ |
| 285 | } |
| 286 | |
| 287 | void helper_sc_probe_write(CPURISCVState *env, target_ulong addr, |
| 288 | target_ulong size) |
| 289 | { |
| 290 | uintptr_t ra = GETPC(); |
| 291 | int mmu_idx = riscv_env_mmu_index(env, false); |
| 292 | |
| 293 | if (addr & (size - 1)) { |
| 294 | env->badaddr = addr; |
| 295 | riscv_raise_exception(env, RISCV_EXCP_STORE_AMO_ADDR_MIS, ra); |
| 296 | } |
| 297 | |
| 298 | probe_write(env, addr, size, mmu_idx, ra); |
| 299 | } |
| 300 | |
| 301 | #ifndef CONFIG_USER_ONLY |
| 302 | |
| 303 | target_ulong helper_sret(CPURISCVState *env) |
| 304 | { |
| 305 | uint64_t mstatus; |
| 306 | privilege_mode_t prev_priv; |
| 307 | bool prev_virt = env->virt_enabled; |
| 308 | const privilege_mode_t src_priv = env->priv; |
| 309 | const bool src_virt = env->virt_enabled; |
| 310 | |
| 311 | if ((env->virt_enabled && env->priv < PRV_S) || |
| 312 | (env->virt_enabled && get_field(env->hstatus, HSTATUS_VTSR))) { |
| 313 | riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC()); |
| 314 | } |
| 315 | |
| 316 | if (!(env->priv >= PRV_S)) { |
| 317 | riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); |
| 318 | } |
| 319 | |
| 320 | target_ulong retpc = env->sepc & get_xepc_mask(env); |
| 321 | if (!riscv_cpu_allow_16bit_insn(&env_archcpu(env)->cfg, |
| 322 | env->priv_ver, |
| 323 | env->misa_ext) && (retpc & 0x3)) { |
| 324 | riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC()); |
| 325 | } |
| 326 | |
| 327 | if (get_field(env->mstatus, MSTATUS_TSR) && !(env->priv >= PRV_M)) { |
| 328 | riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); |
| 329 | } |
| 330 | |
| 331 | mstatus = env->mstatus; |
| 332 | prev_priv = get_field(mstatus, MSTATUS_SPP); |
| 333 | mstatus = set_field(mstatus, MSTATUS_SIE, |
| 334 | get_field(mstatus, MSTATUS_SPIE)); |
| 335 | mstatus = set_field(mstatus, MSTATUS_SPIE, 1); |
| 336 | mstatus = set_field(mstatus, MSTATUS_SPP, PRV_U); |
| 337 | |
| 338 | if (riscv_cpu_cfg(env)->ext_ssdbltrp) { |
| 339 | if (riscv_has_ext(env, RVH)) { |
| 340 | target_ulong prev_vu = get_field(env->hstatus, HSTATUS_SPV) && |
| 341 | prev_priv == PRV_U; |
| 342 | /* Returning to VU from HS, vsstatus.sdt = 0 */ |
| 343 | if (!env->virt_enabled && prev_vu) { |
| 344 | env->vsstatus = set_field(env->vsstatus, MSTATUS_SDT, 0); |
| 345 | } |
| 346 | } |
| 347 | mstatus = set_field(mstatus, MSTATUS_SDT, 0); |
| 348 | } |
| 349 | if (riscv_cpu_cfg(env)->ext_smdbltrp && env->priv >= PRV_M) { |
| 350 | mstatus = set_field(mstatus, MSTATUS_MDT, 0); |
| 351 | } |
| 352 | if (env->priv_ver >= PRIV_VERSION_1_12_0) { |
| 353 | mstatus = set_field(mstatus, MSTATUS_MPRV, 0); |
| 354 | } |
| 355 | env->mstatus = mstatus; |
| 356 | |
| 357 | if (riscv_has_ext(env, RVH) && !env->virt_enabled) { |
| 358 | /* We support Hypervisor extensions and virtulisation is disabled */ |
| 359 | target_ulong hstatus = env->hstatus; |
| 360 | |
| 361 | prev_virt = !!(get_field(hstatus, HSTATUS_SPV)); |
| 362 | hstatus = set_field(hstatus, HSTATUS_SPV, 0); |
| 363 | |
| 364 | env->hstatus = hstatus; |
| 365 | |
| 366 | if (prev_virt) { |
| 367 | riscv_cpu_swap_hypervisor_regs(env); |
| 368 | } |
| 369 | } |
| 370 | |
| 371 | riscv_cpu_set_mode(env, prev_priv, prev_virt); |
| 372 | |
| 373 | /* |
| 374 | * If forward cfi enabled for new priv, restore elp status |
| 375 | * and clear spelp in mstatus |
| 376 | */ |
| 377 | if (cpu_get_fcfien(env)) { |
| 378 | env->elp = get_field(env->mstatus, MSTATUS_SPELP); |
| 379 | } |
| 380 | env->mstatus = set_field(env->mstatus, MSTATUS_SPELP, 0); |
| 381 | |
| 382 | if (riscv_cpu_cfg(env)->ext_smctr || riscv_cpu_cfg(env)->ext_ssctr) { |
| 383 | riscv_ctr_add_entry(env, env->pc, retpc, CTRDATA_TYPE_EXCEP_INT_RET, |
| 384 | src_priv, src_virt); |
| 385 | } |
| 386 | |
| 387 | return retpc; |
| 388 | } |
| 389 | |
| 390 | static void check_ret_from_m_mode(CPURISCVState *env, target_ulong retpc, |
| 391 | privilege_mode_t prev_priv, |
| 392 | uintptr_t ra) |
| 393 | { |
| 394 | if (!(env->priv >= PRV_M)) { |
| 395 | riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, ra); |
| 396 | } |
| 397 | |
| 398 | if (!riscv_cpu_allow_16bit_insn(&env_archcpu(env)->cfg, |
| 399 | env->priv_ver, |
| 400 | env->misa_ext) && (retpc & 0x3)) { |
| 401 | riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, ra); |
| 402 | } |
| 403 | |
| 404 | if (riscv_cpu_cfg(env)->pmp && |
| 405 | !pmp_get_num_rules(env) && (prev_priv != PRV_M)) { |
| 406 | riscv_raise_exception(env, RISCV_EXCP_INST_ACCESS_FAULT, ra); |
| 407 | } |
| 408 | } |
| 409 | static target_ulong ssdbltrp_mxret(CPURISCVState *env, target_ulong mstatus, |
| 410 | privilege_mode_t prev_priv, |
| 411 | bool prev_virt) |
| 412 | { |
| 413 | /* If returning to U, VS or VU, sstatus.sdt = 0 */ |
| 414 | if (prev_priv == PRV_U || (prev_virt && |
| 415 | (prev_priv == PRV_S || prev_priv == PRV_U))) { |
| 416 | mstatus = set_field(mstatus, MSTATUS_SDT, 0); |
| 417 | /* If returning to VU, vsstatus.sdt = 0 */ |
| 418 | if (prev_virt && prev_priv == PRV_U) { |
| 419 | env->vsstatus = set_field(env->vsstatus, MSTATUS_SDT, 0); |
| 420 | } |
| 421 | } |
| 422 | |
| 423 | return mstatus; |
| 424 | } |
| 425 | |
| 426 | target_ulong helper_mret(CPURISCVState *env) |
| 427 | { |
| 428 | target_ulong retpc = env->mepc & get_xepc_mask(env); |
| 429 | uint64_t mstatus = env->mstatus; |
| 430 | privilege_mode_t prev_priv = get_field(mstatus, MSTATUS_MPP); |
| 431 | uintptr_t ra = GETPC(); |
| 432 | |
| 433 | check_ret_from_m_mode(env, retpc, prev_priv, ra); |
| 434 | |
| 435 | bool prev_virt = !!(get_field(env->mstatus, MSTATUS_MPV) && |
| 436 | (prev_priv != PRV_M)); |
| 437 | mstatus = set_field(mstatus, MSTATUS_MIE, |
| 438 | get_field(mstatus, MSTATUS_MPIE)); |
| 439 | mstatus = set_field(mstatus, MSTATUS_MPIE, 1); |
| 440 | mstatus = set_field(mstatus, MSTATUS_MPP, |
| 441 | riscv_has_ext(env, RVU) ? PRV_U : PRV_M); |
| 442 | mstatus = set_field(mstatus, MSTATUS_MPV, 0); |
| 443 | if (riscv_cpu_cfg(env)->ext_ssdbltrp) { |
| 444 | mstatus = ssdbltrp_mxret(env, mstatus, prev_priv, prev_virt); |
| 445 | } |
| 446 | if (riscv_cpu_cfg(env)->ext_smdbltrp) { |
| 447 | mstatus = set_field(mstatus, MSTATUS_MDT, 0); |
| 448 | } |
| 449 | if ((env->priv_ver >= PRIV_VERSION_1_12_0) && (prev_priv != PRV_M)) { |
| 450 | mstatus = set_field(mstatus, MSTATUS_MPRV, 0); |
| 451 | } |
| 452 | env->mstatus = mstatus; |
| 453 | |
| 454 | if (riscv_has_ext(env, RVH) && prev_virt) { |
| 455 | riscv_cpu_swap_hypervisor_regs(env); |
| 456 | } |
| 457 | |
| 458 | riscv_cpu_set_mode(env, prev_priv, prev_virt); |
| 459 | /* |
| 460 | * If forward cfi enabled for new priv, restore elp status |
| 461 | * and clear mpelp in mstatus |
| 462 | */ |
| 463 | if (cpu_get_fcfien(env)) { |
| 464 | env->elp = get_field(env->mstatus, MSTATUS_MPELP); |
| 465 | } |
| 466 | env->mstatus = set_field(env->mstatus, MSTATUS_MPELP, 0); |
| 467 | |
| 468 | if (riscv_cpu_cfg(env)->ext_smctr || riscv_cpu_cfg(env)->ext_ssctr) { |
| 469 | riscv_ctr_add_entry(env, env->pc, retpc, CTRDATA_TYPE_EXCEP_INT_RET, |
| 470 | PRV_M, false); |
| 471 | } |
| 472 | |
| 473 | return retpc; |
| 474 | } |
| 475 | |
| 476 | target_ulong helper_mnret(CPURISCVState *env) |
| 477 | { |
| 478 | target_ulong retpc = env->mnepc; |
| 479 | privilege_mode_t prev_priv = get_field(env->mnstatus, MNSTATUS_MNPP); |
| 480 | bool prev_virt; |
| 481 | uintptr_t ra = GETPC(); |
| 482 | |
| 483 | check_ret_from_m_mode(env, retpc, prev_priv, ra); |
| 484 | |
| 485 | prev_virt = !!(get_field(env->mnstatus, MNSTATUS_MNPV) && |
| 486 | (prev_priv != PRV_M)); |
| 487 | env->mnstatus = set_field(env->mnstatus, MNSTATUS_NMIE, true); |
| 488 | |
| 489 | /* |
| 490 | * If MNRET changes the privilege mode to a mode |
| 491 | * less privileged than M, it also sets mstatus.MPRV to 0. |
| 492 | */ |
| 493 | if (prev_priv < PRV_M) { |
| 494 | env->mstatus = set_field(env->mstatus, MSTATUS_MPRV, false); |
| 495 | } |
| 496 | if (riscv_cpu_cfg(env)->ext_ssdbltrp) { |
| 497 | env->mstatus = ssdbltrp_mxret(env, env->mstatus, prev_priv, prev_virt); |
| 498 | } |
| 499 | |
| 500 | if (riscv_cpu_cfg(env)->ext_smdbltrp) { |
| 501 | if (prev_priv < PRV_M) { |
| 502 | env->mstatus = set_field(env->mstatus, MSTATUS_MDT, 0); |
| 503 | } |
| 504 | } |
| 505 | |
| 506 | if (riscv_has_ext(env, RVH) && prev_virt) { |
| 507 | riscv_cpu_swap_hypervisor_regs(env); |
| 508 | } |
| 509 | |
| 510 | riscv_cpu_set_mode(env, prev_priv, prev_virt); |
| 511 | |
| 512 | /* |
| 513 | * If forward cfi enabled for new priv, restore elp status |
| 514 | * and clear mnpelp in mnstatus |
| 515 | */ |
| 516 | if (cpu_get_fcfien(env)) { |
| 517 | env->elp = get_field(env->mnstatus, MNSTATUS_MNPELP); |
| 518 | } |
| 519 | env->mnstatus = set_field(env->mnstatus, MNSTATUS_MNPELP, 0); |
| 520 | |
| 521 | return retpc; |
| 522 | } |
| 523 | |
| 524 | void helper_ctr_add_entry(CPURISCVState *env, target_ulong src, |
| 525 | target_ulong dest, target_ulong type) |
| 526 | { |
| 527 | riscv_ctr_add_entry(env, src, dest, (enum CTRType)type, |
| 528 | env->priv, env->virt_enabled); |
| 529 | } |
| 530 | |
| 531 | void helper_ctr_clear(CPURISCVState *env) |
| 532 | { |
| 533 | /* |
| 534 | * It's safe to call smstateen_acc_ok() for umode access regardless of the |
| 535 | * state of bit 54 (CTR bit in case of m/hstateen) of sstateen. If the bit |
| 536 | * is zero, smstateen_acc_ok() will return the correct exception code and |
| 537 | * if it's one, smstateen_acc_ok() will return RISCV_EXCP_NONE. In that |
| 538 | * scenario the U-mode check below will handle that case. |
| 539 | */ |
| 540 | RISCVException ret = smstateen_acc_ok(env, 0, SMSTATEEN0_CTR); |
| 541 | if (ret != RISCV_EXCP_NONE) { |
| 542 | riscv_raise_exception(env, ret, GETPC()); |
| 543 | } |
| 544 | |
| 545 | if (env->priv == PRV_U) { |
| 546 | /* |
| 547 | * One corner case is when sctrclr is executed from VU-mode and |
| 548 | * mstateen.CTR = 0, in which case we are supposed to raise |
| 549 | * RISCV_EXCP_ILLEGAL_INST. This case is already handled in |
| 550 | * smstateen_acc_ok(). |
| 551 | */ |
| 552 | uint32_t excep = env->virt_enabled ? RISCV_EXCP_VIRT_INSTRUCTION_FAULT : |
| 553 | RISCV_EXCP_ILLEGAL_INST; |
| 554 | riscv_raise_exception(env, excep, GETPC()); |
| 555 | } |
| 556 | |
| 557 | riscv_ctr_clear(env); |
| 558 | } |
| 559 | |
| 560 | void helper_wfi(CPURISCVState *env) |
| 561 | { |
| 562 | CPUState *cs = env_cpu(env); |
| 563 | bool rvs = riscv_has_ext(env, RVS); |
| 564 | bool prv_u = env->priv == PRV_U; |
| 565 | bool prv_s = env->priv == PRV_S; |
| 566 | |
| 567 | if (((prv_s || (!rvs && prv_u)) && get_field(env->mstatus, MSTATUS_TW)) || |
| 568 | (rvs && prv_u && !env->virt_enabled)) { |
| 569 | riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); |
| 570 | } else if (env->virt_enabled && |
| 571 | (prv_u || (prv_s && get_field(env->hstatus, HSTATUS_VTW)))) { |
| 572 | riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC()); |
| 573 | } else { |
| 574 | cs->halted = 1; |
| 575 | cs->exception_index = EXCP_HLT; |
| 576 | cpu_loop_exit(cs); |
| 577 | } |
| 578 | } |
| 579 | |
| 580 | void helper_wrs_nto(CPURISCVState *env) |
| 581 | { |
| 582 | if (env->virt_enabled && (env->priv == PRV_S || env->priv == PRV_U) && |
| 583 | get_field(env->hstatus, HSTATUS_VTW) && |
| 584 | !get_field(env->mstatus, MSTATUS_TW)) { |
| 585 | riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC()); |
| 586 | } else if (env->priv != PRV_M && get_field(env->mstatus, MSTATUS_TW)) { |
| 587 | riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); |
| 588 | } |
| 589 | } |
| 590 | |
| 591 | void helper_tlb_flush(CPURISCVState *env) |
| 592 | { |
| 593 | CPUState *cs = env_cpu(env); |
| 594 | if (!env->virt_enabled && |
| 595 | (env->priv == PRV_U || |
| 596 | (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)))) { |
| 597 | riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); |
| 598 | } else if (env->virt_enabled && |
| 599 | (env->priv == PRV_U || get_field(env->hstatus, HSTATUS_VTVM))) { |
| 600 | riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC()); |
| 601 | } else { |
| 602 | tlb_flush(cs); |
| 603 | } |
| 604 | } |
| 605 | |
| 606 | void helper_tlb_flush_all(CPURISCVState *env) |
| 607 | { |
| 608 | CPUState *cs = env_cpu(env); |
| 609 | tlb_flush_all_cpus_synced(cs); |
| 610 | } |
| 611 | |
| 612 | void helper_hyp_tlb_flush(CPURISCVState *env) |
| 613 | { |
| 614 | CPUState *cs = env_cpu(env); |
| 615 | |
| 616 | if (env->virt_enabled) { |
| 617 | riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC()); |
| 618 | } |
| 619 | |
| 620 | if (env->priv == PRV_M || |
| 621 | (env->priv == PRV_S && !env->virt_enabled)) { |
| 622 | tlb_flush(cs); |
| 623 | return; |
| 624 | } |
| 625 | |
| 626 | riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); |
| 627 | } |
| 628 | |
| 629 | void helper_hyp_gvma_tlb_flush(CPURISCVState *env) |
| 630 | { |
| 631 | if (env->priv == PRV_S && !env->virt_enabled && |
| 632 | get_field(env->mstatus, MSTATUS_TVM)) { |
| 633 | riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); |
| 634 | } |
| 635 | |
| 636 | helper_hyp_tlb_flush(env); |
| 637 | } |
| 638 | |
| 639 | static int check_access_hlsv(CPURISCVState *env, bool x, uintptr_t ra) |
| 640 | { |
| 641 | if (env->priv == PRV_M) { |
| 642 | /* always allowed */ |
| 643 | } else if (env->virt_enabled) { |
| 644 | riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, ra); |
| 645 | } else if (env->priv == PRV_U && !get_field(env->hstatus, HSTATUS_HU)) { |
| 646 | riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, ra); |
| 647 | } |
| 648 | |
| 649 | int mode = get_field(env->hstatus, HSTATUS_SPVP); |
| 650 | if (!x && mode == PRV_S && get_field(env->vsstatus, MSTATUS_SUM)) { |
| 651 | mode = MMUIdx_S_SUM; |
| 652 | } |
| 653 | return mode | MMU_2STAGE_BIT; |
| 654 | } |
| 655 | |
| 656 | target_ulong helper_hyp_hlv_bu(CPURISCVState *env, target_ulong addr) |
| 657 | { |
| 658 | uintptr_t ra = GETPC(); |
| 659 | int mmu_idx = check_access_hlsv(env, false, ra); |
| 660 | MemOpIdx oi = make_memop_idx(MO_UB, mmu_idx); |
| 661 | |
| 662 | return cpu_ldb_mmu(env, adjust_addr_virt(env, addr), oi, ra); |
| 663 | } |
| 664 | |
| 665 | target_ulong helper_hyp_hlv_hu(CPURISCVState *env, target_ulong addr) |
| 666 | { |
| 667 | uintptr_t ra = GETPC(); |
| 668 | int mmu_idx = check_access_hlsv(env, false, ra); |
| 669 | MemOpIdx oi = make_memop_idx(mo_endian_env(env) | MO_UW, mmu_idx); |
| 670 | |
| 671 | return cpu_ldw_mmu(env, adjust_addr_virt(env, addr), oi, ra); |
| 672 | } |
| 673 | |
| 674 | target_ulong helper_hyp_hlv_wu(CPURISCVState *env, target_ulong addr) |
| 675 | { |
| 676 | uintptr_t ra = GETPC(); |
| 677 | int mmu_idx = check_access_hlsv(env, false, ra); |
| 678 | MemOpIdx oi = make_memop_idx(mo_endian_env(env) | MO_UL, mmu_idx); |
| 679 | |
| 680 | return cpu_ldl_mmu(env, adjust_addr_virt(env, addr), oi, ra); |
| 681 | } |
| 682 | |
| 683 | target_ulong helper_hyp_hlv_d(CPURISCVState *env, target_ulong addr) |
| 684 | { |
| 685 | uintptr_t ra = GETPC(); |
| 686 | int mmu_idx = check_access_hlsv(env, false, ra); |
| 687 | MemOpIdx oi = make_memop_idx(mo_endian_env(env) | MO_UQ, mmu_idx); |
| 688 | |
| 689 | return cpu_ldq_mmu(env, adjust_addr_virt(env, addr), oi, ra); |
| 690 | } |
| 691 | |
| 692 | void helper_hyp_hsv_b(CPURISCVState *env, target_ulong addr, target_ulong val) |
| 693 | { |
| 694 | uintptr_t ra = GETPC(); |
| 695 | int mmu_idx = check_access_hlsv(env, false, ra); |
| 696 | MemOpIdx oi = make_memop_idx(MO_UB, mmu_idx); |
| 697 | |
| 698 | cpu_stb_mmu(env, adjust_addr_virt(env, addr), val, oi, ra); |
| 699 | } |
| 700 | |
| 701 | void helper_hyp_hsv_h(CPURISCVState *env, target_ulong addr, target_ulong val) |
| 702 | { |
| 703 | uintptr_t ra = GETPC(); |
| 704 | int mmu_idx = check_access_hlsv(env, false, ra); |
| 705 | MemOpIdx oi = make_memop_idx(mo_endian_env(env) | MO_UW, mmu_idx); |
| 706 | |
| 707 | cpu_stw_mmu(env, adjust_addr_virt(env, addr), val, oi, ra); |
| 708 | } |
| 709 | |
| 710 | void helper_hyp_hsv_w(CPURISCVState *env, target_ulong addr, target_ulong val) |
| 711 | { |
| 712 | uintptr_t ra = GETPC(); |
| 713 | int mmu_idx = check_access_hlsv(env, false, ra); |
| 714 | MemOpIdx oi = make_memop_idx(mo_endian_env(env) | MO_UL, mmu_idx); |
| 715 | |
| 716 | cpu_stl_mmu(env, adjust_addr_virt(env, addr), val, oi, ra); |
| 717 | } |
| 718 | |
| 719 | void helper_hyp_hsv_d(CPURISCVState *env, target_ulong addr, target_ulong val) |
| 720 | { |
| 721 | uintptr_t ra = GETPC(); |
| 722 | int mmu_idx = check_access_hlsv(env, false, ra); |
| 723 | MemOpIdx oi = make_memop_idx(mo_endian_env(env) | MO_UQ, mmu_idx); |
| 724 | |
| 725 | cpu_stq_mmu(env, adjust_addr_virt(env, addr), val, oi, ra); |
| 726 | } |
| 727 | |
| 728 | /* |
| 729 | * TODO: These implementations are not quite correct. They perform the |
| 730 | * access using execute permission just fine, but the final PMP check |
| 731 | * is supposed to have read permission as well. Without replicating |
| 732 | * a fair fraction of cputlb.c, fixing this requires adding new mmu_idx |
| 733 | * which would imply that exact check in tlb_fill. |
| 734 | */ |
| 735 | target_ulong helper_hyp_hlvx_hu(CPURISCVState *env, target_ulong addr) |
| 736 | { |
| 737 | uintptr_t ra = GETPC(); |
| 738 | int mmu_idx = check_access_hlsv(env, true, ra); |
| 739 | MemOpIdx oi = make_memop_idx(mo_endian_env(env) | MO_UW, mmu_idx); |
| 740 | |
| 741 | return cpu_ldw_code_mmu(env, addr, oi, GETPC()); |
| 742 | } |
| 743 | |
| 744 | target_ulong helper_hyp_hlvx_wu(CPURISCVState *env, target_ulong addr) |
| 745 | { |
| 746 | uintptr_t ra = GETPC(); |
| 747 | int mmu_idx = check_access_hlsv(env, true, ra); |
| 748 | MemOpIdx oi = make_memop_idx(mo_endian_env(env) | MO_UL, mmu_idx); |
| 749 | |
| 750 | return cpu_ldl_code_mmu(env, addr, oi, ra); |
| 751 | } |
| 752 | |
| 753 | void helper_ssamoswap_disabled(CPURISCVState *env) |
| 754 | { |
| 755 | int exception = RISCV_EXCP_ILLEGAL_INST; |
| 756 | |
| 757 | /* |
| 758 | * Here we follow the RISC-V CFI spec [1] to implement the exception type |
| 759 | * of ssamoswap* instruction. |
| 760 | * |
| 761 | * [1] RISC-V CFI spec v1.0, ch2.7 Atomic Swap from a Shadow Stack Location |
| 762 | * |
| 763 | * Note: We have already checked some conditions in trans_* functions: |
| 764 | * 1. The effective priv mode is not M-mode. |
| 765 | * 2. The xSSE specific to the effictive priv mode is disabled. |
| 766 | */ |
| 767 | if (!get_field(env->menvcfg, MENVCFG_SSE)) { |
| 768 | /* |
| 769 | * Disabled M-mode SSE always trigger illegal instruction when |
| 770 | * current priv mode is not M-mode. |
| 771 | */ |
| 772 | exception = RISCV_EXCP_ILLEGAL_INST; |
| 773 | goto done; |
| 774 | } |
| 775 | |
| 776 | if (!riscv_has_ext(env, RVS)) { |
| 777 | /* S-mode is not implemented */ |
| 778 | exception = RISCV_EXCP_ILLEGAL_INST; |
| 779 | goto done; |
| 780 | } else if (env->virt_enabled) { |
| 781 | /* |
| 782 | * VU/VS-mode with disabled xSSE will trigger the virtual instruction |
| 783 | * exception. |
| 784 | */ |
| 785 | exception = RISCV_EXCP_VIRT_INSTRUCTION_FAULT; |
| 786 | goto done; |
| 787 | } else { |
| 788 | /* |
| 789 | * U-mode with disabled S-mode SSE will trigger the illegal instruction |
| 790 | * exception. |
| 791 | * |
| 792 | * Note: S-mode is already handled in the disabled M-mode SSE case. |
| 793 | */ |
| 794 | exception = RISCV_EXCP_ILLEGAL_INST; |
| 795 | goto done; |
| 796 | } |
| 797 | |
| 798 | done: |
| 799 | riscv_raise_exception(env, exception, GETPC()); |
| 800 | } |
| 801 | |
| 802 | #endif /* !CONFIG_USER_ONLY */ |