| 1 | /* |
| 2 | * QEMU RISC-V PMP (Physical Memory Protection) |
| 3 | * |
| 4 | * Author: Daire McNamara, daire.mcnamara@emdalo.com |
| 5 | * Ivan Griffin, ivan.griffin@emdalo.com |
| 6 | * |
| 7 | * This provides a RISC-V Physical Memory Protection interface |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify it |
| 10 | * under the terms and conditions of the GNU General Public License, |
| 11 | * version 2 or later, as published by the Free Software Foundation. |
| 12 | * |
| 13 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 14 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 16 | * more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License along with |
| 19 | * this program. If not, see <http://www.gnu.org/licenses/>. |
| 20 | */ |
| 21 | |
| 22 | #ifndef RISCV_PMP_H |
| 23 | #define RISCV_PMP_H |
| 24 | |
| 25 | #define MAX_RISCV_PMPS (64) |
| 26 | #define OLD_MAX_RISCV_PMPS (16) |
| 27 | #define MIN_RISCV_PMP_GRANULARITY 4 |
| 28 | |
| 29 | typedef enum { |
| 30 | PMP_READ = 1 << 0, |
| 31 | PMP_WRITE = 1 << 1, |
| 32 | PMP_EXEC = 1 << 2, |
| 33 | PMP_AMATCH = (3 << 3), |
| 34 | PMP_MTMATCH = (3 << 5), |
| 35 | PMP_LOCK = 1 << 7 |
| 36 | } pmp_priv_t; |
| 37 | |
| 38 | typedef enum { |
| 39 | PMP_AMATCH_OFF, /* Null (off) */ |
| 40 | PMP_AMATCH_TOR, /* Top of Range */ |
| 41 | PMP_AMATCH_NA4, /* Naturally aligned four-byte region */ |
| 42 | PMP_AMATCH_NAPOT /* Naturally aligned power-of-two region */ |
| 43 | } pmp_am_t; |
| 44 | |
| 45 | typedef enum { |
| 46 | MSECCFG_MML = 1 << 0, |
| 47 | MSECCFG_MMWP = 1 << 1, |
| 48 | MSECCFG_RLB = 1 << 2, |
| 49 | MSECCFG_USEED = 1 << 8, |
| 50 | MSECCFG_SSEED = 1 << 9, |
| 51 | MSECCFG_MLPE = 1 << 10, |
| 52 | MSECCFG_PMM = 3ULL << 32, |
| 53 | } mseccfg_field_t; |
| 54 | |
| 55 | typedef struct { |
| 56 | uint64_t addr_reg; |
| 57 | uint8_t cfg_reg; |
| 58 | } pmp_entry_t; |
| 59 | |
| 60 | typedef struct { |
| 61 | hwaddr sa; |
| 62 | hwaddr ea; |
| 63 | } pmp_addr_t; |
| 64 | |
| 65 | typedef struct { |
| 66 | pmp_entry_t pmp[MAX_RISCV_PMPS]; |
| 67 | pmp_addr_t addr[MAX_RISCV_PMPS]; |
| 68 | uint32_t num_rules; |
| 69 | } pmp_table_t; |
| 70 | |
| 71 | typedef struct CPUArchState CPURISCVState; |
| 72 | |
| 73 | bool pmp_hart_has_privs(CPURISCVState *env, hwaddr addr, |
| 74 | int size, pmp_priv_t privs, |
| 75 | pmp_priv_t *allowed_privs, |
| 76 | privilege_mode_t mode); |
| 77 | uint64_t pmp_get_tlb_size(CPURISCVState *env, hwaddr addr); |
| 78 | void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index); |
| 79 | void pmp_update_rule_nums(CPURISCVState *env); |
| 80 | uint32_t pmp_get_num_rules(CPURISCVState *env); |
| 81 | int pmp_priv_to_page_prot(pmp_priv_t pmp_priv); |
| 82 | void pmp_unlock_entries(CPURISCVState *env); |
| 83 | |
| 84 | #define MSECCFG_MML_ISSET(env) get_field(env->mseccfg, MSECCFG_MML) |
| 85 | #define MSECCFG_MMWP_ISSET(env) get_field(env->mseccfg, MSECCFG_MMWP) |
| 86 | #define MSECCFG_RLB_ISSET(env) get_field(env->mseccfg, MSECCFG_RLB) |
| 87 | |
| 88 | #endif |