| 1 | /* |
| 2 | * riscv TCG cpu class initialization |
| 3 | * |
| 4 | * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu |
| 5 | * Copyright (c) 2017-2018 SiFive, Inc. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify it |
| 8 | * under the terms and conditions of the GNU General Public License, |
| 9 | * version 2 or later, as published by the Free Software Foundation. |
| 10 | * |
| 11 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 14 | * more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License along with |
| 17 | * this program. If not, see <http://www.gnu.org/licenses/>. |
| 18 | */ |
| 19 | |
| 20 | #include "qemu/osdep.h" |
| 21 | #include "exec/translation-block.h" |
| 22 | #include "tcg-cpu.h" |
| 23 | #include "cpu.h" |
| 24 | #include "exec/target_page.h" |
| 25 | #include "internals.h" |
| 26 | #include "pmu.h" |
| 27 | #include "time_helper.h" |
| 28 | #include "qapi/error.h" |
| 29 | #include "qapi/visitor.h" |
| 30 | #include "qemu/accel.h" |
| 31 | #include "qemu/error-report.h" |
| 32 | #include "qemu/log.h" |
| 33 | #include "accel/accel-cpu-target.h" |
| 34 | #include "accel/tcg/cpu-ops.h" |
| 35 | #include "tcg/tcg.h" |
| 36 | #ifndef CONFIG_USER_ONLY |
| 37 | #include "hw/core/boards.h" |
| 38 | #include "system/tcg.h" |
| 39 | #include "exec/icount.h" |
| 40 | #include "target/riscv/tcg/debug.h" |
| 41 | #include "target/riscv/tcg/csr.h" |
| 42 | #endif |
| 43 | |
| 44 | /* Hash that stores user set extensions */ |
| 45 | static GHashTable *multi_ext_user_opts; |
| 46 | static GHashTable *misa_ext_user_opts; |
| 47 | |
| 48 | static GHashTable *multi_ext_implied_rules; |
| 49 | static GHashTable *misa_ext_implied_rules; |
| 50 | |
| 51 | static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset) |
| 52 | { |
| 53 | return g_hash_table_contains(multi_ext_user_opts, |
| 54 | GUINT_TO_POINTER(ext_offset)); |
| 55 | } |
| 56 | |
| 57 | static bool cpu_misa_ext_is_user_set(uint32_t misa_bit) |
| 58 | { |
| 59 | return g_hash_table_contains(misa_ext_user_opts, |
| 60 | GUINT_TO_POINTER(misa_bit)); |
| 61 | } |
| 62 | |
| 63 | static void cpu_cfg_ext_add_user_opt(uint32_t ext_offset, bool value) |
| 64 | { |
| 65 | g_hash_table_insert(multi_ext_user_opts, GUINT_TO_POINTER(ext_offset), |
| 66 | (gpointer)value); |
| 67 | } |
| 68 | |
| 69 | static void cpu_misa_ext_add_user_opt(uint32_t bit, bool value) |
| 70 | { |
| 71 | g_hash_table_insert(misa_ext_user_opts, GUINT_TO_POINTER(bit), |
| 72 | (gpointer)value); |
| 73 | } |
| 74 | |
| 75 | static void riscv_cpu_write_misa_bit(RISCVCPU *cpu, uint32_t bit, |
| 76 | bool enabled) |
| 77 | { |
| 78 | CPURISCVState *env = &cpu->env; |
| 79 | |
| 80 | if (enabled) { |
| 81 | env->misa_ext |= bit; |
| 82 | env->misa_ext_mask |= bit; |
| 83 | } else { |
| 84 | env->misa_ext &= ~bit; |
| 85 | env->misa_ext_mask &= ~bit; |
| 86 | } |
| 87 | } |
| 88 | |
| 89 | static const char *cpu_priv_ver_to_str(int priv_ver) |
| 90 | { |
| 91 | const char *priv_spec_str = priv_spec_to_str(priv_ver); |
| 92 | |
| 93 | g_assert(priv_spec_str); |
| 94 | |
| 95 | return priv_spec_str; |
| 96 | } |
| 97 | |
| 98 | static int riscv_cpu_mmu_index(CPUState *cs, bool ifetch) |
| 99 | { |
| 100 | return riscv_env_mmu_index(cpu_env(cs), ifetch); |
| 101 | } |
| 102 | |
| 103 | static TCGTBCPUState riscv_get_tb_cpu_state(CPUState *cs) |
| 104 | { |
| 105 | CPURISCVState *env = cpu_env(cs); |
| 106 | RISCVCPU *cpu = env_archcpu(env); |
| 107 | RISCVExtStatus fs, vs; |
| 108 | uint32_t flags = 0; |
| 109 | uint64_t ext_flags = 0; |
| 110 | bool pm_signext = riscv_cpu_virt_mem_enabled(env, false); |
| 111 | |
| 112 | if (cpu->cfg.ext_zve32x) { |
| 113 | /* |
| 114 | * If env->vl equals to VLMAX, we can use generic vector operation |
| 115 | * expanders (GVEC) to accerlate the vector operations. |
| 116 | * However, as LMUL could be a fractional number. The maximum |
| 117 | * vector size can be operated might be less than 8 bytes, |
| 118 | * which is not supported by GVEC. So we set vl_eq_vlmax flag to true |
| 119 | * only when maxsz >= 8 bytes. |
| 120 | */ |
| 121 | |
| 122 | /* lmul encoded as in DisasContext::lmul */ |
| 123 | int8_t lmul = sextract32(FIELD_EX64(env->vtype, VTYPE, VLMUL), 0, 3); |
| 124 | uint8_t altfmt = FIELD_EX64(env->vtype, VTYPE, ALTFMT); |
| 125 | uint32_t vsew = FIELD_EX64(env->vtype, VTYPE, VSEW); |
| 126 | uint32_t vlmax = vext_get_vlmax(cpu->cfg.vlenb, vsew, lmul); |
| 127 | uint32_t maxsz = vlmax << vsew; |
| 128 | bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl) && |
| 129 | (maxsz >= 8); |
| 130 | flags = FIELD_DP32(flags, TB_FLAGS, VILL, env->vill); |
| 131 | flags = FIELD_DP32(flags, TB_FLAGS, SEW, vsew); |
| 132 | flags = FIELD_DP32(flags, TB_FLAGS, LMUL, |
| 133 | FIELD_EX64(env->vtype, VTYPE, VLMUL)); |
| 134 | flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax); |
| 135 | flags = FIELD_DP32(flags, TB_FLAGS, VTA, |
| 136 | FIELD_EX64(env->vtype, VTYPE, VTA)); |
| 137 | flags = FIELD_DP32(flags, TB_FLAGS, VMA, |
| 138 | FIELD_EX64(env->vtype, VTYPE, VMA)); |
| 139 | flags = FIELD_DP32(flags, TB_FLAGS, VSTART_EQ_ZERO, env->vstart == 0); |
| 140 | ext_flags = FIELD_DP64(ext_flags, EXT_TB_FLAGS, ALTFMT, altfmt); |
| 141 | } else { |
| 142 | flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1); |
| 143 | } |
| 144 | |
| 145 | if (cpu_get_fcfien(env)) { |
| 146 | /* |
| 147 | * For Forward CFI, only the expectation of a lpad at |
| 148 | * the start of the block is tracked via env->elp. env->elp |
| 149 | * is turned on during jalr translation. |
| 150 | */ |
| 151 | flags = FIELD_DP32(flags, TB_FLAGS, FCFI_LP_EXPECTED, env->elp); |
| 152 | flags = FIELD_DP32(flags, TB_FLAGS, FCFI_ENABLED, 1); |
| 153 | } |
| 154 | |
| 155 | if (cpu_get_bcfien(env)) { |
| 156 | flags = FIELD_DP32(flags, TB_FLAGS, BCFI_ENABLED, 1); |
| 157 | } |
| 158 | |
| 159 | #ifdef CONFIG_USER_ONLY |
| 160 | fs = EXT_STATUS_DIRTY; |
| 161 | vs = EXT_STATUS_DIRTY; |
| 162 | #else |
| 163 | flags = FIELD_DP32(flags, TB_FLAGS, PRIV, env->priv); |
| 164 | |
| 165 | flags |= riscv_env_mmu_index(env, 0); |
| 166 | fs = get_field(env->mstatus, MSTATUS_FS); |
| 167 | vs = get_field(env->mstatus, MSTATUS_VS); |
| 168 | |
| 169 | if (env->virt_enabled) { |
| 170 | flags = FIELD_DP32(flags, TB_FLAGS, VIRT_ENABLED, 1); |
| 171 | /* |
| 172 | * Merge DISABLED and !DIRTY states using MIN. |
| 173 | * We will set both fields when dirtying. |
| 174 | */ |
| 175 | fs = MIN(fs, get_field(env->mstatus_hs, MSTATUS_FS)); |
| 176 | vs = MIN(vs, get_field(env->mstatus_hs, MSTATUS_VS)); |
| 177 | } |
| 178 | |
| 179 | /* With Zfinx, floating point is enabled/disabled by Smstateen. */ |
| 180 | if (!riscv_has_ext(env, RVF)) { |
| 181 | fs = (smstateen_acc_ok(env, 0, SMSTATEEN0_FCSR) == RISCV_EXCP_NONE) |
| 182 | ? EXT_STATUS_DIRTY : EXT_STATUS_DISABLED; |
| 183 | } |
| 184 | |
| 185 | if (cpu->cfg.debug && !icount_enabled()) { |
| 186 | flags = FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enabled); |
| 187 | } |
| 188 | #endif |
| 189 | |
| 190 | flags = FIELD_DP32(flags, TB_FLAGS, FS, fs); |
| 191 | flags = FIELD_DP32(flags, TB_FLAGS, VS, vs); |
| 192 | flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl); |
| 193 | flags = FIELD_DP32(flags, TB_FLAGS, AXL, cpu_address_xl(env)); |
| 194 | flags = FIELD_DP32(flags, TB_FLAGS, PM_PMM, riscv_pm_get_pmm(env)); |
| 195 | flags = FIELD_DP32(flags, TB_FLAGS, PM_SIGNEXTEND, pm_signext); |
| 196 | |
| 197 | ext_flags = FIELD_DP64(ext_flags, EXT_TB_FLAGS, MISA_EXT, env->misa_ext); |
| 198 | ext_flags = FIELD_DP64(ext_flags, EXT_TB_FLAGS, BIG_ENDIAN, |
| 199 | mo_endian_env(env) == MO_BE); |
| 200 | |
| 201 | return (TCGTBCPUState){ |
| 202 | .pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc, |
| 203 | .flags = flags, |
| 204 | .cs_base = ext_flags, |
| 205 | }; |
| 206 | } |
| 207 | |
| 208 | static void riscv_cpu_synchronize_from_tb(CPUState *cs, |
| 209 | const TranslationBlock *tb) |
| 210 | { |
| 211 | if (!(tb_cflags(tb) & CF_PCREL)) { |
| 212 | RISCVCPU *cpu = RISCV_CPU(cs); |
| 213 | CPURISCVState *env = &cpu->env; |
| 214 | RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); |
| 215 | |
| 216 | tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL)); |
| 217 | |
| 218 | if (xl == MXL_RV32) { |
| 219 | env->pc = (int32_t) tb->pc; |
| 220 | } else { |
| 221 | env->pc = tb->pc; |
| 222 | } |
| 223 | } |
| 224 | } |
| 225 | |
| 226 | static void riscv_restore_state_to_opc(CPUState *cs, |
| 227 | const TranslationBlock *tb, |
| 228 | const uint64_t *data) |
| 229 | { |
| 230 | RISCVCPU *cpu = RISCV_CPU(cs); |
| 231 | CPURISCVState *env = &cpu->env; |
| 232 | RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); |
| 233 | target_ulong pc; |
| 234 | |
| 235 | if (tb_cflags(tb) & CF_PCREL) { |
| 236 | pc = (env->pc & TARGET_PAGE_MASK) | data[0]; |
| 237 | } else { |
| 238 | pc = data[0]; |
| 239 | } |
| 240 | |
| 241 | if (xl == MXL_RV32) { |
| 242 | env->pc = (int32_t)pc; |
| 243 | } else { |
| 244 | env->pc = pc; |
| 245 | } |
| 246 | env->bins = data[1]; |
| 247 | env->excp_uw2 = data[2]; |
| 248 | } |
| 249 | |
| 250 | #ifndef CONFIG_USER_ONLY |
| 251 | static vaddr riscv_pointer_wrap(CPUState *cs, int mmu_idx, |
| 252 | vaddr result, vaddr base) |
| 253 | { |
| 254 | CPURISCVState *env = cpu_env(cs); |
| 255 | uint32_t pm_len; |
| 256 | bool pm_signext; |
| 257 | |
| 258 | if (cpu_address_xl(env) == MXL_RV32) { |
| 259 | return (uint32_t)result; |
| 260 | } |
| 261 | |
| 262 | pm_len = riscv_pm_get_pmlen(riscv_pm_get_pmm(env)); |
| 263 | if (pm_len == 0) { |
| 264 | return result; |
| 265 | } |
| 266 | |
| 267 | pm_signext = riscv_cpu_virt_mem_enabled(env, false); |
| 268 | if (pm_signext) { |
| 269 | return sextract64(result, 0, 64 - pm_len); |
| 270 | } |
| 271 | return extract64(result, 0, 64 - pm_len); |
| 272 | } |
| 273 | #endif |
| 274 | |
| 275 | const TCGCPUOps riscv_tcg_ops = { |
| 276 | .mttcg_supported = true, |
| 277 | .guest_default_memory_order = 0, |
| 278 | |
| 279 | .initialize = riscv_translate_init, |
| 280 | .translate_code = riscv_translate_code, |
| 281 | .get_tb_cpu_state = riscv_get_tb_cpu_state, |
| 282 | .synchronize_from_tb = riscv_cpu_synchronize_from_tb, |
| 283 | .restore_state_to_opc = riscv_restore_state_to_opc, |
| 284 | .mmu_index = riscv_cpu_mmu_index, |
| 285 | |
| 286 | #ifndef CONFIG_USER_ONLY |
| 287 | .tlb_fill = riscv_cpu_tlb_fill, |
| 288 | .pointer_wrap = riscv_pointer_wrap, |
| 289 | .cpu_exec_interrupt = riscv_cpu_exec_interrupt, |
| 290 | .cpu_exec_halt = riscv_cpu_has_work, |
| 291 | .cpu_exec_reset = cpu_reset, |
| 292 | .do_interrupt = riscv_cpu_do_interrupt, |
| 293 | .do_transaction_failed = riscv_cpu_do_transaction_failed, |
| 294 | .do_unaligned_access = riscv_cpu_do_unaligned_access, |
| 295 | .debug_excp_handler = riscv_cpu_debug_excp_handler, |
| 296 | .debug_check_breakpoint = riscv_cpu_debug_check_breakpoint, |
| 297 | .debug_check_watchpoint = riscv_cpu_debug_check_watchpoint, |
| 298 | #endif /* !CONFIG_USER_ONLY */ |
| 299 | }; |
| 300 | |
| 301 | static int cpu_cfg_ext_get_min_version(uint32_t ext_offset) |
| 302 | { |
| 303 | const RISCVIsaExtData *edata; |
| 304 | |
| 305 | for (edata = isa_edata_arr; edata && edata->name; edata++) { |
| 306 | if (edata->ext_enable_offset != ext_offset) { |
| 307 | continue; |
| 308 | } |
| 309 | |
| 310 | return edata->min_version; |
| 311 | } |
| 312 | |
| 313 | g_assert_not_reached(); |
| 314 | } |
| 315 | |
| 316 | static const char *cpu_cfg_ext_get_name(uint32_t ext_offset) |
| 317 | { |
| 318 | const RISCVIsaExtData *edata; |
| 319 | |
| 320 | for (edata = isa_edata_arr; edata->name != NULL; edata++) { |
| 321 | if (edata->ext_enable_offset == ext_offset) { |
| 322 | return edata->name; |
| 323 | } |
| 324 | } |
| 325 | |
| 326 | g_assert_not_reached(); |
| 327 | } |
| 328 | |
| 329 | static void cpu_bump_multi_ext_priv_ver(CPURISCVState *env, |
| 330 | uint32_t ext_offset) |
| 331 | { |
| 332 | int ext_priv_ver; |
| 333 | |
| 334 | if (env->priv_ver == PRIV_VERSION_LATEST) { |
| 335 | return; |
| 336 | } |
| 337 | |
| 338 | ext_priv_ver = cpu_cfg_ext_get_min_version(ext_offset); |
| 339 | |
| 340 | if (env->priv_ver < ext_priv_ver) { |
| 341 | /* |
| 342 | * Note: the 'priv_spec' command line option, if present, |
| 343 | * will take precedence over this priv_ver bump. |
| 344 | */ |
| 345 | env->priv_ver = ext_priv_ver; |
| 346 | } |
| 347 | } |
| 348 | |
| 349 | static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset, |
| 350 | bool value) |
| 351 | { |
| 352 | CPURISCVState *env = &cpu->env; |
| 353 | bool prev_val = isa_ext_is_enabled(cpu, ext_offset); |
| 354 | int min_version; |
| 355 | |
| 356 | if (prev_val == value) { |
| 357 | return; |
| 358 | } |
| 359 | |
| 360 | if (cpu_cfg_ext_is_user_set(ext_offset)) { |
| 361 | return; |
| 362 | } |
| 363 | |
| 364 | if (value && env->priv_ver != PRIV_VERSION_LATEST) { |
| 365 | /* Do not enable it if priv_ver is older than min_version */ |
| 366 | min_version = cpu_cfg_ext_get_min_version(ext_offset); |
| 367 | if (env->priv_ver < min_version) { |
| 368 | return; |
| 369 | } |
| 370 | } |
| 371 | |
| 372 | isa_ext_update_enabled(cpu, ext_offset, value); |
| 373 | } |
| 374 | |
| 375 | static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp) |
| 376 | { |
| 377 | if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) { |
| 378 | error_setg(errp, "H extension requires priv spec 1.12.0"); |
| 379 | return; |
| 380 | } |
| 381 | } |
| 382 | |
| 383 | static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg, |
| 384 | Error **errp) |
| 385 | { |
| 386 | uint32_t min_vlen; |
| 387 | uint32_t vlen = cfg->vlenb << 3; |
| 388 | |
| 389 | if (riscv_has_ext(env, RVV)) { |
| 390 | min_vlen = 128; |
| 391 | } else if (cfg->ext_zve64x) { |
| 392 | min_vlen = 64; |
| 393 | } else if (cfg->ext_zve32x) { |
| 394 | min_vlen = 32; |
| 395 | } else { |
| 396 | return; |
| 397 | } |
| 398 | |
| 399 | if (vlen > RV_VLEN_MAX || vlen < min_vlen) { |
| 400 | error_setg(errp, |
| 401 | "Vector extension implementation only supports VLEN " |
| 402 | "in the range [%d, %d]", min_vlen, RV_VLEN_MAX); |
| 403 | return; |
| 404 | } |
| 405 | |
| 406 | if (cfg->elen > 64 || cfg->elen < 8) { |
| 407 | error_setg(errp, |
| 408 | "Vector extension implementation only supports ELEN " |
| 409 | "in the range [8, 64]"); |
| 410 | return; |
| 411 | } |
| 412 | |
| 413 | if (vlen < cfg->elen) { |
| 414 | error_setg(errp, "Vector extension implementation requires VLEN " |
| 415 | "to be greater than or equal to ELEN"); |
| 416 | return; |
| 417 | } |
| 418 | } |
| 419 | |
| 420 | static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) |
| 421 | { |
| 422 | CPURISCVState *env = &cpu->env; |
| 423 | const RISCVIsaExtData *edata; |
| 424 | |
| 425 | /* Force disable extensions if priv spec version does not match */ |
| 426 | for (edata = isa_edata_arr; edata && edata->name; edata++) { |
| 427 | if (isa_ext_is_enabled(cpu, edata->ext_enable_offset) && |
| 428 | (env->priv_ver < edata->min_version)) { |
| 429 | /* |
| 430 | * These two extensions are always enabled as they were supported |
| 431 | * by QEMU before they were added as extensions in the ISA. |
| 432 | */ |
| 433 | if (!strcmp(edata->name, "zicntr") || |
| 434 | !strcmp(edata->name, "zihpm")) { |
| 435 | continue; |
| 436 | } |
| 437 | |
| 438 | /* |
| 439 | * cpu.debug = true is marked as 'sdtrig', priv spec 1.12. |
| 440 | * Skip this warning since existing CPUs with older priv |
| 441 | * spec and debug = true will be impacted. |
| 442 | */ |
| 443 | if (!strcmp(edata->name, "sdtrig")) { |
| 444 | continue; |
| 445 | } |
| 446 | |
| 447 | isa_ext_update_enabled(cpu, edata->ext_enable_offset, false); |
| 448 | #ifndef CONFIG_USER_ONLY |
| 449 | warn_report("disabling %s extension for hart 0x%" PRIx64 |
| 450 | " because privilege spec version does not match", |
| 451 | edata->name, env->mhartid); |
| 452 | #else |
| 453 | warn_report("disabling %s extension because " |
| 454 | "privilege spec version does not match", |
| 455 | edata->name); |
| 456 | #endif |
| 457 | } |
| 458 | } |
| 459 | } |
| 460 | |
| 461 | static void riscv_cpu_update_cfg(RISCVCPU *cpu) |
| 462 | { |
| 463 | if (cpu->env.priv_ver >= PRIV_VERSION_1_11_0) { |
| 464 | cpu->cfg.has_priv_1_11 = true; |
| 465 | } |
| 466 | |
| 467 | if (cpu->env.priv_ver >= PRIV_VERSION_1_12_0) { |
| 468 | cpu->cfg.has_priv_1_12 = true; |
| 469 | } |
| 470 | |
| 471 | if (cpu->env.priv_ver >= PRIV_VERSION_1_13_0) { |
| 472 | cpu->cfg.has_priv_1_13 = true; |
| 473 | } |
| 474 | |
| 475 | /* zic64b is 1.12 or later */ |
| 476 | cpu->cfg.ext_zic64b = cpu->cfg.cbom_blocksize == 64 && |
| 477 | cpu->cfg.cbop_blocksize == 64 && |
| 478 | cpu->cfg.cboz_blocksize == 64 && |
| 479 | cpu->cfg.has_priv_1_12; |
| 480 | |
| 481 | cpu->cfg.ext_ssstateen = cpu->cfg.ext_smstateen; |
| 482 | |
| 483 | cpu->cfg.ext_sha = riscv_has_ext(&cpu->env, RVH) && |
| 484 | cpu->cfg.ext_ssstateen; |
| 485 | |
| 486 | cpu->cfg.ext_ziccrse = cpu->cfg.has_priv_1_11; |
| 487 | } |
| 488 | |
| 489 | static void riscv_cpu_validate_g(RISCVCPU *cpu) |
| 490 | { |
| 491 | const char *warn_msg = "RVG mandates disabled extension %s"; |
| 492 | uint32_t g_misa_bits[] = {RVI, RVM, RVA, RVF, RVD}; |
| 493 | bool send_warn = cpu_misa_ext_is_user_set(RVG); |
| 494 | |
| 495 | for (int i = 0; i < ARRAY_SIZE(g_misa_bits); i++) { |
| 496 | uint32_t bit = g_misa_bits[i]; |
| 497 | |
| 498 | if (riscv_has_ext(&cpu->env, bit)) { |
| 499 | continue; |
| 500 | } |
| 501 | |
| 502 | if (send_warn) { |
| 503 | warn_report(warn_msg, riscv_get_misa_ext_name(bit)); |
| 504 | } |
| 505 | } |
| 506 | |
| 507 | if (!cpu->cfg.ext_zicsr && send_warn) { |
| 508 | warn_report(warn_msg, "zicsr"); |
| 509 | } |
| 510 | |
| 511 | if (!cpu->cfg.ext_zifencei && send_warn) { |
| 512 | warn_report(warn_msg, "zifencei"); |
| 513 | } |
| 514 | } |
| 515 | |
| 516 | static void riscv_cpu_validate_b(RISCVCPU *cpu) |
| 517 | { |
| 518 | const char *warn_msg = "RVB mandates disabled extension %s"; |
| 519 | |
| 520 | if (!cpu->cfg.ext_zba) { |
| 521 | warn_report(warn_msg, "zba"); |
| 522 | } |
| 523 | |
| 524 | if (!cpu->cfg.ext_zbb) { |
| 525 | warn_report(warn_msg, "zbb"); |
| 526 | } |
| 527 | |
| 528 | if (!cpu->cfg.ext_zbs) { |
| 529 | warn_report(warn_msg, "zbs"); |
| 530 | } |
| 531 | } |
| 532 | |
| 533 | /* |
| 534 | * Check consistency between chosen extensions while setting |
| 535 | * cpu->cfg accordingly. |
| 536 | */ |
| 537 | void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) |
| 538 | { |
| 539 | RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); |
| 540 | CPURISCVState *env = &cpu->env; |
| 541 | Error *local_err = NULL; |
| 542 | |
| 543 | if (riscv_has_ext(env, RVG)) { |
| 544 | riscv_cpu_validate_g(cpu); |
| 545 | } |
| 546 | |
| 547 | if (riscv_has_ext(env, RVB)) { |
| 548 | riscv_cpu_validate_b(cpu); |
| 549 | } |
| 550 | |
| 551 | if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) { |
| 552 | error_setg(errp, |
| 553 | "I and E extensions are incompatible"); |
| 554 | return; |
| 555 | } |
| 556 | |
| 557 | if (!riscv_has_ext(env, RVI) && !riscv_has_ext(env, RVE)) { |
| 558 | error_setg(errp, |
| 559 | "Either I or E extension must be set"); |
| 560 | return; |
| 561 | } |
| 562 | |
| 563 | if (riscv_has_ext(env, RVS) && !riscv_has_ext(env, RVU)) { |
| 564 | error_setg(errp, |
| 565 | "Setting S extension without U extension is illegal"); |
| 566 | return; |
| 567 | } |
| 568 | |
| 569 | if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVI)) { |
| 570 | error_setg(errp, |
| 571 | "H depends on an I base integer ISA with 32 x registers"); |
| 572 | return; |
| 573 | } |
| 574 | |
| 575 | if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVS)) { |
| 576 | error_setg(errp, "H extension implicitly requires S-mode"); |
| 577 | return; |
| 578 | } |
| 579 | |
| 580 | if (riscv_has_ext(env, RVF) && !cpu->cfg.ext_zicsr) { |
| 581 | error_setg(errp, "F extension requires Zicsr"); |
| 582 | return; |
| 583 | } |
| 584 | |
| 585 | if ((cpu->cfg.ext_zacas) && !riscv_has_ext(env, RVA)) { |
| 586 | error_setg(errp, "Zacas extension requires A extension"); |
| 587 | return; |
| 588 | } |
| 589 | |
| 590 | if ((cpu->cfg.ext_zawrs) && !riscv_has_ext(env, RVA)) { |
| 591 | error_setg(errp, "Zawrs extension requires A extension"); |
| 592 | return; |
| 593 | } |
| 594 | |
| 595 | if (cpu->cfg.ext_zfa && !riscv_has_ext(env, RVF)) { |
| 596 | error_setg(errp, "Zfa extension requires F extension"); |
| 597 | return; |
| 598 | } |
| 599 | |
| 600 | if (cpu->cfg.ext_zfhmin && !riscv_has_ext(env, RVF)) { |
| 601 | error_setg(errp, "Zfh/Zfhmin extensions require F extension"); |
| 602 | return; |
| 603 | } |
| 604 | |
| 605 | if (cpu->cfg.ext_zfbfmin && !riscv_has_ext(env, RVF)) { |
| 606 | error_setg(errp, "Zfbfmin extension depends on F extension"); |
| 607 | return; |
| 608 | } |
| 609 | |
| 610 | if (riscv_has_ext(env, RVD) && !riscv_has_ext(env, RVF)) { |
| 611 | error_setg(errp, "D extension requires F extension"); |
| 612 | return; |
| 613 | } |
| 614 | |
| 615 | riscv_cpu_validate_v(env, &cpu->cfg, &local_err); |
| 616 | if (local_err != NULL) { |
| 617 | error_propagate(errp, local_err); |
| 618 | return; |
| 619 | } |
| 620 | |
| 621 | /* The Zve64d extension depends on the Zve64f extension */ |
| 622 | if (cpu->cfg.ext_zve64d) { |
| 623 | if (!riscv_has_ext(env, RVD)) { |
| 624 | error_setg(errp, "Zve64d/V extensions require D extension"); |
| 625 | return; |
| 626 | } |
| 627 | } |
| 628 | |
| 629 | /* The Zve32f extension depends on the Zve32x extension */ |
| 630 | if (cpu->cfg.ext_zve32f) { |
| 631 | if (!riscv_has_ext(env, RVF)) { |
| 632 | error_setg(errp, "Zve32f/Zve64f extensions require F extension"); |
| 633 | return; |
| 634 | } |
| 635 | } |
| 636 | |
| 637 | if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) { |
| 638 | error_setg(errp, "Zvfh/Zvfhmin extensions require Zve32f extension"); |
| 639 | return; |
| 640 | } |
| 641 | |
| 642 | if (cpu->cfg.ext_zvfh && !cpu->cfg.ext_zfhmin) { |
| 643 | error_setg(errp, "Zvfh extensions requires Zfhmin extension"); |
| 644 | return; |
| 645 | } |
| 646 | |
| 647 | if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zve32f) { |
| 648 | error_setg(errp, "Zvfbfmin extension depends on Zve32f extension"); |
| 649 | return; |
| 650 | } |
| 651 | |
| 652 | if (cpu->cfg.ext_zvfbfwma && !cpu->cfg.ext_zvfbfmin) { |
| 653 | error_setg(errp, "Zvfbfwma extension depends on Zvfbfmin extension"); |
| 654 | return; |
| 655 | } |
| 656 | |
| 657 | if (cpu->cfg.ext_zvfbfa) { |
| 658 | if (!cpu->cfg.ext_zve32f || !cpu->cfg.ext_zfbfmin) { |
| 659 | error_setg(errp, "Zvfbfa extension requires Zve32f extension " |
| 660 | "and Zfbfmin extension"); |
| 661 | return; |
| 662 | } |
| 663 | } |
| 664 | |
| 665 | if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) { |
| 666 | error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx"); |
| 667 | return; |
| 668 | } |
| 669 | |
| 670 | if (cpu->cfg.ext_zfinx) { |
| 671 | if (!cpu->cfg.ext_zicsr) { |
| 672 | error_setg(errp, "Zfinx extension requires Zicsr"); |
| 673 | return; |
| 674 | } |
| 675 | if (riscv_has_ext(env, RVF)) { |
| 676 | error_setg(errp, |
| 677 | "Zfinx cannot be supported together with F extension"); |
| 678 | return; |
| 679 | } |
| 680 | } |
| 681 | |
| 682 | if (cpu->cfg.ext_zcmop && !cpu->cfg.ext_zca) { |
| 683 | error_setg(errp, "Zcmop extensions require Zca"); |
| 684 | return; |
| 685 | } |
| 686 | |
| 687 | if (mcc->def->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) { |
| 688 | error_setg(errp, "Zcf extension is only relevant to RV32"); |
| 689 | return; |
| 690 | } |
| 691 | |
| 692 | if (!riscv_has_ext(env, RVF) && cpu->cfg.ext_zcf) { |
| 693 | error_setg(errp, "Zcf extension requires F extension"); |
| 694 | return; |
| 695 | } |
| 696 | |
| 697 | if (!riscv_has_ext(env, RVD) && cpu->cfg.ext_zcd) { |
| 698 | error_setg(errp, "Zcd extension requires D extension"); |
| 699 | return; |
| 700 | } |
| 701 | |
| 702 | if ((cpu->cfg.ext_zcf || cpu->cfg.ext_zcd || cpu->cfg.ext_zcb || |
| 703 | cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt) && !cpu->cfg.ext_zca) { |
| 704 | error_setg(errp, "Zcf/Zcd/Zcb/Zcmp/Zcmt extensions require Zca " |
| 705 | "extension"); |
| 706 | return; |
| 707 | } |
| 708 | |
| 709 | if (cpu->cfg.ext_zcd && (cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt)) { |
| 710 | error_setg(errp, "Zcmp/Zcmt extensions are incompatible with " |
| 711 | "Zcd extension"); |
| 712 | return; |
| 713 | } |
| 714 | |
| 715 | if (cpu->cfg.ext_zcmt && !cpu->cfg.ext_zicsr) { |
| 716 | error_setg(errp, "Zcmt extension requires Zicsr extension"); |
| 717 | return; |
| 718 | } |
| 719 | |
| 720 | if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkg || |
| 721 | cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed || |
| 722 | cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32x) { |
| 723 | error_setg(errp, |
| 724 | "Vector crypto extensions require V or Zve* extensions"); |
| 725 | return; |
| 726 | } |
| 727 | |
| 728 | if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64x) { |
| 729 | error_setg( |
| 730 | errp, |
| 731 | "Zvbc and Zvknhb extensions require V or Zve64x extensions"); |
| 732 | return; |
| 733 | } |
| 734 | |
| 735 | if (cpu->cfg.ext_zicntr && !cpu->cfg.ext_zicsr) { |
| 736 | if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zicntr))) { |
| 737 | error_setg(errp, "zicntr requires zicsr"); |
| 738 | return; |
| 739 | } |
| 740 | cpu->cfg.ext_zicntr = false; |
| 741 | } |
| 742 | |
| 743 | if (cpu->cfg.ext_zihpm && !cpu->cfg.ext_zicsr) { |
| 744 | if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zihpm))) { |
| 745 | error_setg(errp, "zihpm requires zicsr"); |
| 746 | return; |
| 747 | } |
| 748 | cpu->cfg.ext_zihpm = false; |
| 749 | } |
| 750 | |
| 751 | if (cpu->cfg.ext_zicfiss) { |
| 752 | if (!cpu->cfg.ext_zicsr) { |
| 753 | error_setg(errp, "zicfiss extension requires zicsr extension"); |
| 754 | return; |
| 755 | } |
| 756 | if (!riscv_has_ext(env, RVA)) { |
| 757 | error_setg(errp, "zicfiss extension requires A extension"); |
| 758 | return; |
| 759 | } |
| 760 | if (!riscv_has_ext(env, RVS)) { |
| 761 | error_setg(errp, "zicfiss extension requires S"); |
| 762 | return; |
| 763 | } |
| 764 | if (!cpu->cfg.ext_zimop) { |
| 765 | error_setg(errp, "zicfiss extension requires zimop extension"); |
| 766 | return; |
| 767 | } |
| 768 | if (cpu->cfg.ext_zca && !cpu->cfg.ext_zcmop) { |
| 769 | error_setg(errp, "zicfiss with zca requires zcmop extension"); |
| 770 | return; |
| 771 | } |
| 772 | } |
| 773 | |
| 774 | if (!cpu->cfg.ext_zihpm) { |
| 775 | cpu->cfg.pmu_mask = 0; |
| 776 | cpu->pmu_avail_ctrs = 0; |
| 777 | } |
| 778 | |
| 779 | if (cpu->cfg.ext_zclsd) { |
| 780 | if (riscv_has_ext(env, RVC) && riscv_has_ext(env, RVF)) { |
| 781 | error_setg(errp, |
| 782 | "Zclsd cannot be supported together with C and F extension"); |
| 783 | return; |
| 784 | } |
| 785 | if (cpu->cfg.ext_zcf) { |
| 786 | error_setg(errp, |
| 787 | "Zclsd cannot be supported together with Zcf extension"); |
| 788 | return; |
| 789 | } |
| 790 | } |
| 791 | |
| 792 | if (cpu->cfg.ext_zicfilp && !cpu->cfg.ext_zicsr) { |
| 793 | error_setg(errp, "zicfilp extension requires zicsr extension"); |
| 794 | return; |
| 795 | } |
| 796 | |
| 797 | if (mcc->def->misa_mxl_max == MXL_RV32 && cpu->cfg.ext_svukte) { |
| 798 | error_setg(errp, "svukte is not supported for RV32"); |
| 799 | return; |
| 800 | } |
| 801 | |
| 802 | if ((cpu->cfg.ext_smctr || cpu->cfg.ext_ssctr) && |
| 803 | (!riscv_has_ext(env, RVS) || !cpu->cfg.ext_sscsrind)) { |
| 804 | if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_smctr)) || |
| 805 | cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_ssctr))) { |
| 806 | error_setg(errp, "Smctr and Ssctr require S-mode and Sscsrind"); |
| 807 | return; |
| 808 | } |
| 809 | cpu->cfg.ext_smctr = false; |
| 810 | cpu->cfg.ext_ssctr = false; |
| 811 | } |
| 812 | |
| 813 | if (cpu->cfg.ext_svrsw60t59b && |
| 814 | (!cpu->cfg.mmu || mcc->def->misa_mxl_max == MXL_RV32)) { |
| 815 | error_setg(errp, "svrsw60t59b is not supported on RV32 and MMU-less platforms"); |
| 816 | return; |
| 817 | } |
| 818 | |
| 819 | #ifndef CONFIG_USER_ONLY |
| 820 | if (cpu->cfg.ext_svpbmt && cpu->cfg.max_satp_mode < VM_1_10_SV39) { |
| 821 | cpu->cfg.ext_svpbmt = false; |
| 822 | if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_svpbmt))) { |
| 823 | warn_report("svpbmt requires at least satp sv39, " |
| 824 | "current satp mode: %s", |
| 825 | satp_mode_str(cpu->cfg.max_satp_mode, |
| 826 | riscv_cpu_is_32bit(cpu))); |
| 827 | } |
| 828 | } |
| 829 | |
| 830 | if (cpu->cfg.ext_svnapot && cpu->cfg.max_satp_mode < VM_1_10_SV39) { |
| 831 | cpu->cfg.ext_svnapot = false; |
| 832 | if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_svnapot))) { |
| 833 | warn_report("svnapot requires at least satp sv39, " |
| 834 | "current satp mode: %s", |
| 835 | satp_mode_str(cpu->cfg.max_satp_mode, |
| 836 | riscv_cpu_is_32bit(cpu))); |
| 837 | } |
| 838 | } |
| 839 | #endif |
| 840 | /* |
| 841 | * Disable isa extensions based on priv spec after we |
| 842 | * validated and set everything we need. |
| 843 | */ |
| 844 | riscv_cpu_disable_priv_spec_isa_exts(cpu); |
| 845 | } |
| 846 | |
| 847 | #ifndef CONFIG_USER_ONLY |
| 848 | static bool riscv_cpu_validate_profile_satp(RISCVCPU *cpu, |
| 849 | RISCVCPUProfile *profile, |
| 850 | bool send_warn) |
| 851 | { |
| 852 | int satp_max = cpu->cfg.max_satp_mode; |
| 853 | |
| 854 | assert(satp_max >= 0); |
| 855 | if (profile->satp_mode > satp_max) { |
| 856 | if (send_warn) { |
| 857 | bool is_32bit = riscv_cpu_is_32bit(cpu); |
| 858 | const char *req_satp = satp_mode_str(profile->satp_mode, is_32bit); |
| 859 | const char *cur_satp = satp_mode_str(satp_max, is_32bit); |
| 860 | |
| 861 | warn_report("Profile %s requires satp mode %s, " |
| 862 | "but satp mode %s was set", profile->name, |
| 863 | req_satp, cur_satp); |
| 864 | } |
| 865 | |
| 866 | return false; |
| 867 | } |
| 868 | |
| 869 | return true; |
| 870 | } |
| 871 | #endif |
| 872 | |
| 873 | static void riscv_cpu_check_parent_profile(RISCVCPU *cpu, |
| 874 | RISCVCPUProfile *profile, |
| 875 | RISCVCPUProfile *parent) |
| 876 | { |
| 877 | if (!profile->present || !parent) { |
| 878 | return; |
| 879 | } |
| 880 | |
| 881 | profile->present = parent->present; |
| 882 | } |
| 883 | |
| 884 | static void riscv_cpu_validate_profile(RISCVCPU *cpu, |
| 885 | RISCVCPUProfile *profile) |
| 886 | { |
| 887 | CPURISCVState *env = &cpu->env; |
| 888 | const char *warn_msg = "Profile %s mandates disabled extension %s"; |
| 889 | bool send_warn = profile->user_set && profile->enabled; |
| 890 | bool profile_impl = true; |
| 891 | int i; |
| 892 | |
| 893 | #ifndef CONFIG_USER_ONLY |
| 894 | if (profile->satp_mode != RISCV_PROFILE_ATTR_UNUSED) { |
| 895 | profile_impl = riscv_cpu_validate_profile_satp(cpu, profile, |
| 896 | send_warn); |
| 897 | } |
| 898 | #endif |
| 899 | |
| 900 | if (profile->priv_spec != RISCV_PROFILE_ATTR_UNUSED && |
| 901 | profile->priv_spec > env->priv_ver) { |
| 902 | profile_impl = false; |
| 903 | |
| 904 | if (send_warn) { |
| 905 | warn_report("Profile %s requires priv spec %s, " |
| 906 | "but priv ver %s was set", profile->name, |
| 907 | cpu_priv_ver_to_str(profile->priv_spec), |
| 908 | cpu_priv_ver_to_str(env->priv_ver)); |
| 909 | } |
| 910 | } |
| 911 | |
| 912 | for (i = 0; misa_bits[i] != 0; i++) { |
| 913 | uint32_t bit = misa_bits[i]; |
| 914 | |
| 915 | if (!(profile->misa_ext & bit)) { |
| 916 | continue; |
| 917 | } |
| 918 | |
| 919 | if (!riscv_has_ext(&cpu->env, bit)) { |
| 920 | profile_impl = false; |
| 921 | |
| 922 | if (send_warn) { |
| 923 | warn_report(warn_msg, profile->name, |
| 924 | riscv_get_misa_ext_name(bit)); |
| 925 | } |
| 926 | } |
| 927 | } |
| 928 | |
| 929 | for (i = 0; profile->ext_offsets[i] != RISCV_PROFILE_EXT_LIST_END; i++) { |
| 930 | int ext_offset = profile->ext_offsets[i]; |
| 931 | |
| 932 | if (!isa_ext_is_enabled(cpu, ext_offset)) { |
| 933 | profile_impl = false; |
| 934 | |
| 935 | if (send_warn) { |
| 936 | warn_report(warn_msg, profile->name, |
| 937 | cpu_cfg_ext_get_name(ext_offset)); |
| 938 | } |
| 939 | } |
| 940 | } |
| 941 | |
| 942 | profile->present = profile_impl; |
| 943 | |
| 944 | riscv_cpu_check_parent_profile(cpu, profile, profile->u_parent); |
| 945 | riscv_cpu_check_parent_profile(cpu, profile, profile->s_parent); |
| 946 | } |
| 947 | |
| 948 | static void riscv_cpu_validate_profiles(RISCVCPU *cpu) |
| 949 | { |
| 950 | for (int i = 0; riscv_profiles[i] != NULL; i++) { |
| 951 | riscv_cpu_validate_profile(cpu, riscv_profiles[i]); |
| 952 | } |
| 953 | } |
| 954 | |
| 955 | static void riscv_cpu_init_implied_exts_rules(void) |
| 956 | { |
| 957 | RISCVCPUImpliedExtsRule *rule; |
| 958 | #ifndef CONFIG_USER_ONLY |
| 959 | MachineState *ms = MACHINE(qdev_get_machine()); |
| 960 | #endif |
| 961 | static bool initialized; |
| 962 | int i; |
| 963 | |
| 964 | /* Implied rules only need to be initialized once. */ |
| 965 | if (initialized) { |
| 966 | return; |
| 967 | } |
| 968 | |
| 969 | for (i = 0; (rule = riscv_misa_ext_implied_rules[i]); i++) { |
| 970 | #ifndef CONFIG_USER_ONLY |
| 971 | rule->enabled = bitmap_new(ms->smp.cpus); |
| 972 | #endif |
| 973 | g_hash_table_insert(misa_ext_implied_rules, |
| 974 | GUINT_TO_POINTER(rule->ext), (gpointer)rule); |
| 975 | } |
| 976 | |
| 977 | for (i = 0; (rule = riscv_multi_ext_implied_rules[i]); i++) { |
| 978 | #ifndef CONFIG_USER_ONLY |
| 979 | rule->enabled = bitmap_new(ms->smp.cpus); |
| 980 | #endif |
| 981 | g_hash_table_insert(multi_ext_implied_rules, |
| 982 | GUINT_TO_POINTER(rule->ext), (gpointer)rule); |
| 983 | } |
| 984 | |
| 985 | initialized = true; |
| 986 | } |
| 987 | |
| 988 | static void cpu_enable_implied_rule(RISCVCPU *cpu, |
| 989 | RISCVCPUImpliedExtsRule *rule) |
| 990 | { |
| 991 | CPURISCVState *env = &cpu->env; |
| 992 | RISCVCPUImpliedExtsRule *ir; |
| 993 | bool enabled = false; |
| 994 | int i; |
| 995 | |
| 996 | #ifndef CONFIG_USER_ONLY |
| 997 | enabled = test_bit(cpu->env.mhartid, rule->enabled); |
| 998 | #endif |
| 999 | |
| 1000 | if (!enabled) { |
| 1001 | /* Enable the implied MISAs. */ |
| 1002 | if (rule->implied_misa_exts) { |
| 1003 | for (i = 0; misa_bits[i] != 0; i++) { |
| 1004 | if (rule->implied_misa_exts & misa_bits[i]) { |
| 1005 | /* |
| 1006 | * If the user disabled the misa_bit do not re-enable it |
| 1007 | * and do not apply any implied rules related to it. |
| 1008 | */ |
| 1009 | if (cpu_misa_ext_is_user_set(misa_bits[i]) && |
| 1010 | !(env->misa_ext & misa_bits[i])) { |
| 1011 | continue; |
| 1012 | } |
| 1013 | |
| 1014 | riscv_cpu_set_misa_ext(env, env->misa_ext | misa_bits[i]); |
| 1015 | ir = g_hash_table_lookup(misa_ext_implied_rules, |
| 1016 | GUINT_TO_POINTER(misa_bits[i])); |
| 1017 | |
| 1018 | if (ir) { |
| 1019 | cpu_enable_implied_rule(cpu, ir); |
| 1020 | } |
| 1021 | } |
| 1022 | } |
| 1023 | } |
| 1024 | |
| 1025 | /* Enable the implied extensions. */ |
| 1026 | for (i = 0; |
| 1027 | rule->implied_multi_exts[i] != RISCV_IMPLIED_EXTS_RULE_END; i++) { |
| 1028 | cpu_cfg_ext_auto_update(cpu, rule->implied_multi_exts[i], true); |
| 1029 | |
| 1030 | ir = g_hash_table_lookup(multi_ext_implied_rules, |
| 1031 | GUINT_TO_POINTER( |
| 1032 | rule->implied_multi_exts[i])); |
| 1033 | |
| 1034 | if (ir) { |
| 1035 | cpu_enable_implied_rule(cpu, ir); |
| 1036 | } |
| 1037 | } |
| 1038 | |
| 1039 | #ifndef CONFIG_USER_ONLY |
| 1040 | bitmap_set(rule->enabled, cpu->env.mhartid, 1); |
| 1041 | #endif |
| 1042 | } |
| 1043 | } |
| 1044 | |
| 1045 | /* Zc extension has special implied rules that need to be handled separately. */ |
| 1046 | static void cpu_enable_zc_implied_rules(RISCVCPU *cpu) |
| 1047 | { |
| 1048 | RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); |
| 1049 | CPURISCVState *env = &cpu->env; |
| 1050 | |
| 1051 | if (cpu->cfg.ext_zce) { |
| 1052 | cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); |
| 1053 | cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcb), true); |
| 1054 | cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmp), true); |
| 1055 | cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmt), true); |
| 1056 | |
| 1057 | if (riscv_has_ext(env, RVF) && mcc->def->misa_mxl_max == MXL_RV32) { |
| 1058 | cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); |
| 1059 | } |
| 1060 | } |
| 1061 | |
| 1062 | /* Zca, Zcd and Zcf has a PRIV 1.12.0 restriction */ |
| 1063 | if (riscv_has_ext(env, RVC) && env->priv_ver >= PRIV_VERSION_1_12_0) { |
| 1064 | cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); |
| 1065 | |
| 1066 | if (riscv_has_ext(env, RVF) && mcc->def->misa_mxl_max == MXL_RV32) { |
| 1067 | cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); |
| 1068 | } |
| 1069 | |
| 1070 | if (riscv_has_ext(env, RVD)) { |
| 1071 | cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcd), true); |
| 1072 | } |
| 1073 | } |
| 1074 | } |
| 1075 | |
| 1076 | static void cpu_enable_zilsd_implied_rules(RISCVCPU *cpu) |
| 1077 | { |
| 1078 | CPURISCVState *env = &cpu->env; |
| 1079 | |
| 1080 | if (cpu->cfg.ext_zilsd && riscv_has_ext(env, RVC)) { |
| 1081 | cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zclsd), true); |
| 1082 | } |
| 1083 | |
| 1084 | if (cpu->cfg.ext_zclsd) { |
| 1085 | cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); |
| 1086 | cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zilsd), true); |
| 1087 | } |
| 1088 | } |
| 1089 | |
| 1090 | static void riscv_cpu_enable_implied_rules(RISCVCPU *cpu) |
| 1091 | { |
| 1092 | RISCVCPUImpliedExtsRule *rule; |
| 1093 | int i; |
| 1094 | |
| 1095 | /* Enable the implied extensions for Zc. */ |
| 1096 | cpu_enable_zc_implied_rules(cpu); |
| 1097 | |
| 1098 | /* Enable the implied extensions for Zilsd. */ |
| 1099 | cpu_enable_zilsd_implied_rules(cpu); |
| 1100 | |
| 1101 | /* Enable the implied MISAs. */ |
| 1102 | for (i = 0; (rule = riscv_misa_ext_implied_rules[i]); i++) { |
| 1103 | if (riscv_has_ext(&cpu->env, rule->ext)) { |
| 1104 | cpu_enable_implied_rule(cpu, rule); |
| 1105 | } |
| 1106 | } |
| 1107 | |
| 1108 | /* Enable the implied extensions. */ |
| 1109 | for (i = 0; (rule = riscv_multi_ext_implied_rules[i]); i++) { |
| 1110 | if (isa_ext_is_enabled(cpu, rule->ext)) { |
| 1111 | cpu_enable_implied_rule(cpu, rule); |
| 1112 | } |
| 1113 | } |
| 1114 | } |
| 1115 | |
| 1116 | /* |
| 1117 | * MISA.C is set if the following extensions are selected: |
| 1118 | * - Zca and not F. |
| 1119 | * - Zca, Zcf and F (but not D) is specified on RV32. |
| 1120 | * - Zca, Zcf and Zcd if D is specified on RV32. |
| 1121 | * - Zca, Zcd if D is specified on RV64. |
| 1122 | */ |
| 1123 | static void riscv_cpu_update_misa_c(RISCVCPU *cpu) |
| 1124 | { |
| 1125 | CPURISCVState *env = &cpu->env; |
| 1126 | bool set_misa_c = false; |
| 1127 | |
| 1128 | if (riscv_has_ext(env, RVC)) { |
| 1129 | return; |
| 1130 | } |
| 1131 | |
| 1132 | if (cpu->cfg.ext_zca && !riscv_has_ext(env, RVF)) { |
| 1133 | set_misa_c = true; |
| 1134 | } else if (riscv_cpu_mxl(env) == MXL_RV32 && |
| 1135 | cpu->cfg.ext_zca && cpu->cfg.ext_zcf && |
| 1136 | (riscv_has_ext(env, RVD) ? cpu->cfg.ext_zcd : |
| 1137 | riscv_has_ext(env, RVF))) { |
| 1138 | set_misa_c = true; |
| 1139 | } else if (riscv_cpu_mxl(env) == MXL_RV64 && |
| 1140 | cpu->cfg.ext_zca && cpu->cfg.ext_zcd) { |
| 1141 | set_misa_c = true; |
| 1142 | } |
| 1143 | |
| 1144 | if (set_misa_c) { |
| 1145 | if (cpu_misa_ext_is_user_set(RVC)) { |
| 1146 | warn_report("RVC mandated by Zca/Zcf/Zcd extensions"); |
| 1147 | return; |
| 1148 | } |
| 1149 | |
| 1150 | riscv_cpu_set_misa_ext(env, env->misa_ext | RVC); |
| 1151 | } |
| 1152 | } |
| 1153 | |
| 1154 | /* MISA.X is set when any of the non-standard extensions is enabled. */ |
| 1155 | static void riscv_cpu_update_misa_x(RISCVCPU *cpu) |
| 1156 | { |
| 1157 | CPURISCVState *env = &cpu->env; |
| 1158 | const RISCVIsaExtData *edata; |
| 1159 | |
| 1160 | for (edata = isa_edata_arr; edata && edata->name; edata++) { |
| 1161 | if (edata->name[0] == 'x' |
| 1162 | && isa_ext_is_enabled(cpu, edata->ext_enable_offset)) { |
| 1163 | riscv_cpu_set_misa_ext(env, env->misa_ext | RVX); |
| 1164 | break; |
| 1165 | } |
| 1166 | } |
| 1167 | } |
| 1168 | |
| 1169 | void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp) |
| 1170 | { |
| 1171 | CPURISCVState *env = &cpu->env; |
| 1172 | Error *local_err = NULL; |
| 1173 | |
| 1174 | riscv_cpu_init_implied_exts_rules(); |
| 1175 | riscv_cpu_enable_implied_rules(cpu); |
| 1176 | riscv_cpu_update_misa_c(cpu); |
| 1177 | riscv_cpu_update_misa_x(cpu); |
| 1178 | |
| 1179 | riscv_cpu_validate_misa_priv(env, &local_err); |
| 1180 | if (local_err != NULL) { |
| 1181 | error_propagate(errp, local_err); |
| 1182 | return; |
| 1183 | } |
| 1184 | |
| 1185 | riscv_cpu_update_cfg(cpu); |
| 1186 | riscv_cpu_validate_profiles(cpu); |
| 1187 | |
| 1188 | if (cpu->cfg.ext_smepmp && !cpu->cfg.pmp) { |
| 1189 | /* |
| 1190 | * Enhanced PMP should only be available |
| 1191 | * on harts with PMP support |
| 1192 | */ |
| 1193 | error_setg(errp, "Invalid configuration: Smepmp requires PMP support"); |
| 1194 | return; |
| 1195 | } |
| 1196 | |
| 1197 | riscv_cpu_validate_set_extensions(cpu, &local_err); |
| 1198 | if (local_err != NULL) { |
| 1199 | error_propagate(errp, local_err); |
| 1200 | return; |
| 1201 | } |
| 1202 | #ifndef CONFIG_USER_ONLY |
| 1203 | if (cpu->cfg.pmu_mask) { |
| 1204 | riscv_pmu_init(cpu, &local_err); |
| 1205 | if (local_err != NULL) { |
| 1206 | error_propagate(errp, local_err); |
| 1207 | return; |
| 1208 | } |
| 1209 | |
| 1210 | if (cpu->cfg.ext_sscofpmf) { |
| 1211 | cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, |
| 1212 | riscv_pmu_timer_cb, cpu); |
| 1213 | } |
| 1214 | } |
| 1215 | #endif |
| 1216 | } |
| 1217 | |
| 1218 | void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu) |
| 1219 | { |
| 1220 | GPtrArray *dynamic_decoders; |
| 1221 | dynamic_decoders = g_ptr_array_sized_new(decoder_table_size); |
| 1222 | for (size_t i = 0; i < decoder_table_size; ++i) { |
| 1223 | if (decoder_table[i].guard_func && |
| 1224 | decoder_table[i].guard_func(&cpu->cfg)) { |
| 1225 | g_ptr_array_add(dynamic_decoders, |
| 1226 | (gpointer)decoder_table[i].riscv_cpu_decode_fn); |
| 1227 | } |
| 1228 | } |
| 1229 | |
| 1230 | cpu->decoders = dynamic_decoders; |
| 1231 | } |
| 1232 | |
| 1233 | bool riscv_cpu_tcg_compatible(RISCVCPU *cpu) |
| 1234 | { |
| 1235 | return object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST) == NULL; |
| 1236 | } |
| 1237 | |
| 1238 | static bool riscv_cpu_is_generic(Object *cpu_obj) |
| 1239 | { |
| 1240 | return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL; |
| 1241 | } |
| 1242 | |
| 1243 | static void riscv_cpu_set_profile(RISCVCPU *cpu, |
| 1244 | RISCVCPUProfile *profile, |
| 1245 | bool enabled) |
| 1246 | { |
| 1247 | int i, ext_offset; |
| 1248 | |
| 1249 | if (profile->u_parent != NULL) { |
| 1250 | riscv_cpu_set_profile(cpu, profile->u_parent, enabled); |
| 1251 | } |
| 1252 | |
| 1253 | if (profile->s_parent != NULL) { |
| 1254 | riscv_cpu_set_profile(cpu, profile->s_parent, enabled); |
| 1255 | } |
| 1256 | |
| 1257 | profile->enabled = enabled; |
| 1258 | |
| 1259 | if (profile->enabled) { |
| 1260 | cpu->env.priv_ver = profile->priv_spec; |
| 1261 | |
| 1262 | #ifndef CONFIG_USER_ONLY |
| 1263 | if (profile->satp_mode != RISCV_PROFILE_ATTR_UNUSED) { |
| 1264 | object_property_set_bool(OBJECT(cpu), "mmu", true, NULL); |
| 1265 | const char *satp_prop = satp_mode_str(profile->satp_mode, |
| 1266 | riscv_cpu_is_32bit(cpu)); |
| 1267 | object_property_set_bool(OBJECT(cpu), satp_prop, true, NULL); |
| 1268 | } |
| 1269 | #endif |
| 1270 | } |
| 1271 | |
| 1272 | for (i = 0; misa_bits[i] != 0; i++) { |
| 1273 | uint32_t bit = misa_bits[i]; |
| 1274 | |
| 1275 | if (!(profile->misa_ext & bit)) { |
| 1276 | continue; |
| 1277 | } |
| 1278 | |
| 1279 | if (bit == RVI && !profile->enabled) { |
| 1280 | /* |
| 1281 | * Disabling profiles will not disable the base |
| 1282 | * ISA RV64I. |
| 1283 | */ |
| 1284 | continue; |
| 1285 | } |
| 1286 | |
| 1287 | cpu_misa_ext_add_user_opt(bit, profile->enabled); |
| 1288 | riscv_cpu_write_misa_bit(cpu, bit, profile->enabled); |
| 1289 | } |
| 1290 | |
| 1291 | for (i = 0; profile->ext_offsets[i] != RISCV_PROFILE_EXT_LIST_END; i++) { |
| 1292 | ext_offset = profile->ext_offsets[i]; |
| 1293 | |
| 1294 | if (profile->enabled) { |
| 1295 | cpu_bump_multi_ext_priv_ver(&cpu->env, ext_offset); |
| 1296 | } |
| 1297 | |
| 1298 | cpu_cfg_ext_add_user_opt(ext_offset, profile->enabled); |
| 1299 | isa_ext_update_enabled(cpu, ext_offset, profile->enabled); |
| 1300 | } |
| 1301 | } |
| 1302 | |
| 1303 | /* |
| 1304 | * We'll get here via the following path: |
| 1305 | * |
| 1306 | * riscv_cpu_realize() |
| 1307 | * -> cpu_common_realize() |
| 1308 | * -> tcg_cpu_realize() (via accel_cpu_common_realize()) |
| 1309 | */ |
| 1310 | static bool riscv_tcg_cpu_realize(CPUState *cs, Error **errp) |
| 1311 | { |
| 1312 | RISCVCPU *cpu = RISCV_CPU(cs); |
| 1313 | |
| 1314 | if (!riscv_cpu_tcg_compatible(cpu)) { |
| 1315 | g_autofree char *name = riscv_cpu_get_name(cpu); |
| 1316 | error_setg(errp, "'%s' CPU is not compatible with TCG acceleration", |
| 1317 | name); |
| 1318 | return false; |
| 1319 | } |
| 1320 | |
| 1321 | #ifndef CONFIG_USER_ONLY |
| 1322 | CPURISCVState *env = &cpu->env; |
| 1323 | |
| 1324 | tcg_cflags_set(CPU(cs), CF_PCREL); |
| 1325 | |
| 1326 | if (cpu->cfg.ext_sstc) { |
| 1327 | riscv_timer_init(cpu); |
| 1328 | } |
| 1329 | |
| 1330 | /* With H-Ext, VSSIP, VSTIP, VSEIP and SGEIP are hardwired to one. */ |
| 1331 | if (riscv_has_ext(env, RVH)) { |
| 1332 | env->mideleg = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP | MIP_SGEIP; |
| 1333 | } |
| 1334 | #endif |
| 1335 | |
| 1336 | return true; |
| 1337 | } |
| 1338 | |
| 1339 | typedef struct RISCVCPUMisaExtConfig { |
| 1340 | target_ulong misa_bit; |
| 1341 | bool enabled; |
| 1342 | } RISCVCPUMisaExtConfig; |
| 1343 | |
| 1344 | static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name, |
| 1345 | void *opaque, Error **errp) |
| 1346 | { |
| 1347 | const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque; |
| 1348 | target_ulong misa_bit = misa_ext_cfg->misa_bit; |
| 1349 | RISCVCPU *cpu = RISCV_CPU(obj); |
| 1350 | CPURISCVState *env = &cpu->env; |
| 1351 | bool vendor_cpu = riscv_cpu_is_vendor(obj); |
| 1352 | bool prev_val, value; |
| 1353 | |
| 1354 | if (!visit_type_bool(v, name, &value, errp)) { |
| 1355 | return; |
| 1356 | } |
| 1357 | |
| 1358 | cpu_misa_ext_add_user_opt(misa_bit, value); |
| 1359 | |
| 1360 | prev_val = env->misa_ext & misa_bit; |
| 1361 | |
| 1362 | if (value == prev_val) { |
| 1363 | return; |
| 1364 | } |
| 1365 | |
| 1366 | if (value) { |
| 1367 | if (vendor_cpu) { |
| 1368 | g_autofree char *cpuname = riscv_cpu_get_name(cpu); |
| 1369 | error_setg(errp, "'%s' CPU does not allow enabling extensions", |
| 1370 | cpuname); |
| 1371 | return; |
| 1372 | } |
| 1373 | |
| 1374 | if (misa_bit == RVH && env->priv_ver < PRIV_VERSION_1_12_0) { |
| 1375 | /* |
| 1376 | * Note: the 'priv_spec' command line option, if present, |
| 1377 | * will take precedence over this priv_ver bump. |
| 1378 | */ |
| 1379 | env->priv_ver = PRIV_VERSION_1_12_0; |
| 1380 | } |
| 1381 | } |
| 1382 | |
| 1383 | riscv_cpu_write_misa_bit(cpu, misa_bit, value); |
| 1384 | } |
| 1385 | |
| 1386 | static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name, |
| 1387 | void *opaque, Error **errp) |
| 1388 | { |
| 1389 | const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque; |
| 1390 | target_ulong misa_bit = misa_ext_cfg->misa_bit; |
| 1391 | RISCVCPU *cpu = RISCV_CPU(obj); |
| 1392 | CPURISCVState *env = &cpu->env; |
| 1393 | bool value; |
| 1394 | |
| 1395 | value = env->misa_ext & misa_bit; |
| 1396 | |
| 1397 | visit_type_bool(v, name, &value, errp); |
| 1398 | } |
| 1399 | |
| 1400 | #define MISA_CFG(_bit, _enabled) \ |
| 1401 | {.misa_bit = _bit, .enabled = _enabled} |
| 1402 | |
| 1403 | static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = { |
| 1404 | MISA_CFG(RVA, true), |
| 1405 | MISA_CFG(RVC, true), |
| 1406 | MISA_CFG(RVD, true), |
| 1407 | MISA_CFG(RVF, true), |
| 1408 | MISA_CFG(RVI, true), |
| 1409 | MISA_CFG(RVE, false), |
| 1410 | MISA_CFG(RVM, true), |
| 1411 | MISA_CFG(RVS, true), |
| 1412 | MISA_CFG(RVU, true), |
| 1413 | MISA_CFG(RVH, true), |
| 1414 | MISA_CFG(RVV, false), |
| 1415 | MISA_CFG(RVG, false), |
| 1416 | MISA_CFG(RVB, false), |
| 1417 | }; |
| 1418 | |
| 1419 | /* |
| 1420 | * We do not support user choice tracking for MISA |
| 1421 | * extensions yet because, so far, we do not silently |
| 1422 | * change MISA bits during realize() (RVG enables MISA |
| 1423 | * bits but the user is warned about it). |
| 1424 | */ |
| 1425 | static void riscv_cpu_add_misa_properties(Object *cpu_obj) |
| 1426 | { |
| 1427 | bool use_def_vals = riscv_cpu_is_generic(cpu_obj); |
| 1428 | int i; |
| 1429 | |
| 1430 | for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) { |
| 1431 | const RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i]; |
| 1432 | int bit = misa_cfg->misa_bit; |
| 1433 | const char *name = riscv_get_misa_ext_name(bit); |
| 1434 | const char *desc = riscv_get_misa_ext_description(bit); |
| 1435 | |
| 1436 | /* Check if KVM already created the property */ |
| 1437 | if (object_property_find(cpu_obj, name)) { |
| 1438 | continue; |
| 1439 | } |
| 1440 | |
| 1441 | object_property_add(cpu_obj, name, "bool", |
| 1442 | cpu_get_misa_ext_cfg, |
| 1443 | cpu_set_misa_ext_cfg, |
| 1444 | NULL, (void *)misa_cfg); |
| 1445 | object_property_set_description(cpu_obj, name, desc); |
| 1446 | if (use_def_vals) { |
| 1447 | riscv_cpu_write_misa_bit(RISCV_CPU(cpu_obj), bit, |
| 1448 | misa_cfg->enabled); |
| 1449 | } |
| 1450 | } |
| 1451 | } |
| 1452 | |
| 1453 | static void cpu_set_profile(Object *obj, Visitor *v, const char *name, |
| 1454 | void *opaque, Error **errp) |
| 1455 | { |
| 1456 | RISCVCPUProfile *profile = opaque; |
| 1457 | RISCVCPU *cpu = RISCV_CPU(obj); |
| 1458 | bool value; |
| 1459 | |
| 1460 | if (riscv_cpu_is_vendor(obj)) { |
| 1461 | error_setg(errp, "Profile %s is not available for vendor CPUs", |
| 1462 | profile->name); |
| 1463 | return; |
| 1464 | } |
| 1465 | |
| 1466 | if (cpu->env.misa_mxl != MXL_RV64) { |
| 1467 | error_setg(errp, "Profile %s only available for 64 bit CPUs", |
| 1468 | profile->name); |
| 1469 | return; |
| 1470 | } |
| 1471 | |
| 1472 | if (!visit_type_bool(v, name, &value, errp)) { |
| 1473 | return; |
| 1474 | } |
| 1475 | |
| 1476 | profile->user_set = true; |
| 1477 | |
| 1478 | riscv_cpu_set_profile(cpu, profile, value); |
| 1479 | } |
| 1480 | |
| 1481 | static void cpu_get_profile(Object *obj, Visitor *v, const char *name, |
| 1482 | void *opaque, Error **errp) |
| 1483 | { |
| 1484 | RISCVCPUProfile *profile = opaque; |
| 1485 | bool value = profile->enabled; |
| 1486 | |
| 1487 | visit_type_bool(v, name, &value, errp); |
| 1488 | } |
| 1489 | |
| 1490 | static void riscv_cpu_add_profiles(Object *cpu_obj) |
| 1491 | { |
| 1492 | for (int i = 0; riscv_profiles[i] != NULL; i++) { |
| 1493 | RISCVCPUProfile *profile = riscv_profiles[i]; |
| 1494 | |
| 1495 | object_property_add(cpu_obj, profile->name, "bool", |
| 1496 | cpu_get_profile, cpu_set_profile, |
| 1497 | NULL, (void *)profile); |
| 1498 | |
| 1499 | /* |
| 1500 | * CPUs might enable a profile right from the start. |
| 1501 | * Enable its mandatory extensions right away in this |
| 1502 | * case. |
| 1503 | */ |
| 1504 | if (profile->enabled) { |
| 1505 | riscv_cpu_set_profile(RISCV_CPU(cpu_obj), profile, true); |
| 1506 | } |
| 1507 | } |
| 1508 | } |
| 1509 | |
| 1510 | static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name, |
| 1511 | void *opaque, Error **errp) |
| 1512 | { |
| 1513 | RISCVCPU *cpu = RISCV_CPU(obj); |
| 1514 | uint32_t cfg_offset = *(uint32_t *)opaque; |
| 1515 | bool vendor_cpu = riscv_cpu_is_vendor(obj); |
| 1516 | bool prev_val, value; |
| 1517 | |
| 1518 | if (!visit_type_bool(v, name, &value, errp)) { |
| 1519 | return; |
| 1520 | } |
| 1521 | |
| 1522 | cpu_cfg_ext_add_user_opt(cfg_offset, value); |
| 1523 | |
| 1524 | prev_val = isa_ext_is_enabled(cpu, cfg_offset); |
| 1525 | |
| 1526 | if (value == prev_val) { |
| 1527 | return; |
| 1528 | } |
| 1529 | |
| 1530 | if (value && vendor_cpu) { |
| 1531 | g_autofree char *cpuname = riscv_cpu_get_name(cpu); |
| 1532 | error_setg(errp, "'%s' CPU does not allow enabling extensions", |
| 1533 | cpuname); |
| 1534 | return; |
| 1535 | } |
| 1536 | |
| 1537 | if (value) { |
| 1538 | cpu_bump_multi_ext_priv_ver(&cpu->env, cfg_offset); |
| 1539 | } |
| 1540 | |
| 1541 | isa_ext_update_enabled(cpu, cfg_offset, value); |
| 1542 | } |
| 1543 | |
| 1544 | static void cpu_get_multi_ext_cfg(Object *obj, Visitor *v, const char *name, |
| 1545 | void *opaque, Error **errp) |
| 1546 | { |
| 1547 | uint32_t cfg_offset = *(uint32_t *)opaque; |
| 1548 | bool value = isa_ext_is_enabled(RISCV_CPU(obj), cfg_offset); |
| 1549 | |
| 1550 | visit_type_bool(v, name, &value, errp); |
| 1551 | } |
| 1552 | |
| 1553 | /* |
| 1554 | * Add CPU properties with user-facing flags. |
| 1555 | * |
| 1556 | * This will overwrite existing env->misa_ext values with the |
| 1557 | * defaults set via riscv_cpu_add_misa_properties(). |
| 1558 | */ |
| 1559 | static void riscv_cpu_add_user_properties(Object *obj) |
| 1560 | { |
| 1561 | const RISCVIsaExtData *edata; |
| 1562 | |
| 1563 | #ifndef CONFIG_USER_ONLY |
| 1564 | riscv_add_satp_mode_properties(obj); |
| 1565 | #endif |
| 1566 | |
| 1567 | riscv_cpu_add_misa_properties(obj); |
| 1568 | |
| 1569 | for (edata = isa_edata_arr; edata && edata->name; edata++) { |
| 1570 | if (edata->prop_name) { |
| 1571 | object_property_add(obj, edata->prop_name, "bool", |
| 1572 | cpu_get_multi_ext_cfg, |
| 1573 | cpu_set_multi_ext_cfg, |
| 1574 | NULL, (void *)&edata->ext_enable_offset); |
| 1575 | } |
| 1576 | } |
| 1577 | |
| 1578 | riscv_cpu_add_profiles(obj); |
| 1579 | } |
| 1580 | |
| 1581 | /* |
| 1582 | * The 'max' type CPU will have all possible ratified |
| 1583 | * non-vendor extensions enabled. |
| 1584 | */ |
| 1585 | static void riscv_init_max_cpu_extensions(Object *obj) |
| 1586 | { |
| 1587 | RISCVCPU *cpu = RISCV_CPU(obj); |
| 1588 | CPURISCVState *env = &cpu->env; |
| 1589 | const RISCVIsaExtData *edata; |
| 1590 | |
| 1591 | /* Enable RVG and RVV that are disabled by default */ |
| 1592 | riscv_cpu_set_misa_ext(env, env->misa_ext | RVB | RVG | RVV); |
| 1593 | |
| 1594 | for (edata = isa_edata_arr; edata && edata->name; edata++) { |
| 1595 | if (edata->name[0] == 'x' |
| 1596 | || (edata->prop_name && edata->prop_name[0] == 'x')) { |
| 1597 | continue; |
| 1598 | } |
| 1599 | |
| 1600 | isa_ext_update_enabled(cpu, edata->ext_enable_offset, true); |
| 1601 | } |
| 1602 | |
| 1603 | /* |
| 1604 | * Some extensions can't be added without backward compatibilty concerns. |
| 1605 | * Disable those, the user can still opt in to them on the command line. |
| 1606 | */ |
| 1607 | cpu->cfg.ext_svade = false; |
| 1608 | |
| 1609 | /* set vector version */ |
| 1610 | env->vext_ver = VEXT_VERSION_1_00_0; |
| 1611 | |
| 1612 | /* Zfinx is not compatible with F. Disable it */ |
| 1613 | isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zfinx), false); |
| 1614 | isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zdinx), false); |
| 1615 | isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinx), false); |
| 1616 | isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinxmin), false); |
| 1617 | |
| 1618 | isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zce), false); |
| 1619 | isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmp), false); |
| 1620 | isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmt), false); |
| 1621 | |
| 1622 | isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zilsd), false); |
| 1623 | isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zclsd), false); |
| 1624 | |
| 1625 | if (env->misa_mxl != MXL_RV32) { |
| 1626 | isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcf), false); |
| 1627 | } else { |
| 1628 | isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_svrsw60t59b), false); |
| 1629 | } |
| 1630 | |
| 1631 | /* |
| 1632 | * TODO: ext_smrnmi requires OpenSBI changes that our current |
| 1633 | * image does not have. Disable it for now. |
| 1634 | */ |
| 1635 | if (cpu->cfg.ext_smrnmi) { |
| 1636 | isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_smrnmi), false); |
| 1637 | } |
| 1638 | |
| 1639 | /* |
| 1640 | * TODO: ext_smdbltrp requires the firmware to clear MSTATUS.MDT on startup |
| 1641 | * to avoid generating a double trap. OpenSBI does not currently support it, |
| 1642 | * disable it for now. |
| 1643 | */ |
| 1644 | if (cpu->cfg.ext_smdbltrp) { |
| 1645 | isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_smdbltrp), false); |
| 1646 | } |
| 1647 | } |
| 1648 | |
| 1649 | static bool riscv_cpu_has_max_extensions(Object *cpu_obj) |
| 1650 | { |
| 1651 | return object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_MAX) != NULL; |
| 1652 | } |
| 1653 | |
| 1654 | #ifndef CONFIG_USER_ONLY |
| 1655 | static void riscv_register_custom_csrs(RISCVCPU *cpu, const RISCVCSR *csr_list) |
| 1656 | { |
| 1657 | for (size_t i = 0; csr_list[i].csr_ops.name; i++) { |
| 1658 | int csrno = csr_list[i].csrno; |
| 1659 | const riscv_csr_operations *csr_ops = &csr_list[i].csr_ops; |
| 1660 | if (!csr_list[i].insertion_test || csr_list[i].insertion_test(cpu)) { |
| 1661 | riscv_set_csr_ops(csrno, csr_ops); |
| 1662 | } |
| 1663 | } |
| 1664 | } |
| 1665 | |
| 1666 | static inline void riscv_cpu_set_nmi(void *opaque, int irq, int level) |
| 1667 | { |
| 1668 | riscv_cpu_set_rnmi(RISCV_CPU(opaque), irq, level); |
| 1669 | } |
| 1670 | #endif |
| 1671 | |
| 1672 | static void riscv_tcg_cpu_instance_init(CPUState *cs) |
| 1673 | { |
| 1674 | RISCVCPU *cpu = RISCV_CPU(cs); |
| 1675 | Object *obj = OBJECT(cpu); |
| 1676 | #ifndef CONFIG_USER_ONLY |
| 1677 | RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(obj); |
| 1678 | |
| 1679 | if (mcc->def->custom_csrs) { |
| 1680 | riscv_register_custom_csrs(cpu, mcc->def->custom_csrs); |
| 1681 | } |
| 1682 | qdev_init_gpio_in_named(DEVICE(cpu), riscv_cpu_set_nmi, |
| 1683 | "riscv.cpu.rnmi", RNMI_MAX); |
| 1684 | #endif |
| 1685 | |
| 1686 | misa_ext_user_opts = g_hash_table_new(NULL, g_direct_equal); |
| 1687 | multi_ext_user_opts = g_hash_table_new(NULL, g_direct_equal); |
| 1688 | |
| 1689 | if (!misa_ext_implied_rules) { |
| 1690 | misa_ext_implied_rules = g_hash_table_new(NULL, g_direct_equal); |
| 1691 | } |
| 1692 | |
| 1693 | if (!multi_ext_implied_rules) { |
| 1694 | multi_ext_implied_rules = g_hash_table_new(NULL, g_direct_equal); |
| 1695 | } |
| 1696 | |
| 1697 | riscv_cpu_add_user_properties(obj); |
| 1698 | |
| 1699 | if (riscv_cpu_has_max_extensions(obj)) { |
| 1700 | riscv_init_max_cpu_extensions(obj); |
| 1701 | } |
| 1702 | } |
| 1703 | |
| 1704 | static void riscv_tcg_cpu_accel_class_init(ObjectClass *oc, const void *data) |
| 1705 | { |
| 1706 | AccelCPUClass *acc = ACCEL_CPU_CLASS(oc); |
| 1707 | |
| 1708 | acc->cpu_instance_init = riscv_tcg_cpu_instance_init; |
| 1709 | acc->cpu_target_realize = riscv_tcg_cpu_realize; |
| 1710 | } |
| 1711 | |
| 1712 | static const TypeInfo riscv_tcg_cpu_accel_type_info = { |
| 1713 | .name = ACCEL_CPU_NAME("tcg"), |
| 1714 | |
| 1715 | .parent = TYPE_ACCEL_CPU, |
| 1716 | .class_init = riscv_tcg_cpu_accel_class_init, |
| 1717 | .abstract = true, |
| 1718 | }; |
| 1719 | |
| 1720 | static void riscv_tcg_cpu_accel_register_types(void) |
| 1721 | { |
| 1722 | type_register_static(&riscv_tcg_cpu_accel_type_info); |
| 1723 | } |
| 1724 | type_init(riscv_tcg_cpu_accel_register_types); |