| 1 | /* |
| 2 | * RISC-V Zcmt Extension Helper for QEMU. |
| 3 | * |
| 4 | * Copyright (c) 2021-2022 PLCT Lab |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify it |
| 7 | * under the terms and conditions of the GNU General Public License, |
| 8 | * version 2 or later, as published by the Free Software Foundation. |
| 9 | * |
| 10 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 13 | * more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License along with |
| 16 | * this program. If not, see <http://www.gnu.org/licenses/>. |
| 17 | */ |
| 18 | |
| 19 | #include "qemu/osdep.h" |
| 20 | #include "cpu.h" |
| 21 | #include "internals.h" |
| 22 | #include "exec/helper-proto.h" |
| 23 | #include "accel/tcg/cpu-ldst.h" |
| 24 | |
| 25 | target_ulong HELPER(cm_jalt)(CPURISCVState *env, uint32_t index) |
| 26 | { |
| 27 | unsigned mmu_index = cpu_mmu_index(env_cpu(env), true); |
| 28 | MemOp endian = mo_endian_env(env); |
| 29 | MemOpIdx oi; |
| 30 | |
| 31 | #if !defined(CONFIG_USER_ONLY) |
| 32 | RISCVException ret = smstateen_acc_ok(env, 0, SMSTATEEN0_JVT); |
| 33 | if (ret != RISCV_EXCP_NONE) { |
| 34 | riscv_raise_exception(env, ret, 0); |
| 35 | } |
| 36 | #endif |
| 37 | |
| 38 | target_ulong target; |
| 39 | target_ulong val = env->jvt; |
| 40 | int xlen = riscv_cpu_xlen(env); |
| 41 | uint8_t mode = get_field(val, JVT_MODE); |
| 42 | target_ulong base = val & JVT_BASE; |
| 43 | target_ulong t0; |
| 44 | |
| 45 | if (mode != 0) { |
| 46 | riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, 0); |
| 47 | } |
| 48 | |
| 49 | if (xlen == 32) { |
| 50 | oi = make_memop_idx(MO_UL | endian, mmu_index); |
| 51 | t0 = base + (index << 2); |
| 52 | target = cpu_ldl_code_mmu(env, t0, oi, 0); |
| 53 | } else { |
| 54 | oi = make_memop_idx(MO_UQ | endian, mmu_index); |
| 55 | t0 = base + (index << 3); |
| 56 | target = cpu_ldq_code_mmu(env, t0, oi, 0); |
| 57 | } |
| 58 | |
| 59 | return target & ~0x1; |
| 60 | } |