| 1 | /* |
| 2 | * QEMU RX CPU |
| 3 | * |
| 4 | * Copyright (c) 2019 Yoshinori Sato |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify it |
| 7 | * under the terms and conditions of the GNU General Public License, |
| 8 | * version 2 or later, as published by the Free Software Foundation. |
| 9 | * |
| 10 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 13 | * more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License along with |
| 16 | * this program. If not, see <http://www.gnu.org/licenses/>. |
| 17 | */ |
| 18 | |
| 19 | #include "qemu/osdep.h" |
| 20 | #include "qemu/qemu-print.h" |
| 21 | #include "qapi/error.h" |
| 22 | #include "cpu.h" |
| 23 | #include "migration/vmstate.h" |
| 24 | #include "exec/cputlb.h" |
| 25 | #include "exec/page-protection.h" |
| 26 | #include "exec/translation-block.h" |
| 27 | #include "exec/target_page.h" |
| 28 | #include "hw/core/loader.h" |
| 29 | #include "fpu/softfloat.h" |
| 30 | #include "tcg/debug-assert.h" |
| 31 | #include "accel/tcg/cpu-ops.h" |
| 32 | |
| 33 | static void rx_cpu_set_pc(CPUState *cs, vaddr value) |
| 34 | { |
| 35 | RXCPU *cpu = RX_CPU(cs); |
| 36 | |
| 37 | cpu->env.pc = value; |
| 38 | } |
| 39 | |
| 40 | static vaddr rx_cpu_get_pc(CPUState *cs) |
| 41 | { |
| 42 | RXCPU *cpu = RX_CPU(cs); |
| 43 | |
| 44 | return cpu->env.pc; |
| 45 | } |
| 46 | |
| 47 | static TCGTBCPUState rx_get_tb_cpu_state(CPUState *cs) |
| 48 | { |
| 49 | CPURXState *env = cpu_env(cs); |
| 50 | uint32_t flags = 0; |
| 51 | |
| 52 | flags = FIELD_DP32(flags, PSW, PM, env->psw_pm); |
| 53 | flags = FIELD_DP32(flags, PSW, U, env->psw_u); |
| 54 | |
| 55 | return (TCGTBCPUState){ .pc = env->pc, .flags = flags }; |
| 56 | } |
| 57 | |
| 58 | static void rx_cpu_synchronize_from_tb(CPUState *cs, |
| 59 | const TranslationBlock *tb) |
| 60 | { |
| 61 | RXCPU *cpu = RX_CPU(cs); |
| 62 | |
| 63 | tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL)); |
| 64 | cpu->env.pc = tb->pc; |
| 65 | } |
| 66 | |
| 67 | static void rx_restore_state_to_opc(CPUState *cs, |
| 68 | const TranslationBlock *tb, |
| 69 | const uint64_t *data) |
| 70 | { |
| 71 | RXCPU *cpu = RX_CPU(cs); |
| 72 | |
| 73 | cpu->env.pc = data[0]; |
| 74 | } |
| 75 | |
| 76 | static bool rx_cpu_has_work(CPUState *cs) |
| 77 | { |
| 78 | return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIR); |
| 79 | } |
| 80 | |
| 81 | static int rx_cpu_mmu_index(CPUState *cs, bool ifunc) |
| 82 | { |
| 83 | return 0; |
| 84 | } |
| 85 | |
| 86 | static void rx_cpu_reset_hold(Object *obj, ResetType type) |
| 87 | { |
| 88 | CPUState *cs = CPU(obj); |
| 89 | RXCPUClass *rcc = RX_CPU_GET_CLASS(obj); |
| 90 | CPURXState *env = cpu_env(cs); |
| 91 | uint32_t *resetvec; |
| 92 | |
| 93 | if (rcc->parent_phases.hold) { |
| 94 | rcc->parent_phases.hold(obj, type); |
| 95 | } |
| 96 | |
| 97 | memset(env, 0, offsetof(CPURXState, end_reset_fields)); |
| 98 | |
| 99 | resetvec = rom_ptr(0xfffffffc, 4); |
| 100 | if (resetvec) { |
| 101 | /* In the case of kernel, it is ignored because it is not set. */ |
| 102 | env->pc = ldl_le_p(resetvec); |
| 103 | } |
| 104 | rx_cpu_unpack_psw(env, 0, 1); |
| 105 | env->regs[0] = env->isp = env->usp = 0; |
| 106 | env->fpsw = 0; |
| 107 | set_flush_to_zero(1, &env->fp_status); |
| 108 | set_flush_inputs_to_zero(1, &env->fp_status); |
| 109 | /* |
| 110 | * TODO: this is not the correct NaN propagation rule for this |
| 111 | * architecture. The "RX Family User's Manual: Software" table 1.6 |
| 112 | * defines the propagation rules as "prefer SNaN over QNaN; |
| 113 | * then prefer dest over source", which is float_2nan_prop_s_ab. |
| 114 | */ |
| 115 | set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status); |
| 116 | /* Default NaN value: sign bit clear, set frac msb */ |
| 117 | set_float_default_nan_pattern(0b01000000, &env->fp_status); |
| 118 | /* |
| 119 | * TODO: "RX Family RXv1 Instruction Set Architecture" is not 100% clear |
| 120 | * on whether flush-to-zero should happen before or after rounding, but |
| 121 | * section 1.3.2 says that it happens when underflow is detected, and |
| 122 | * implies that underflow is detected after rounding. So this may not |
| 123 | * be the correct setting. |
| 124 | */ |
| 125 | set_float_ftz_detection(float_ftz_before_rounding, &env->fp_status); |
| 126 | } |
| 127 | |
| 128 | static ObjectClass *rx_cpu_class_by_name(const char *cpu_model) |
| 129 | { |
| 130 | ObjectClass *oc; |
| 131 | char *typename; |
| 132 | |
| 133 | oc = object_class_by_name(cpu_model); |
| 134 | if (oc != NULL && object_class_dynamic_cast(oc, TYPE_RX_CPU) != NULL) { |
| 135 | return oc; |
| 136 | } |
| 137 | typename = g_strdup_printf(RX_CPU_TYPE_NAME("%s"), cpu_model); |
| 138 | oc = object_class_by_name(typename); |
| 139 | g_free(typename); |
| 140 | |
| 141 | return oc; |
| 142 | } |
| 143 | |
| 144 | static void rx_cpu_realize(DeviceState *dev, Error **errp) |
| 145 | { |
| 146 | CPUState *cs = CPU(dev); |
| 147 | RXCPUClass *rcc = RX_CPU_GET_CLASS(dev); |
| 148 | Error *local_err = NULL; |
| 149 | |
| 150 | cpu_common_realize(cs, &local_err); |
| 151 | if (local_err != NULL) { |
| 152 | error_propagate(errp, local_err); |
| 153 | return; |
| 154 | } |
| 155 | |
| 156 | qemu_init_vcpu(cs); |
| 157 | cpu_reset(cs); |
| 158 | |
| 159 | rcc->parent_realize(dev, errp); |
| 160 | } |
| 161 | |
| 162 | static void rx_cpu_set_irq(void *opaque, int no, int request) |
| 163 | { |
| 164 | RXCPU *cpu = opaque; |
| 165 | CPUState *cs = CPU(cpu); |
| 166 | int irq = request & 0xff; |
| 167 | |
| 168 | static const int mask[] = { |
| 169 | [RX_CPU_IRQ] = CPU_INTERRUPT_HARD, |
| 170 | [RX_CPU_FIR] = CPU_INTERRUPT_FIR, |
| 171 | }; |
| 172 | if (irq) { |
| 173 | cpu->env.req_irq = irq; |
| 174 | cpu->env.req_ipl = (request >> 8) & 0x0f; |
| 175 | cpu_interrupt(cs, mask[no]); |
| 176 | } else { |
| 177 | cpu_reset_interrupt(cs, mask[no]); |
| 178 | } |
| 179 | } |
| 180 | |
| 181 | static void rx_cpu_disas_set_info(const CPUState *cpu, disassemble_info *info) |
| 182 | { |
| 183 | info->endian = BFD_ENDIAN_LITTLE; |
| 184 | info->mach = bfd_mach_rx; |
| 185 | info->print_insn = print_insn_rx; |
| 186 | } |
| 187 | |
| 188 | static bool rx_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, |
| 189 | MMUAccessType access_type, int mmu_idx, |
| 190 | bool probe, uintptr_t retaddr) |
| 191 | { |
| 192 | uint32_t address, physical, prot; |
| 193 | |
| 194 | /* Linear mapping */ |
| 195 | address = physical = addr & TARGET_PAGE_MASK; |
| 196 | prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
| 197 | tlb_set_page(cs, address, physical, prot, mmu_idx, TARGET_PAGE_SIZE); |
| 198 | return true; |
| 199 | } |
| 200 | |
| 201 | static void rx_cpu_init(Object *obj) |
| 202 | { |
| 203 | RXCPU *cpu = RX_CPU(obj); |
| 204 | |
| 205 | qdev_init_gpio_in(DEVICE(cpu), rx_cpu_set_irq, 2); |
| 206 | } |
| 207 | |
| 208 | #include "hw/core/sysemu-cpu-ops.h" |
| 209 | |
| 210 | static const struct SysemuCPUOps rx_sysemu_ops = { |
| 211 | .has_work = rx_cpu_has_work, |
| 212 | .get_phys_addr_debug = rx_cpu_get_phys_addr_debug, |
| 213 | }; |
| 214 | |
| 215 | static const TCGCPUOps rx_tcg_ops = { |
| 216 | /* MTTCG not yet supported: require strict ordering */ |
| 217 | .guest_default_memory_order = TCG_MO_ALL, |
| 218 | .mttcg_supported = false, |
| 219 | |
| 220 | .initialize = rx_translate_init, |
| 221 | .translate_code = rx_translate_code, |
| 222 | .get_tb_cpu_state = rx_get_tb_cpu_state, |
| 223 | .synchronize_from_tb = rx_cpu_synchronize_from_tb, |
| 224 | .restore_state_to_opc = rx_restore_state_to_opc, |
| 225 | .mmu_index = rx_cpu_mmu_index, |
| 226 | .tlb_fill = rx_cpu_tlb_fill, |
| 227 | .pointer_wrap = cpu_pointer_wrap_uint32, |
| 228 | |
| 229 | .cpu_exec_interrupt = rx_cpu_exec_interrupt, |
| 230 | .cpu_exec_halt = rx_cpu_has_work, |
| 231 | .cpu_exec_reset = cpu_reset, |
| 232 | .do_interrupt = rx_cpu_do_interrupt, |
| 233 | }; |
| 234 | |
| 235 | static void rx_cpu_class_init(ObjectClass *klass, const void *data) |
| 236 | { |
| 237 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 238 | CPUClass *cc = CPU_CLASS(klass); |
| 239 | RXCPUClass *rcc = RX_CPU_CLASS(klass); |
| 240 | ResettableClass *rc = RESETTABLE_CLASS(klass); |
| 241 | |
| 242 | device_class_set_parent_realize(dc, rx_cpu_realize, |
| 243 | &rcc->parent_realize); |
| 244 | resettable_class_set_parent_phases(rc, NULL, rx_cpu_reset_hold, NULL, |
| 245 | &rcc->parent_phases); |
| 246 | |
| 247 | cc->class_by_name = rx_cpu_class_by_name; |
| 248 | cc->dump_state = rx_cpu_dump_state; |
| 249 | cc->set_pc = rx_cpu_set_pc; |
| 250 | cc->get_pc = rx_cpu_get_pc; |
| 251 | |
| 252 | cc->sysemu_ops = &rx_sysemu_ops; |
| 253 | cc->gdb_read_register = rx_cpu_gdb_read_register; |
| 254 | cc->gdb_write_register = rx_cpu_gdb_write_register; |
| 255 | cc->disas_set_info = rx_cpu_disas_set_info; |
| 256 | |
| 257 | cc->gdb_core_xml_file = "rx-core.xml"; |
| 258 | cc->tcg_ops = &rx_tcg_ops; |
| 259 | } |
| 260 | |
| 261 | static const TypeInfo rx_cpu_info = { |
| 262 | .name = TYPE_RX_CPU, |
| 263 | .parent = TYPE_CPU, |
| 264 | .instance_size = sizeof(RXCPU), |
| 265 | .instance_align = __alignof(RXCPU), |
| 266 | .instance_init = rx_cpu_init, |
| 267 | .abstract = true, |
| 268 | .class_size = sizeof(RXCPUClass), |
| 269 | .class_init = rx_cpu_class_init, |
| 270 | }; |
| 271 | |
| 272 | static const TypeInfo rx62n_rx_cpu_info = { |
| 273 | .name = TYPE_RX62N_CPU, |
| 274 | .parent = TYPE_RX_CPU, |
| 275 | }; |
| 276 | |
| 277 | static void rx_cpu_register_types(void) |
| 278 | { |
| 279 | type_register_static(&rx_cpu_info); |
| 280 | type_register_static(&rx62n_rx_cpu_info); |
| 281 | } |
| 282 | |
| 283 | type_init(rx_cpu_register_types) |