| 1 | /* |
| 2 | * RX emulation definition |
| 3 | * |
| 4 | * Copyright (c) 2019 Yoshinori Sato |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify it |
| 7 | * under the terms and conditions of the GNU General Public License, |
| 8 | * version 2 or later, as published by the Free Software Foundation. |
| 9 | * |
| 10 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 13 | * more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License along with |
| 16 | * this program. If not, see <http://www.gnu.org/licenses/>. |
| 17 | */ |
| 18 | |
| 19 | #ifndef RX_CPU_H |
| 20 | #define RX_CPU_H |
| 21 | |
| 22 | #include "qemu/bitops.h" |
| 23 | #include "hw/core/registerfields.h" |
| 24 | #include "cpu-qom.h" |
| 25 | |
| 26 | #include "exec/cpu-common.h" |
| 27 | #include "exec/cpu-interrupt.h" |
| 28 | #include "qemu/cpu-float.h" |
| 29 | |
| 30 | #ifdef CONFIG_USER_ONLY |
| 31 | #error "RX does not support user mode emulation" |
| 32 | #endif |
| 33 | |
| 34 | /* PSW define */ |
| 35 | REG32(PSW, 0) |
| 36 | FIELD(PSW, C, 0, 1) |
| 37 | FIELD(PSW, Z, 1, 1) |
| 38 | FIELD(PSW, S, 2, 1) |
| 39 | FIELD(PSW, O, 3, 1) |
| 40 | FIELD(PSW, I, 16, 1) |
| 41 | FIELD(PSW, U, 17, 1) |
| 42 | FIELD(PSW, PM, 20, 1) |
| 43 | FIELD(PSW, IPL, 24, 4) |
| 44 | |
| 45 | /* FPSW define */ |
| 46 | REG32(FPSW, 0) |
| 47 | FIELD(FPSW, RM, 0, 2) |
| 48 | FIELD(FPSW, CV, 2, 1) |
| 49 | FIELD(FPSW, CO, 3, 1) |
| 50 | FIELD(FPSW, CZ, 4, 1) |
| 51 | FIELD(FPSW, CU, 5, 1) |
| 52 | FIELD(FPSW, CX, 6, 1) |
| 53 | FIELD(FPSW, CE, 7, 1) |
| 54 | FIELD(FPSW, CAUSE, 2, 6) |
| 55 | FIELD(FPSW, DN, 8, 1) |
| 56 | FIELD(FPSW, EV, 10, 1) |
| 57 | FIELD(FPSW, EO, 11, 1) |
| 58 | FIELD(FPSW, EZ, 12, 1) |
| 59 | FIELD(FPSW, EU, 13, 1) |
| 60 | FIELD(FPSW, EX, 14, 1) |
| 61 | FIELD(FPSW, ENABLE, 10, 5) |
| 62 | FIELD(FPSW, FV, 26, 1) |
| 63 | FIELD(FPSW, FO, 27, 1) |
| 64 | FIELD(FPSW, FZ, 28, 1) |
| 65 | FIELD(FPSW, FU, 29, 1) |
| 66 | FIELD(FPSW, FX, 30, 1) |
| 67 | FIELD(FPSW, FLAGS, 26, 4) |
| 68 | FIELD(FPSW, FS, 31, 1) |
| 69 | |
| 70 | enum { |
| 71 | NUM_REGS = 16, |
| 72 | }; |
| 73 | |
| 74 | typedef struct CPUArchState { |
| 75 | /* CPU registers */ |
| 76 | uint32_t regs[NUM_REGS]; /* general registers */ |
| 77 | uint32_t psw_o; /* O bit of status register */ |
| 78 | uint32_t psw_s; /* S bit of status register */ |
| 79 | uint32_t psw_z; /* Z bit of status register */ |
| 80 | uint32_t psw_c; /* C bit of status register */ |
| 81 | uint32_t psw_u; |
| 82 | uint32_t psw_i; |
| 83 | uint32_t psw_pm; |
| 84 | uint32_t psw_ipl; |
| 85 | uint32_t bpsw; /* backup status */ |
| 86 | uint32_t bpc; /* backup pc */ |
| 87 | uint32_t isp; /* global base register */ |
| 88 | uint32_t usp; /* vector base register */ |
| 89 | uint32_t pc; /* program counter */ |
| 90 | uint32_t intb; /* interrupt vector */ |
| 91 | uint32_t fintv; |
| 92 | uint32_t fpsw; |
| 93 | uint64_t acc; |
| 94 | |
| 95 | /* Fields up to this point are cleared by a CPU reset */ |
| 96 | struct {} end_reset_fields; |
| 97 | |
| 98 | /* Internal use */ |
| 99 | uint32_t in_sleep; |
| 100 | uint32_t req_irq; /* Requested interrupt no (hard) */ |
| 101 | uint32_t req_ipl; /* Requested interrupt level */ |
| 102 | uint32_t ack_irq; /* execute irq */ |
| 103 | uint32_t ack_ipl; /* execute ipl */ |
| 104 | float_status fp_status; |
| 105 | qemu_irq ack; /* Interrupt acknowledge */ |
| 106 | } CPURXState; |
| 107 | |
| 108 | /* |
| 109 | * RXCPU: |
| 110 | * @env: #CPURXState |
| 111 | * |
| 112 | * A RX CPU |
| 113 | */ |
| 114 | struct ArchCPU { |
| 115 | CPUState parent_obj; |
| 116 | |
| 117 | CPURXState env; |
| 118 | }; |
| 119 | |
| 120 | /* |
| 121 | * RXCPUClass: |
| 122 | * @parent_realize: The parent class' realize handler. |
| 123 | * @parent_phases: The parent class' reset phase handlers. |
| 124 | * |
| 125 | * A RX CPU model. |
| 126 | */ |
| 127 | struct RXCPUClass { |
| 128 | CPUClass parent_class; |
| 129 | |
| 130 | DeviceRealize parent_realize; |
| 131 | ResettablePhases parent_phases; |
| 132 | }; |
| 133 | |
| 134 | #define CPU_RESOLVING_TYPE TYPE_RX_CPU |
| 135 | |
| 136 | const char *rx_crname(uint8_t cr); |
| 137 | void rx_cpu_do_interrupt(CPUState *cpu); |
| 138 | bool rx_cpu_exec_interrupt(CPUState *cpu, int int_req); |
| 139 | hwaddr rx_cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr); |
| 140 | void rx_cpu_dump_state(CPUState *cpu, FILE *f, int flags); |
| 141 | int rx_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); |
| 142 | int rx_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); |
| 143 | |
| 144 | void rx_translate_init(void); |
| 145 | void rx_translate_code(CPUState *cs, TranslationBlock *tb, |
| 146 | int *max_insns, vaddr pc, void *host_pc); |
| 147 | void rx_cpu_unpack_psw(CPURXState *env, uint32_t psw, int rte); |
| 148 | |
| 149 | #define CPU_INTERRUPT_SOFT CPU_INTERRUPT_TGT_INT_0 |
| 150 | #define CPU_INTERRUPT_FIR CPU_INTERRUPT_TGT_INT_1 |
| 151 | |
| 152 | #define RX_CPU_IRQ 0 |
| 153 | #define RX_CPU_FIR 1 |
| 154 | |
| 155 | static inline uint32_t rx_cpu_pack_psw(CPURXState *env) |
| 156 | { |
| 157 | uint32_t psw = 0; |
| 158 | psw = FIELD_DP32(psw, PSW, IPL, env->psw_ipl); |
| 159 | psw = FIELD_DP32(psw, PSW, PM, env->psw_pm); |
| 160 | psw = FIELD_DP32(psw, PSW, U, env->psw_u); |
| 161 | psw = FIELD_DP32(psw, PSW, I, env->psw_i); |
| 162 | psw = FIELD_DP32(psw, PSW, O, env->psw_o >> 31); |
| 163 | psw = FIELD_DP32(psw, PSW, S, env->psw_s >> 31); |
| 164 | psw = FIELD_DP32(psw, PSW, Z, env->psw_z == 0); |
| 165 | psw = FIELD_DP32(psw, PSW, C, env->psw_c); |
| 166 | return psw; |
| 167 | } |
| 168 | |
| 169 | #endif /* RX_CPU_H */ |