| 1 | /* |
| 2 | * S/390 virtual CPU header |
| 3 | * |
| 4 | * For details on the s390x architecture and used definitions (e.g., |
| 5 | * PSW, PER and DAT (Dynamic Address Translation)), please refer to |
| 6 | * the "z/Architecture Principles of Operations" - a.k.a. PoP. |
| 7 | * |
| 8 | * Copyright (c) 2009 Ulrich Hecht |
| 9 | * Copyright IBM Corp. 2012, 2018 |
| 10 | * |
| 11 | * This program is free software; you can redistribute it and/or modify |
| 12 | * it under the terms of the GNU General Public License as published by |
| 13 | * the Free Software Foundation; either version 2 of the License, or |
| 14 | * (at your option) any later version. |
| 15 | * |
| 16 | * This program is distributed in the hope that it will be useful, |
| 17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 19 | * General Public License for more details. |
| 20 | * |
| 21 | * You should have received a copy of the GNU General Public License |
| 22 | * along with this program; if not, see <http://www.gnu.org/licenses/>. |
| 23 | */ |
| 24 | |
| 25 | #ifndef S390X_CPU_H |
| 26 | #define S390X_CPU_H |
| 27 | |
| 28 | #include "cpu-qom.h" |
| 29 | #include "cpu_models.h" |
| 30 | #include "exec/cpu-common.h" |
| 31 | #include "exec/cpu-interrupt.h" |
| 32 | #include "qemu/cpu-float.h" |
| 33 | #include "qapi/qapi-types-machine-common.h" |
| 34 | |
| 35 | #define ELF_MACHINE_UNAME "S390X" |
| 36 | |
| 37 | #define MMU_USER_IDX 0 |
| 38 | |
| 39 | #define S390_MAX_CPUS 248 |
| 40 | |
| 41 | typedef struct PSW { |
| 42 | uint64_t mask; |
| 43 | uint64_t addr; |
| 44 | } PSW; |
| 45 | |
| 46 | typedef struct CPUArchState { |
| 47 | uint64_t regs[16]; /* GP registers */ |
| 48 | /* |
| 49 | * The floating point registers are part of the vector registers. |
| 50 | * vregs[0][0] -> vregs[15][0] are 16 floating point registers |
| 51 | */ |
| 52 | uint64_t vregs[32][2] QEMU_ALIGNED(16); /* vector registers */ |
| 53 | uint32_t aregs[16]; /* access registers */ |
| 54 | uint64_t gscb[4]; /* guarded storage control */ |
| 55 | uint64_t etoken; /* etoken */ |
| 56 | uint64_t etoken_extension; /* etoken extension */ |
| 57 | |
| 58 | uint64_t diag318_info; |
| 59 | |
| 60 | /* Fields up to this point are not cleared by initial CPU reset */ |
| 61 | struct {} start_initial_reset_fields; |
| 62 | |
| 63 | uint32_t fpc; /* floating-point control register */ |
| 64 | uint32_t cc_op; |
| 65 | bool bpbc; /* branch prediction blocking */ |
| 66 | |
| 67 | float_status fpu_status; /* passed to softfloat lib */ |
| 68 | |
| 69 | PSW psw; |
| 70 | |
| 71 | S390CrashReason crash_reason; |
| 72 | |
| 73 | uint64_t cc_src; |
| 74 | uint64_t cc_dst; |
| 75 | uint64_t cc_vr; |
| 76 | |
| 77 | uint64_t ex_value; |
| 78 | uint64_t ex_target; |
| 79 | |
| 80 | uint64_t __excp_addr; |
| 81 | uint64_t psa; |
| 82 | |
| 83 | uint32_t int_pgm_code; |
| 84 | uint32_t int_pgm_ilen; |
| 85 | |
| 86 | uint32_t int_svc_code; |
| 87 | uint32_t int_svc_ilen; |
| 88 | |
| 89 | uint64_t per_address; |
| 90 | uint16_t per_perc_atmid; |
| 91 | |
| 92 | uint64_t cregs[16]; /* control registers */ |
| 93 | |
| 94 | uint64_t ckc; |
| 95 | uint64_t cputm; |
| 96 | uint32_t todpr; |
| 97 | |
| 98 | uint64_t pfault_token; |
| 99 | uint64_t pfault_compare; |
| 100 | uint64_t pfault_select; |
| 101 | |
| 102 | uint64_t gbea; |
| 103 | uint64_t pp; |
| 104 | |
| 105 | /* Fields up to this point are not cleared by normal CPU reset */ |
| 106 | struct {} start_normal_reset_fields; |
| 107 | uint8_t riccb[64]; /* runtime instrumentation control */ |
| 108 | |
| 109 | int pending_int; |
| 110 | uint16_t external_call_addr; |
| 111 | DECLARE_BITMAP(emergency_signals, S390_MAX_CPUS); |
| 112 | |
| 113 | #if !defined(CONFIG_USER_ONLY) |
| 114 | uint64_t tlb_fill_tec; /* translation exception code during tlb_fill */ |
| 115 | int tlb_fill_exc; /* exception number seen during tlb_fill */ |
| 116 | #endif |
| 117 | |
| 118 | /* Fields up to this point are cleared by a CPU reset */ |
| 119 | struct {} end_reset_fields; |
| 120 | |
| 121 | #if !defined(CONFIG_USER_ONLY) |
| 122 | uint32_t core_id; /* PoP "CPU address", same as cpu_index */ |
| 123 | int32_t socket_id; |
| 124 | int32_t book_id; |
| 125 | int32_t drawer_id; |
| 126 | bool dedicated; |
| 127 | S390CpuEntitlement entitlement; /* Used only for vertical polarization */ |
| 128 | uint64_t cpuid; |
| 129 | #endif |
| 130 | |
| 131 | QEMUTimer *tod_timer; |
| 132 | |
| 133 | QEMUTimer *cpu_timer; |
| 134 | |
| 135 | /* |
| 136 | * The cpu state represents the logical state of a cpu. In contrast to other |
| 137 | * architectures, there is a difference between a halt and a stop on s390. |
| 138 | * If all cpus are either stopped (including check stop) or in the disabled |
| 139 | * wait state, the vm can be shut down. |
| 140 | * The acceptable cpu_state values are defined in the CpuInfoS390State |
| 141 | * enum. |
| 142 | */ |
| 143 | uint8_t cpu_state; |
| 144 | |
| 145 | /* currently processed sigp order */ |
| 146 | uint8_t sigp_order; |
| 147 | |
| 148 | } CPUS390XState; |
| 149 | |
| 150 | static inline uint64_t *get_freg(CPUS390XState *cs, int nr) |
| 151 | { |
| 152 | return &cs->vregs[nr][0]; |
| 153 | } |
| 154 | |
| 155 | /** |
| 156 | * S390CPU: |
| 157 | * @env: #CPUS390XState. |
| 158 | * |
| 159 | * An S/390 CPU. |
| 160 | */ |
| 161 | struct ArchCPU { |
| 162 | CPUState parent_obj; |
| 163 | |
| 164 | CPUS390XState env; |
| 165 | S390CPUModel *model; |
| 166 | /* needed for live migration */ |
| 167 | void *irqstate; |
| 168 | uint32_t irqstate_saved_size; |
| 169 | }; |
| 170 | |
| 171 | /** |
| 172 | * S390CPUClass: |
| 173 | * @parent_realize: The parent class' realize handler. |
| 174 | * @parent_phases: The parent class' reset phase handlers. |
| 175 | * @load_normal: Performs a load normal. |
| 176 | * |
| 177 | * An S/390 CPU model. |
| 178 | */ |
| 179 | struct S390CPUClass { |
| 180 | CPUClass parent_class; |
| 181 | |
| 182 | const S390CPUDef *cpu_def; |
| 183 | bool kvm_required; |
| 184 | bool is_static; |
| 185 | bool is_migration_safe; |
| 186 | const char *desc; |
| 187 | |
| 188 | DeviceRealize parent_realize; |
| 189 | ResettablePhases parent_phases; |
| 190 | void (*load_normal)(CPUState *cpu); |
| 191 | }; |
| 192 | |
| 193 | #ifndef CONFIG_USER_ONLY |
| 194 | extern const VMStateDescription vmstate_s390_cpu; |
| 195 | #endif |
| 196 | |
| 197 | /* distinguish between 24 bit and 31 bit addressing */ |
| 198 | #define HIGH_ORDER_BIT 0x80000000 |
| 199 | |
| 200 | /* Interrupt Codes */ |
| 201 | /* Program Interrupts */ |
| 202 | #define PGM_OPERATION 0x0001 |
| 203 | #define PGM_PRIVILEGED 0x0002 |
| 204 | #define PGM_EXECUTE 0x0003 |
| 205 | #define PGM_PROTECTION 0x0004 |
| 206 | #define PGM_ADDRESSING 0x0005 |
| 207 | #define PGM_SPECIFICATION 0x0006 |
| 208 | #define PGM_DATA 0x0007 |
| 209 | #define PGM_FIXPT_OVERFLOW 0x0008 |
| 210 | #define PGM_FIXPT_DIVIDE 0x0009 |
| 211 | #define PGM_DEC_OVERFLOW 0x000a |
| 212 | #define PGM_DEC_DIVIDE 0x000b |
| 213 | #define PGM_HFP_EXP_OVERFLOW 0x000c |
| 214 | #define PGM_HFP_EXP_UNDERFLOW 0x000d |
| 215 | #define PGM_HFP_SIGNIFICANCE 0x000e |
| 216 | #define PGM_HFP_DIVIDE 0x000f |
| 217 | #define PGM_SEGMENT_TRANS 0x0010 |
| 218 | #define PGM_PAGE_TRANS 0x0011 |
| 219 | #define PGM_TRANS_SPEC 0x0012 |
| 220 | #define PGM_SPECIAL_OP 0x0013 |
| 221 | #define PGM_OPERAND 0x0015 |
| 222 | #define PGM_TRACE_TABLE 0x0016 |
| 223 | #define PGM_VECTOR_PROCESSING 0x001b |
| 224 | #define PGM_SPACE_SWITCH 0x001c |
| 225 | #define PGM_HFP_SQRT 0x001d |
| 226 | #define PGM_PC_TRANS_SPEC 0x001f |
| 227 | #define PGM_AFX_TRANS 0x0020 |
| 228 | #define PGM_ASX_TRANS 0x0021 |
| 229 | #define PGM_LX_TRANS 0x0022 |
| 230 | #define PGM_EX_TRANS 0x0023 |
| 231 | #define PGM_PRIM_AUTH 0x0024 |
| 232 | #define PGM_SEC_AUTH 0x0025 |
| 233 | #define PGM_ALET_SPEC 0x0028 |
| 234 | #define PGM_ALEN_SPEC 0x0029 |
| 235 | #define PGM_ALE_SEQ 0x002a |
| 236 | #define PGM_ASTE_VALID 0x002b |
| 237 | #define PGM_ASTE_SEQ 0x002c |
| 238 | #define PGM_EXT_AUTH 0x002d |
| 239 | #define PGM_STACK_FULL 0x0030 |
| 240 | #define PGM_STACK_EMPTY 0x0031 |
| 241 | #define PGM_STACK_SPEC 0x0032 |
| 242 | #define PGM_STACK_TYPE 0x0033 |
| 243 | #define PGM_STACK_OP 0x0034 |
| 244 | #define PGM_ASCE_TYPE 0x0038 |
| 245 | #define PGM_REG_FIRST_TRANS 0x0039 |
| 246 | #define PGM_REG_SEC_TRANS 0x003a |
| 247 | #define PGM_REG_THIRD_TRANS 0x003b |
| 248 | #define PGM_MONITOR 0x0040 |
| 249 | #define PGM_PER 0x0080 |
| 250 | #define PGM_CRYPTO 0x0119 |
| 251 | |
| 252 | /* External Interrupts */ |
| 253 | #define EXT_INTERRUPT_KEY 0x0040 |
| 254 | #define EXT_CLOCK_COMP 0x1004 |
| 255 | #define EXT_CPU_TIMER 0x1005 |
| 256 | #define EXT_MALFUNCTION 0x1200 |
| 257 | #define EXT_EMERGENCY 0x1201 |
| 258 | #define EXT_EXTERNAL_CALL 0x1202 |
| 259 | #define EXT_ETR 0x1406 |
| 260 | #define EXT_SERVICE 0x2401 |
| 261 | #define EXT_VIRTIO 0x2603 |
| 262 | |
| 263 | /* PSW defines */ |
| 264 | #undef PSW_MASK_PER |
| 265 | #undef PSW_MASK_UNUSED_2 |
| 266 | #undef PSW_MASK_UNUSED_3 |
| 267 | #undef PSW_MASK_DAT |
| 268 | #undef PSW_MASK_IO |
| 269 | #undef PSW_MASK_EXT |
| 270 | #undef PSW_MASK_KEY |
| 271 | #undef PSW_SHIFT_KEY |
| 272 | #undef PSW_MASK_MCHECK |
| 273 | #undef PSW_MASK_WAIT |
| 274 | #undef PSW_MASK_PSTATE |
| 275 | #undef PSW_MASK_ASC |
| 276 | #undef PSW_SHIFT_ASC |
| 277 | #undef PSW_MASK_CC |
| 278 | #undef PSW_MASK_PM |
| 279 | #undef PSW_MASK_RI |
| 280 | #undef PSW_SHIFT_MASK_PM |
| 281 | #undef PSW_MASK_64 |
| 282 | #undef PSW_MASK_32 |
| 283 | #undef PSW_MASK_ESA_ADDR |
| 284 | |
| 285 | #define PSW_MASK_PER 0x4000000000000000ULL |
| 286 | #define PSW_MASK_UNUSED_2 0x2000000000000000ULL |
| 287 | #define PSW_MASK_UNUSED_3 0x1000000000000000ULL |
| 288 | #define PSW_MASK_DAT 0x0400000000000000ULL |
| 289 | #define PSW_MASK_IO 0x0200000000000000ULL |
| 290 | #define PSW_MASK_EXT 0x0100000000000000ULL |
| 291 | #define PSW_MASK_KEY 0x00F0000000000000ULL |
| 292 | #define PSW_SHIFT_KEY 52 |
| 293 | #define PSW_MASK_SHORTPSW 0x0008000000000000ULL |
| 294 | #define PSW_MASK_MCHECK 0x0004000000000000ULL |
| 295 | #define PSW_MASK_WAIT 0x0002000000000000ULL |
| 296 | #define PSW_MASK_PSTATE 0x0001000000000000ULL |
| 297 | #define PSW_MASK_ASC 0x0000C00000000000ULL |
| 298 | #define PSW_SHIFT_ASC 46 |
| 299 | #define PSW_MASK_CC 0x0000300000000000ULL |
| 300 | #define PSW_MASK_PM 0x00000F0000000000ULL |
| 301 | #define PSW_SHIFT_MASK_PM 40 |
| 302 | #define PSW_MASK_RI 0x0000008000000000ULL |
| 303 | #define PSW_MASK_64 0x0000000100000000ULL |
| 304 | #define PSW_MASK_32 0x0000000080000000ULL |
| 305 | #define PSW_MASK_SHORT_ADDR 0x000000007fffffffULL |
| 306 | #define PSW_MASK_SHORT_CTRL 0xffffffff80000000ULL |
| 307 | #define PSW_MASK_RESERVED 0xb80800fe7fffffffULL |
| 308 | |
| 309 | #undef PSW_ASC_PRIMARY |
| 310 | #undef PSW_ASC_ACCREG |
| 311 | #undef PSW_ASC_SECONDARY |
| 312 | #undef PSW_ASC_HOME |
| 313 | |
| 314 | #define PSW_ASC_PRIMARY 0x0000000000000000ULL |
| 315 | #define PSW_ASC_ACCREG 0x0000400000000000ULL |
| 316 | #define PSW_ASC_SECONDARY 0x0000800000000000ULL |
| 317 | #define PSW_ASC_HOME 0x0000C00000000000ULL |
| 318 | |
| 319 | /* the address space values shifted */ |
| 320 | #define AS_PRIMARY 0 |
| 321 | #define AS_ACCREG 1 |
| 322 | #define AS_SECONDARY 2 |
| 323 | #define AS_HOME 3 |
| 324 | |
| 325 | /* tb flags */ |
| 326 | |
| 327 | #define FLAG_MASK_PSW_SHIFT 31 |
| 328 | #define FLAG_MASK_32 0x00000001u |
| 329 | #define FLAG_MASK_64 0x00000002u |
| 330 | #define FLAG_MASK_AFP 0x00000004u |
| 331 | #define FLAG_MASK_VECTOR 0x00000008u |
| 332 | #define FLAG_MASK_ASC 0x00018000u |
| 333 | #define FLAG_MASK_PSTATE 0x00020000u |
| 334 | #define FLAG_MASK_PER_IFETCH_NULLIFY 0x01000000u |
| 335 | #define FLAG_MASK_DAT 0x08000000u |
| 336 | #define FLAG_MASK_PER_STORE_REAL 0x20000000u |
| 337 | #define FLAG_MASK_PER_IFETCH 0x40000000u |
| 338 | #define FLAG_MASK_PER_BRANCH 0x80000000u |
| 339 | |
| 340 | QEMU_BUILD_BUG_ON(FLAG_MASK_32 != PSW_MASK_32 >> FLAG_MASK_PSW_SHIFT); |
| 341 | QEMU_BUILD_BUG_ON(FLAG_MASK_64 != PSW_MASK_64 >> FLAG_MASK_PSW_SHIFT); |
| 342 | QEMU_BUILD_BUG_ON(FLAG_MASK_ASC != PSW_MASK_ASC >> FLAG_MASK_PSW_SHIFT); |
| 343 | QEMU_BUILD_BUG_ON(FLAG_MASK_PSTATE != PSW_MASK_PSTATE >> FLAG_MASK_PSW_SHIFT); |
| 344 | QEMU_BUILD_BUG_ON(FLAG_MASK_DAT != PSW_MASK_DAT >> FLAG_MASK_PSW_SHIFT); |
| 345 | |
| 346 | #define FLAG_MASK_PSW (FLAG_MASK_DAT | FLAG_MASK_PSTATE | \ |
| 347 | FLAG_MASK_ASC | FLAG_MASK_64 | FLAG_MASK_32) |
| 348 | #define FLAG_MASK_CR9 (FLAG_MASK_PER_BRANCH | FLAG_MASK_PER_IFETCH) |
| 349 | #define FLAG_MASK_PER (FLAG_MASK_PER_BRANCH | \ |
| 350 | FLAG_MASK_PER_IFETCH | \ |
| 351 | FLAG_MASK_PER_IFETCH_NULLIFY | \ |
| 352 | FLAG_MASK_PER_STORE_REAL) |
| 353 | |
| 354 | /* Control register 0 bits */ |
| 355 | #define CR0_LOWPROT 0x0000000010000000ULL |
| 356 | #define CR0_SECONDARY 0x0000000004000000ULL |
| 357 | #define CR0_EDAT 0x0000000000800000ULL |
| 358 | #define CR0_AFP 0x0000000000040000ULL |
| 359 | #define CR0_VECTOR 0x0000000000020000ULL |
| 360 | #define CR0_IEP 0x0000000000100000ULL |
| 361 | #define CR0_EMERGENCY_SIGNAL_SC 0x0000000000004000ULL |
| 362 | #define CR0_EXTERNAL_CALL_SC 0x0000000000002000ULL |
| 363 | #define CR0_CKC_SC 0x0000000000000800ULL |
| 364 | #define CR0_CPU_TIMER_SC 0x0000000000000400ULL |
| 365 | #define CR0_SERVICE_SC 0x0000000000000200ULL |
| 366 | |
| 367 | /* Control register 14 bits */ |
| 368 | #define CR14_CHANNEL_REPORT_SC 0x0000000010000000ULL |
| 369 | |
| 370 | /* MMU */ |
| 371 | #define MMU_PRIMARY_IDX 0 |
| 372 | #define MMU_SECONDARY_IDX 1 |
| 373 | #define MMU_HOME_IDX 2 |
| 374 | #define MMU_REAL_IDX 3 |
| 375 | |
| 376 | static inline int s390x_env_mmu_index(CPUS390XState *env, bool ifetch) |
| 377 | { |
| 378 | #ifdef CONFIG_USER_ONLY |
| 379 | return MMU_USER_IDX; |
| 380 | #else |
| 381 | if (!(env->psw.mask & PSW_MASK_DAT)) { |
| 382 | return MMU_REAL_IDX; |
| 383 | } |
| 384 | |
| 385 | if (ifetch) { |
| 386 | if ((env->psw.mask & PSW_MASK_ASC) == PSW_ASC_HOME) { |
| 387 | return MMU_HOME_IDX; |
| 388 | } |
| 389 | return MMU_PRIMARY_IDX; |
| 390 | } |
| 391 | |
| 392 | switch (env->psw.mask & PSW_MASK_ASC) { |
| 393 | case PSW_ASC_PRIMARY: |
| 394 | return MMU_PRIMARY_IDX; |
| 395 | case PSW_ASC_SECONDARY: |
| 396 | return MMU_SECONDARY_IDX; |
| 397 | case PSW_ASC_HOME: |
| 398 | return MMU_HOME_IDX; |
| 399 | case PSW_ASC_ACCREG: |
| 400 | /* Fallthrough: access register mode is not yet supported */ |
| 401 | default: |
| 402 | abort(); |
| 403 | } |
| 404 | #endif |
| 405 | } |
| 406 | |
| 407 | /* PER bits from control register 9 */ |
| 408 | #define PER_CR9_EVENT_BRANCH 0x80000000 |
| 409 | #define PER_CR9_EVENT_IFETCH 0x40000000 |
| 410 | #define PER_CR9_EVENT_STORE 0x20000000 |
| 411 | #define PER_CR9_EVENT_STORAGE_KEY_ALTERATION 0x10000000 |
| 412 | #define PER_CR9_EVENT_STORE_REAL 0x08000000 |
| 413 | #define PER_CR9_EVENT_ZERO_ADDRESS_DETECTION 0x04000000 |
| 414 | #define PER_CR9_EVENT_TRANSACTION_END 0x02000000 |
| 415 | #define PER_CR9_EVENT_IFETCH_NULLIFICATION 0x01000000 |
| 416 | #define PER_CR9_CONTROL_BRANCH_ADDRESS 0x00800000 |
| 417 | #define PER_CR9_CONTROL_TRANSACTION_SUPRESS 0x00400000 |
| 418 | #define PER_CR9_CONTROL_STORAGE_ALTERATION 0x00200000 |
| 419 | |
| 420 | QEMU_BUILD_BUG_ON(FLAG_MASK_PER_BRANCH != PER_CR9_EVENT_BRANCH); |
| 421 | QEMU_BUILD_BUG_ON(FLAG_MASK_PER_IFETCH != PER_CR9_EVENT_IFETCH); |
| 422 | QEMU_BUILD_BUG_ON(FLAG_MASK_PER_IFETCH_NULLIFY != |
| 423 | PER_CR9_EVENT_IFETCH_NULLIFICATION); |
| 424 | |
| 425 | /* PER bits from the PER CODE/ATMID/AI in lowcore */ |
| 426 | #define PER_CODE_EVENT_BRANCH 0x8000 |
| 427 | #define PER_CODE_EVENT_IFETCH 0x4000 |
| 428 | #define PER_CODE_EVENT_STORE 0x2000 |
| 429 | #define PER_CODE_EVENT_STORE_REAL 0x0800 |
| 430 | #define PER_CODE_EVENT_NULLIFICATION 0x0100 |
| 431 | |
| 432 | #define EXCP_EXT 1 /* external interrupt */ |
| 433 | #define EXCP_SVC 2 /* supervisor call (syscall) */ |
| 434 | #define EXCP_PGM 3 /* program interruption */ |
| 435 | #define EXCP_RESTART 4 /* restart interrupt */ |
| 436 | #define EXCP_STOP 5 /* stop interrupt */ |
| 437 | #define EXCP_IO 7 /* I/O interrupt */ |
| 438 | #define EXCP_MCHK 8 /* machine check */ |
| 439 | |
| 440 | #define INTERRUPT_EXT_CPU_TIMER (1 << 3) |
| 441 | #define INTERRUPT_EXT_CLOCK_COMPARATOR (1 << 4) |
| 442 | #define INTERRUPT_EXTERNAL_CALL (1 << 5) |
| 443 | #define INTERRUPT_EMERGENCY_SIGNAL (1 << 6) |
| 444 | #define INTERRUPT_RESTART (1 << 7) |
| 445 | #define INTERRUPT_STOP (1 << 8) |
| 446 | |
| 447 | /* Program Status Word. */ |
| 448 | #define S390_PSWM_REGNUM 0 |
| 449 | #define S390_PSWA_REGNUM 1 |
| 450 | /* General Purpose Registers. */ |
| 451 | #define S390_R0_REGNUM 2 |
| 452 | #define S390_R1_REGNUM 3 |
| 453 | #define S390_R2_REGNUM 4 |
| 454 | #define S390_R3_REGNUM 5 |
| 455 | #define S390_R4_REGNUM 6 |
| 456 | #define S390_R5_REGNUM 7 |
| 457 | #define S390_R6_REGNUM 8 |
| 458 | #define S390_R7_REGNUM 9 |
| 459 | #define S390_R8_REGNUM 10 |
| 460 | #define S390_R9_REGNUM 11 |
| 461 | #define S390_R10_REGNUM 12 |
| 462 | #define S390_R11_REGNUM 13 |
| 463 | #define S390_R12_REGNUM 14 |
| 464 | #define S390_R13_REGNUM 15 |
| 465 | #define S390_R14_REGNUM 16 |
| 466 | #define S390_R15_REGNUM 17 |
| 467 | |
| 468 | static inline void setcc(S390CPU *cpu, uint64_t cc) |
| 469 | { |
| 470 | CPUS390XState *env = &cpu->env; |
| 471 | |
| 472 | env->psw.mask &= ~(3ull << 44); |
| 473 | env->psw.mask |= (cc & 3) << 44; |
| 474 | env->cc_op = cc; |
| 475 | } |
| 476 | |
| 477 | /* STSI */ |
| 478 | #define STSI_R0_FC_MASK 0x00000000f0000000ULL |
| 479 | #define STSI_R0_FC_CURRENT 0x0000000000000000ULL |
| 480 | #define STSI_R0_FC_LEVEL_1 0x0000000010000000ULL |
| 481 | #define STSI_R0_FC_LEVEL_2 0x0000000020000000ULL |
| 482 | #define STSI_R0_FC_LEVEL_3 0x0000000030000000ULL |
| 483 | #define STSI_R0_RESERVED_MASK 0x000000000fffff00ULL |
| 484 | #define STSI_R0_SEL1_MASK 0x00000000000000ffULL |
| 485 | #define STSI_R1_RESERVED_MASK 0x00000000ffff0000ULL |
| 486 | #define STSI_R1_SEL2_MASK 0x000000000000ffffULL |
| 487 | |
| 488 | /* Basic Machine Configuration */ |
| 489 | typedef struct SysIB_111 { |
| 490 | uint8_t res1[32]; |
| 491 | uint8_t manuf[16]; |
| 492 | uint8_t type[4]; |
| 493 | uint8_t res2[12]; |
| 494 | uint8_t model[16]; |
| 495 | uint8_t sequence[16]; |
| 496 | uint8_t plant[4]; |
| 497 | uint8_t res3[3996]; |
| 498 | } SysIB_111; |
| 499 | QEMU_BUILD_BUG_ON(sizeof(SysIB_111) != 4096); |
| 500 | |
| 501 | /* Basic Machine CPU */ |
| 502 | typedef struct SysIB_121 { |
| 503 | uint8_t res1[80]; |
| 504 | uint8_t sequence[16]; |
| 505 | uint8_t plant[4]; |
| 506 | uint8_t res2[2]; |
| 507 | uint16_t cpu_addr; |
| 508 | uint8_t res3[3992]; |
| 509 | } SysIB_121; |
| 510 | QEMU_BUILD_BUG_ON(sizeof(SysIB_121) != 4096); |
| 511 | |
| 512 | /* Basic Machine CPUs */ |
| 513 | typedef struct SysIB_122 { |
| 514 | uint8_t res1[32]; |
| 515 | uint32_t capability; |
| 516 | uint16_t total_cpus; |
| 517 | uint16_t conf_cpus; |
| 518 | uint16_t standby_cpus; |
| 519 | uint16_t reserved_cpus; |
| 520 | uint16_t adjustments[2026]; |
| 521 | } SysIB_122; |
| 522 | QEMU_BUILD_BUG_ON(sizeof(SysIB_122) != 4096); |
| 523 | |
| 524 | /* LPAR CPU */ |
| 525 | typedef struct SysIB_221 { |
| 526 | uint8_t res1[80]; |
| 527 | uint8_t sequence[16]; |
| 528 | uint8_t plant[4]; |
| 529 | uint16_t cpu_id; |
| 530 | uint16_t cpu_addr; |
| 531 | uint8_t res3[3992]; |
| 532 | } SysIB_221; |
| 533 | QEMU_BUILD_BUG_ON(sizeof(SysIB_221) != 4096); |
| 534 | |
| 535 | /* LPAR CPUs */ |
| 536 | typedef struct SysIB_222 { |
| 537 | uint8_t res1[32]; |
| 538 | uint16_t lpar_num; |
| 539 | uint8_t res2; |
| 540 | uint8_t lcpuc; |
| 541 | uint16_t total_cpus; |
| 542 | uint16_t conf_cpus; |
| 543 | uint16_t standby_cpus; |
| 544 | uint16_t reserved_cpus; |
| 545 | uint8_t name[8]; |
| 546 | uint32_t caf; |
| 547 | uint8_t res3[16]; |
| 548 | uint16_t dedicated_cpus; |
| 549 | uint16_t shared_cpus; |
| 550 | uint8_t res4[4020]; |
| 551 | } SysIB_222; |
| 552 | QEMU_BUILD_BUG_ON(sizeof(SysIB_222) != 4096); |
| 553 | |
| 554 | /* VM CPUs */ |
| 555 | typedef struct SysIB_322 { |
| 556 | uint8_t res1[31]; |
| 557 | uint8_t count; |
| 558 | struct { |
| 559 | uint8_t res2[4]; |
| 560 | uint16_t total_cpus; |
| 561 | uint16_t conf_cpus; |
| 562 | uint16_t standby_cpus; |
| 563 | uint16_t reserved_cpus; |
| 564 | uint8_t name[8]; |
| 565 | uint32_t caf; |
| 566 | uint8_t cpi[16]; |
| 567 | uint8_t res5[3]; |
| 568 | uint8_t ext_name_encoding; |
| 569 | uint32_t res3; |
| 570 | uint8_t uuid[16]; |
| 571 | } vm[8]; |
| 572 | uint8_t res4[1504]; |
| 573 | uint8_t ext_names[8][256]; |
| 574 | } SysIB_322; |
| 575 | QEMU_BUILD_BUG_ON(sizeof(SysIB_322) != 4096); |
| 576 | |
| 577 | /* |
| 578 | * Topology Magnitude fields (MAG) indicates the maximum number of |
| 579 | * topology list entries (TLE) at the corresponding nesting level. |
| 580 | */ |
| 581 | #define S390_TOPOLOGY_MAG 6 |
| 582 | #define S390_TOPOLOGY_MAG6 0 |
| 583 | #define S390_TOPOLOGY_MAG5 1 |
| 584 | #define S390_TOPOLOGY_MAG4 2 |
| 585 | #define S390_TOPOLOGY_MAG3 3 |
| 586 | #define S390_TOPOLOGY_MAG2 4 |
| 587 | #define S390_TOPOLOGY_MAG1 5 |
| 588 | /* Configuration topology */ |
| 589 | typedef struct SysIB_151x { |
| 590 | uint8_t reserved0[2]; |
| 591 | uint16_t length; |
| 592 | uint8_t mag[S390_TOPOLOGY_MAG]; |
| 593 | uint8_t reserved1; |
| 594 | uint8_t mnest; |
| 595 | uint32_t reserved2; |
| 596 | char tle[]; |
| 597 | } SysIB_151x; |
| 598 | QEMU_BUILD_BUG_ON(sizeof(SysIB_151x) != 16); |
| 599 | |
| 600 | typedef union SysIB { |
| 601 | SysIB_111 sysib_111; |
| 602 | SysIB_121 sysib_121; |
| 603 | SysIB_122 sysib_122; |
| 604 | SysIB_221 sysib_221; |
| 605 | SysIB_222 sysib_222; |
| 606 | SysIB_322 sysib_322; |
| 607 | SysIB_151x sysib_151x; |
| 608 | } SysIB; |
| 609 | QEMU_BUILD_BUG_ON(sizeof(SysIB) != 4096); |
| 610 | |
| 611 | /* |
| 612 | * CPU Topology List provided by STSI with fc=15 provides a list |
| 613 | * of two different Topology List Entries (TLE) types to specify |
| 614 | * the topology hierarchy. |
| 615 | * |
| 616 | * - Container Topology List Entry |
| 617 | * Defines a container to contain other Topology List Entries |
| 618 | * of any type, nested containers or CPU. |
| 619 | * - CPU Topology List Entry |
| 620 | * Specifies the CPUs position, type, entitlement and polarization |
| 621 | * of the CPUs contained in the last container TLE. |
| 622 | * |
| 623 | * There can be theoretically up to five levels of containers, QEMU |
| 624 | * uses only three levels, the drawer's, book's and socket's level. |
| 625 | * |
| 626 | * A container with a nesting level (NL) greater than 1 can only |
| 627 | * contain another container of nesting level NL-1. |
| 628 | * |
| 629 | * A container of nesting level 1 (socket), contains as many CPU TLE |
| 630 | * as needed to describe the position and qualities of all CPUs inside |
| 631 | * the container. |
| 632 | * The qualities of a CPU are polarization, entitlement and type. |
| 633 | * |
| 634 | * The CPU TLE defines the position of the CPUs of identical qualities |
| 635 | * using a 64bits mask which first bit has its offset defined by |
| 636 | * the CPU address origin field of the CPU TLE like in: |
| 637 | * CPU address = origin * 64 + bit position within the mask |
| 638 | */ |
| 639 | /* Container type Topology List Entry */ |
| 640 | typedef struct SYSIBContainerListEntry { |
| 641 | uint8_t nl; |
| 642 | uint8_t reserved[6]; |
| 643 | uint8_t id; |
| 644 | } SYSIBContainerListEntry; |
| 645 | QEMU_BUILD_BUG_ON(sizeof(SYSIBContainerListEntry) != 8); |
| 646 | |
| 647 | /* CPU type Topology List Entry */ |
| 648 | typedef struct SysIBCPUListEntry { |
| 649 | uint8_t nl; |
| 650 | uint8_t reserved0[3]; |
| 651 | #define SYSIB_TLE_POLARITY_MASK 0x03 |
| 652 | #define SYSIB_TLE_DEDICATED 0x04 |
| 653 | uint8_t flags; |
| 654 | uint8_t type; |
| 655 | uint16_t origin; |
| 656 | uint64_t mask; |
| 657 | } SysIBCPUListEntry; |
| 658 | QEMU_BUILD_BUG_ON(sizeof(SysIBCPUListEntry) != 16); |
| 659 | |
| 660 | void insert_stsi_15_1_x(S390CPU *cpu, int sel2, uint64_t addr, uint8_t ar, uintptr_t ra); |
| 661 | void s390_cpu_topology_set_changed(bool changed); |
| 662 | |
| 663 | /* MMU defines */ |
| 664 | #define ASCE_ORIGIN (~0xfffULL) /* segment table origin */ |
| 665 | #define ASCE_SUBSPACE 0x200 /* subspace group control */ |
| 666 | #define ASCE_PRIVATE_SPACE 0x100 /* private space control */ |
| 667 | #define ASCE_ALT_EVENT 0x80 /* storage alteration event control */ |
| 668 | #define ASCE_SPACE_SWITCH 0x40 /* space switch event */ |
| 669 | #define ASCE_REAL_SPACE 0x20 /* real space control */ |
| 670 | #define ASCE_TYPE_MASK 0x0c /* asce table type mask */ |
| 671 | #define ASCE_TYPE_REGION1 0x0c /* region first table type */ |
| 672 | #define ASCE_TYPE_REGION2 0x08 /* region second table type */ |
| 673 | #define ASCE_TYPE_REGION3 0x04 /* region third table type */ |
| 674 | #define ASCE_TYPE_SEGMENT 0x00 /* segment table type */ |
| 675 | #define ASCE_TABLE_LENGTH 0x03 /* region table length */ |
| 676 | |
| 677 | #define REGION_ENTRY_ORIGIN 0xfffffffffffff000ULL |
| 678 | #define REGION_ENTRY_P 0x0000000000000200ULL |
| 679 | #define REGION_ENTRY_TF 0x00000000000000c0ULL |
| 680 | #define REGION_ENTRY_I 0x0000000000000020ULL |
| 681 | #define REGION_ENTRY_TT 0x000000000000000cULL |
| 682 | #define REGION_ENTRY_TL 0x0000000000000003ULL |
| 683 | |
| 684 | #define REGION_ENTRY_TT_REGION1 0x000000000000000cULL |
| 685 | #define REGION_ENTRY_TT_REGION2 0x0000000000000008ULL |
| 686 | #define REGION_ENTRY_TT_REGION3 0x0000000000000004ULL |
| 687 | |
| 688 | #define REGION3_ENTRY_RFAA 0xffffffff80000000ULL |
| 689 | #define REGION3_ENTRY_AV 0x0000000000010000ULL |
| 690 | #define REGION3_ENTRY_ACC 0x000000000000f000ULL |
| 691 | #define REGION3_ENTRY_F 0x0000000000000800ULL |
| 692 | #define REGION3_ENTRY_FC 0x0000000000000400ULL |
| 693 | #define REGION3_ENTRY_IEP 0x0000000000000100ULL |
| 694 | #define REGION3_ENTRY_CR 0x0000000000000010ULL |
| 695 | |
| 696 | #define SEGMENT_ENTRY_ORIGIN 0xfffffffffffff800ULL |
| 697 | #define SEGMENT_ENTRY_SFAA 0xfffffffffff00000ULL |
| 698 | #define SEGMENT_ENTRY_AV 0x0000000000010000ULL |
| 699 | #define SEGMENT_ENTRY_ACC 0x000000000000f000ULL |
| 700 | #define SEGMENT_ENTRY_F 0x0000000000000800ULL |
| 701 | #define SEGMENT_ENTRY_FC 0x0000000000000400ULL |
| 702 | #define SEGMENT_ENTRY_P 0x0000000000000200ULL |
| 703 | #define SEGMENT_ENTRY_IEP 0x0000000000000100ULL |
| 704 | #define SEGMENT_ENTRY_I 0x0000000000000020ULL |
| 705 | #define SEGMENT_ENTRY_CS 0x0000000000000010ULL |
| 706 | #define SEGMENT_ENTRY_TT 0x000000000000000cULL |
| 707 | |
| 708 | #define SEGMENT_ENTRY_TT_SEGMENT 0x0000000000000000ULL |
| 709 | |
| 710 | #define PAGE_ENTRY_0 0x0000000000000800ULL |
| 711 | #define PAGE_ENTRY_I 0x0000000000000400ULL |
| 712 | #define PAGE_ENTRY_P 0x0000000000000200ULL |
| 713 | #define PAGE_ENTRY_IEP 0x0000000000000100ULL |
| 714 | |
| 715 | #define VADDR_REGION1_TX_MASK 0xffe0000000000000ULL |
| 716 | #define VADDR_REGION2_TX_MASK 0x001ffc0000000000ULL |
| 717 | #define VADDR_REGION3_TX_MASK 0x000003ff80000000ULL |
| 718 | #define VADDR_SEGMENT_TX_MASK 0x000000007ff00000ULL |
| 719 | #define VADDR_PAGE_TX_MASK 0x00000000000ff000ULL |
| 720 | |
| 721 | #define VADDR_REGION1_TX(vaddr) (((vaddr) & VADDR_REGION1_TX_MASK) >> 53) |
| 722 | #define VADDR_REGION2_TX(vaddr) (((vaddr) & VADDR_REGION2_TX_MASK) >> 42) |
| 723 | #define VADDR_REGION3_TX(vaddr) (((vaddr) & VADDR_REGION3_TX_MASK) >> 31) |
| 724 | #define VADDR_SEGMENT_TX(vaddr) (((vaddr) & VADDR_SEGMENT_TX_MASK) >> 20) |
| 725 | #define VADDR_PAGE_TX(vaddr) (((vaddr) & VADDR_PAGE_TX_MASK) >> 12) |
| 726 | |
| 727 | #define VADDR_REGION1_TL(vaddr) (((vaddr) & 0xc000000000000000ULL) >> 62) |
| 728 | #define VADDR_REGION2_TL(vaddr) (((vaddr) & 0x0018000000000000ULL) >> 51) |
| 729 | #define VADDR_REGION3_TL(vaddr) (((vaddr) & 0x0000030000000000ULL) >> 40) |
| 730 | #define VADDR_SEGMENT_TL(vaddr) (((vaddr) & 0x0000000060000000ULL) >> 29) |
| 731 | |
| 732 | #define SK_C (0x1 << 1) |
| 733 | #define SK_R (0x1 << 2) |
| 734 | #define SK_F (0x1 << 3) |
| 735 | #define SK_ACC_MASK (0xf << 4) |
| 736 | |
| 737 | /* SIGP order codes */ |
| 738 | #define SIGP_SENSE 0x01 |
| 739 | #define SIGP_EXTERNAL_CALL 0x02 |
| 740 | #define SIGP_EMERGENCY 0x03 |
| 741 | #define SIGP_START 0x04 |
| 742 | #define SIGP_STOP 0x05 |
| 743 | #define SIGP_RESTART 0x06 |
| 744 | #define SIGP_STOP_STORE_STATUS 0x09 |
| 745 | #define SIGP_INITIAL_CPU_RESET 0x0b |
| 746 | #define SIGP_CPU_RESET 0x0c |
| 747 | #define SIGP_SET_PREFIX 0x0d |
| 748 | #define SIGP_STORE_STATUS_ADDR 0x0e |
| 749 | #define SIGP_SET_ARCH 0x12 |
| 750 | #define SIGP_COND_EMERGENCY 0x13 |
| 751 | #define SIGP_SENSE_RUNNING 0x15 |
| 752 | #define SIGP_STORE_ADTL_STATUS 0x17 |
| 753 | |
| 754 | /* SIGP condition codes */ |
| 755 | #define SIGP_CC_ORDER_CODE_ACCEPTED 0 |
| 756 | #define SIGP_CC_STATUS_STORED 1 |
| 757 | #define SIGP_CC_BUSY 2 |
| 758 | #define SIGP_CC_NOT_OPERATIONAL 3 |
| 759 | |
| 760 | /* SIGP status bits */ |
| 761 | #define SIGP_STAT_EQUIPMENT_CHECK 0x80000000UL |
| 762 | #define SIGP_STAT_NOT_RUNNING 0x00000400UL |
| 763 | #define SIGP_STAT_INCORRECT_STATE 0x00000200UL |
| 764 | #define SIGP_STAT_INVALID_PARAMETER 0x00000100UL |
| 765 | #define SIGP_STAT_EXT_CALL_PENDING 0x00000080UL |
| 766 | #define SIGP_STAT_STOPPED 0x00000040UL |
| 767 | #define SIGP_STAT_OPERATOR_INTERV 0x00000020UL |
| 768 | #define SIGP_STAT_CHECK_STOP 0x00000010UL |
| 769 | #define SIGP_STAT_INOPERATIVE 0x00000004UL |
| 770 | #define SIGP_STAT_INVALID_ORDER 0x00000002UL |
| 771 | #define SIGP_STAT_RECEIVER_CHECK 0x00000001UL |
| 772 | |
| 773 | /* SIGP order code mask corresponding to bit positions 56-63 */ |
| 774 | #define SIGP_ORDER_MASK 0x000000ff |
| 775 | |
| 776 | /* machine check interruption code */ |
| 777 | |
| 778 | /* subclasses */ |
| 779 | #define MCIC_SC_SD 0x8000000000000000ULL |
| 780 | #define MCIC_SC_PD 0x4000000000000000ULL |
| 781 | #define MCIC_SC_SR 0x2000000000000000ULL |
| 782 | #define MCIC_SC_CD 0x0800000000000000ULL |
| 783 | #define MCIC_SC_ED 0x0400000000000000ULL |
| 784 | #define MCIC_SC_DG 0x0100000000000000ULL |
| 785 | #define MCIC_SC_W 0x0080000000000000ULL |
| 786 | #define MCIC_SC_CP 0x0040000000000000ULL |
| 787 | #define MCIC_SC_SP 0x0020000000000000ULL |
| 788 | #define MCIC_SC_CK 0x0010000000000000ULL |
| 789 | |
| 790 | /* subclass modifiers */ |
| 791 | #define MCIC_SCM_B 0x0002000000000000ULL |
| 792 | #define MCIC_SCM_DA 0x0000000020000000ULL |
| 793 | #define MCIC_SCM_AP 0x0000000000080000ULL |
| 794 | |
| 795 | /* storage errors */ |
| 796 | #define MCIC_SE_SE 0x0000800000000000ULL |
| 797 | #define MCIC_SE_SC 0x0000400000000000ULL |
| 798 | #define MCIC_SE_KE 0x0000200000000000ULL |
| 799 | #define MCIC_SE_DS 0x0000100000000000ULL |
| 800 | #define MCIC_SE_IE 0x0000000080000000ULL |
| 801 | |
| 802 | /* validity bits */ |
| 803 | #define MCIC_VB_WP 0x0000080000000000ULL |
| 804 | #define MCIC_VB_MS 0x0000040000000000ULL |
| 805 | #define MCIC_VB_PM 0x0000020000000000ULL |
| 806 | #define MCIC_VB_IA 0x0000010000000000ULL |
| 807 | #define MCIC_VB_FA 0x0000008000000000ULL |
| 808 | #define MCIC_VB_VR 0x0000004000000000ULL |
| 809 | #define MCIC_VB_EC 0x0000002000000000ULL |
| 810 | #define MCIC_VB_FP 0x0000001000000000ULL |
| 811 | #define MCIC_VB_GR 0x0000000800000000ULL |
| 812 | #define MCIC_VB_CR 0x0000000400000000ULL |
| 813 | #define MCIC_VB_ST 0x0000000100000000ULL |
| 814 | #define MCIC_VB_AR 0x0000000040000000ULL |
| 815 | #define MCIC_VB_GS 0x0000000008000000ULL |
| 816 | #define MCIC_VB_PR 0x0000000000200000ULL |
| 817 | #define MCIC_VB_FC 0x0000000000100000ULL |
| 818 | #define MCIC_VB_CT 0x0000000000020000ULL |
| 819 | #define MCIC_VB_CC 0x0000000000010000ULL |
| 820 | |
| 821 | static inline uint64_t s390_build_validity_mcic(void) |
| 822 | { |
| 823 | uint64_t mcic; |
| 824 | |
| 825 | /* |
| 826 | * Indicate all validity bits (no damage) only. Other bits have to be |
| 827 | * added by the caller. (storage errors, subclasses and subclass modifiers) |
| 828 | */ |
| 829 | mcic = MCIC_VB_WP | MCIC_VB_MS | MCIC_VB_PM | MCIC_VB_IA | MCIC_VB_FP | |
| 830 | MCIC_VB_GR | MCIC_VB_CR | MCIC_VB_ST | MCIC_VB_AR | MCIC_VB_PR | |
| 831 | MCIC_VB_FC | MCIC_VB_CT | MCIC_VB_CC; |
| 832 | if (s390_has_feat(S390_FEAT_VECTOR)) { |
| 833 | mcic |= MCIC_VB_VR; |
| 834 | } |
| 835 | if (s390_has_feat(S390_FEAT_GUARDED_STORAGE)) { |
| 836 | mcic |= MCIC_VB_GS; |
| 837 | } |
| 838 | return mcic; |
| 839 | } |
| 840 | |
| 841 | /* cpu.c */ |
| 842 | void s390_do_cpu_full_reset(CPUState *cs, run_on_cpu_data arg); |
| 843 | void s390_crypto_reset(void); |
| 844 | void s390_cmma_reset(void); |
| 845 | void s390_enable_css_support(S390CPU *cpu); |
| 846 | void s390_do_cpu_set_diag318(CPUState *cs, run_on_cpu_data arg); |
| 847 | int s390_assign_subch_ioeventfd(EventNotifier *notifier, uint32_t sch_id, |
| 848 | int vq, bool assign); |
| 849 | #ifndef CONFIG_USER_ONLY |
| 850 | unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu); |
| 851 | #else |
| 852 | static inline unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu) |
| 853 | { |
| 854 | return 0; |
| 855 | } |
| 856 | #endif /* CONFIG_USER_ONLY */ |
| 857 | static inline uint8_t s390_cpu_get_state(S390CPU *cpu) |
| 858 | { |
| 859 | return cpu->env.cpu_state; |
| 860 | } |
| 861 | |
| 862 | |
| 863 | /* helper.c */ |
| 864 | #define CPU_RESOLVING_TYPE TYPE_S390_CPU |
| 865 | |
| 866 | /* interrupt.c */ |
| 867 | #define RA_IGNORED 0 |
| 868 | void s390_program_interrupt(CPUS390XState *env, uint32_t code, uintptr_t ra); |
| 869 | /* service interrupts are floating therefore we must not pass an cpustate */ |
| 870 | void s390_sclp_extint(uint32_t parm); |
| 871 | |
| 872 | /* mmu_helper.c */ |
| 873 | int s390_cpu_virt_mem_rw(S390CPU *cpu, vaddr laddr, uint8_t ar, void *hostbuf, |
| 874 | int len, bool is_write); |
| 875 | #define s390_cpu_virt_mem_read(cpu, laddr, ar, dest, len) \ |
| 876 | s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, false) |
| 877 | #define s390_cpu_virt_mem_write(cpu, laddr, ar, dest, len) \ |
| 878 | s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, true) |
| 879 | #define s390_cpu_virt_mem_check_read(cpu, laddr, ar, len) \ |
| 880 | s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, false) |
| 881 | #define s390_cpu_virt_mem_check_write(cpu, laddr, ar, len) \ |
| 882 | s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, true) |
| 883 | void s390_cpu_virt_mem_handle_exc(S390CPU *cpu, uintptr_t ra); |
| 884 | int s390_cpu_pv_mem_rw(S390CPU *cpu, unsigned int offset, void *hostbuf, |
| 885 | int len, bool is_write); |
| 886 | #define s390_cpu_pv_mem_read(cpu, offset, dest, len) \ |
| 887 | s390_cpu_pv_mem_rw(cpu, offset, dest, len, false) |
| 888 | #define s390_cpu_pv_mem_write(cpu, offset, dest, len) \ |
| 889 | s390_cpu_pv_mem_rw(cpu, offset, dest, len, true) |
| 890 | |
| 891 | /* sigp.c */ |
| 892 | int s390_cpu_restart(S390CPU *cpu); |
| 893 | void s390_init_sigp(void); |
| 894 | |
| 895 | /* helper.c */ |
| 896 | void s390_cpu_set_psw(CPUS390XState *env, uint64_t mask, uint64_t addr); |
| 897 | uint64_t s390_cpu_get_psw_mask(CPUS390XState *env); |
| 898 | void cpu_s390x_load_fpc(CPUS390XState *env, uint32_t fpc); |
| 899 | |
| 900 | /* outside of target/s390x/ */ |
| 901 | S390CPU *s390_cpu_addr2state(uint16_t cpu_addr); |
| 902 | |
| 903 | #endif |