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1 /*
2 * S390x MMU related functions
3 *
4 * Copyright (c) 2011 Alexander Graf
5 * Copyright (c) 2015 Thomas Huth, IBM Corporation
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18 #include "qemu/osdep.h"
19 #include "qemu/error-report.h"
20 #include "system/address-spaces.h"
21 #include "cpu.h"
22 #include "s390x-internal.h"
23 #include "kvm/kvm_s390x.h"
24 #include "system/kvm.h"
25 #include "system/tcg.h"
26 #include "system/memory.h"
27 #ifdef CONFIG_TCG
28 #include "accel/tcg/cpu-loop.h"
29 #endif
30 #include "exec/page-protection.h"
31 #include "exec/target_page.h"
32 #include "hw/core/hw-error.h"
33 #include "hw/s390x/storage-keys.h"
34 #include "hw/core/boards.h"
35
36 /* Fetch/store bits in the translation exception code: */
37 #define FS_READ 0x800
38 #define FS_WRITE 0x400
39
40 static void trigger_access_exception(CPUS390XState *env, uint32_t type,
41 uint64_t tec)
42 {
43 S390CPU *cpu = env_archcpu(env);
44
45 if (kvm_enabled()) {
46 kvm_s390_access_exception(cpu, type, tec);
47 } else {
48 CPUState *cs = env_cpu(env);
49 if (type != PGM_ADDRESSING) {
50 address_space_stq_be(cs->as,
51 env->psa + offsetof(LowCore, trans_exc_code),
52 tec, MEMTXATTRS_UNSPECIFIED, NULL);
53 }
54 trigger_pgm_exception(env, type);
55 }
56 }
57
58 /* check whether the address would be proteted by Low-Address Protection */
59 static bool is_low_address(uint64_t addr)
60 {
61 return addr <= 511 || (addr >= 4096 && addr <= 4607);
62 }
63
64 /* check whether Low-Address Protection is enabled for mmu_translate() */
65 static bool lowprot_enabled(const CPUS390XState *env, uint64_t asc)
66 {
67 if (!(env->cregs[0] & CR0_LOWPROT)) {
68 return false;
69 }
70 if (!(env->psw.mask & PSW_MASK_DAT)) {
71 return true;
72 }
73
74 /* Check the private-space control bit */
75 switch (asc) {
76 case PSW_ASC_PRIMARY:
77 return !(env->cregs[1] & ASCE_PRIVATE_SPACE);
78 case PSW_ASC_SECONDARY:
79 return !(env->cregs[7] & ASCE_PRIVATE_SPACE);
80 case PSW_ASC_HOME:
81 return !(env->cregs[13] & ASCE_PRIVATE_SPACE);
82 default:
83 /* We don't support access register mode */
84 error_report("unsupported addressing mode");
85 exit(1);
86 }
87 }
88
89 /**
90 * Translate real address to absolute (= physical)
91 * address by taking care of the prefix mapping.
92 */
93 hwaddr mmu_real2abs(CPUS390XState *env, hwaddr raddr)
94 {
95 if (raddr < 0x2000) {
96 return raddr + env->psa; /* Map the lowcore. */
97 } else if (raddr >= env->psa && raddr < env->psa + 0x2000) {
98 return raddr - env->psa; /* Map the 0 page. */
99 }
100 return raddr;
101 }
102
103 bool mmu_absolute_addr_valid(hwaddr addr, bool is_write)
104 {
105 return address_space_access_valid(&address_space_memory,
106 addr & TARGET_PAGE_MASK,
107 TARGET_PAGE_SIZE, is_write,
108 MEMTXATTRS_UNSPECIFIED);
109 }
110
111 static inline bool read_table_entry(CPUS390XState *env, hwaddr gaddr,
112 uint64_t *entry)
113 {
114 CPUState *cs = env_cpu(env);
115 MemTxResult ret;
116
117 /*
118 * According to the PoP, these table addresses are "unpredictably real
119 * or absolute". Also, "it is unpredictable whether the address wraps
120 * or an addressing exception is recognized".
121 *
122 * We treat them as absolute addresses and don't wrap them.
123 */
124 *entry = address_space_ldq_be(cs->as, gaddr, MEMTXATTRS_UNSPECIFIED, &ret);
125
126 return ret == MEMTX_OK;
127 }
128
129 static int mmu_translate_asce(CPUS390XState *env, vaddr vaddr,
130 uint64_t asc, uint64_t asce, hwaddr *raddr,
131 int *flags)
132 {
133 const bool edat1 = (env->cregs[0] & CR0_EDAT) &&
134 s390_has_feat(S390_FEAT_EDAT);
135 const bool edat2 = edat1 && s390_has_feat(S390_FEAT_EDAT_2);
136 const bool iep = (env->cregs[0] & CR0_IEP) &&
137 s390_has_feat(S390_FEAT_INSTRUCTION_EXEC_PROT);
138 const int asce_tl = asce & ASCE_TABLE_LENGTH;
139 const int asce_p = asce & ASCE_PRIVATE_SPACE;
140 hwaddr gaddr = asce & ASCE_ORIGIN;
141 uint64_t entry;
142
143 if (asce & ASCE_REAL_SPACE) {
144 /* direct mapping */
145 *raddr = vaddr;
146 return 0;
147 }
148
149 switch (asce & ASCE_TYPE_MASK) {
150 case ASCE_TYPE_REGION1:
151 if (VADDR_REGION1_TL(vaddr) > asce_tl) {
152 return PGM_REG_FIRST_TRANS;
153 }
154 gaddr += VADDR_REGION1_TX(vaddr) * 8;
155 break;
156 case ASCE_TYPE_REGION2:
157 if (VADDR_REGION1_TX(vaddr)) {
158 return PGM_ASCE_TYPE;
159 }
160 if (VADDR_REGION2_TL(vaddr) > asce_tl) {
161 return PGM_REG_SEC_TRANS;
162 }
163 gaddr += VADDR_REGION2_TX(vaddr) * 8;
164 break;
165 case ASCE_TYPE_REGION3:
166 if (VADDR_REGION1_TX(vaddr) || VADDR_REGION2_TX(vaddr)) {
167 return PGM_ASCE_TYPE;
168 }
169 if (VADDR_REGION3_TL(vaddr) > asce_tl) {
170 return PGM_REG_THIRD_TRANS;
171 }
172 gaddr += VADDR_REGION3_TX(vaddr) * 8;
173 break;
174 case ASCE_TYPE_SEGMENT:
175 if (VADDR_REGION1_TX(vaddr) || VADDR_REGION2_TX(vaddr) ||
176 VADDR_REGION3_TX(vaddr)) {
177 return PGM_ASCE_TYPE;
178 }
179 if (VADDR_SEGMENT_TL(vaddr) > asce_tl) {
180 return PGM_SEGMENT_TRANS;
181 }
182 gaddr += VADDR_SEGMENT_TX(vaddr) * 8;
183 break;
184 }
185
186 switch (asce & ASCE_TYPE_MASK) {
187 case ASCE_TYPE_REGION1:
188 if (!read_table_entry(env, gaddr, &entry)) {
189 return PGM_ADDRESSING;
190 }
191 if (entry & REGION_ENTRY_I) {
192 return PGM_REG_FIRST_TRANS;
193 }
194 if ((entry & REGION_ENTRY_TT) != REGION_ENTRY_TT_REGION1) {
195 return PGM_TRANS_SPEC;
196 }
197 if (VADDR_REGION2_TL(vaddr) < (entry & REGION_ENTRY_TF) >> 6 ||
198 VADDR_REGION2_TL(vaddr) > (entry & REGION_ENTRY_TL)) {
199 return PGM_REG_SEC_TRANS;
200 }
201 if (edat1 && (entry & REGION_ENTRY_P)) {
202 *flags &= ~PAGE_WRITE;
203 }
204 gaddr = (entry & REGION_ENTRY_ORIGIN) + VADDR_REGION2_TX(vaddr) * 8;
205 /* fall through */
206 case ASCE_TYPE_REGION2:
207 if (!read_table_entry(env, gaddr, &entry)) {
208 return PGM_ADDRESSING;
209 }
210 if (entry & REGION_ENTRY_I) {
211 return PGM_REG_SEC_TRANS;
212 }
213 if ((entry & REGION_ENTRY_TT) != REGION_ENTRY_TT_REGION2) {
214 return PGM_TRANS_SPEC;
215 }
216 if (VADDR_REGION3_TL(vaddr) < (entry & REGION_ENTRY_TF) >> 6 ||
217 VADDR_REGION3_TL(vaddr) > (entry & REGION_ENTRY_TL)) {
218 return PGM_REG_THIRD_TRANS;
219 }
220 if (edat1 && (entry & REGION_ENTRY_P)) {
221 *flags &= ~PAGE_WRITE;
222 }
223 gaddr = (entry & REGION_ENTRY_ORIGIN) + VADDR_REGION3_TX(vaddr) * 8;
224 /* fall through */
225 case ASCE_TYPE_REGION3:
226 if (!read_table_entry(env, gaddr, &entry)) {
227 return PGM_ADDRESSING;
228 }
229 if (entry & REGION_ENTRY_I) {
230 return PGM_REG_THIRD_TRANS;
231 }
232 if ((entry & REGION_ENTRY_TT) != REGION_ENTRY_TT_REGION3) {
233 return PGM_TRANS_SPEC;
234 }
235 if (edat2 && (entry & REGION3_ENTRY_CR) && asce_p) {
236 return PGM_TRANS_SPEC;
237 }
238 if (edat1 && (entry & REGION_ENTRY_P)) {
239 *flags &= ~PAGE_WRITE;
240 }
241 if (edat2 && (entry & REGION3_ENTRY_FC)) {
242 if (iep && (entry & REGION3_ENTRY_IEP)) {
243 *flags &= ~PAGE_EXEC;
244 }
245 *raddr = (entry & REGION3_ENTRY_RFAA) |
246 (vaddr & ~REGION3_ENTRY_RFAA);
247 return 0;
248 }
249 if (VADDR_SEGMENT_TL(vaddr) < (entry & REGION_ENTRY_TF) >> 6 ||
250 VADDR_SEGMENT_TL(vaddr) > (entry & REGION_ENTRY_TL)) {
251 return PGM_SEGMENT_TRANS;
252 }
253 gaddr = (entry & REGION_ENTRY_ORIGIN) + VADDR_SEGMENT_TX(vaddr) * 8;
254 /* fall through */
255 case ASCE_TYPE_SEGMENT:
256 if (!read_table_entry(env, gaddr, &entry)) {
257 return PGM_ADDRESSING;
258 }
259 if (entry & SEGMENT_ENTRY_I) {
260 return PGM_SEGMENT_TRANS;
261 }
262 if ((entry & SEGMENT_ENTRY_TT) != SEGMENT_ENTRY_TT_SEGMENT) {
263 return PGM_TRANS_SPEC;
264 }
265 if ((entry & SEGMENT_ENTRY_CS) && asce_p) {
266 return PGM_TRANS_SPEC;
267 }
268 if (entry & SEGMENT_ENTRY_P) {
269 *flags &= ~PAGE_WRITE;
270 }
271 if (edat1 && (entry & SEGMENT_ENTRY_FC)) {
272 if (iep && (entry & SEGMENT_ENTRY_IEP)) {
273 *flags &= ~PAGE_EXEC;
274 }
275 *raddr = (entry & SEGMENT_ENTRY_SFAA) |
276 (vaddr & ~SEGMENT_ENTRY_SFAA);
277 return 0;
278 }
279 gaddr = (entry & SEGMENT_ENTRY_ORIGIN) + VADDR_PAGE_TX(vaddr) * 8;
280 break;
281 }
282
283 if (!read_table_entry(env, gaddr, &entry)) {
284 return PGM_ADDRESSING;
285 }
286 if (entry & PAGE_ENTRY_I) {
287 return PGM_PAGE_TRANS;
288 }
289 if (entry & PAGE_ENTRY_0) {
290 return PGM_TRANS_SPEC;
291 }
292 if (entry & PAGE_ENTRY_P) {
293 *flags &= ~PAGE_WRITE;
294 }
295 if (iep && (entry & PAGE_ENTRY_IEP)) {
296 *flags &= ~PAGE_EXEC;
297 }
298
299 *raddr = entry & TARGET_PAGE_MASK;
300 return 0;
301 }
302
303 static void mmu_handle_skey(hwaddr addr, int rw, int *flags)
304 {
305 static S390SKeysClass *skeyclass;
306 static S390SKeysState *ss;
307 uint8_t key, old_key;
308
309 /*
310 * We expect to be called with an absolute address that has already been
311 * validated, such that we can reliably use it to lookup the storage key.
312 */
313 if (unlikely(!ss)) {
314 ss = s390_get_skeys_device();
315 skeyclass = S390_SKEYS_GET_CLASS(ss);
316 }
317
318 /*
319 * Don't enable storage keys if they are still disabled, i.e., no actual
320 * storage key instruction was issued yet.
321 */
322 if (!skeyclass->skeys_are_enabled(ss)) {
323 return;
324 }
325
326 /*
327 * Whenever we create a new TLB entry, we set the storage key reference
328 * bit. In case we allow write accesses, we set the storage key change
329 * bit. Whenever the guest changes the storage key, we have to flush the
330 * TLBs of all CPUs (the whole TLB or all affected entries), so that the
331 * next reference/change will result in an MMU fault and make us properly
332 * update the storage key here.
333 *
334 * Note 1: "record of references ... is not necessarily accurate",
335 * "change bit may be set in case no storing has occurred".
336 * -> We can set reference/change bits even on exceptions.
337 * Note 2: certain accesses seem to ignore storage keys. For example,
338 * DAT translation does not set reference bits for table accesses.
339 *
340 * TODO: key-controlled protection. Only CPU accesses make use of the
341 * PSW key. CSS accesses are different - we have to pass in the key.
342 *
343 * TODO: we have races between getting and setting the key.
344 */
345 if (s390_skeys_get(ss, addr / TARGET_PAGE_SIZE, 1, &key)) {
346 return;
347 }
348 old_key = key;
349
350 switch (rw) {
351 case MMU_DATA_LOAD:
352 case MMU_INST_FETCH:
353 /*
354 * The TLB entry has to remain write-protected on read-faults if
355 * the storage key does not indicate a change already. Otherwise
356 * we might miss setting the change bit on write accesses.
357 */
358 if (!(key & SK_C)) {
359 *flags &= ~PAGE_WRITE;
360 }
361 break;
362 case MMU_DATA_STORE:
363 key |= SK_C;
364 break;
365 default:
366 g_assert_not_reached();
367 }
368
369 /* Any store/fetch sets the reference bit */
370 key |= SK_R;
371
372 if (key != old_key) {
373 s390_skeys_set(ss, addr / TARGET_PAGE_SIZE, 1, &key);
374 }
375 }
376
377 /**
378 * Translate a virtual (logical) address into a physical (absolute) address.
379 * @param vaddr the virtual address
380 * @param rw 0 = read, 1 = write, 2 = code fetch, < 0 = load real address
381 * @param asc address space control (one of the PSW_ASC_* modes)
382 * @param raddr the translated address is stored to this pointer
383 * @param flags the PAGE_READ/WRITE/EXEC flags are stored to this pointer
384 * @param tec the translation exception code if stored to this pointer if
385 * there is an exception to raise
386 * @return 0 = success, != 0, the exception to raise
387 */
388 int mmu_translate(CPUS390XState *env, vaddr vaddr, int rw, uint64_t asc,
389 hwaddr *raddr, int *flags, uint64_t *tec)
390 {
391 uint64_t asce;
392 int r;
393
394 *tec = (vaddr & TARGET_PAGE_MASK) | (asc >> 46) |
395 (rw == MMU_DATA_STORE ? FS_WRITE : FS_READ);
396 *flags = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
397
398 if (is_low_address(vaddr & TARGET_PAGE_MASK) && lowprot_enabled(env, asc)) {
399 /*
400 * If any part of this page is currently protected, make sure the
401 * TLB entry will not be reused.
402 *
403 * As the protected range is always the first 512 bytes of the
404 * two first pages, we are able to catch all writes to these areas
405 * just by looking at the start address (triggering the tlb miss).
406 */
407 *flags |= PAGE_WRITE_INV;
408 if (is_low_address(vaddr) && rw == MMU_DATA_STORE) {
409 /* LAP sets bit 56 */
410 *tec |= 0x80;
411 return PGM_PROTECTION;
412 }
413 }
414
415 vaddr &= TARGET_PAGE_MASK;
416
417 if (rw != MMU_S390_LRA && !(env->psw.mask & PSW_MASK_DAT)) {
418 *raddr = vaddr;
419 goto nodat;
420 }
421
422 switch (asc) {
423 case PSW_ASC_PRIMARY:
424 asce = env->cregs[1];
425 break;
426 case PSW_ASC_HOME:
427 asce = env->cregs[13];
428 break;
429 case PSW_ASC_SECONDARY:
430 asce = env->cregs[7];
431 break;
432 case PSW_ASC_ACCREG:
433 default:
434 hw_error("guest switched to unknown asc mode\n");
435 break;
436 }
437
438 /* perform the DAT translation */
439 r = mmu_translate_asce(env, vaddr, asc, asce, raddr, flags);
440 if (unlikely(r)) {
441 return r;
442 }
443
444 /* check for DAT protection */
445 if (unlikely(rw == MMU_DATA_STORE && !(*flags & PAGE_WRITE))) {
446 /* DAT sets bit 61 only */
447 *tec |= 0x4;
448 return PGM_PROTECTION;
449 }
450
451 /* check for Instruction-Execution-Protection */
452 if (unlikely(rw == MMU_INST_FETCH && !(*flags & PAGE_EXEC))) {
453 /* IEP sets bit 56 and 61 */
454 *tec |= 0x84;
455 return PGM_PROTECTION;
456 }
457
458 nodat:
459 if (rw >= 0) {
460 /* Convert real address -> absolute address */
461 *raddr = mmu_real2abs(env, *raddr);
462
463 if (!mmu_absolute_addr_valid(*raddr, rw == MMU_DATA_STORE)) {
464 *tec = 0; /* unused */
465 return PGM_ADDRESSING;
466 }
467
468 mmu_handle_skey(*raddr, rw, flags);
469 }
470 return 0;
471 }
472
473 /**
474 * translate_pages: Translate a set of consecutive logical page addresses
475 * to absolute addresses. This function is used for TCG and old KVM without
476 * the MEMOP interface.
477 */
478 static int translate_pages(S390CPU *cpu, vaddr addr, int nr_pages,
479 hwaddr *pages, bool is_write, uint64_t *tec)
480 {
481 uint64_t asc = cpu->env.psw.mask & PSW_MASK_ASC;
482 CPUS390XState *env = &cpu->env;
483 int ret, i, pflags;
484
485 for (i = 0; i < nr_pages; i++) {
486 ret = mmu_translate(env, addr, is_write, asc, &pages[i], &pflags, tec);
487 if (ret) {
488 return ret;
489 }
490 addr += TARGET_PAGE_SIZE;
491 }
492
493 return 0;
494 }
495
496 int s390_cpu_pv_mem_rw(S390CPU *cpu, unsigned int offset, void *hostbuf,
497 int len, bool is_write)
498 {
499 int ret;
500
501 if (kvm_enabled()) {
502 ret = kvm_s390_mem_op_pv(cpu, offset, hostbuf, len, is_write);
503 } else {
504 /* Protected Virtualization is a KVM/Hardware only feature */
505 g_assert_not_reached();
506 }
507 return ret;
508 }
509
510 /**
511 * s390_cpu_virt_mem_rw:
512 * @laddr: the logical start address
513 * @ar: the access register number
514 * @hostbuf: buffer in host memory. NULL = do only checks w/o copying
515 * @len: length that should be transferred
516 * @is_write: true = write, false = read
517 * Returns: 0 on success, non-zero if an exception occurred
518 *
519 * Copy from/to guest memory using logical addresses. Note that we inject a
520 * program interrupt in case there is an error while accessing the memory.
521 *
522 * This function will always return (also for TCG), make sure to call
523 * s390_cpu_virt_mem_handle_exc() to properly exit the CPU loop.
524 */
525 int s390_cpu_virt_mem_rw(S390CPU *cpu, vaddr laddr, uint8_t ar, void *hostbuf,
526 int len, bool is_write)
527 {
528 const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
529 int currlen, nr_pages, i;
530 hwaddr *pages;
531 uint64_t tec;
532 int ret;
533
534 if (kvm_enabled()) {
535 ret = kvm_s390_mem_op(cpu, laddr, ar, hostbuf, len, is_write);
536 if (ret >= 0) {
537 return ret;
538 }
539 }
540
541 nr_pages = (((laddr & ~TARGET_PAGE_MASK) + len - 1) >> TARGET_PAGE_BITS)
542 + 1;
543 pages = g_malloc(nr_pages * sizeof(*pages));
544
545 ret = translate_pages(cpu, laddr, nr_pages, pages, is_write, &tec);
546 if (ret == 0 && hostbuf != NULL) {
547 AddressSpace *as = CPU(cpu)->as;
548
549 /* Copy data by stepping through the area page by page */
550 for (i = 0; i < nr_pages; i++) {
551 MemTxResult res;
552
553 currlen = MIN(len, TARGET_PAGE_SIZE - (laddr % TARGET_PAGE_SIZE));
554 res = address_space_rw(as, pages[i] | (laddr & ~TARGET_PAGE_MASK),
555 attrs, hostbuf, currlen, is_write);
556 if (res != MEMTX_OK) {
557 ret = PGM_ADDRESSING;
558 break;
559 }
560 laddr += currlen;
561 hostbuf += currlen;
562 len -= currlen;
563 }
564 }
565 if (ret) {
566 trigger_access_exception(&cpu->env, ret, tec);
567 }
568
569 g_free(pages);
570 return ret;
571 }
572
573 void s390_cpu_virt_mem_handle_exc(S390CPU *cpu, uintptr_t ra)
574 {
575 /* KVM will handle the interrupt automatically, TCG has to exit the TB */
576 #ifdef CONFIG_TCG
577 if (tcg_enabled()) {
578 cpu_loop_exit_restore(CPU(cpu), ra);
579 }
580 #endif
581 }
582
583 /**
584 * Translate a real address into a physical (absolute) address.
585 * @param raddr the real address
586 * @param rw 0 = read, 1 = write, 2 = code fetch
587 * @param addr the translated address is stored to this pointer
588 * @param flags the PAGE_READ/WRITE/EXEC flags are stored to this pointer
589 * @return 0 = success, != 0, the exception to raise
590 */
591 int mmu_translate_real(CPUS390XState *env, hwaddr raddr, int rw,
592 hwaddr *addr, int *flags, uint64_t *tec)
593 {
594 const bool lowprot_enabled = env->cregs[0] & CR0_LOWPROT;
595
596 *flags = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
597 if (is_low_address(raddr & TARGET_PAGE_MASK) && lowprot_enabled) {
598 /* see comment in mmu_translate() how this works */
599 *flags |= PAGE_WRITE_INV;
600 if (is_low_address(raddr) && rw == MMU_DATA_STORE) {
601 /* LAP sets bit 56 */
602 *tec = (raddr & TARGET_PAGE_MASK) | FS_WRITE | 0x80;
603 return PGM_PROTECTION;
604 }
605 }
606
607 *addr = mmu_real2abs(env, raddr & TARGET_PAGE_MASK);
608
609 if (!mmu_absolute_addr_valid(*addr, rw == MMU_DATA_STORE)) {
610 /* unused */
611 *tec = 0;
612 return PGM_ADDRESSING;
613 }
614
615 mmu_handle_skey(*addr, rw, flags);
616 return 0;
617 }