| 1 | /* |
| 2 | * SH4 emulation |
| 3 | * |
| 4 | * Copyright (c) 2005 Samuel Tardieu |
| 5 | * |
| 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2.1 of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU Lesser General Public |
| 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
| 18 | */ |
| 19 | |
| 20 | #ifndef SH4_CPU_H |
| 21 | #define SH4_CPU_H |
| 22 | |
| 23 | #include "cpu-qom.h" |
| 24 | #include "exec/cpu-common.h" |
| 25 | #include "exec/cpu-interrupt.h" |
| 26 | #include "qemu/cpu-float.h" |
| 27 | |
| 28 | /* CPU Subtypes */ |
| 29 | #define SH_CPU_SH7750 (1 << 0) |
| 30 | #define SH_CPU_SH7750S (1 << 1) |
| 31 | #define SH_CPU_SH7750R (1 << 2) |
| 32 | #define SH_CPU_SH7751 (1 << 3) |
| 33 | #define SH_CPU_SH7751R (1 << 4) |
| 34 | #define SH_CPU_SH7785 (1 << 5) |
| 35 | #define SH_CPU_SH7750_ALL (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7750R) |
| 36 | #define SH_CPU_SH7751_ALL (SH_CPU_SH7751 | SH_CPU_SH7751R) |
| 37 | |
| 38 | #define SR_MD 30 |
| 39 | #define SR_RB 29 |
| 40 | #define SR_BL 28 |
| 41 | #define SR_FD 15 |
| 42 | #define SR_M 9 |
| 43 | #define SR_Q 8 |
| 44 | #define SR_I3 7 |
| 45 | #define SR_I2 6 |
| 46 | #define SR_I1 5 |
| 47 | #define SR_I0 4 |
| 48 | #define SR_S 1 |
| 49 | #define SR_T 0 |
| 50 | |
| 51 | #define FPSCR_MASK (0x003fffff) |
| 52 | #define FPSCR_FR (1 << 21) |
| 53 | #define FPSCR_SZ (1 << 20) |
| 54 | #define FPSCR_PR (1 << 19) |
| 55 | #define FPSCR_DN (1 << 18) |
| 56 | #define FPSCR_CAUSE_MASK (0x3f << 12) |
| 57 | #define FPSCR_CAUSE_SHIFT (12) |
| 58 | #define FPSCR_CAUSE_E (1 << 17) |
| 59 | #define FPSCR_CAUSE_V (1 << 16) |
| 60 | #define FPSCR_CAUSE_Z (1 << 15) |
| 61 | #define FPSCR_CAUSE_O (1 << 14) |
| 62 | #define FPSCR_CAUSE_U (1 << 13) |
| 63 | #define FPSCR_CAUSE_I (1 << 12) |
| 64 | #define FPSCR_ENABLE_MASK (0x1f << 7) |
| 65 | #define FPSCR_ENABLE_SHIFT (7) |
| 66 | #define FPSCR_ENABLE_V (1 << 11) |
| 67 | #define FPSCR_ENABLE_Z (1 << 10) |
| 68 | #define FPSCR_ENABLE_O (1 << 9) |
| 69 | #define FPSCR_ENABLE_U (1 << 8) |
| 70 | #define FPSCR_ENABLE_I (1 << 7) |
| 71 | #define FPSCR_FLAG_MASK (0x1f << 2) |
| 72 | #define FPSCR_FLAG_SHIFT (2) |
| 73 | #define FPSCR_FLAG_V (1 << 6) |
| 74 | #define FPSCR_FLAG_Z (1 << 5) |
| 75 | #define FPSCR_FLAG_O (1 << 4) |
| 76 | #define FPSCR_FLAG_U (1 << 3) |
| 77 | #define FPSCR_FLAG_I (1 << 2) |
| 78 | #define FPSCR_RM_MASK (0x03 << 0) |
| 79 | #define FPSCR_RM_NEAREST (0 << 0) |
| 80 | #define FPSCR_RM_ZERO (1 << 0) |
| 81 | |
| 82 | #define TB_FLAG_DELAY_SLOT (1 << 0) |
| 83 | #define TB_FLAG_DELAY_SLOT_COND (1 << 1) |
| 84 | #define TB_FLAG_DELAY_SLOT_RTE (1 << 2) |
| 85 | #define TB_FLAG_PENDING_MOVCA (1 << 3) |
| 86 | #define TB_FLAG_GUSA_SHIFT 4 /* [11:4] */ |
| 87 | #define TB_FLAG_GUSA_EXCLUSIVE (1 << 12) |
| 88 | #define TB_FLAG_UNALIGN (1 << 13) |
| 89 | #define TB_FLAG_SR_FD (1 << SR_FD) /* 15 */ |
| 90 | #define TB_FLAG_FPSCR_PR FPSCR_PR /* 19 */ |
| 91 | #define TB_FLAG_FPSCR_SZ FPSCR_SZ /* 20 */ |
| 92 | #define TB_FLAG_FPSCR_FR FPSCR_FR /* 21 */ |
| 93 | #define TB_FLAG_SR_RB (1 << SR_RB) /* 29 */ |
| 94 | #define TB_FLAG_SR_MD (1 << SR_MD) /* 30 */ |
| 95 | |
| 96 | #define TB_FLAG_DELAY_SLOT_MASK (TB_FLAG_DELAY_SLOT | \ |
| 97 | TB_FLAG_DELAY_SLOT_COND | \ |
| 98 | TB_FLAG_DELAY_SLOT_RTE) |
| 99 | #define TB_FLAG_GUSA_MASK ((0xff << TB_FLAG_GUSA_SHIFT) | \ |
| 100 | TB_FLAG_GUSA_EXCLUSIVE) |
| 101 | #define TB_FLAG_FPSCR_MASK (TB_FLAG_FPSCR_PR | \ |
| 102 | TB_FLAG_FPSCR_SZ | \ |
| 103 | TB_FLAG_FPSCR_FR) |
| 104 | #define TB_FLAG_SR_MASK (TB_FLAG_SR_FD | \ |
| 105 | TB_FLAG_SR_RB | \ |
| 106 | TB_FLAG_SR_MD) |
| 107 | #define TB_FLAG_ENVFLAGS_MASK (TB_FLAG_DELAY_SLOT_MASK | \ |
| 108 | TB_FLAG_GUSA_MASK) |
| 109 | |
| 110 | typedef struct tlb_t { |
| 111 | uint32_t vpn; /* virtual page number */ |
| 112 | uint32_t ppn; /* physical page number */ |
| 113 | uint32_t size; /* mapped page size in bytes */ |
| 114 | uint8_t asid; /* address space identifier */ |
| 115 | uint8_t v:1; /* validity */ |
| 116 | uint8_t sz:2; /* page size */ |
| 117 | uint8_t sh:1; /* share status */ |
| 118 | uint8_t c:1; /* cacheability */ |
| 119 | uint8_t pr:2; /* protection key */ |
| 120 | uint8_t d:1; /* dirty */ |
| 121 | uint8_t wt:1; /* write through */ |
| 122 | uint8_t sa:3; /* space attribute (PCMCIA) */ |
| 123 | uint8_t tc:1; /* timing control */ |
| 124 | } tlb_t; |
| 125 | |
| 126 | #define UTLB_SIZE 64 |
| 127 | #define ITLB_SIZE 4 |
| 128 | |
| 129 | enum sh_features { |
| 130 | SH_FEATURE_SH4A = 1, |
| 131 | SH_FEATURE_BCR3_AND_BCR4 = 2, |
| 132 | }; |
| 133 | |
| 134 | typedef struct memory_content { |
| 135 | uint32_t address; |
| 136 | uint32_t value; |
| 137 | struct memory_content *next; |
| 138 | } memory_content; |
| 139 | |
| 140 | typedef struct CPUArchState { |
| 141 | uint32_t flags; /* general execution flags */ |
| 142 | uint32_t gregs[24]; /* general registers */ |
| 143 | float32 fregs[32]; /* floating point registers */ |
| 144 | uint32_t sr; /* status register (with T split out) */ |
| 145 | uint32_t sr_m; /* M bit of status register */ |
| 146 | uint32_t sr_q; /* Q bit of status register */ |
| 147 | uint32_t sr_t; /* T bit of status register */ |
| 148 | uint32_t ssr; /* saved status register */ |
| 149 | uint32_t spc; /* saved program counter */ |
| 150 | uint32_t gbr; /* global base register */ |
| 151 | uint32_t vbr; /* vector base register */ |
| 152 | uint32_t sgr; /* saved global register 15 */ |
| 153 | uint32_t dbr; /* debug base register */ |
| 154 | uint32_t pc; /* program counter */ |
| 155 | uint32_t delayed_pc; /* target of delayed branch */ |
| 156 | uint32_t delayed_cond; /* condition of delayed branch */ |
| 157 | uint32_t pr; /* procedure register */ |
| 158 | uint32_t fpscr; /* floating point status/control register */ |
| 159 | uint32_t fpul; /* floating point communication register */ |
| 160 | |
| 161 | /* multiply and accumulate: high, low and combined. */ |
| 162 | union { |
| 163 | uint64_t mac; |
| 164 | struct { |
| 165 | #if HOST_BIG_ENDIAN |
| 166 | uint32_t mach, macl; |
| 167 | #else |
| 168 | uint32_t macl, mach; |
| 169 | #endif |
| 170 | }; |
| 171 | }; |
| 172 | |
| 173 | /* float point status register */ |
| 174 | float_status fp_status; |
| 175 | |
| 176 | /* Those belong to the specific unit (SH7750) but are handled here */ |
| 177 | uint32_t mmucr; /* MMU control register */ |
| 178 | uint32_t pteh; /* page table entry high register */ |
| 179 | uint32_t ptel; /* page table entry low register */ |
| 180 | uint32_t ptea; /* page table entry assistance register */ |
| 181 | uint32_t ttb; /* translation table base register */ |
| 182 | uint32_t tea; /* TLB exception address register */ |
| 183 | uint32_t tra; /* TRAPA exception register */ |
| 184 | uint32_t expevt; /* exception event register */ |
| 185 | uint32_t intevt; /* interrupt event register */ |
| 186 | |
| 187 | tlb_t itlb[ITLB_SIZE]; /* instruction translation table */ |
| 188 | tlb_t utlb[UTLB_SIZE]; /* unified translation table */ |
| 189 | |
| 190 | /* LDST = LOCK_ADDR != -1. */ |
| 191 | uint32_t lock_addr; |
| 192 | uint32_t lock_value; |
| 193 | |
| 194 | /* Fields up to this point are cleared by a CPU reset */ |
| 195 | struct {} end_reset_fields; |
| 196 | |
| 197 | /* Fields from here on are preserved over CPU reset. */ |
| 198 | int id; /* CPU model */ |
| 199 | |
| 200 | /* The features that we should emulate. See sh_features above. */ |
| 201 | uint32_t features; |
| 202 | |
| 203 | void *intc_handle; |
| 204 | int in_sleep; /* SR_BL ignored during sleep */ |
| 205 | memory_content *movcal_backup; |
| 206 | memory_content **movcal_backup_tail; |
| 207 | } CPUSH4State; |
| 208 | |
| 209 | /** |
| 210 | * SuperHCPU: |
| 211 | * @env: #CPUSH4State |
| 212 | * |
| 213 | * A SuperH CPU. |
| 214 | */ |
| 215 | struct ArchCPU { |
| 216 | CPUState parent_obj; |
| 217 | |
| 218 | CPUSH4State env; |
| 219 | }; |
| 220 | |
| 221 | /** |
| 222 | * SuperHCPUClass: |
| 223 | * @parent_realize: The parent class' realize handler. |
| 224 | * @parent_phases: The parent class' reset phase handlers. |
| 225 | * @pvr: Processor Version Register |
| 226 | * @prr: Processor Revision Register |
| 227 | * @cvr: Cache Version Register |
| 228 | * |
| 229 | * A SuperH CPU model. |
| 230 | */ |
| 231 | struct SuperHCPUClass { |
| 232 | CPUClass parent_class; |
| 233 | |
| 234 | DeviceRealize parent_realize; |
| 235 | ResettablePhases parent_phases; |
| 236 | |
| 237 | uint32_t pvr; |
| 238 | uint32_t prr; |
| 239 | uint32_t cvr; |
| 240 | }; |
| 241 | |
| 242 | void superh_cpu_dump_state(CPUState *cpu, FILE *f, int flags); |
| 243 | int superh_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); |
| 244 | int superh_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); |
| 245 | G_NORETURN void superh_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, |
| 246 | MMUAccessType access_type, int mmu_idx, |
| 247 | uintptr_t retaddr); |
| 248 | |
| 249 | void sh4_translate_init(void); |
| 250 | void sh4_translate_code(CPUState *cs, TranslationBlock *tb, |
| 251 | int *max_insns, vaddr pc, void *host_pc); |
| 252 | |
| 253 | #if !defined(CONFIG_USER_ONLY) |
| 254 | hwaddr superh_cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr); |
| 255 | bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size, |
| 256 | MMUAccessType access_type, int mmu_idx, |
| 257 | bool probe, uintptr_t retaddr); |
| 258 | void superh_cpu_do_interrupt(CPUState *cpu); |
| 259 | bool superh_cpu_exec_interrupt(CPUState *cpu, int int_req); |
| 260 | void cpu_sh4_invalidate_tlb(CPUSH4State *s); |
| 261 | uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s, |
| 262 | hwaddr addr); |
| 263 | void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, hwaddr addr, |
| 264 | uint32_t mem_value); |
| 265 | uint32_t cpu_sh4_read_mmaped_itlb_data(CPUSH4State *s, |
| 266 | hwaddr addr); |
| 267 | void cpu_sh4_write_mmaped_itlb_data(CPUSH4State *s, hwaddr addr, |
| 268 | uint32_t mem_value); |
| 269 | uint32_t cpu_sh4_read_mmaped_utlb_addr(CPUSH4State *s, |
| 270 | hwaddr addr); |
| 271 | void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, hwaddr addr, |
| 272 | uint32_t mem_value); |
| 273 | uint32_t cpu_sh4_read_mmaped_utlb_data(CPUSH4State *s, |
| 274 | hwaddr addr); |
| 275 | void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, hwaddr addr, |
| 276 | uint32_t mem_value); |
| 277 | #endif |
| 278 | |
| 279 | int cpu_sh4_is_cached(CPUSH4State *env, uint32_t addr); |
| 280 | |
| 281 | void cpu_load_tlb(CPUSH4State * env); |
| 282 | |
| 283 | #define CPU_RESOLVING_TYPE TYPE_SUPERH_CPU |
| 284 | |
| 285 | /* MMU modes definitions */ |
| 286 | #define MMU_USER_IDX 1 |
| 287 | |
| 288 | /* MMU control register */ |
| 289 | #define MMUCR 0x1F000010 |
| 290 | #define MMUCR_AT (1<<0) |
| 291 | #define MMUCR_TI (1<<2) |
| 292 | #define MMUCR_SV (1<<8) |
| 293 | #define MMUCR_URC_BITS (6) |
| 294 | #define MMUCR_URC_OFFSET (10) |
| 295 | #define MMUCR_URC_SIZE (1 << MMUCR_URC_BITS) |
| 296 | #define MMUCR_URC_MASK (((MMUCR_URC_SIZE) - 1) << MMUCR_URC_OFFSET) |
| 297 | static inline int cpu_mmucr_urc (uint32_t mmucr) |
| 298 | { |
| 299 | return ((mmucr & MMUCR_URC_MASK) >> MMUCR_URC_OFFSET); |
| 300 | } |
| 301 | |
| 302 | /* PTEH : Page Translation Entry High register */ |
| 303 | #define PTEH_ASID_BITS (8) |
| 304 | #define PTEH_ASID_SIZE (1 << PTEH_ASID_BITS) |
| 305 | #define PTEH_ASID_MASK (PTEH_ASID_SIZE - 1) |
| 306 | #define cpu_pteh_asid(pteh) ((pteh) & PTEH_ASID_MASK) |
| 307 | #define PTEH_VPN_BITS (22) |
| 308 | #define PTEH_VPN_OFFSET (10) |
| 309 | #define PTEH_VPN_SIZE (1 << PTEH_VPN_BITS) |
| 310 | #define PTEH_VPN_MASK (((PTEH_VPN_SIZE) - 1) << PTEH_VPN_OFFSET) |
| 311 | static inline int cpu_pteh_vpn (uint32_t pteh) |
| 312 | { |
| 313 | return ((pteh & PTEH_VPN_MASK) >> PTEH_VPN_OFFSET); |
| 314 | } |
| 315 | |
| 316 | /* PTEL : Page Translation Entry Low register */ |
| 317 | #define PTEL_V (1 << 8) |
| 318 | #define cpu_ptel_v(ptel) (((ptel) & PTEL_V) >> 8) |
| 319 | #define PTEL_C (1 << 3) |
| 320 | #define cpu_ptel_c(ptel) (((ptel) & PTEL_C) >> 3) |
| 321 | #define PTEL_D (1 << 2) |
| 322 | #define cpu_ptel_d(ptel) (((ptel) & PTEL_D) >> 2) |
| 323 | #define PTEL_SH (1 << 1) |
| 324 | #define cpu_ptel_sh(ptel)(((ptel) & PTEL_SH) >> 1) |
| 325 | #define PTEL_WT (1 << 0) |
| 326 | #define cpu_ptel_wt(ptel) ((ptel) & PTEL_WT) |
| 327 | |
| 328 | #define PTEL_SZ_HIGH_OFFSET (7) |
| 329 | #define PTEL_SZ_HIGH (1 << PTEL_SZ_HIGH_OFFSET) |
| 330 | #define PTEL_SZ_LOW_OFFSET (4) |
| 331 | #define PTEL_SZ_LOW (1 << PTEL_SZ_LOW_OFFSET) |
| 332 | static inline int cpu_ptel_sz (uint32_t ptel) |
| 333 | { |
| 334 | int sz; |
| 335 | sz = (ptel & PTEL_SZ_HIGH) >> PTEL_SZ_HIGH_OFFSET; |
| 336 | sz <<= 1; |
| 337 | sz |= (ptel & PTEL_SZ_LOW) >> PTEL_SZ_LOW_OFFSET; |
| 338 | return sz; |
| 339 | } |
| 340 | |
| 341 | #define PTEL_PPN_BITS (19) |
| 342 | #define PTEL_PPN_OFFSET (10) |
| 343 | #define PTEL_PPN_SIZE (1 << PTEL_PPN_BITS) |
| 344 | #define PTEL_PPN_MASK (((PTEL_PPN_SIZE) - 1) << PTEL_PPN_OFFSET) |
| 345 | static inline int cpu_ptel_ppn (uint32_t ptel) |
| 346 | { |
| 347 | return ((ptel & PTEL_PPN_MASK) >> PTEL_PPN_OFFSET); |
| 348 | } |
| 349 | |
| 350 | #define PTEL_PR_BITS (2) |
| 351 | #define PTEL_PR_OFFSET (5) |
| 352 | #define PTEL_PR_SIZE (1 << PTEL_PR_BITS) |
| 353 | #define PTEL_PR_MASK (((PTEL_PR_SIZE) - 1) << PTEL_PR_OFFSET) |
| 354 | static inline int cpu_ptel_pr (uint32_t ptel) |
| 355 | { |
| 356 | return ((ptel & PTEL_PR_MASK) >> PTEL_PR_OFFSET); |
| 357 | } |
| 358 | |
| 359 | /* PTEA : Page Translation Entry Assistance register */ |
| 360 | #define PTEA_SA_BITS (3) |
| 361 | #define PTEA_SA_SIZE (1 << PTEA_SA_BITS) |
| 362 | #define PTEA_SA_MASK (PTEA_SA_SIZE - 1) |
| 363 | #define cpu_ptea_sa(ptea) ((ptea) & PTEA_SA_MASK) |
| 364 | #define PTEA_TC (1 << 3) |
| 365 | #define cpu_ptea_tc(ptea) (((ptea) & PTEA_TC) >> 3) |
| 366 | |
| 367 | static inline uint32_t cpu_read_sr(CPUSH4State *env) |
| 368 | { |
| 369 | return env->sr | (env->sr_m << SR_M) | |
| 370 | (env->sr_q << SR_Q) | |
| 371 | (env->sr_t << SR_T); |
| 372 | } |
| 373 | |
| 374 | static inline void cpu_write_sr(CPUSH4State *env, uint32_t sr) |
| 375 | { |
| 376 | env->sr_m = (sr >> SR_M) & 1; |
| 377 | env->sr_q = (sr >> SR_Q) & 1; |
| 378 | env->sr_t = (sr >> SR_T) & 1; |
| 379 | env->sr = sr & ~((1u << SR_M) | (1u << SR_Q) | (1u << SR_T)); |
| 380 | } |
| 381 | |
| 382 | /* Set FPSCR and the derived float_status rounding/flush-to-zero state. */ |
| 383 | void cpu_load_fpscr(CPUSH4State *env, uint32_t val); |
| 384 | |
| 385 | #endif /* SH4_CPU_H */ |