| 1 | /* |
| 2 | * SH4 emulation |
| 3 | * |
| 4 | * Copyright (c) 2005 Samuel Tardieu |
| 5 | * |
| 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2.1 of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU Lesser General Public |
| 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
| 18 | */ |
| 19 | |
| 20 | #include "qemu/osdep.h" |
| 21 | |
| 22 | #include "cpu.h" |
| 23 | #include "exec/cputlb.h" |
| 24 | #include "exec/page-protection.h" |
| 25 | #include "exec/target_page.h" |
| 26 | #include "exec/log.h" |
| 27 | #include "accel/tcg/cpu-loop.h" |
| 28 | #include "qemu/plugin.h" |
| 29 | |
| 30 | #if !defined(CONFIG_USER_ONLY) |
| 31 | #include "hw/sh4/sh_intc.h" |
| 32 | #include "system/runstate.h" |
| 33 | #endif |
| 34 | |
| 35 | #define MMU_OK 0 |
| 36 | #define MMU_ITLB_MISS (-1) |
| 37 | #define MMU_ITLB_MULTIPLE (-2) |
| 38 | #define MMU_ITLB_VIOLATION (-3) |
| 39 | #define MMU_DTLB_MISS_READ (-4) |
| 40 | #define MMU_DTLB_MISS_WRITE (-5) |
| 41 | #define MMU_DTLB_INITIAL_WRITE (-6) |
| 42 | #define MMU_DTLB_VIOLATION_READ (-7) |
| 43 | #define MMU_DTLB_VIOLATION_WRITE (-8) |
| 44 | #define MMU_DTLB_MULTIPLE (-9) |
| 45 | #define MMU_DTLB_MISS (-10) |
| 46 | #define MMU_IADDR_ERROR (-11) |
| 47 | #define MMU_DADDR_ERROR_READ (-12) |
| 48 | #define MMU_DADDR_ERROR_WRITE (-13) |
| 49 | |
| 50 | #if defined(CONFIG_USER_ONLY) |
| 51 | |
| 52 | int cpu_sh4_is_cached(CPUSH4State *env, uint32_t addr) |
| 53 | { |
| 54 | /* For user mode, only U0 area is cacheable. */ |
| 55 | return !(addr & 0x80000000); |
| 56 | } |
| 57 | |
| 58 | #else /* !CONFIG_USER_ONLY */ |
| 59 | |
| 60 | void superh_cpu_do_interrupt(CPUState *cs) |
| 61 | { |
| 62 | CPUSH4State *env = cpu_env(cs); |
| 63 | int do_irq = cpu_test_interrupt(cs, CPU_INTERRUPT_HARD); |
| 64 | int do_exp, irq_vector = cs->exception_index; |
| 65 | uint64_t last_pc = env->pc; |
| 66 | |
| 67 | /* prioritize exceptions over interrupts */ |
| 68 | |
| 69 | do_exp = cs->exception_index != -1; |
| 70 | do_irq = do_irq && (cs->exception_index == -1); |
| 71 | |
| 72 | if (env->sr & (1u << SR_BL)) { |
| 73 | if (do_exp && cs->exception_index != 0x1e0) { |
| 74 | /* In theory a masked exception generates a reset exception, |
| 75 | which in turn jumps to the reset vector. However this only |
| 76 | works when using a bootloader. When using a kernel and an |
| 77 | initrd, they need to be reloaded and the program counter |
| 78 | should be loaded with the kernel entry point. |
| 79 | qemu_system_reset_request takes care of that. */ |
| 80 | qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); |
| 81 | return; |
| 82 | } |
| 83 | if (do_irq && !env->in_sleep) { |
| 84 | return; /* masked */ |
| 85 | } |
| 86 | } |
| 87 | env->in_sleep = 0; |
| 88 | |
| 89 | if (do_irq) { |
| 90 | irq_vector = sh_intc_get_pending_vector(env->intc_handle, |
| 91 | (env->sr >> 4) & 0xf); |
| 92 | if (irq_vector == -1) { |
| 93 | return; /* masked */ |
| 94 | } |
| 95 | } |
| 96 | |
| 97 | if (qemu_loglevel_mask(CPU_LOG_INT)) { |
| 98 | const char *expname; |
| 99 | switch (cs->exception_index) { |
| 100 | case 0x0e0: |
| 101 | expname = "addr_error"; |
| 102 | break; |
| 103 | case 0x040: |
| 104 | expname = "tlb_miss"; |
| 105 | break; |
| 106 | case 0x0a0: |
| 107 | expname = "tlb_violation"; |
| 108 | break; |
| 109 | case 0x180: |
| 110 | expname = "illegal_instruction"; |
| 111 | break; |
| 112 | case 0x1a0: |
| 113 | expname = "slot_illegal_instruction"; |
| 114 | break; |
| 115 | case 0x800: |
| 116 | expname = "fpu_disable"; |
| 117 | break; |
| 118 | case 0x820: |
| 119 | expname = "slot_fpu"; |
| 120 | break; |
| 121 | case 0x100: |
| 122 | expname = "data_write"; |
| 123 | break; |
| 124 | case 0x060: |
| 125 | expname = "dtlb_miss_write"; |
| 126 | break; |
| 127 | case 0x0c0: |
| 128 | expname = "dtlb_violation_write"; |
| 129 | break; |
| 130 | case 0x120: |
| 131 | expname = "fpu_exception"; |
| 132 | break; |
| 133 | case 0x080: |
| 134 | expname = "initial_page_write"; |
| 135 | break; |
| 136 | case 0x160: |
| 137 | expname = "trapa"; |
| 138 | break; |
| 139 | default: |
| 140 | expname = do_irq ? "interrupt" : "???"; |
| 141 | break; |
| 142 | } |
| 143 | qemu_log("exception 0x%03x [%s] raised\n", |
| 144 | irq_vector, expname); |
| 145 | log_cpu_state(cs, 0); |
| 146 | } |
| 147 | |
| 148 | env->ssr = cpu_read_sr(env); |
| 149 | env->spc = env->pc; |
| 150 | env->sgr = env->gregs[15]; |
| 151 | env->sr |= (1u << SR_BL) | (1u << SR_MD) | (1u << SR_RB); |
| 152 | env->lock_addr = -1; |
| 153 | |
| 154 | if (env->flags & TB_FLAG_DELAY_SLOT_MASK) { |
| 155 | /* Branch instruction should be executed again before delay slot. */ |
| 156 | env->spc -= 2; |
| 157 | /* Clear flags for exception/interrupt routine. */ |
| 158 | env->flags &= ~TB_FLAG_DELAY_SLOT_MASK; |
| 159 | } |
| 160 | |
| 161 | if (do_exp) { |
| 162 | env->expevt = cs->exception_index; |
| 163 | switch (cs->exception_index) { |
| 164 | case 0x000: |
| 165 | case 0x020: |
| 166 | case 0x140: |
| 167 | env->sr &= ~(1u << SR_FD); |
| 168 | env->sr |= 0xf << 4; /* IMASK */ |
| 169 | env->pc = 0xa0000000; |
| 170 | break; |
| 171 | case 0x040: |
| 172 | case 0x060: |
| 173 | env->pc = env->vbr + 0x400; |
| 174 | break; |
| 175 | case 0x160: |
| 176 | env->spc += 2; /* special case for TRAPA */ |
| 177 | /* fall through */ |
| 178 | default: |
| 179 | env->pc = env->vbr + 0x100; |
| 180 | break; |
| 181 | } |
| 182 | qemu_plugin_vcpu_exception_cb(cs, last_pc); |
| 183 | return; |
| 184 | } |
| 185 | |
| 186 | if (do_irq) { |
| 187 | env->intevt = irq_vector; |
| 188 | env->pc = env->vbr + 0x600; |
| 189 | qemu_plugin_vcpu_interrupt_cb(cs, last_pc); |
| 190 | return; |
| 191 | } |
| 192 | } |
| 193 | |
| 194 | static void update_itlb_use(CPUSH4State * env, int itlbnb) |
| 195 | { |
| 196 | uint32_t or_mask = 0, and_mask = 0xff; |
| 197 | |
| 198 | switch (itlbnb) { |
| 199 | case 0: |
| 200 | and_mask = 0x1f; |
| 201 | break; |
| 202 | case 1: |
| 203 | and_mask = 0xe7; |
| 204 | or_mask = 0x80; |
| 205 | break; |
| 206 | case 2: |
| 207 | and_mask = 0xfb; |
| 208 | or_mask = 0x50; |
| 209 | break; |
| 210 | case 3: |
| 211 | or_mask = 0x2c; |
| 212 | break; |
| 213 | } |
| 214 | |
| 215 | env->mmucr &= (and_mask << 24) | 0x00ffffff; |
| 216 | env->mmucr |= (or_mask << 24); |
| 217 | } |
| 218 | |
| 219 | static int itlb_replacement(CPUSH4State * env) |
| 220 | { |
| 221 | if ((env->mmucr & 0xe0000000) == 0xe0000000) { |
| 222 | return 0; |
| 223 | } |
| 224 | if ((env->mmucr & 0x98000000) == 0x18000000) { |
| 225 | return 1; |
| 226 | } |
| 227 | if ((env->mmucr & 0x54000000) == 0x04000000) { |
| 228 | return 2; |
| 229 | } |
| 230 | if ((env->mmucr & 0x2c000000) == 0x00000000) { |
| 231 | return 3; |
| 232 | } |
| 233 | cpu_abort(env_cpu(env), "Unhandled itlb_replacement"); |
| 234 | } |
| 235 | |
| 236 | /* Find the corresponding entry in the right TLB |
| 237 | Return entry, MMU_DTLB_MISS or MMU_DTLB_MULTIPLE |
| 238 | */ |
| 239 | static int find_tlb_entry(CPUSH4State *env, vaddr address, |
| 240 | tlb_t * entries, uint8_t nbtlb, int use_asid) |
| 241 | { |
| 242 | int match = MMU_DTLB_MISS; |
| 243 | vaddr start, end; |
| 244 | uint8_t asid; |
| 245 | int i; |
| 246 | |
| 247 | asid = env->pteh & 0xff; |
| 248 | |
| 249 | for (i = 0; i < nbtlb; i++) { |
| 250 | if (!entries[i].v) |
| 251 | continue; /* Invalid entry */ |
| 252 | if (!entries[i].sh && use_asid && entries[i].asid != asid) |
| 253 | continue; /* Bad ASID */ |
| 254 | start = (entries[i].vpn << 10) & ~(entries[i].size - 1); |
| 255 | end = start + entries[i].size - 1; |
| 256 | if (address >= start && address <= end) { /* Match */ |
| 257 | if (match != MMU_DTLB_MISS) |
| 258 | return MMU_DTLB_MULTIPLE; /* Multiple match */ |
| 259 | match = i; |
| 260 | } |
| 261 | } |
| 262 | return match; |
| 263 | } |
| 264 | |
| 265 | static void increment_urc(CPUSH4State * env) |
| 266 | { |
| 267 | uint8_t urb, urc; |
| 268 | |
| 269 | /* Increment URC */ |
| 270 | urb = ((env->mmucr) >> 18) & 0x3f; |
| 271 | urc = ((env->mmucr) >> 10) & 0x3f; |
| 272 | urc++; |
| 273 | if ((urb > 0 && urc > urb) || urc > (UTLB_SIZE - 1)) |
| 274 | urc = 0; |
| 275 | env->mmucr = (env->mmucr & 0xffff03ff) | (urc << 10); |
| 276 | } |
| 277 | |
| 278 | /* Copy and utlb entry into itlb |
| 279 | Return entry |
| 280 | */ |
| 281 | static int copy_utlb_entry_itlb(CPUSH4State *env, int utlb) |
| 282 | { |
| 283 | int itlb; |
| 284 | |
| 285 | tlb_t * ientry; |
| 286 | itlb = itlb_replacement(env); |
| 287 | ientry = &env->itlb[itlb]; |
| 288 | if (ientry->v) { |
| 289 | tlb_flush_page(env_cpu(env), ientry->vpn << 10); |
| 290 | } |
| 291 | *ientry = env->utlb[utlb]; |
| 292 | update_itlb_use(env, itlb); |
| 293 | return itlb; |
| 294 | } |
| 295 | |
| 296 | /* Find itlb entry |
| 297 | Return entry, MMU_ITLB_MISS, MMU_ITLB_MULTIPLE or MMU_DTLB_MULTIPLE |
| 298 | */ |
| 299 | static int find_itlb_entry(CPUSH4State *env, vaddr address, |
| 300 | int use_asid) |
| 301 | { |
| 302 | int e; |
| 303 | |
| 304 | e = find_tlb_entry(env, address, env->itlb, ITLB_SIZE, use_asid); |
| 305 | if (e == MMU_DTLB_MULTIPLE) { |
| 306 | e = MMU_ITLB_MULTIPLE; |
| 307 | } else if (e == MMU_DTLB_MISS) { |
| 308 | e = MMU_ITLB_MISS; |
| 309 | } else if (e >= 0) { |
| 310 | update_itlb_use(env, e); |
| 311 | } |
| 312 | return e; |
| 313 | } |
| 314 | |
| 315 | /* Find utlb entry |
| 316 | Return entry, MMU_DTLB_MISS, MMU_DTLB_MULTIPLE */ |
| 317 | static int find_utlb_entry(CPUSH4State *env, vaddr address, int use_asid) |
| 318 | { |
| 319 | /* per utlb access */ |
| 320 | increment_urc(env); |
| 321 | |
| 322 | /* Return entry */ |
| 323 | return find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid); |
| 324 | } |
| 325 | |
| 326 | /* Match address against MMU |
| 327 | Return MMU_OK, MMU_DTLB_MISS_READ, MMU_DTLB_MISS_WRITE, |
| 328 | MMU_DTLB_INITIAL_WRITE, MMU_DTLB_VIOLATION_READ, |
| 329 | MMU_DTLB_VIOLATION_WRITE, MMU_ITLB_MISS, |
| 330 | MMU_ITLB_MULTIPLE, MMU_ITLB_VIOLATION, |
| 331 | MMU_IADDR_ERROR, MMU_DADDR_ERROR_READ, MMU_DADDR_ERROR_WRITE. |
| 332 | */ |
| 333 | static int get_mmu_address(CPUSH4State *env, hwaddr *physical, |
| 334 | int *prot, vaddr address, |
| 335 | MMUAccessType access_type) |
| 336 | { |
| 337 | int use_asid, n; |
| 338 | tlb_t *matching = NULL; |
| 339 | |
| 340 | use_asid = !(env->mmucr & MMUCR_SV) || !(env->sr & (1u << SR_MD)); |
| 341 | |
| 342 | if (access_type == MMU_INST_FETCH) { |
| 343 | n = find_itlb_entry(env, address, use_asid); |
| 344 | if (n >= 0) { |
| 345 | matching = &env->itlb[n]; |
| 346 | if (!(env->sr & (1u << SR_MD)) && !(matching->pr & 2)) { |
| 347 | n = MMU_ITLB_VIOLATION; |
| 348 | } else { |
| 349 | *prot = PAGE_EXEC; |
| 350 | } |
| 351 | } else { |
| 352 | n = find_utlb_entry(env, address, use_asid); |
| 353 | if (n >= 0) { |
| 354 | n = copy_utlb_entry_itlb(env, n); |
| 355 | matching = &env->itlb[n]; |
| 356 | if (!(env->sr & (1u << SR_MD)) && !(matching->pr & 2)) { |
| 357 | n = MMU_ITLB_VIOLATION; |
| 358 | } else { |
| 359 | *prot = PAGE_READ | PAGE_EXEC; |
| 360 | if ((matching->pr & 1) && matching->d) { |
| 361 | *prot |= PAGE_WRITE; |
| 362 | } |
| 363 | } |
| 364 | } else if (n == MMU_DTLB_MULTIPLE) { |
| 365 | n = MMU_ITLB_MULTIPLE; |
| 366 | } else if (n == MMU_DTLB_MISS) { |
| 367 | n = MMU_ITLB_MISS; |
| 368 | } |
| 369 | } |
| 370 | } else { |
| 371 | n = find_utlb_entry(env, address, use_asid); |
| 372 | if (n >= 0) { |
| 373 | matching = &env->utlb[n]; |
| 374 | if (!(env->sr & (1u << SR_MD)) && !(matching->pr & 2)) { |
| 375 | n = (access_type == MMU_DATA_STORE) |
| 376 | ? MMU_DTLB_VIOLATION_WRITE : MMU_DTLB_VIOLATION_READ; |
| 377 | } else if ((access_type == MMU_DATA_STORE) && !(matching->pr & 1)) { |
| 378 | n = MMU_DTLB_VIOLATION_WRITE; |
| 379 | } else if ((access_type == MMU_DATA_STORE) && !matching->d) { |
| 380 | n = MMU_DTLB_INITIAL_WRITE; |
| 381 | } else { |
| 382 | *prot = PAGE_READ; |
| 383 | if ((matching->pr & 1) && matching->d) { |
| 384 | *prot |= PAGE_WRITE; |
| 385 | } |
| 386 | } |
| 387 | } else if (n == MMU_DTLB_MISS) { |
| 388 | n = (access_type == MMU_DATA_STORE) |
| 389 | ? MMU_DTLB_MISS_WRITE : MMU_DTLB_MISS_READ; |
| 390 | } |
| 391 | } |
| 392 | if (n >= 0) { |
| 393 | n = MMU_OK; |
| 394 | *physical = ((matching->ppn << 10) & ~(matching->size - 1)) |
| 395 | | (address & (matching->size - 1)); |
| 396 | } |
| 397 | return n; |
| 398 | } |
| 399 | |
| 400 | static int get_physical_address(CPUSH4State *env, hwaddr* physical, |
| 401 | int *prot, vaddr address, |
| 402 | MMUAccessType access_type) |
| 403 | { |
| 404 | /* P1, P2 and P4 areas do not use translation */ |
| 405 | if ((address >= 0x80000000 && address < 0xc0000000) || address >= 0xe0000000) { |
| 406 | if (!(env->sr & (1u << SR_MD)) |
| 407 | && (address < 0xe0000000 || address >= 0xe4000000)) { |
| 408 | /* Unauthorized access in user mode (only store queues are available) */ |
| 409 | qemu_log_mask(LOG_GUEST_ERROR, "Unauthorized access\n"); |
| 410 | if (access_type == MMU_DATA_LOAD) { |
| 411 | return MMU_DADDR_ERROR_READ; |
| 412 | } else if (access_type == MMU_DATA_STORE) { |
| 413 | return MMU_DADDR_ERROR_WRITE; |
| 414 | } else { |
| 415 | return MMU_IADDR_ERROR; |
| 416 | } |
| 417 | } |
| 418 | if (address >= 0x80000000 && address < 0xc0000000) { |
| 419 | /* Mask upper 3 bits for P1 and P2 areas */ |
| 420 | *physical = address & 0x1fffffff; |
| 421 | } else { |
| 422 | *physical = address; |
| 423 | } |
| 424 | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
| 425 | return MMU_OK; |
| 426 | } |
| 427 | |
| 428 | /* If MMU is disabled, return the corresponding physical page */ |
| 429 | if (!(env->mmucr & MMUCR_AT)) { |
| 430 | *physical = address & 0x1FFFFFFF; |
| 431 | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
| 432 | return MMU_OK; |
| 433 | } |
| 434 | |
| 435 | /* We need to resort to the MMU */ |
| 436 | return get_mmu_address(env, physical, prot, address, access_type); |
| 437 | } |
| 438 | |
| 439 | hwaddr superh_cpu_get_phys_addr_debug(CPUState *cs, vaddr addr) |
| 440 | { |
| 441 | hwaddr physical; |
| 442 | int prot; |
| 443 | |
| 444 | if (get_physical_address(cpu_env(cs), &physical, &prot, addr, MMU_DATA_LOAD) |
| 445 | == MMU_OK) { |
| 446 | return physical; |
| 447 | } |
| 448 | |
| 449 | return -1; |
| 450 | } |
| 451 | |
| 452 | void cpu_load_tlb(CPUSH4State * env) |
| 453 | { |
| 454 | CPUState *cs = env_cpu(env); |
| 455 | int n = cpu_mmucr_urc(env->mmucr); |
| 456 | tlb_t * entry = &env->utlb[n]; |
| 457 | |
| 458 | if (entry->v) { |
| 459 | /* Overwriting valid entry in utlb. */ |
| 460 | vaddr address = entry->vpn << 10; |
| 461 | tlb_flush_page(cs, address); |
| 462 | } |
| 463 | |
| 464 | /* Take values into cpu status from registers. */ |
| 465 | entry->asid = (uint8_t)cpu_pteh_asid(env->pteh); |
| 466 | entry->vpn = cpu_pteh_vpn(env->pteh); |
| 467 | entry->v = (uint8_t)cpu_ptel_v(env->ptel); |
| 468 | entry->ppn = cpu_ptel_ppn(env->ptel); |
| 469 | entry->sz = (uint8_t)cpu_ptel_sz(env->ptel); |
| 470 | switch (entry->sz) { |
| 471 | case 0: /* 00 */ |
| 472 | entry->size = 1024; /* 1K */ |
| 473 | break; |
| 474 | case 1: /* 01 */ |
| 475 | entry->size = 1024 * 4; /* 4K */ |
| 476 | break; |
| 477 | case 2: /* 10 */ |
| 478 | entry->size = 1024 * 64; /* 64K */ |
| 479 | break; |
| 480 | case 3: /* 11 */ |
| 481 | entry->size = 1024 * 1024; /* 1M */ |
| 482 | break; |
| 483 | default: |
| 484 | cpu_abort(cs, "Unhandled load_tlb"); |
| 485 | break; |
| 486 | } |
| 487 | entry->sh = (uint8_t)cpu_ptel_sh(env->ptel); |
| 488 | entry->c = (uint8_t)cpu_ptel_c(env->ptel); |
| 489 | entry->pr = (uint8_t)cpu_ptel_pr(env->ptel); |
| 490 | entry->d = (uint8_t)cpu_ptel_d(env->ptel); |
| 491 | entry->wt = (uint8_t)cpu_ptel_wt(env->ptel); |
| 492 | entry->sa = (uint8_t)cpu_ptea_sa(env->ptea); |
| 493 | entry->tc = (uint8_t)cpu_ptea_tc(env->ptea); |
| 494 | } |
| 495 | |
| 496 | void cpu_sh4_invalidate_tlb(CPUSH4State *s) |
| 497 | { |
| 498 | int i; |
| 499 | |
| 500 | /* UTLB */ |
| 501 | for (i = 0; i < UTLB_SIZE; i++) { |
| 502 | tlb_t * entry = &s->utlb[i]; |
| 503 | entry->v = 0; |
| 504 | } |
| 505 | /* ITLB */ |
| 506 | for (i = 0; i < ITLB_SIZE; i++) { |
| 507 | tlb_t * entry = &s->itlb[i]; |
| 508 | entry->v = 0; |
| 509 | } |
| 510 | |
| 511 | tlb_flush(env_cpu(s)); |
| 512 | } |
| 513 | |
| 514 | uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s, |
| 515 | hwaddr addr) |
| 516 | { |
| 517 | int index = (addr & 0x00000300) >> 8; |
| 518 | tlb_t * entry = &s->itlb[index]; |
| 519 | |
| 520 | return (entry->vpn << 10) | |
| 521 | (entry->v << 8) | |
| 522 | (entry->asid); |
| 523 | } |
| 524 | |
| 525 | void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, hwaddr addr, |
| 526 | uint32_t mem_value) |
| 527 | { |
| 528 | uint32_t vpn = (mem_value & 0xfffffc00) >> 10; |
| 529 | uint8_t v = (uint8_t)((mem_value & 0x00000100) >> 8); |
| 530 | uint8_t asid = (uint8_t)(mem_value & 0x000000ff); |
| 531 | |
| 532 | int index = (addr & 0x00000300) >> 8; |
| 533 | tlb_t * entry = &s->itlb[index]; |
| 534 | if (entry->v) { |
| 535 | /* Overwriting valid entry in itlb. */ |
| 536 | vaddr address = entry->vpn << 10; |
| 537 | tlb_flush_page(env_cpu(s), address); |
| 538 | } |
| 539 | entry->asid = asid; |
| 540 | entry->vpn = vpn; |
| 541 | entry->v = v; |
| 542 | } |
| 543 | |
| 544 | uint32_t cpu_sh4_read_mmaped_itlb_data(CPUSH4State *s, |
| 545 | hwaddr addr) |
| 546 | { |
| 547 | int array = (addr & 0x00800000) >> 23; |
| 548 | int index = (addr & 0x00000300) >> 8; |
| 549 | tlb_t * entry = &s->itlb[index]; |
| 550 | |
| 551 | if (array == 0) { |
| 552 | /* ITLB Data Array 1 */ |
| 553 | return (entry->ppn << 10) | |
| 554 | (entry->v << 8) | |
| 555 | (entry->pr << 5) | |
| 556 | ((entry->sz & 1) << 6) | |
| 557 | ((entry->sz & 2) << 4) | |
| 558 | (entry->c << 3) | |
| 559 | (entry->sh << 1); |
| 560 | } else { |
| 561 | /* ITLB Data Array 2 */ |
| 562 | return (entry->tc << 1) | |
| 563 | (entry->sa); |
| 564 | } |
| 565 | } |
| 566 | |
| 567 | void cpu_sh4_write_mmaped_itlb_data(CPUSH4State *s, hwaddr addr, |
| 568 | uint32_t mem_value) |
| 569 | { |
| 570 | int array = (addr & 0x00800000) >> 23; |
| 571 | int index = (addr & 0x00000300) >> 8; |
| 572 | tlb_t * entry = &s->itlb[index]; |
| 573 | |
| 574 | if (array == 0) { |
| 575 | /* ITLB Data Array 1 */ |
| 576 | if (entry->v) { |
| 577 | /* Overwriting valid entry in utlb. */ |
| 578 | vaddr address = entry->vpn << 10; |
| 579 | tlb_flush_page(env_cpu(s), address); |
| 580 | } |
| 581 | entry->ppn = (mem_value & 0x1ffffc00) >> 10; |
| 582 | entry->v = (mem_value & 0x00000100) >> 8; |
| 583 | entry->sz = (mem_value & 0x00000080) >> 6 | |
| 584 | (mem_value & 0x00000010) >> 4; |
| 585 | entry->pr = (mem_value & 0x00000040) >> 5; |
| 586 | entry->c = (mem_value & 0x00000008) >> 3; |
| 587 | entry->sh = (mem_value & 0x00000002) >> 1; |
| 588 | } else { |
| 589 | /* ITLB Data Array 2 */ |
| 590 | entry->tc = (mem_value & 0x00000008) >> 3; |
| 591 | entry->sa = (mem_value & 0x00000007); |
| 592 | } |
| 593 | } |
| 594 | |
| 595 | uint32_t cpu_sh4_read_mmaped_utlb_addr(CPUSH4State *s, |
| 596 | hwaddr addr) |
| 597 | { |
| 598 | int index = (addr & 0x00003f00) >> 8; |
| 599 | tlb_t * entry = &s->utlb[index]; |
| 600 | |
| 601 | increment_urc(s); /* per utlb access */ |
| 602 | |
| 603 | return (entry->vpn << 10) | |
| 604 | (entry->v << 8) | |
| 605 | (entry->asid); |
| 606 | } |
| 607 | |
| 608 | void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, hwaddr addr, |
| 609 | uint32_t mem_value) |
| 610 | { |
| 611 | int associate = addr & 0x0000080; |
| 612 | uint32_t vpn = (mem_value & 0xfffffc00) >> 10; |
| 613 | uint8_t d = (uint8_t)((mem_value & 0x00000200) >> 9); |
| 614 | uint8_t v = (uint8_t)((mem_value & 0x00000100) >> 8); |
| 615 | uint8_t asid = (uint8_t)(mem_value & 0x000000ff); |
| 616 | int use_asid = !(s->mmucr & MMUCR_SV) || !(s->sr & (1u << SR_MD)); |
| 617 | |
| 618 | if (associate) { |
| 619 | int i; |
| 620 | tlb_t * utlb_match_entry = NULL; |
| 621 | int needs_tlb_flush = 0; |
| 622 | |
| 623 | /* search UTLB */ |
| 624 | for (i = 0; i < UTLB_SIZE; i++) { |
| 625 | tlb_t * entry = &s->utlb[i]; |
| 626 | if (!entry->v) |
| 627 | continue; |
| 628 | |
| 629 | if (entry->vpn == vpn |
| 630 | && (!use_asid || entry->asid == asid || entry->sh)) { |
| 631 | if (utlb_match_entry) { |
| 632 | CPUState *cs = env_cpu(s); |
| 633 | |
| 634 | /* Multiple TLB Exception */ |
| 635 | cs->exception_index = 0x140; |
| 636 | s->tea = addr; |
| 637 | break; |
| 638 | } |
| 639 | if (entry->v && !v) |
| 640 | needs_tlb_flush = 1; |
| 641 | entry->v = v; |
| 642 | entry->d = d; |
| 643 | utlb_match_entry = entry; |
| 644 | } |
| 645 | increment_urc(s); /* per utlb access */ |
| 646 | } |
| 647 | |
| 648 | /* search ITLB */ |
| 649 | for (i = 0; i < ITLB_SIZE; i++) { |
| 650 | tlb_t * entry = &s->itlb[i]; |
| 651 | if (entry->vpn == vpn |
| 652 | && (!use_asid || entry->asid == asid || entry->sh)) { |
| 653 | if (entry->v && !v) |
| 654 | needs_tlb_flush = 1; |
| 655 | if (utlb_match_entry) |
| 656 | *entry = *utlb_match_entry; |
| 657 | else |
| 658 | entry->v = v; |
| 659 | break; |
| 660 | } |
| 661 | } |
| 662 | |
| 663 | if (needs_tlb_flush) { |
| 664 | tlb_flush_page(env_cpu(s), vpn << 10); |
| 665 | } |
| 666 | } else { |
| 667 | int index = (addr & 0x00003f00) >> 8; |
| 668 | tlb_t * entry = &s->utlb[index]; |
| 669 | if (entry->v) { |
| 670 | CPUState *cs = env_cpu(s); |
| 671 | |
| 672 | /* Overwriting valid entry in utlb. */ |
| 673 | vaddr address = entry->vpn << 10; |
| 674 | tlb_flush_page(cs, address); |
| 675 | } |
| 676 | entry->asid = asid; |
| 677 | entry->vpn = vpn; |
| 678 | entry->d = d; |
| 679 | entry->v = v; |
| 680 | increment_urc(s); |
| 681 | } |
| 682 | } |
| 683 | |
| 684 | uint32_t cpu_sh4_read_mmaped_utlb_data(CPUSH4State *s, |
| 685 | hwaddr addr) |
| 686 | { |
| 687 | int array = (addr & 0x00800000) >> 23; |
| 688 | int index = (addr & 0x00003f00) >> 8; |
| 689 | tlb_t * entry = &s->utlb[index]; |
| 690 | |
| 691 | increment_urc(s); /* per utlb access */ |
| 692 | |
| 693 | if (array == 0) { |
| 694 | /* ITLB Data Array 1 */ |
| 695 | return (entry->ppn << 10) | |
| 696 | (entry->v << 8) | |
| 697 | (entry->pr << 5) | |
| 698 | ((entry->sz & 1) << 6) | |
| 699 | ((entry->sz & 2) << 4) | |
| 700 | (entry->c << 3) | |
| 701 | (entry->d << 2) | |
| 702 | (entry->sh << 1) | |
| 703 | (entry->wt); |
| 704 | } else { |
| 705 | /* ITLB Data Array 2 */ |
| 706 | return (entry->tc << 1) | |
| 707 | (entry->sa); |
| 708 | } |
| 709 | } |
| 710 | |
| 711 | void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, hwaddr addr, |
| 712 | uint32_t mem_value) |
| 713 | { |
| 714 | int array = (addr & 0x00800000) >> 23; |
| 715 | int index = (addr & 0x00003f00) >> 8; |
| 716 | tlb_t * entry = &s->utlb[index]; |
| 717 | |
| 718 | increment_urc(s); /* per utlb access */ |
| 719 | |
| 720 | if (array == 0) { |
| 721 | /* UTLB Data Array 1 */ |
| 722 | if (entry->v) { |
| 723 | /* Overwriting valid entry in utlb. */ |
| 724 | vaddr address = entry->vpn << 10; |
| 725 | tlb_flush_page(env_cpu(s), address); |
| 726 | } |
| 727 | entry->ppn = (mem_value & 0x1ffffc00) >> 10; |
| 728 | entry->v = (mem_value & 0x00000100) >> 8; |
| 729 | entry->sz = (mem_value & 0x00000080) >> 6 | |
| 730 | (mem_value & 0x00000010) >> 4; |
| 731 | entry->pr = (mem_value & 0x00000060) >> 5; |
| 732 | entry->c = (mem_value & 0x00000008) >> 3; |
| 733 | entry->d = (mem_value & 0x00000004) >> 2; |
| 734 | entry->sh = (mem_value & 0x00000002) >> 1; |
| 735 | entry->wt = (mem_value & 0x00000001); |
| 736 | } else { |
| 737 | /* UTLB Data Array 2 */ |
| 738 | entry->tc = (mem_value & 0x00000008) >> 3; |
| 739 | entry->sa = (mem_value & 0x00000007); |
| 740 | } |
| 741 | } |
| 742 | |
| 743 | int cpu_sh4_is_cached(CPUSH4State *env, uint32_t addr) |
| 744 | { |
| 745 | int n; |
| 746 | int use_asid = !(env->mmucr & MMUCR_SV) || !(env->sr & (1u << SR_MD)); |
| 747 | |
| 748 | /* check area */ |
| 749 | if (env->sr & (1u << SR_MD)) { |
| 750 | /* For privileged mode, P2 and P4 area is not cacheable. */ |
| 751 | if ((0xA0000000 <= addr && addr < 0xC0000000) || 0xE0000000 <= addr) |
| 752 | return 0; |
| 753 | } else { |
| 754 | /* For user mode, only U0 area is cacheable. */ |
| 755 | if (0x80000000 <= addr) |
| 756 | return 0; |
| 757 | } |
| 758 | |
| 759 | /* |
| 760 | * TODO : Evaluate CCR and check if the cache is on or off. |
| 761 | * Now CCR is not in CPUSH4State, but in SH7750State. |
| 762 | * When you move the ccr into CPUSH4State, the code will be |
| 763 | * as follows. |
| 764 | */ |
| 765 | #if 0 |
| 766 | /* check if operand cache is enabled or not. */ |
| 767 | if (!(env->ccr & 1)) |
| 768 | return 0; |
| 769 | #endif |
| 770 | |
| 771 | /* if MMU is off, no check for TLB. */ |
| 772 | if (env->mmucr & MMUCR_AT) |
| 773 | return 1; |
| 774 | |
| 775 | /* check TLB */ |
| 776 | n = find_tlb_entry(env, addr, env->itlb, ITLB_SIZE, use_asid); |
| 777 | if (n >= 0) |
| 778 | return env->itlb[n].c; |
| 779 | |
| 780 | n = find_tlb_entry(env, addr, env->utlb, UTLB_SIZE, use_asid); |
| 781 | if (n >= 0) |
| 782 | return env->utlb[n].c; |
| 783 | |
| 784 | return 0; |
| 785 | } |
| 786 | |
| 787 | bool superh_cpu_exec_interrupt(CPUState *cs, int interrupt_request) |
| 788 | { |
| 789 | if (interrupt_request & CPU_INTERRUPT_HARD) { |
| 790 | /* Delay slots are indivisible, ignore interrupts */ |
| 791 | if (cpu_env(cs)->flags & TB_FLAG_DELAY_SLOT_MASK) { |
| 792 | return false; |
| 793 | } else { |
| 794 | superh_cpu_do_interrupt(cs); |
| 795 | return true; |
| 796 | } |
| 797 | } |
| 798 | return false; |
| 799 | } |
| 800 | |
| 801 | bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size, |
| 802 | MMUAccessType access_type, int mmu_idx, |
| 803 | bool probe, uintptr_t retaddr) |
| 804 | { |
| 805 | CPUSH4State *env = cpu_env(cs); |
| 806 | int ret; |
| 807 | |
| 808 | hwaddr physical; |
| 809 | int prot; |
| 810 | |
| 811 | ret = get_physical_address(env, &physical, &prot, address, access_type); |
| 812 | |
| 813 | if (ret == MMU_OK) { |
| 814 | address &= TARGET_PAGE_MASK; |
| 815 | physical &= TARGET_PAGE_MASK; |
| 816 | tlb_set_page(cs, address, physical, prot, mmu_idx, TARGET_PAGE_SIZE); |
| 817 | return true; |
| 818 | } |
| 819 | if (probe) { |
| 820 | return false; |
| 821 | } |
| 822 | |
| 823 | if (ret != MMU_DTLB_MULTIPLE && ret != MMU_ITLB_MULTIPLE) { |
| 824 | env->pteh = (env->pteh & PTEH_ASID_MASK) | (address & PTEH_VPN_MASK); |
| 825 | } |
| 826 | |
| 827 | env->tea = address; |
| 828 | switch (ret) { |
| 829 | case MMU_ITLB_MISS: |
| 830 | case MMU_DTLB_MISS_READ: |
| 831 | cs->exception_index = 0x040; |
| 832 | break; |
| 833 | case MMU_DTLB_MULTIPLE: |
| 834 | case MMU_ITLB_MULTIPLE: |
| 835 | cs->exception_index = 0x140; |
| 836 | break; |
| 837 | case MMU_ITLB_VIOLATION: |
| 838 | cs->exception_index = 0x0a0; |
| 839 | break; |
| 840 | case MMU_DTLB_MISS_WRITE: |
| 841 | cs->exception_index = 0x060; |
| 842 | break; |
| 843 | case MMU_DTLB_INITIAL_WRITE: |
| 844 | cs->exception_index = 0x080; |
| 845 | break; |
| 846 | case MMU_DTLB_VIOLATION_READ: |
| 847 | cs->exception_index = 0x0a0; |
| 848 | break; |
| 849 | case MMU_DTLB_VIOLATION_WRITE: |
| 850 | cs->exception_index = 0x0c0; |
| 851 | break; |
| 852 | case MMU_IADDR_ERROR: |
| 853 | case MMU_DADDR_ERROR_READ: |
| 854 | cs->exception_index = 0x0e0; |
| 855 | break; |
| 856 | case MMU_DADDR_ERROR_WRITE: |
| 857 | cs->exception_index = 0x100; |
| 858 | break; |
| 859 | default: |
| 860 | cpu_abort(cs, "Unhandled MMU fault"); |
| 861 | } |
| 862 | cpu_loop_exit_restore(cs, retaddr); |
| 863 | } |
| 864 | #endif /* !CONFIG_USER_ONLY */ |