| 1 | /* |
| 2 | * SH4 emulation |
| 3 | * |
| 4 | * Copyright (c) 2005 Samuel Tardieu |
| 5 | * |
| 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2.1 of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU Lesser General Public |
| 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
| 18 | */ |
| 19 | #include "qemu/osdep.h" |
| 20 | #include "cpu.h" |
| 21 | #include "exec/helper-proto.h" |
| 22 | #include "accel/tcg/cpu-ldst.h" |
| 23 | #include "accel/tcg/cpu-loop.h" |
| 24 | #include "fpu/softfloat.h" |
| 25 | |
| 26 | #ifndef CONFIG_USER_ONLY |
| 27 | |
| 28 | void superh_cpu_do_unaligned_access(CPUState *cs, vaddr addr, |
| 29 | MMUAccessType access_type, |
| 30 | int mmu_idx, uintptr_t retaddr) |
| 31 | { |
| 32 | cpu_env(cs)->tea = addr; |
| 33 | switch (access_type) { |
| 34 | case MMU_INST_FETCH: |
| 35 | case MMU_DATA_LOAD: |
| 36 | cs->exception_index = 0x0e0; |
| 37 | break; |
| 38 | case MMU_DATA_STORE: |
| 39 | cs->exception_index = 0x100; |
| 40 | break; |
| 41 | default: |
| 42 | g_assert_not_reached(); |
| 43 | } |
| 44 | cpu_loop_exit_restore(cs, retaddr); |
| 45 | } |
| 46 | |
| 47 | #endif |
| 48 | |
| 49 | void helper_ldtlb(CPUSH4State *env) |
| 50 | { |
| 51 | #ifdef CONFIG_USER_ONLY |
| 52 | cpu_abort(env_cpu(env), "Unhandled ldtlb"); |
| 53 | #else |
| 54 | cpu_load_tlb(env); |
| 55 | #endif |
| 56 | } |
| 57 | |
| 58 | static inline G_NORETURN |
| 59 | void raise_exception(CPUSH4State *env, int index, |
| 60 | uintptr_t retaddr) |
| 61 | { |
| 62 | CPUState *cs = env_cpu(env); |
| 63 | |
| 64 | cs->exception_index = index; |
| 65 | cpu_loop_exit_restore(cs, retaddr); |
| 66 | } |
| 67 | |
| 68 | void helper_raise_illegal_instruction(CPUSH4State *env) |
| 69 | { |
| 70 | raise_exception(env, 0x180, 0); |
| 71 | } |
| 72 | |
| 73 | void helper_raise_slot_illegal_instruction(CPUSH4State *env) |
| 74 | { |
| 75 | raise_exception(env, 0x1a0, 0); |
| 76 | } |
| 77 | |
| 78 | void helper_raise_fpu_disable(CPUSH4State *env) |
| 79 | { |
| 80 | raise_exception(env, 0x800, 0); |
| 81 | } |
| 82 | |
| 83 | void helper_raise_slot_fpu_disable(CPUSH4State *env) |
| 84 | { |
| 85 | raise_exception(env, 0x820, 0); |
| 86 | } |
| 87 | |
| 88 | void helper_sleep(CPUSH4State *env) |
| 89 | { |
| 90 | CPUState *cs = env_cpu(env); |
| 91 | |
| 92 | cs->halted = 1; |
| 93 | env->in_sleep = 1; |
| 94 | raise_exception(env, EXCP_HLT, 0); |
| 95 | } |
| 96 | |
| 97 | void helper_trapa(CPUSH4State *env, uint32_t tra) |
| 98 | { |
| 99 | env->tra = tra << 2; |
| 100 | raise_exception(env, 0x160, 0); |
| 101 | } |
| 102 | |
| 103 | void helper_exclusive(CPUSH4State *env) |
| 104 | { |
| 105 | /* We do not want cpu_restore_state to run. */ |
| 106 | cpu_loop_exit_atomic(env_cpu(env), 0); |
| 107 | } |
| 108 | |
| 109 | void helper_movcal(CPUSH4State *env, uint32_t address, uint32_t value) |
| 110 | { |
| 111 | if (cpu_sh4_is_cached (env, address)) |
| 112 | { |
| 113 | memory_content *r = g_new(memory_content, 1); |
| 114 | |
| 115 | r->address = address; |
| 116 | r->value = value; |
| 117 | r->next = NULL; |
| 118 | |
| 119 | *(env->movcal_backup_tail) = r; |
| 120 | env->movcal_backup_tail = &(r->next); |
| 121 | } |
| 122 | } |
| 123 | |
| 124 | void helper_discard_movcal_backup(CPUSH4State *env) |
| 125 | { |
| 126 | memory_content *current = env->movcal_backup; |
| 127 | |
| 128 | while(current) |
| 129 | { |
| 130 | memory_content *next = current->next; |
| 131 | g_free(current); |
| 132 | env->movcal_backup = current = next; |
| 133 | if (current == NULL) |
| 134 | env->movcal_backup_tail = &(env->movcal_backup); |
| 135 | } |
| 136 | } |
| 137 | |
| 138 | void helper_ocbi(CPUSH4State *env, uint32_t address) |
| 139 | { |
| 140 | unsigned mmu_idx = cpu_mmu_index(env_cpu(env), false); |
| 141 | MemOpIdx oi = make_memop_idx(MO_TE | MO_UL | MO_UNALN, mmu_idx); |
| 142 | memory_content **current = &(env->movcal_backup); |
| 143 | while (*current) |
| 144 | { |
| 145 | uint32_t a = (*current)->address; |
| 146 | if ((a & ~0x1F) == (address & ~0x1F)) |
| 147 | { |
| 148 | memory_content *next = (*current)->next; |
| 149 | |
| 150 | cpu_stl_mmu(env, a, (*current)->value, oi, GETPC()); |
| 151 | |
| 152 | if (next == NULL) |
| 153 | { |
| 154 | env->movcal_backup_tail = current; |
| 155 | } |
| 156 | |
| 157 | g_free(*current); |
| 158 | *current = next; |
| 159 | break; |
| 160 | } |
| 161 | } |
| 162 | } |
| 163 | |
| 164 | void helper_macl(CPUSH4State *env, int32_t arg0, int32_t arg1) |
| 165 | { |
| 166 | const int64_t min = -(1ll << 47); |
| 167 | const int64_t max = (1ll << 47) - 1; |
| 168 | int64_t mul = (int64_t)arg0 * arg1; |
| 169 | int64_t mac = env->mac; |
| 170 | int64_t res; |
| 171 | |
| 172 | if (!(env->sr & (1u << SR_S))) { |
| 173 | res = mac + mul; |
| 174 | } else if (sadd64_overflow(mac, mul, &res)) { |
| 175 | res = mac < 0 ? min : max; |
| 176 | } else { |
| 177 | res = MIN(MAX(res, min), max); |
| 178 | } |
| 179 | |
| 180 | env->mac = res; |
| 181 | } |
| 182 | |
| 183 | void helper_macw(CPUSH4State *env, int32_t arg0, int32_t arg1) |
| 184 | { |
| 185 | /* Inputs are already sign-extended from 16 bits. */ |
| 186 | int32_t mul = arg0 * arg1; |
| 187 | |
| 188 | if (env->sr & (1u << SR_S)) { |
| 189 | /* |
| 190 | * In saturation arithmetic mode, the accumulator is 32-bit |
| 191 | * with carry. MACH is not considered during the addition |
| 192 | * operation nor the 32-bit saturation logic. |
| 193 | */ |
| 194 | int32_t res, macl = env->macl; |
| 195 | |
| 196 | if (sadd32_overflow(macl, mul, &res)) { |
| 197 | res = macl < 0 ? INT32_MIN : INT32_MAX; |
| 198 | /* If overflow occurs, the MACH register is set to 1. */ |
| 199 | env->mach = 1; |
| 200 | } |
| 201 | env->macl = res; |
| 202 | } else { |
| 203 | /* In non-saturation arithmetic mode, the accumulator is 64-bit */ |
| 204 | env->mac += mul; |
| 205 | } |
| 206 | } |
| 207 | |
| 208 | void cpu_load_fpscr(CPUSH4State *env, uint32_t val) |
| 209 | { |
| 210 | env->fpscr = val & FPSCR_MASK; |
| 211 | if ((val & FPSCR_RM_MASK) == FPSCR_RM_ZERO) { |
| 212 | set_float_rounding_mode(float_round_to_zero, &env->fp_status); |
| 213 | } else { |
| 214 | set_float_rounding_mode(float_round_nearest_even, &env->fp_status); |
| 215 | } |
| 216 | set_flush_to_zero((val & FPSCR_DN) != 0, &env->fp_status); |
| 217 | } |
| 218 | |
| 219 | void helper_ld_fpscr(CPUSH4State *env, uint32_t val) |
| 220 | { |
| 221 | cpu_load_fpscr(env, val); |
| 222 | } |
| 223 | |
| 224 | static void update_fpscr(CPUSH4State *env, uintptr_t retaddr) |
| 225 | { |
| 226 | int xcpt, cause, enable; |
| 227 | |
| 228 | xcpt = get_float_exception_flags(&env->fp_status); |
| 229 | |
| 230 | /* Clear the cause entries */ |
| 231 | env->fpscr &= ~FPSCR_CAUSE_MASK; |
| 232 | |
| 233 | if (unlikely(xcpt)) { |
| 234 | if (xcpt & float_flag_invalid) { |
| 235 | env->fpscr |= FPSCR_CAUSE_V; |
| 236 | } |
| 237 | if (xcpt & float_flag_divbyzero) { |
| 238 | env->fpscr |= FPSCR_CAUSE_Z; |
| 239 | } |
| 240 | if (xcpt & float_flag_overflow) { |
| 241 | env->fpscr |= FPSCR_CAUSE_O; |
| 242 | } |
| 243 | if (xcpt & float_flag_underflow) { |
| 244 | env->fpscr |= FPSCR_CAUSE_U; |
| 245 | } |
| 246 | if (xcpt & float_flag_inexact) { |
| 247 | env->fpscr |= FPSCR_CAUSE_I; |
| 248 | } |
| 249 | |
| 250 | /* Accumulate in flag entries */ |
| 251 | env->fpscr |= (env->fpscr & FPSCR_CAUSE_MASK) |
| 252 | >> (FPSCR_CAUSE_SHIFT - FPSCR_FLAG_SHIFT); |
| 253 | |
| 254 | /* Generate an exception if enabled */ |
| 255 | cause = (env->fpscr & FPSCR_CAUSE_MASK) >> FPSCR_CAUSE_SHIFT; |
| 256 | enable = (env->fpscr & FPSCR_ENABLE_MASK) >> FPSCR_ENABLE_SHIFT; |
| 257 | if (cause & enable) { |
| 258 | raise_exception(env, 0x120, retaddr); |
| 259 | } |
| 260 | } |
| 261 | } |
| 262 | |
| 263 | float32 helper_fadd_FT(CPUSH4State *env, float32 t0, float32 t1) |
| 264 | { |
| 265 | set_float_exception_flags(0, &env->fp_status); |
| 266 | t0 = float32_add(t0, t1, &env->fp_status); |
| 267 | update_fpscr(env, GETPC()); |
| 268 | return t0; |
| 269 | } |
| 270 | |
| 271 | float64 helper_fadd_DT(CPUSH4State *env, float64 t0, float64 t1) |
| 272 | { |
| 273 | set_float_exception_flags(0, &env->fp_status); |
| 274 | t0 = float64_add(t0, t1, &env->fp_status); |
| 275 | update_fpscr(env, GETPC()); |
| 276 | return t0; |
| 277 | } |
| 278 | |
| 279 | uint32_t helper_fcmp_eq_FT(CPUSH4State *env, float32 t0, float32 t1) |
| 280 | { |
| 281 | int relation; |
| 282 | |
| 283 | set_float_exception_flags(0, &env->fp_status); |
| 284 | relation = float32_compare(t0, t1, &env->fp_status); |
| 285 | update_fpscr(env, GETPC()); |
| 286 | return relation == float_relation_equal; |
| 287 | } |
| 288 | |
| 289 | uint32_t helper_fcmp_eq_DT(CPUSH4State *env, float64 t0, float64 t1) |
| 290 | { |
| 291 | int relation; |
| 292 | |
| 293 | set_float_exception_flags(0, &env->fp_status); |
| 294 | relation = float64_compare(t0, t1, &env->fp_status); |
| 295 | update_fpscr(env, GETPC()); |
| 296 | return relation == float_relation_equal; |
| 297 | } |
| 298 | |
| 299 | uint32_t helper_fcmp_gt_FT(CPUSH4State *env, float32 t0, float32 t1) |
| 300 | { |
| 301 | int relation; |
| 302 | |
| 303 | set_float_exception_flags(0, &env->fp_status); |
| 304 | relation = float32_compare(t0, t1, &env->fp_status); |
| 305 | update_fpscr(env, GETPC()); |
| 306 | return relation == float_relation_greater; |
| 307 | } |
| 308 | |
| 309 | uint32_t helper_fcmp_gt_DT(CPUSH4State *env, float64 t0, float64 t1) |
| 310 | { |
| 311 | int relation; |
| 312 | |
| 313 | set_float_exception_flags(0, &env->fp_status); |
| 314 | relation = float64_compare(t0, t1, &env->fp_status); |
| 315 | update_fpscr(env, GETPC()); |
| 316 | return relation == float_relation_greater; |
| 317 | } |
| 318 | |
| 319 | float64 helper_fcnvsd_FT_DT(CPUSH4State *env, float32 t0) |
| 320 | { |
| 321 | float64 ret; |
| 322 | set_float_exception_flags(0, &env->fp_status); |
| 323 | ret = float32_to_float64(t0, &env->fp_status); |
| 324 | update_fpscr(env, GETPC()); |
| 325 | return ret; |
| 326 | } |
| 327 | |
| 328 | float32 helper_fcnvds_DT_FT(CPUSH4State *env, float64 t0) |
| 329 | { |
| 330 | float32 ret; |
| 331 | set_float_exception_flags(0, &env->fp_status); |
| 332 | ret = float64_to_float32(t0, &env->fp_status); |
| 333 | update_fpscr(env, GETPC()); |
| 334 | return ret; |
| 335 | } |
| 336 | |
| 337 | float32 helper_fdiv_FT(CPUSH4State *env, float32 t0, float32 t1) |
| 338 | { |
| 339 | set_float_exception_flags(0, &env->fp_status); |
| 340 | t0 = float32_div(t0, t1, &env->fp_status); |
| 341 | update_fpscr(env, GETPC()); |
| 342 | return t0; |
| 343 | } |
| 344 | |
| 345 | float64 helper_fdiv_DT(CPUSH4State *env, float64 t0, float64 t1) |
| 346 | { |
| 347 | set_float_exception_flags(0, &env->fp_status); |
| 348 | t0 = float64_div(t0, t1, &env->fp_status); |
| 349 | update_fpscr(env, GETPC()); |
| 350 | return t0; |
| 351 | } |
| 352 | |
| 353 | float32 helper_float_FT(CPUSH4State *env, uint32_t t0) |
| 354 | { |
| 355 | float32 ret; |
| 356 | set_float_exception_flags(0, &env->fp_status); |
| 357 | ret = int32_to_float32(t0, &env->fp_status); |
| 358 | update_fpscr(env, GETPC()); |
| 359 | return ret; |
| 360 | } |
| 361 | |
| 362 | float64 helper_float_DT(CPUSH4State *env, uint32_t t0) |
| 363 | { |
| 364 | float64 ret; |
| 365 | set_float_exception_flags(0, &env->fp_status); |
| 366 | ret = int32_to_float64(t0, &env->fp_status); |
| 367 | update_fpscr(env, GETPC()); |
| 368 | return ret; |
| 369 | } |
| 370 | |
| 371 | float32 helper_fmac_FT(CPUSH4State *env, float32 t0, float32 t1, float32 t2) |
| 372 | { |
| 373 | set_float_exception_flags(0, &env->fp_status); |
| 374 | t0 = float32_muladd(t0, t1, t2, 0, &env->fp_status); |
| 375 | update_fpscr(env, GETPC()); |
| 376 | return t0; |
| 377 | } |
| 378 | |
| 379 | float32 helper_fmul_FT(CPUSH4State *env, float32 t0, float32 t1) |
| 380 | { |
| 381 | set_float_exception_flags(0, &env->fp_status); |
| 382 | t0 = float32_mul(t0, t1, &env->fp_status); |
| 383 | update_fpscr(env, GETPC()); |
| 384 | return t0; |
| 385 | } |
| 386 | |
| 387 | float64 helper_fmul_DT(CPUSH4State *env, float64 t0, float64 t1) |
| 388 | { |
| 389 | set_float_exception_flags(0, &env->fp_status); |
| 390 | t0 = float64_mul(t0, t1, &env->fp_status); |
| 391 | update_fpscr(env, GETPC()); |
| 392 | return t0; |
| 393 | } |
| 394 | |
| 395 | float32 helper_fsqrt_FT(CPUSH4State *env, float32 t0) |
| 396 | { |
| 397 | set_float_exception_flags(0, &env->fp_status); |
| 398 | t0 = float32_sqrt(t0, &env->fp_status); |
| 399 | update_fpscr(env, GETPC()); |
| 400 | return t0; |
| 401 | } |
| 402 | |
| 403 | float64 helper_fsqrt_DT(CPUSH4State *env, float64 t0) |
| 404 | { |
| 405 | set_float_exception_flags(0, &env->fp_status); |
| 406 | t0 = float64_sqrt(t0, &env->fp_status); |
| 407 | update_fpscr(env, GETPC()); |
| 408 | return t0; |
| 409 | } |
| 410 | |
| 411 | float32 helper_fsrra_FT(CPUSH4State *env, float32 t0) |
| 412 | { |
| 413 | set_float_exception_flags(0, &env->fp_status); |
| 414 | /* "Approximate" 1/sqrt(x) via actual computation. */ |
| 415 | t0 = float32_sqrt(t0, &env->fp_status); |
| 416 | t0 = float32_div(float32_one, t0, &env->fp_status); |
| 417 | /* |
| 418 | * Since this is supposed to be an approximation, an imprecision |
| 419 | * exception is required. One supposes this also follows the usual |
| 420 | * IEEE rule that other exceptions take precedence. |
| 421 | */ |
| 422 | if (get_float_exception_flags(&env->fp_status) == 0) { |
| 423 | set_float_exception_flags(float_flag_inexact, &env->fp_status); |
| 424 | } |
| 425 | update_fpscr(env, GETPC()); |
| 426 | return t0; |
| 427 | } |
| 428 | |
| 429 | float32 helper_fsub_FT(CPUSH4State *env, float32 t0, float32 t1) |
| 430 | { |
| 431 | set_float_exception_flags(0, &env->fp_status); |
| 432 | t0 = float32_sub(t0, t1, &env->fp_status); |
| 433 | update_fpscr(env, GETPC()); |
| 434 | return t0; |
| 435 | } |
| 436 | |
| 437 | float64 helper_fsub_DT(CPUSH4State *env, float64 t0, float64 t1) |
| 438 | { |
| 439 | set_float_exception_flags(0, &env->fp_status); |
| 440 | t0 = float64_sub(t0, t1, &env->fp_status); |
| 441 | update_fpscr(env, GETPC()); |
| 442 | return t0; |
| 443 | } |
| 444 | |
| 445 | uint32_t helper_ftrc_FT(CPUSH4State *env, float32 t0) |
| 446 | { |
| 447 | uint32_t ret; |
| 448 | set_float_exception_flags(0, &env->fp_status); |
| 449 | ret = float32_to_int32_round_to_zero(t0, &env->fp_status); |
| 450 | update_fpscr(env, GETPC()); |
| 451 | return ret; |
| 452 | } |
| 453 | |
| 454 | uint32_t helper_ftrc_DT(CPUSH4State *env, float64 t0) |
| 455 | { |
| 456 | uint32_t ret; |
| 457 | set_float_exception_flags(0, &env->fp_status); |
| 458 | ret = float64_to_int32_round_to_zero(t0, &env->fp_status); |
| 459 | update_fpscr(env, GETPC()); |
| 460 | return ret; |
| 461 | } |
| 462 | |
| 463 | void helper_fipr(CPUSH4State *env, uint32_t m, uint32_t n) |
| 464 | { |
| 465 | int bank, i; |
| 466 | float32 r, p; |
| 467 | |
| 468 | bank = (env->sr & FPSCR_FR) ? 16 : 0; |
| 469 | r = float32_zero; |
| 470 | set_float_exception_flags(0, &env->fp_status); |
| 471 | |
| 472 | for (i = 0 ; i < 4 ; i++) { |
| 473 | p = float32_mul(env->fregs[bank + m + i], |
| 474 | env->fregs[bank + n + i], |
| 475 | &env->fp_status); |
| 476 | r = float32_add(r, p, &env->fp_status); |
| 477 | } |
| 478 | update_fpscr(env, GETPC()); |
| 479 | |
| 480 | env->fregs[bank + n + 3] = r; |
| 481 | } |
| 482 | |
| 483 | void helper_ftrv(CPUSH4State *env, uint32_t n) |
| 484 | { |
| 485 | int bank_matrix, bank_vector; |
| 486 | int i, j; |
| 487 | float32 r[4]; |
| 488 | float32 p; |
| 489 | |
| 490 | bank_matrix = (env->sr & FPSCR_FR) ? 0 : 16; |
| 491 | bank_vector = (env->sr & FPSCR_FR) ? 16 + n : n; |
| 492 | set_float_exception_flags(0, &env->fp_status); |
| 493 | for (i = 0 ; i < 4 ; i++) { |
| 494 | r[i] = float32_zero; |
| 495 | for (j = 0 ; j < 4 ; j++) { |
| 496 | p = float32_mul(env->fregs[bank_matrix + 4 * j + i], |
| 497 | env->fregs[bank_vector + j], |
| 498 | &env->fp_status); |
| 499 | r[i] = float32_add(r[i], p, &env->fp_status); |
| 500 | } |
| 501 | } |
| 502 | update_fpscr(env, GETPC()); |
| 503 | |
| 504 | for (i = 0 ; i < 4 ; i++) { |
| 505 | env->fregs[bank_vector + i] = r[i]; |
| 506 | } |
| 507 | } |