| 1 | /* |
| 2 | * Sparc CPU init helpers |
| 3 | * |
| 4 | * Copyright (c) 2003-2005 Fabrice Bellard |
| 5 | * |
| 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2.1 of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU Lesser General Public |
| 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
| 18 | */ |
| 19 | |
| 20 | #include "qemu/osdep.h" |
| 21 | #include "qapi/error.h" |
| 22 | #include "cpu.h" |
| 23 | #include "qemu/module.h" |
| 24 | #include "qemu/qemu-print.h" |
| 25 | #include "accel/tcg/cpu-mmu-index.h" |
| 26 | #include "accel/tcg/cpu-ops.h" |
| 27 | #include "exec/translation-block.h" |
| 28 | #include "hw/core/qdev-properties.h" |
| 29 | #include "qapi/visitor.h" |
| 30 | #include "tcg/tcg.h" |
| 31 | #include "fpu/softfloat.h" |
| 32 | #include "target/sparc/translate.h" |
| 33 | |
| 34 | //#define DEBUG_FEATURES |
| 35 | |
| 36 | static void sparc_cpu_reset_hold(Object *obj, ResetType type) |
| 37 | { |
| 38 | CPUState *cs = CPU(obj); |
| 39 | SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(obj); |
| 40 | CPUSPARCState *env = cpu_env(cs); |
| 41 | |
| 42 | if (scc->parent_phases.hold) { |
| 43 | scc->parent_phases.hold(obj, type); |
| 44 | } |
| 45 | |
| 46 | memset(env, 0, offsetof(CPUSPARCState, end_reset_fields)); |
| 47 | env->cwp = 0; |
| 48 | #ifndef TARGET_SPARC64 |
| 49 | env->wim = 1; |
| 50 | #endif |
| 51 | env->regwptr = env->regbase + (env->cwp * 16); |
| 52 | #if defined(CONFIG_USER_ONLY) |
| 53 | #ifdef TARGET_SPARC64 |
| 54 | env->cleanwin = env->nwindows - 2; |
| 55 | env->cansave = env->nwindows - 2; |
| 56 | env->pstate = PS_RMO | PS_PEF | PS_IE; |
| 57 | env->asi = 0x82; /* Primary no-fault */ |
| 58 | #endif |
| 59 | #else |
| 60 | #if !defined(TARGET_SPARC64) |
| 61 | env->psret = 0; |
| 62 | env->psrs = 1; |
| 63 | env->psrps = 1; |
| 64 | #endif |
| 65 | #ifdef TARGET_SPARC64 |
| 66 | env->pstate = PS_PRIV | PS_RED | PS_PEF; |
| 67 | if (!cpu_has_hypervisor(env)) { |
| 68 | env->pstate |= PS_AG; |
| 69 | } |
| 70 | env->hpstate = cpu_has_hypervisor(env) ? HS_PRIV : 0; |
| 71 | env->tl = env->maxtl; |
| 72 | env->gl = 2; |
| 73 | cpu_tsptr(env)->tt = TT_POWER_ON_RESET; |
| 74 | env->lsu = 0; |
| 75 | #else |
| 76 | env->mmuregs[0] &= ~(MMU_E | MMU_NF); |
| 77 | env->mmuregs[0] |= env->def.mmu_bm; |
| 78 | #endif |
| 79 | env->pc = 0; |
| 80 | env->npc = env->pc + 4; |
| 81 | #endif |
| 82 | env->cache_control = 0; |
| 83 | cpu_put_fsr(env, 0); |
| 84 | } |
| 85 | |
| 86 | #ifndef CONFIG_USER_ONLY |
| 87 | static bool sparc_cpu_exec_interrupt(CPUState *cs, int interrupt_request) |
| 88 | { |
| 89 | if (interrupt_request & CPU_INTERRUPT_HARD) { |
| 90 | CPUSPARCState *env = cpu_env(cs); |
| 91 | |
| 92 | if (cpu_interrupts_enabled(env) && env->interrupt_index > 0) { |
| 93 | int pil = env->interrupt_index & 0xf; |
| 94 | int type = env->interrupt_index & 0xf0; |
| 95 | |
| 96 | if (type != TT_EXTINT || cpu_pil_allowed(env, pil)) { |
| 97 | cs->exception_index = env->interrupt_index; |
| 98 | sparc_cpu_do_interrupt(cs); |
| 99 | return true; |
| 100 | } |
| 101 | } |
| 102 | } |
| 103 | return false; |
| 104 | } |
| 105 | #endif /* !CONFIG_USER_ONLY */ |
| 106 | |
| 107 | static void cpu_sparc_disas_set_info(const CPUState *cpu, |
| 108 | disassemble_info *info) |
| 109 | { |
| 110 | info->print_insn = print_insn_sparc; |
| 111 | info->endian = BFD_ENDIAN_BIG; |
| 112 | #ifdef TARGET_SPARC64 |
| 113 | info->mach = bfd_mach_sparc_v9b; |
| 114 | #endif |
| 115 | } |
| 116 | |
| 117 | static void |
| 118 | cpu_add_feat_as_prop(const char *typename, const char *name, const char *val) |
| 119 | { |
| 120 | GlobalProperty *prop = g_new0(typeof(*prop), 1); |
| 121 | prop->driver = typename; |
| 122 | prop->property = g_strdup(name); |
| 123 | prop->value = g_strdup(val); |
| 124 | qdev_prop_register_global(prop); |
| 125 | } |
| 126 | |
| 127 | /* Parse "+feature,-feature,feature=foo" CPU feature string */ |
| 128 | static void sparc_cpu_parse_features(const char *typename, char *features, |
| 129 | Error **errp) |
| 130 | { |
| 131 | GList *l, *plus_features = NULL, *minus_features = NULL; |
| 132 | char *featurestr; /* Single 'key=value" string being parsed */ |
| 133 | static bool cpu_globals_initialized; |
| 134 | |
| 135 | if (cpu_globals_initialized) { |
| 136 | return; |
| 137 | } |
| 138 | cpu_globals_initialized = true; |
| 139 | |
| 140 | if (!features) { |
| 141 | return; |
| 142 | } |
| 143 | |
| 144 | for (featurestr = strtok(features, ","); |
| 145 | featurestr; |
| 146 | featurestr = strtok(NULL, ",")) { |
| 147 | const char *name; |
| 148 | const char *val = NULL; |
| 149 | char *eq = NULL; |
| 150 | |
| 151 | /* Compatibility syntax: */ |
| 152 | if (featurestr[0] == '+') { |
| 153 | plus_features = g_list_append(plus_features, |
| 154 | g_strdup(featurestr + 1)); |
| 155 | continue; |
| 156 | } else if (featurestr[0] == '-') { |
| 157 | minus_features = g_list_append(minus_features, |
| 158 | g_strdup(featurestr + 1)); |
| 159 | continue; |
| 160 | } |
| 161 | |
| 162 | eq = strchr(featurestr, '='); |
| 163 | name = featurestr; |
| 164 | if (eq) { |
| 165 | *eq++ = 0; |
| 166 | val = eq; |
| 167 | |
| 168 | /* |
| 169 | * Temporarily, only +feat/-feat will be supported |
| 170 | * for boolean properties until we remove the |
| 171 | * minus-overrides-plus semantics and just follow |
| 172 | * the order options appear on the command-line. |
| 173 | * |
| 174 | * TODO: warn if user is relying on minus-override-plus semantics |
| 175 | * TODO: remove minus-override-plus semantics after |
| 176 | * warning for a few releases |
| 177 | */ |
| 178 | if (!g_ascii_strcasecmp(val, "on") || |
| 179 | !g_ascii_strcasecmp(val, "off") || |
| 180 | !g_ascii_strcasecmp(val, "true") || |
| 181 | !g_ascii_strcasecmp(val, "false")) { |
| 182 | error_setg(errp, "Boolean properties in format %s=%s" |
| 183 | " are not supported", name, val); |
| 184 | return; |
| 185 | } |
| 186 | } else { |
| 187 | error_setg(errp, "Unsupported property format: %s", name); |
| 188 | return; |
| 189 | } |
| 190 | cpu_add_feat_as_prop(typename, name, val); |
| 191 | } |
| 192 | |
| 193 | for (l = plus_features; l; l = l->next) { |
| 194 | const char *name = l->data; |
| 195 | cpu_add_feat_as_prop(typename, name, "on"); |
| 196 | } |
| 197 | g_list_free_full(plus_features, g_free); |
| 198 | |
| 199 | for (l = minus_features; l; l = l->next) { |
| 200 | const char *name = l->data; |
| 201 | cpu_add_feat_as_prop(typename, name, "off"); |
| 202 | } |
| 203 | g_list_free_full(minus_features, g_free); |
| 204 | } |
| 205 | |
| 206 | void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu) |
| 207 | { |
| 208 | #if !defined(TARGET_SPARC64) |
| 209 | env->mxccregs[7] = ((cpu + 8) & 0xf) << 24; |
| 210 | #endif |
| 211 | } |
| 212 | |
| 213 | static const sparc_def_t sparc_defs[] = { |
| 214 | #ifdef TARGET_SPARC64 |
| 215 | { |
| 216 | .name = "Fujitsu-Sparc64", |
| 217 | .iu_version = ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24)), |
| 218 | .fpu_version = 0x00000000, |
| 219 | .mmu_version = mmu_us_12, |
| 220 | .nwindows = 4, |
| 221 | .maxtl = 4, |
| 222 | .features = CPU_DEFAULT_FEATURES, |
| 223 | }, |
| 224 | { |
| 225 | .name = "Fujitsu-Sparc64-III", |
| 226 | .iu_version = ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24)), |
| 227 | .fpu_version = 0x00000000, |
| 228 | .mmu_version = mmu_us_12, |
| 229 | .nwindows = 5, |
| 230 | .maxtl = 4, |
| 231 | .features = CPU_DEFAULT_FEATURES, |
| 232 | }, |
| 233 | { |
| 234 | .name = "Fujitsu-Sparc64-IV", |
| 235 | .iu_version = ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24)), |
| 236 | .fpu_version = 0x00000000, |
| 237 | .mmu_version = mmu_us_12, |
| 238 | .nwindows = 8, |
| 239 | .maxtl = 5, |
| 240 | .features = CPU_DEFAULT_FEATURES, |
| 241 | }, |
| 242 | { |
| 243 | .name = "Fujitsu-Sparc64-V", |
| 244 | .iu_version = ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24)), |
| 245 | .fpu_version = 0x00000000, |
| 246 | .mmu_version = mmu_us_12, |
| 247 | .nwindows = 8, |
| 248 | .maxtl = 5, |
| 249 | .features = CPU_DEFAULT_FEATURES, |
| 250 | }, |
| 251 | { |
| 252 | .name = "TI-UltraSparc-I", |
| 253 | .iu_version = ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)), |
| 254 | .fpu_version = 0x00000000, |
| 255 | .mmu_version = mmu_us_12, |
| 256 | .nwindows = 8, |
| 257 | .maxtl = 5, |
| 258 | .features = CPU_DEFAULT_FEATURES, |
| 259 | }, |
| 260 | { |
| 261 | .name = "TI-UltraSparc-II", |
| 262 | .iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24)), |
| 263 | .fpu_version = 0x00000000, |
| 264 | .mmu_version = mmu_us_12, |
| 265 | .nwindows = 8, |
| 266 | .maxtl = 5, |
| 267 | .features = CPU_DEFAULT_FEATURES, |
| 268 | }, |
| 269 | { |
| 270 | .name = "TI-UltraSparc-IIi", |
| 271 | .iu_version = ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24)), |
| 272 | .fpu_version = 0x00000000, |
| 273 | .mmu_version = mmu_us_12, |
| 274 | .nwindows = 8, |
| 275 | .maxtl = 5, |
| 276 | .features = CPU_DEFAULT_FEATURES, |
| 277 | }, |
| 278 | { |
| 279 | .name = "TI-UltraSparc-IIe", |
| 280 | .iu_version = ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24)), |
| 281 | .fpu_version = 0x00000000, |
| 282 | .mmu_version = mmu_us_12, |
| 283 | .nwindows = 8, |
| 284 | .maxtl = 5, |
| 285 | .features = CPU_DEFAULT_FEATURES, |
| 286 | }, |
| 287 | { |
| 288 | .name = "Sun-UltraSparc-III", |
| 289 | .iu_version = ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24)), |
| 290 | .fpu_version = 0x00000000, |
| 291 | .mmu_version = mmu_us_12, |
| 292 | .nwindows = 8, |
| 293 | .maxtl = 5, |
| 294 | .features = CPU_DEFAULT_FEATURES, |
| 295 | }, |
| 296 | { |
| 297 | .name = "Sun-UltraSparc-III-Cu", |
| 298 | .iu_version = ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24)), |
| 299 | .fpu_version = 0x00000000, |
| 300 | .mmu_version = mmu_us_3, |
| 301 | .nwindows = 8, |
| 302 | .maxtl = 5, |
| 303 | .features = CPU_DEFAULT_FEATURES, |
| 304 | }, |
| 305 | { |
| 306 | .name = "Sun-UltraSparc-IIIi", |
| 307 | .iu_version = ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 24)), |
| 308 | .fpu_version = 0x00000000, |
| 309 | .mmu_version = mmu_us_12, |
| 310 | .nwindows = 8, |
| 311 | .maxtl = 5, |
| 312 | .features = CPU_DEFAULT_FEATURES, |
| 313 | }, |
| 314 | { |
| 315 | .name = "Sun-UltraSparc-IV", |
| 316 | .iu_version = ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 24)), |
| 317 | .fpu_version = 0x00000000, |
| 318 | .mmu_version = mmu_us_4, |
| 319 | .nwindows = 8, |
| 320 | .maxtl = 5, |
| 321 | .features = CPU_DEFAULT_FEATURES, |
| 322 | }, |
| 323 | { |
| 324 | .name = "Sun-UltraSparc-IV-plus", |
| 325 | .iu_version = ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 24)), |
| 326 | .fpu_version = 0x00000000, |
| 327 | .mmu_version = mmu_us_12, |
| 328 | .nwindows = 8, |
| 329 | .maxtl = 5, |
| 330 | .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_CMT, |
| 331 | }, |
| 332 | { |
| 333 | .name = "Sun-UltraSparc-IIIi-plus", |
| 334 | .iu_version = ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24)), |
| 335 | .fpu_version = 0x00000000, |
| 336 | .mmu_version = mmu_us_3, |
| 337 | .nwindows = 8, |
| 338 | .maxtl = 5, |
| 339 | .features = CPU_DEFAULT_FEATURES, |
| 340 | }, |
| 341 | { |
| 342 | .name = "Sun-UltraSparc-T1", |
| 343 | /* defined in sparc_ifu_fdp.v and ctu.h */ |
| 344 | .iu_version = ((0x3eULL << 48) | (0x23ULL << 32) | (0x02ULL << 24)), |
| 345 | .fpu_version = 0x00000000, |
| 346 | .mmu_version = mmu_sun4v, |
| 347 | .nwindows = 8, |
| 348 | .maxtl = 6, |
| 349 | .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT |
| 350 | | CPU_FEATURE_GL, |
| 351 | }, |
| 352 | { |
| 353 | .name = "Sun-UltraSparc-T2", |
| 354 | /* defined in tlu_asi_ctl.v and n2_revid_cust.v */ |
| 355 | .iu_version = ((0x3eULL << 48) | (0x24ULL << 32) | (0x02ULL << 24)), |
| 356 | .fpu_version = 0x00000000, |
| 357 | .mmu_version = mmu_sun4v, |
| 358 | .nwindows = 8, |
| 359 | .maxtl = 6, |
| 360 | .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT |
| 361 | | CPU_FEATURE_GL, |
| 362 | }, |
| 363 | { |
| 364 | .name = "NEC-UltraSparc-I", |
| 365 | .iu_version = ((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)), |
| 366 | .fpu_version = 0x00000000, |
| 367 | .mmu_version = mmu_us_12, |
| 368 | .nwindows = 8, |
| 369 | .maxtl = 5, |
| 370 | .features = CPU_DEFAULT_FEATURES, |
| 371 | }, |
| 372 | #else |
| 373 | { |
| 374 | .name = "Fujitsu-MB86904", |
| 375 | .iu_version = 0x04 << 24, /* Impl 0, ver 4 */ |
| 376 | .fpu_version = 4 << FSR_VER_SHIFT, /* FPU version 4 (Meiko) */ |
| 377 | .mmu_version = 0x04 << 24, /* Impl 0, ver 4 */ |
| 378 | .mmu_bm = 0x00004000, |
| 379 | .mmu_ctpr_mask = 0x00ffffc0, |
| 380 | .mmu_cxr_mask = 0x000000ff, |
| 381 | .mmu_sfsr_mask = 0x00016fff, |
| 382 | .mmu_trcr_mask = 0x00ffffff, |
| 383 | .nwindows = 8, |
| 384 | .features = CPU_DEFAULT_FEATURES, |
| 385 | }, |
| 386 | { |
| 387 | .name = "Fujitsu-MB86907", |
| 388 | .iu_version = 0x05 << 24, /* Impl 0, ver 5 */ |
| 389 | .fpu_version = 4 << FSR_VER_SHIFT, /* FPU version 4 (Meiko) */ |
| 390 | .mmu_version = 0x05 << 24, /* Impl 0, ver 5 */ |
| 391 | .mmu_bm = 0x00004000, |
| 392 | .mmu_ctpr_mask = 0xffffffc0, |
| 393 | .mmu_cxr_mask = 0x000000ff, |
| 394 | .mmu_sfsr_mask = 0x00016fff, |
| 395 | .mmu_trcr_mask = 0xffffffff, |
| 396 | .nwindows = 8, |
| 397 | .features = CPU_DEFAULT_FEATURES, |
| 398 | }, |
| 399 | { |
| 400 | .name = "TI-MicroSparc-I", |
| 401 | .iu_version = 0x41000000, |
| 402 | .fpu_version = 4 << FSR_VER_SHIFT, |
| 403 | .mmu_version = 0x41000000, |
| 404 | .mmu_bm = 0x00004000, |
| 405 | .mmu_ctpr_mask = 0x007ffff0, |
| 406 | .mmu_cxr_mask = 0x0000003f, |
| 407 | .mmu_sfsr_mask = 0x00016fff, |
| 408 | .mmu_trcr_mask = 0x0000003f, |
| 409 | .nwindows = 7, |
| 410 | .features = CPU_FEATURE_MUL | CPU_FEATURE_DIV, |
| 411 | }, |
| 412 | { |
| 413 | .name = "TI-MicroSparc-II", |
| 414 | .iu_version = 0x42000000, |
| 415 | .fpu_version = 4 << FSR_VER_SHIFT, |
| 416 | .mmu_version = 0x02000000, |
| 417 | .mmu_bm = 0x00004000, |
| 418 | .mmu_ctpr_mask = 0x00ffffc0, |
| 419 | .mmu_cxr_mask = 0x000000ff, |
| 420 | .mmu_sfsr_mask = 0x00016fff, |
| 421 | .mmu_trcr_mask = 0x00ffffff, |
| 422 | .nwindows = 8, |
| 423 | .features = CPU_DEFAULT_FEATURES, |
| 424 | }, |
| 425 | { |
| 426 | .name = "TI-MicroSparc-IIep", |
| 427 | .iu_version = 0x42000000, |
| 428 | .fpu_version = 4 << FSR_VER_SHIFT, |
| 429 | .mmu_version = 0x04000000, |
| 430 | .mmu_bm = 0x00004000, |
| 431 | .mmu_ctpr_mask = 0x00ffffc0, |
| 432 | .mmu_cxr_mask = 0x000000ff, |
| 433 | .mmu_sfsr_mask = 0x00016bff, |
| 434 | .mmu_trcr_mask = 0x00ffffff, |
| 435 | .nwindows = 8, |
| 436 | .features = CPU_DEFAULT_FEATURES, |
| 437 | }, |
| 438 | { |
| 439 | .name = "TI-SuperSparc-40", /* STP1020NPGA */ |
| 440 | .iu_version = 0x41000000, /* SuperSPARC 2.x */ |
| 441 | .fpu_version = 0 << FSR_VER_SHIFT, |
| 442 | .mmu_version = 0x00000800, /* SuperSPARC 2.x, no MXCC */ |
| 443 | .mmu_bm = 0x00002000, |
| 444 | .mmu_ctpr_mask = 0xffffffc0, |
| 445 | .mmu_cxr_mask = 0x0000ffff, |
| 446 | .mmu_sfsr_mask = 0xffffffff, |
| 447 | .mmu_trcr_mask = 0xffffffff, |
| 448 | .nwindows = 8, |
| 449 | .features = CPU_DEFAULT_FEATURES, |
| 450 | }, |
| 451 | { |
| 452 | .name = "TI-SuperSparc-50", /* STP1020PGA */ |
| 453 | .iu_version = 0x40000000, /* SuperSPARC 3.x */ |
| 454 | .fpu_version = 0 << FSR_VER_SHIFT, |
| 455 | .mmu_version = 0x01000800, /* SuperSPARC 3.x, no MXCC */ |
| 456 | .mmu_bm = 0x00002000, |
| 457 | .mmu_ctpr_mask = 0xffffffc0, |
| 458 | .mmu_cxr_mask = 0x0000ffff, |
| 459 | .mmu_sfsr_mask = 0xffffffff, |
| 460 | .mmu_trcr_mask = 0xffffffff, |
| 461 | .nwindows = 8, |
| 462 | .features = CPU_DEFAULT_FEATURES, |
| 463 | }, |
| 464 | { |
| 465 | .name = "TI-SuperSparc-51", |
| 466 | .iu_version = 0x40000000, /* SuperSPARC 3.x */ |
| 467 | .fpu_version = 0 << FSR_VER_SHIFT, |
| 468 | .mmu_version = 0x01000000, /* SuperSPARC 3.x, MXCC */ |
| 469 | .mmu_bm = 0x00002000, |
| 470 | .mmu_ctpr_mask = 0xffffffc0, |
| 471 | .mmu_cxr_mask = 0x0000ffff, |
| 472 | .mmu_sfsr_mask = 0xffffffff, |
| 473 | .mmu_trcr_mask = 0xffffffff, |
| 474 | .mxcc_version = 0x00000104, |
| 475 | .nwindows = 8, |
| 476 | .features = CPU_DEFAULT_FEATURES, |
| 477 | }, |
| 478 | { |
| 479 | .name = "TI-SuperSparc-60", /* STP1020APGA */ |
| 480 | .iu_version = 0x40000000, /* SuperSPARC 3.x */ |
| 481 | .fpu_version = 0 << FSR_VER_SHIFT, |
| 482 | .mmu_version = 0x01000800, /* SuperSPARC 3.x, no MXCC */ |
| 483 | .mmu_bm = 0x00002000, |
| 484 | .mmu_ctpr_mask = 0xffffffc0, |
| 485 | .mmu_cxr_mask = 0x0000ffff, |
| 486 | .mmu_sfsr_mask = 0xffffffff, |
| 487 | .mmu_trcr_mask = 0xffffffff, |
| 488 | .nwindows = 8, |
| 489 | .features = CPU_DEFAULT_FEATURES, |
| 490 | }, |
| 491 | { |
| 492 | .name = "TI-SuperSparc-61", |
| 493 | .iu_version = 0x44000000, /* SuperSPARC 3.x */ |
| 494 | .fpu_version = 0 << FSR_VER_SHIFT, |
| 495 | .mmu_version = 0x01000000, /* SuperSPARC 3.x, MXCC */ |
| 496 | .mmu_bm = 0x00002000, |
| 497 | .mmu_ctpr_mask = 0xffffffc0, |
| 498 | .mmu_cxr_mask = 0x0000ffff, |
| 499 | .mmu_sfsr_mask = 0xffffffff, |
| 500 | .mmu_trcr_mask = 0xffffffff, |
| 501 | .mxcc_version = 0x00000104, |
| 502 | .nwindows = 8, |
| 503 | .features = CPU_DEFAULT_FEATURES, |
| 504 | }, |
| 505 | { |
| 506 | .name = "TI-SuperSparc-II", |
| 507 | .iu_version = 0x40000000, /* SuperSPARC II 1.x */ |
| 508 | .fpu_version = 0 << FSR_VER_SHIFT, |
| 509 | .mmu_version = 0x08000000, /* SuperSPARC II 1.x, MXCC */ |
| 510 | .mmu_bm = 0x00002000, |
| 511 | .mmu_ctpr_mask = 0xffffffc0, |
| 512 | .mmu_cxr_mask = 0x0000ffff, |
| 513 | .mmu_sfsr_mask = 0xffffffff, |
| 514 | .mmu_trcr_mask = 0xffffffff, |
| 515 | .mxcc_version = 0x00000104, |
| 516 | .nwindows = 8, |
| 517 | .features = CPU_DEFAULT_FEATURES, |
| 518 | }, |
| 519 | { |
| 520 | .name = "LEON2", |
| 521 | .iu_version = 0xf2000000, |
| 522 | .fpu_version = 4 << FSR_VER_SHIFT, /* FPU version 4 (Meiko) */ |
| 523 | .mmu_version = 0xf2000000, |
| 524 | .mmu_bm = 0x00004000, |
| 525 | .mmu_ctpr_mask = 0x007ffff0, |
| 526 | .mmu_cxr_mask = 0x0000003f, |
| 527 | .mmu_sfsr_mask = 0xffffffff, |
| 528 | .mmu_trcr_mask = 0xffffffff, |
| 529 | .nwindows = 8, |
| 530 | .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_TA0_SHUTDOWN, |
| 531 | }, |
| 532 | { |
| 533 | .name = "LEON3", |
| 534 | .iu_version = 0xf3000000, |
| 535 | .fpu_version = 4 << FSR_VER_SHIFT, /* FPU version 4 (Meiko) */ |
| 536 | .mmu_version = 0xf3000000, |
| 537 | .mmu_bm = 0x00000000, |
| 538 | .mmu_ctpr_mask = 0xfffffffc, |
| 539 | .mmu_cxr_mask = 0x000000ff, |
| 540 | .mmu_sfsr_mask = 0xffffffff, |
| 541 | .mmu_trcr_mask = 0xffffffff, |
| 542 | .nwindows = 8, |
| 543 | .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_TA0_SHUTDOWN | |
| 544 | CPU_FEATURE_ASR17 | CPU_FEATURE_CACHE_CTRL | CPU_FEATURE_POWERDOWN | |
| 545 | CPU_FEATURE_CASA, |
| 546 | }, |
| 547 | #endif |
| 548 | }; |
| 549 | |
| 550 | /* This must match sparc_cpu_properties[]. */ |
| 551 | static const char * const feature_name[] = { |
| 552 | [CPU_FEATURE_BIT_FLOAT128] = "float128", |
| 553 | #ifdef TARGET_SPARC64 |
| 554 | [CPU_FEATURE_BIT_CMT] = "cmt", |
| 555 | [CPU_FEATURE_BIT_GL] = "gl", |
| 556 | [CPU_FEATURE_BIT_HYPV] = "hypv", |
| 557 | [CPU_FEATURE_BIT_VIS1] = "vis1", |
| 558 | [CPU_FEATURE_BIT_VIS2] = "vis2", |
| 559 | [CPU_FEATURE_BIT_FMAF] = "fmaf", |
| 560 | [CPU_FEATURE_BIT_VIS3] = "vis3", |
| 561 | [CPU_FEATURE_BIT_IMA] = "ima", |
| 562 | [CPU_FEATURE_BIT_VIS4] = "vis4", |
| 563 | #else |
| 564 | [CPU_FEATURE_BIT_MUL] = "mul", |
| 565 | [CPU_FEATURE_BIT_DIV] = "div", |
| 566 | [CPU_FEATURE_BIT_FSMULD] = "fsmuld", |
| 567 | #endif |
| 568 | }; |
| 569 | |
| 570 | static void print_features(uint32_t features, const char *prefix) |
| 571 | { |
| 572 | unsigned int i; |
| 573 | |
| 574 | for (i = 0; i < ARRAY_SIZE(feature_name); i++) { |
| 575 | if (feature_name[i] && (features & (1 << i))) { |
| 576 | if (prefix) { |
| 577 | qemu_printf("%s", prefix); |
| 578 | } |
| 579 | qemu_printf("%s ", feature_name[i]); |
| 580 | } |
| 581 | } |
| 582 | } |
| 583 | |
| 584 | static void sparc_cpu_list(void) |
| 585 | { |
| 586 | unsigned int i; |
| 587 | |
| 588 | qemu_printf("Available CPU types:\n"); |
| 589 | for (i = 0; i < ARRAY_SIZE(sparc_defs); i++) { |
| 590 | qemu_printf(" %-20s (IU " TARGET_FMT_lx |
| 591 | " FPU %08x MMU %08x NWINS %d) ", |
| 592 | sparc_defs[i].name, |
| 593 | sparc_defs[i].iu_version, |
| 594 | sparc_defs[i].fpu_version, |
| 595 | sparc_defs[i].mmu_version, |
| 596 | sparc_defs[i].nwindows); |
| 597 | print_features(CPU_DEFAULT_FEATURES & ~sparc_defs[i].features, "-"); |
| 598 | print_features(~CPU_DEFAULT_FEATURES & sparc_defs[i].features, "+"); |
| 599 | qemu_printf("\n"); |
| 600 | } |
| 601 | qemu_printf("Default CPU feature flags (use '-' to remove): "); |
| 602 | print_features(CPU_DEFAULT_FEATURES, NULL); |
| 603 | qemu_printf("\n"); |
| 604 | qemu_printf("Available CPU feature flags (use '+' to add): "); |
| 605 | print_features(~CPU_DEFAULT_FEATURES, NULL); |
| 606 | qemu_printf("\n"); |
| 607 | qemu_printf("Numerical features (use '=' to set): iu_version " |
| 608 | "fpu_version mmu_version nwindows\n"); |
| 609 | } |
| 610 | |
| 611 | static void cpu_print_cc(FILE *f, uint32_t cc) |
| 612 | { |
| 613 | qemu_fprintf(f, "%c%c%c%c", cc & PSR_NEG ? 'N' : '-', |
| 614 | cc & PSR_ZERO ? 'Z' : '-', cc & PSR_OVF ? 'V' : '-', |
| 615 | cc & PSR_CARRY ? 'C' : '-'); |
| 616 | } |
| 617 | |
| 618 | #ifdef TARGET_SPARC64 |
| 619 | #define REGS_PER_LINE 4 |
| 620 | #else |
| 621 | #define REGS_PER_LINE 8 |
| 622 | #endif |
| 623 | |
| 624 | static void sparc_cpu_dump_state(CPUState *cs, FILE *f, int flags) |
| 625 | { |
| 626 | CPUSPARCState *env = cpu_env(cs); |
| 627 | int i, x; |
| 628 | |
| 629 | qemu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc, |
| 630 | env->npc); |
| 631 | |
| 632 | for (i = 0; i < 8; i++) { |
| 633 | if (i % REGS_PER_LINE == 0) { |
| 634 | qemu_fprintf(f, "%%g%d-%d:", i, i + REGS_PER_LINE - 1); |
| 635 | } |
| 636 | qemu_fprintf(f, " " TARGET_FMT_lx, env->gregs[i]); |
| 637 | if (i % REGS_PER_LINE == REGS_PER_LINE - 1) { |
| 638 | qemu_fprintf(f, "\n"); |
| 639 | } |
| 640 | } |
| 641 | for (x = 0; x < 3; x++) { |
| 642 | for (i = 0; i < 8; i++) { |
| 643 | if (i % REGS_PER_LINE == 0) { |
| 644 | qemu_fprintf(f, "%%%c%d-%d: ", |
| 645 | x == 0 ? 'o' : (x == 1 ? 'l' : 'i'), |
| 646 | i, i + REGS_PER_LINE - 1); |
| 647 | } |
| 648 | qemu_fprintf(f, TARGET_FMT_lx " ", env->regwptr[i + x * 8]); |
| 649 | if (i % REGS_PER_LINE == REGS_PER_LINE - 1) { |
| 650 | qemu_fprintf(f, "\n"); |
| 651 | } |
| 652 | } |
| 653 | } |
| 654 | |
| 655 | if (flags & CPU_DUMP_FPU) { |
| 656 | for (i = 0; i < TARGET_DPREGS; i++) { |
| 657 | if ((i & 3) == 0) { |
| 658 | qemu_fprintf(f, "%%f%02d: ", i * 2); |
| 659 | } |
| 660 | qemu_fprintf(f, " %016" PRIx64, env->fpr[i].ll); |
| 661 | if ((i & 3) == 3) { |
| 662 | qemu_fprintf(f, "\n"); |
| 663 | } |
| 664 | } |
| 665 | } |
| 666 | |
| 667 | #ifdef TARGET_SPARC64 |
| 668 | qemu_fprintf(f, "pstate: %08x ccr: %02x (icc: ", env->pstate, |
| 669 | (unsigned)cpu_get_ccr(env)); |
| 670 | cpu_print_cc(f, cpu_get_ccr(env) << PSR_CARRY_SHIFT); |
| 671 | qemu_fprintf(f, " xcc: "); |
| 672 | cpu_print_cc(f, cpu_get_ccr(env) << (PSR_CARRY_SHIFT - 4)); |
| 673 | qemu_fprintf(f, ") asi: %02x tl: %d pil: %x gl: %d\n", env->asi, env->tl, |
| 674 | env->psrpil, env->gl); |
| 675 | qemu_fprintf(f, "tbr: " TARGET_FMT_lx " hpstate: " TARGET_FMT_lx " htba: " |
| 676 | TARGET_FMT_lx "\n", env->tbr, env->hpstate, env->htba); |
| 677 | qemu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate: %d " |
| 678 | "cleanwin: %d cwp: %d\n", |
| 679 | env->cansave, env->canrestore, env->otherwin, env->wstate, |
| 680 | env->cleanwin, env->nwindows - 1 - env->cwp); |
| 681 | qemu_fprintf(f, "fsr: " TARGET_FMT_lx " y: " TARGET_FMT_lx " fprs: %016x\n", |
| 682 | cpu_get_fsr(env), env->y, env->fprs); |
| 683 | |
| 684 | #else |
| 685 | qemu_fprintf(f, "psr: %08x (icc: ", cpu_get_psr(env)); |
| 686 | cpu_print_cc(f, cpu_get_psr(env)); |
| 687 | qemu_fprintf(f, " SPE: %c%c%c) wim: %08x\n", env->psrs ? 'S' : '-', |
| 688 | env->psrps ? 'P' : '-', env->psret ? 'E' : '-', |
| 689 | env->wim); |
| 690 | qemu_fprintf(f, "fsr: " TARGET_FMT_lx " y: " TARGET_FMT_lx "\n", |
| 691 | cpu_get_fsr(env), env->y); |
| 692 | #endif |
| 693 | qemu_fprintf(f, "\n"); |
| 694 | } |
| 695 | |
| 696 | static void sparc_cpu_set_pc(CPUState *cs, vaddr value) |
| 697 | { |
| 698 | SPARCCPU *cpu = SPARC_CPU(cs); |
| 699 | |
| 700 | cpu->env.pc = value; |
| 701 | cpu->env.npc = value + 4; |
| 702 | } |
| 703 | |
| 704 | static vaddr sparc_cpu_get_pc(CPUState *cs) |
| 705 | { |
| 706 | SPARCCPU *cpu = SPARC_CPU(cs); |
| 707 | |
| 708 | return cpu->env.pc; |
| 709 | } |
| 710 | |
| 711 | static void sparc_cpu_synchronize_from_tb(CPUState *cs, |
| 712 | const TranslationBlock *tb) |
| 713 | { |
| 714 | SPARCCPU *cpu = SPARC_CPU(cs); |
| 715 | |
| 716 | tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL)); |
| 717 | cpu->env.pc = tb->pc; |
| 718 | cpu->env.npc = tb->cs_base; |
| 719 | } |
| 720 | |
| 721 | static TCGTBCPUState sparc_get_tb_cpu_state(CPUState *cs) |
| 722 | { |
| 723 | CPUSPARCState *env = cpu_env(cs); |
| 724 | uint32_t flags = cpu_mmu_index(cs, false); |
| 725 | |
| 726 | #ifndef CONFIG_USER_ONLY |
| 727 | if (cpu_supervisor_mode(env)) { |
| 728 | flags |= TB_FLAG_SUPER; |
| 729 | } |
| 730 | #endif |
| 731 | #ifdef TARGET_SPARC64 |
| 732 | #ifndef CONFIG_USER_ONLY |
| 733 | if (cpu_hypervisor_mode(env)) { |
| 734 | flags |= TB_FLAG_HYPER; |
| 735 | } |
| 736 | #endif |
| 737 | if (env->pstate & PS_AM) { |
| 738 | flags |= TB_FLAG_AM_ENABLED; |
| 739 | } |
| 740 | if ((env->pstate & PS_PEF) && (env->fprs & FPRS_FEF)) { |
| 741 | flags |= TB_FLAG_FPU_ENABLED; |
| 742 | } |
| 743 | flags |= env->asi << TB_FLAG_ASI_SHIFT; |
| 744 | #else |
| 745 | if (env->psref) { |
| 746 | flags |= TB_FLAG_FPU_ENABLED; |
| 747 | } |
| 748 | #ifndef CONFIG_USER_ONLY |
| 749 | if (env->fsr_qne) { |
| 750 | flags |= TB_FLAG_FSR_QNE; |
| 751 | } |
| 752 | #endif /* !CONFIG_USER_ONLY */ |
| 753 | #endif /* TARGET_SPARC64 */ |
| 754 | |
| 755 | return (TCGTBCPUState){ |
| 756 | .pc = env->pc, |
| 757 | .flags = flags, |
| 758 | .cs_base = env->npc, |
| 759 | }; |
| 760 | } |
| 761 | |
| 762 | static void sparc_restore_state_to_opc(CPUState *cs, |
| 763 | const TranslationBlock *tb, |
| 764 | const uint64_t *data) |
| 765 | { |
| 766 | CPUSPARCState *env = cpu_env(cs); |
| 767 | target_ulong pc = data[0]; |
| 768 | target_ulong npc = data[1]; |
| 769 | |
| 770 | env->pc = pc; |
| 771 | if (npc == DYNAMIC_PC) { |
| 772 | /* dynamic NPC: already stored */ |
| 773 | } else if (npc & JUMP_PC) { |
| 774 | /* jump PC: use 'cond' and the jump targets of the translation */ |
| 775 | if (env->cond) { |
| 776 | env->npc = npc & ~3; |
| 777 | } else { |
| 778 | env->npc = pc + 4; |
| 779 | } |
| 780 | } else { |
| 781 | env->npc = npc; |
| 782 | } |
| 783 | } |
| 784 | |
| 785 | #ifndef CONFIG_USER_ONLY |
| 786 | static bool sparc_cpu_has_work(CPUState *cs) |
| 787 | { |
| 788 | return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD) && |
| 789 | cpu_interrupts_enabled(cpu_env(cs)); |
| 790 | } |
| 791 | #endif /* !CONFIG_USER_ONLY */ |
| 792 | |
| 793 | static int sparc_cpu_mmu_index(CPUState *cs, bool ifetch) |
| 794 | { |
| 795 | CPUSPARCState *env = cpu_env(cs); |
| 796 | |
| 797 | #ifndef TARGET_SPARC64 |
| 798 | if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */ |
| 799 | return MMU_PHYS_IDX; |
| 800 | } else { |
| 801 | return env->psrs; |
| 802 | } |
| 803 | #else |
| 804 | /* IMMU or DMMU disabled. */ |
| 805 | if (ifetch |
| 806 | ? (env->lsu & IMMU_E) == 0 || (env->pstate & PS_RED) != 0 |
| 807 | : (env->lsu & DMMU_E) == 0) { |
| 808 | return MMU_PHYS_IDX; |
| 809 | } else if (cpu_hypervisor_mode(env)) { |
| 810 | return MMU_PHYS_IDX; |
| 811 | } else if (env->tl > 0) { |
| 812 | return MMU_NUCLEUS_IDX; |
| 813 | } else if (cpu_supervisor_mode(env)) { |
| 814 | return MMU_KERNEL_IDX; |
| 815 | } else { |
| 816 | return MMU_USER_IDX; |
| 817 | } |
| 818 | #endif |
| 819 | } |
| 820 | |
| 821 | static char *sparc_cpu_type_name(const char *cpu_model) |
| 822 | { |
| 823 | char *name = g_strdup_printf(SPARC_CPU_TYPE_NAME("%s"), cpu_model); |
| 824 | char *s = name; |
| 825 | |
| 826 | /* SPARC cpu model names happen to have whitespaces, |
| 827 | * as type names shouldn't have spaces replace them with '-' |
| 828 | */ |
| 829 | while ((s = strchr(s, ' '))) { |
| 830 | *s = '-'; |
| 831 | } |
| 832 | |
| 833 | return name; |
| 834 | } |
| 835 | |
| 836 | static ObjectClass *sparc_cpu_class_by_name(const char *cpu_model) |
| 837 | { |
| 838 | ObjectClass *oc; |
| 839 | char *typename; |
| 840 | |
| 841 | typename = sparc_cpu_type_name(cpu_model); |
| 842 | |
| 843 | /* Fix up legacy names with '+' in it */ |
| 844 | if (g_str_equal(typename, SPARC_CPU_TYPE_NAME("Sun-UltraSparc-IV+"))) { |
| 845 | g_free(typename); |
| 846 | typename = g_strdup(SPARC_CPU_TYPE_NAME("Sun-UltraSparc-IV-plus")); |
| 847 | } else if (g_str_equal(typename, SPARC_CPU_TYPE_NAME("Sun-UltraSparc-IIIi+"))) { |
| 848 | g_free(typename); |
| 849 | typename = g_strdup(SPARC_CPU_TYPE_NAME("Sun-UltraSparc-IIIi-plus")); |
| 850 | } |
| 851 | |
| 852 | oc = object_class_by_name(typename); |
| 853 | g_free(typename); |
| 854 | return oc; |
| 855 | } |
| 856 | |
| 857 | static void sparc_cpu_realizefn(DeviceState *dev, Error **errp) |
| 858 | { |
| 859 | CPUState *cs = CPU(dev); |
| 860 | SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(dev); |
| 861 | Error *local_err = NULL; |
| 862 | CPUSPARCState *env = cpu_env(cs); |
| 863 | |
| 864 | #if defined(CONFIG_USER_ONLY) |
| 865 | /* We are emulating the kernel, which will trap and emulate float128. */ |
| 866 | env->def.features |= CPU_FEATURE_FLOAT128; |
| 867 | #endif |
| 868 | |
| 869 | env->version = env->def.iu_version; |
| 870 | env->nwindows = env->def.nwindows; |
| 871 | #if !defined(TARGET_SPARC64) |
| 872 | env->mmuregs[0] |= env->def.mmu_version; |
| 873 | cpu_sparc_set_id(env, 0); |
| 874 | env->mxccregs[7] |= env->def.mxcc_version; |
| 875 | #else |
| 876 | env->mmu_version = env->def.mmu_version; |
| 877 | env->maxtl = env->def.maxtl; |
| 878 | env->version |= env->def.maxtl << 8; |
| 879 | env->version |= env->def.nwindows - 1; |
| 880 | #endif |
| 881 | |
| 882 | /* |
| 883 | * Prefer SNaN over QNaN, order B then A. It's OK to do this in realize |
| 884 | * rather than reset, because fp_status is after 'end_reset_fields' in |
| 885 | * the CPU state struct so it won't get zeroed on reset. |
| 886 | */ |
| 887 | set_float_2nan_prop_rule(float_2nan_prop_s_ba, &env->fp_status); |
| 888 | /* For fused-multiply add, prefer SNaN over QNaN, then C->B->A */ |
| 889 | set_float_3nan_prop_rule(float_3nan_prop_s_cba, &env->fp_status); |
| 890 | /* For inf * 0 + NaN, return the input NaN */ |
| 891 | set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); |
| 892 | /* Default NaN value: sign bit clear, all frac bits set */ |
| 893 | set_float_default_nan_pattern(0b01111111, &env->fp_status); |
| 894 | |
| 895 | cpu_common_realize(cs, &local_err); |
| 896 | if (local_err != NULL) { |
| 897 | error_propagate(errp, local_err); |
| 898 | return; |
| 899 | } |
| 900 | |
| 901 | sparc_cpu_register_gdb_regs(cs); |
| 902 | |
| 903 | qemu_init_vcpu(cs); |
| 904 | |
| 905 | scc->parent_realize(dev, errp); |
| 906 | } |
| 907 | |
| 908 | static void sparc_cpu_initfn(Object *obj) |
| 909 | { |
| 910 | SPARCCPU *cpu = SPARC_CPU(obj); |
| 911 | SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(obj); |
| 912 | CPUSPARCState *env = &cpu->env; |
| 913 | |
| 914 | if (scc->cpu_def) { |
| 915 | env->def = *scc->cpu_def; |
| 916 | } |
| 917 | } |
| 918 | |
| 919 | static void sparc_get_nwindows(Object *obj, Visitor *v, const char *name, |
| 920 | void *opaque, Error **errp) |
| 921 | { |
| 922 | SPARCCPU *cpu = SPARC_CPU(obj); |
| 923 | int64_t value = cpu->env.def.nwindows; |
| 924 | |
| 925 | visit_type_int(v, name, &value, errp); |
| 926 | } |
| 927 | |
| 928 | static void sparc_set_nwindows(Object *obj, Visitor *v, const char *name, |
| 929 | void *opaque, Error **errp) |
| 930 | { |
| 931 | const int64_t min = MIN_NWINDOWS; |
| 932 | const int64_t max = MAX_NWINDOWS; |
| 933 | SPARCCPU *cpu = SPARC_CPU(obj); |
| 934 | int64_t value; |
| 935 | |
| 936 | if (!visit_type_int(v, name, &value, errp)) { |
| 937 | return; |
| 938 | } |
| 939 | |
| 940 | if (value < min || value > max) { |
| 941 | error_setg(errp, "Property %s.%s doesn't take value %" PRId64 |
| 942 | " (minimum: %" PRId64 ", maximum: %" PRId64 ")", |
| 943 | object_get_typename(obj), name ? name : "null", |
| 944 | value, min, max); |
| 945 | return; |
| 946 | } |
| 947 | cpu->env.def.nwindows = value; |
| 948 | } |
| 949 | |
| 950 | static const PropertyInfo qdev_prop_nwindows = { |
| 951 | .type = "int", |
| 952 | .description = "Number of register windows", |
| 953 | .get = sparc_get_nwindows, |
| 954 | .set = sparc_set_nwindows, |
| 955 | }; |
| 956 | |
| 957 | /* This must match feature_name[]. */ |
| 958 | static const Property sparc_cpu_properties[] = { |
| 959 | DEFINE_PROP_BIT("float128", SPARCCPU, env.def.features, |
| 960 | CPU_FEATURE_BIT_FLOAT128, false), |
| 961 | #ifdef TARGET_SPARC64 |
| 962 | DEFINE_PROP_BIT("cmt", SPARCCPU, env.def.features, |
| 963 | CPU_FEATURE_BIT_CMT, false), |
| 964 | DEFINE_PROP_BIT("gl", SPARCCPU, env.def.features, |
| 965 | CPU_FEATURE_BIT_GL, false), |
| 966 | DEFINE_PROP_BIT("hypv", SPARCCPU, env.def.features, |
| 967 | CPU_FEATURE_BIT_HYPV, false), |
| 968 | DEFINE_PROP_BIT("vis1", SPARCCPU, env.def.features, |
| 969 | CPU_FEATURE_BIT_VIS1, false), |
| 970 | DEFINE_PROP_BIT("vis2", SPARCCPU, env.def.features, |
| 971 | CPU_FEATURE_BIT_VIS2, false), |
| 972 | DEFINE_PROP_BIT("fmaf", SPARCCPU, env.def.features, |
| 973 | CPU_FEATURE_BIT_FMAF, false), |
| 974 | DEFINE_PROP_BIT("vis3", SPARCCPU, env.def.features, |
| 975 | CPU_FEATURE_BIT_VIS3, false), |
| 976 | DEFINE_PROP_BIT("ima", SPARCCPU, env.def.features, |
| 977 | CPU_FEATURE_BIT_IMA, false), |
| 978 | DEFINE_PROP_BIT("vis4", SPARCCPU, env.def.features, |
| 979 | CPU_FEATURE_BIT_VIS4, false), |
| 980 | #else |
| 981 | DEFINE_PROP_BIT("mul", SPARCCPU, env.def.features, |
| 982 | CPU_FEATURE_BIT_MUL, false), |
| 983 | DEFINE_PROP_BIT("div", SPARCCPU, env.def.features, |
| 984 | CPU_FEATURE_BIT_DIV, false), |
| 985 | DEFINE_PROP_BIT("fsmuld", SPARCCPU, env.def.features, |
| 986 | CPU_FEATURE_BIT_FSMULD, false), |
| 987 | #endif |
| 988 | DEFINE_PROP_UNSIGNED("iu-version", SPARCCPU, env.def.iu_version, 0, |
| 989 | qdev_prop_uint64, target_ulong), |
| 990 | DEFINE_PROP_UINT32("fpu-version", SPARCCPU, env.def.fpu_version, 0), |
| 991 | DEFINE_PROP_UINT32("mmu-version", SPARCCPU, env.def.mmu_version, 0), |
| 992 | DEFINE_PROP("nwindows", SPARCCPU, env.def.nwindows, |
| 993 | qdev_prop_nwindows, uint32_t), |
| 994 | }; |
| 995 | |
| 996 | #ifndef CONFIG_USER_ONLY |
| 997 | |
| 998 | #ifdef TARGET_SPARC64 |
| 999 | #include "monitor/hmp.h" |
| 1000 | #ifdef CONFIG_HMP |
| 1001 | static const MonitorDef sparc64_monitor_defs[] = { |
| 1002 | { "asi", offsetof(CPUSPARCState, asi) }, |
| 1003 | { "pstate", offsetof(CPUSPARCState, pstate) }, |
| 1004 | { "cansave", offsetof(CPUSPARCState, cansave) }, |
| 1005 | { "canrestore", offsetof(CPUSPARCState, canrestore) }, |
| 1006 | { "otherwin", offsetof(CPUSPARCState, otherwin) }, |
| 1007 | { "wstate", offsetof(CPUSPARCState, wstate) }, |
| 1008 | { "cleanwin", offsetof(CPUSPARCState, cleanwin) }, |
| 1009 | { NULL }, |
| 1010 | }; |
| 1011 | #endif |
| 1012 | #endif |
| 1013 | |
| 1014 | #include "hw/core/sysemu-cpu-ops.h" |
| 1015 | |
| 1016 | static const struct SysemuCPUOps sparc_sysemu_ops = { |
| 1017 | .has_work = sparc_cpu_has_work, |
| 1018 | .get_phys_addr_debug = sparc_cpu_get_phys_addr_debug, |
| 1019 | .legacy_vmsd = &vmstate_sparc_cpu, |
| 1020 | #if defined(TARGET_SPARC64) && defined(CONFIG_HMP) |
| 1021 | .monitor_defs = sparc64_monitor_defs, |
| 1022 | #endif |
| 1023 | }; |
| 1024 | #endif |
| 1025 | |
| 1026 | #ifdef CONFIG_TCG |
| 1027 | #include "accel/tcg/cpu-ops.h" |
| 1028 | |
| 1029 | #ifndef CONFIG_USER_ONLY |
| 1030 | static vaddr sparc_pointer_wrap(CPUState *cs, int mmu_idx, |
| 1031 | vaddr result, vaddr base) |
| 1032 | { |
| 1033 | #ifdef TARGET_SPARC64 |
| 1034 | return cpu_env(cs)->pstate & PS_AM ? (uint32_t)result : result; |
| 1035 | #else |
| 1036 | return (uint32_t)result; |
| 1037 | #endif |
| 1038 | } |
| 1039 | #endif |
| 1040 | |
| 1041 | static const TCGCPUOps sparc_tcg_ops = { |
| 1042 | /* |
| 1043 | * From Oracle SPARC Architecture 2015: |
| 1044 | * |
| 1045 | * Compatibility notes: The PSO memory model described in SPARC V8 and |
| 1046 | * SPARC V9 compatibility architecture specifications was never |
| 1047 | * implemented in a SPARC V9 implementation and is not included in the |
| 1048 | * Oracle SPARC Architecture specification. |
| 1049 | * |
| 1050 | * The RMO memory model described in the SPARC V9 specification was |
| 1051 | * implemented in some non-Sun SPARC V9 implementations, but is not |
| 1052 | * directly supported in Oracle SPARC Architecture 2015 implementations. |
| 1053 | * |
| 1054 | * Therefore always use TSO in QEMU. |
| 1055 | * |
| 1056 | * D.5 Specification of Partial Store Order (PSO) |
| 1057 | * ... [loads] are followed by an implied MEMBAR #LoadLoad | #LoadStore. |
| 1058 | * |
| 1059 | * D.6 Specification of Total Store Order (TSO) |
| 1060 | * ... PSO with the additional requirement that all [stores] are followed |
| 1061 | * by an implied MEMBAR #StoreStore. |
| 1062 | */ |
| 1063 | .guest_default_memory_order = TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST, |
| 1064 | .mttcg_supported = true, |
| 1065 | |
| 1066 | .initialize = sparc_tcg_init, |
| 1067 | .translate_code = sparc_translate_code, |
| 1068 | .get_tb_cpu_state = sparc_get_tb_cpu_state, |
| 1069 | .synchronize_from_tb = sparc_cpu_synchronize_from_tb, |
| 1070 | .restore_state_to_opc = sparc_restore_state_to_opc, |
| 1071 | .mmu_index = sparc_cpu_mmu_index, |
| 1072 | |
| 1073 | #ifndef CONFIG_USER_ONLY |
| 1074 | .tlb_fill = sparc_cpu_tlb_fill, |
| 1075 | .pointer_wrap = sparc_pointer_wrap, |
| 1076 | .cpu_exec_interrupt = sparc_cpu_exec_interrupt, |
| 1077 | .cpu_exec_halt = sparc_cpu_has_work, |
| 1078 | .cpu_exec_reset = cpu_reset, |
| 1079 | .do_interrupt = sparc_cpu_do_interrupt, |
| 1080 | .do_transaction_failed = sparc_cpu_do_transaction_failed, |
| 1081 | .do_unaligned_access = sparc_cpu_do_unaligned_access, |
| 1082 | #endif /* !CONFIG_USER_ONLY */ |
| 1083 | }; |
| 1084 | #endif /* CONFIG_TCG */ |
| 1085 | |
| 1086 | static void sparc_cpu_class_init(ObjectClass *oc, const void *data) |
| 1087 | { |
| 1088 | SPARCCPUClass *scc = SPARC_CPU_CLASS(oc); |
| 1089 | CPUClass *cc = CPU_CLASS(oc); |
| 1090 | DeviceClass *dc = DEVICE_CLASS(oc); |
| 1091 | ResettableClass *rc = RESETTABLE_CLASS(oc); |
| 1092 | |
| 1093 | device_class_set_parent_realize(dc, sparc_cpu_realizefn, |
| 1094 | &scc->parent_realize); |
| 1095 | device_class_set_props(dc, sparc_cpu_properties); |
| 1096 | |
| 1097 | resettable_class_set_parent_phases(rc, NULL, sparc_cpu_reset_hold, NULL, |
| 1098 | &scc->parent_phases); |
| 1099 | |
| 1100 | cc->class_by_name = sparc_cpu_class_by_name; |
| 1101 | cc->list_cpus = sparc_cpu_list, |
| 1102 | cc->parse_features = sparc_cpu_parse_features; |
| 1103 | cc->dump_state = sparc_cpu_dump_state; |
| 1104 | #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) |
| 1105 | cc->memory_rw_debug = sparc_cpu_memory_rw_debug; |
| 1106 | #endif |
| 1107 | cc->set_pc = sparc_cpu_set_pc; |
| 1108 | cc->get_pc = sparc_cpu_get_pc; |
| 1109 | cc->gdb_read_register = sparc_cpu_gdb_read_register; |
| 1110 | cc->gdb_write_register = sparc_cpu_gdb_write_register; |
| 1111 | #ifndef CONFIG_USER_ONLY |
| 1112 | cc->sysemu_ops = &sparc_sysemu_ops; |
| 1113 | #endif |
| 1114 | cc->disas_set_info = cpu_sparc_disas_set_info; |
| 1115 | |
| 1116 | #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32) |
| 1117 | cc->gdb_core_xml_file = "sparc64-cpu.xml"; |
| 1118 | #else |
| 1119 | cc->gdb_core_xml_file = "sparc32-cpu.xml"; |
| 1120 | #endif |
| 1121 | cc->tcg_ops = &sparc_tcg_ops; |
| 1122 | } |
| 1123 | |
| 1124 | static const TypeInfo sparc_cpu_type_info = { |
| 1125 | .name = TYPE_SPARC_CPU, |
| 1126 | .parent = TYPE_CPU, |
| 1127 | .instance_size = sizeof(SPARCCPU), |
| 1128 | .instance_align = __alignof(SPARCCPU), |
| 1129 | .instance_init = sparc_cpu_initfn, |
| 1130 | .abstract = true, |
| 1131 | .class_size = sizeof(SPARCCPUClass), |
| 1132 | .class_init = sparc_cpu_class_init, |
| 1133 | }; |
| 1134 | |
| 1135 | static void sparc_cpu_cpudef_class_init(ObjectClass *oc, const void *data) |
| 1136 | { |
| 1137 | SPARCCPUClass *scc = SPARC_CPU_CLASS(oc); |
| 1138 | scc->cpu_def = data; |
| 1139 | } |
| 1140 | |
| 1141 | static void sparc_register_cpudef_type(const struct sparc_def_t *def) |
| 1142 | { |
| 1143 | char *typename = sparc_cpu_type_name(def->name); |
| 1144 | TypeInfo ti = { |
| 1145 | .name = typename, |
| 1146 | .parent = TYPE_SPARC_CPU, |
| 1147 | .class_init = sparc_cpu_cpudef_class_init, |
| 1148 | .class_data = def, |
| 1149 | }; |
| 1150 | |
| 1151 | type_register_static(&ti); |
| 1152 | g_free(typename); |
| 1153 | } |
| 1154 | |
| 1155 | static void sparc_cpu_register_types(void) |
| 1156 | { |
| 1157 | int i; |
| 1158 | |
| 1159 | type_register_static(&sparc_cpu_type_info); |
| 1160 | for (i = 0; i < ARRAY_SIZE(sparc_defs); i++) { |
| 1161 | sparc_register_cpudef_type(&sparc_defs[i]); |
| 1162 | } |
| 1163 | } |
| 1164 | |
| 1165 | type_init(sparc_cpu_register_types) |