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1 /*
2 * SPARC gdb server stub
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 * Copyright (c) 2013 SUSE LINUX Products GmbH
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20 #include "qemu/osdep.h"
21 #include "exec/gdbstub.h"
22 #include "cpu.h"
23 #include "gdbstub/helpers.h"
24
25 static inline int gdb_get_rega(GByteArray *buf, uint64_t val)
26 {
27 #if defined(TARGET_ABI32) || !defined(TARGET_SPARC64)
28 return gdb_get_reg32(buf, val);
29 #else
30 return gdb_get_reg64(buf, val);
31 #endif
32 }
33
34 int sparc_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
35 {
36 CPUSPARCState *env = cpu_env(cs);
37
38 if (n < 8) {
39 /* g0..g7 */
40 return gdb_get_rega(mem_buf, env->gregs[n]);
41 }
42 if (n < 32) {
43 /* register window */
44 return gdb_get_rega(mem_buf, env->regwptr[n - 8]);
45 }
46 return 0;
47 }
48
49 static int sparc_fpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
50 {
51 CPUSPARCState *env = cpu_env(cs);
52
53 #if defined(TARGET_ABI32) || !defined(TARGET_SPARC64)
54 if (n < 32) {
55 /* fprs */
56 if (n & 1) {
57 return gdb_get_reg32(mem_buf, env->fpr[n / 2].l.lower);
58 } else {
59 return gdb_get_reg32(mem_buf, env->fpr[n / 2].l.upper);
60 }
61 }
62 #else
63 if (n < 32) {
64 /* f0-f31 */
65 if (n & 1) {
66 return gdb_get_reg32(mem_buf, env->fpr[n / 2].l.lower);
67 } else {
68 return gdb_get_reg32(mem_buf, env->fpr[n / 2].l.upper);
69 }
70 }
71 if (n < 48) {
72 /* f32-f62 (16 double width registers, even register numbers only)
73 * n == 32: f32 : env->fpr[16]
74 * n == 33: f34 : env->fpr[17]
75 * etc...
76 * n == 47: f62 : env->fpr[31]
77 */
78 return gdb_get_reg64(mem_buf, env->fpr[(n - 32) + 16].ll);
79 }
80 #endif
81 return 0;
82 }
83
84 static int sparc_cp0_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
85 {
86 CPUSPARCState *env = cpu_env(cs);
87
88 #if defined(TARGET_ABI32) || !defined(TARGET_SPARC64)
89 /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
90 switch (n) {
91 case 0:
92 return gdb_get_rega(mem_buf, env->y);
93 case 1:
94 return gdb_get_rega(mem_buf, cpu_get_psr(env));
95 case 2:
96 return gdb_get_rega(mem_buf, env->wim);
97 case 3:
98 return gdb_get_rega(mem_buf, env->tbr);
99 case 4:
100 return gdb_get_rega(mem_buf, env->pc);
101 case 5:
102 return gdb_get_rega(mem_buf, env->npc);
103 case 6:
104 return gdb_get_rega(mem_buf, cpu_get_fsr(env));
105 case 7:
106 return gdb_get_rega(mem_buf, 0); /* csr */
107 }
108 #else
109 switch (n) {
110 case 0:
111 return gdb_get_regl(mem_buf, env->pc);
112 case 1:
113 return gdb_get_regl(mem_buf, env->npc);
114 case 2:
115 return gdb_get_regl(mem_buf, (cpu_get_ccr(env) << 32) |
116 ((env->asi & 0xff) << 24) |
117 ((env->pstate & 0xfff) << 8) |
118 cpu_get_cwp64(env));
119 case 3:
120 return gdb_get_regl(mem_buf, cpu_get_fsr(env));
121 case 4:
122 return gdb_get_regl(mem_buf, env->fprs);
123 case 5:
124 return gdb_get_regl(mem_buf, env->y);
125 }
126 #endif
127 return 0;
128 }
129
130 static unsigned sparc_gdb_register_bytes(void)
131 {
132 #ifdef CONFIG_USER_ONLY
133 # if defined(TARGET_ABI32)
134 return 4;
135 # endif
136 #endif
137 return target_long_bits() / 8;
138 }
139
140 int sparc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
141 {
142 SPARCCPU *cpu = SPARC_CPU(cs);
143 CPUSPARCState *env = &cpu->env;
144 const unsigned regsz = sparc_gdb_register_bytes();
145 uint64_t tmp = ldn_p(mem_buf, regsz);
146
147 if (n < 8) {
148 /* g0..g7 */
149 env->gregs[n] = tmp;
150 } else {
151 /* register window */
152 env->regwptr[n - 8] = tmp;
153 }
154 return regsz;
155 }
156
157 static int sparc_fpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
158 {
159 CPUSPARCState *env = cpu_env(cs);
160
161 #if defined(TARGET_ABI32) || !defined(TARGET_SPARC64)
162 uint32_t tmp;
163
164 tmp = ldl_p(mem_buf);
165
166 /* fprs */
167 /* f0-f31 */
168 if (n & 1) {
169 env->fpr[n / 2].l.lower = tmp;
170 } else {
171 env->fpr[n / 2].l.upper = tmp;
172 }
173
174 return 4;
175 #else
176 if (n < 32) {
177 /* f0-f31 */
178 uint32_t tmp = ldl_p(mem_buf);
179 if (n & 1) {
180 env->fpr[n / 2].l.lower = tmp;
181 } else {
182 env->fpr[n / 2].l.upper = tmp;
183 }
184 return 4;
185 } else {
186 uint64_t tmp = ldq_p(mem_buf);
187 /* f32-f62 (16 double width registers, even register numbers only)
188 * n == 32: f32 : env->fpr[16]
189 * n == 33: f34 : env->fpr[17]
190 * etc...
191 * n == 47: f62 : env->fpr[31]
192 */
193 env->fpr[(n - 32) + 16].ll = tmp;
194 }
195 return 8;
196 #endif
197 }
198
199 static int sparc_cp0_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
200 {
201 CPUSPARCState *env = cpu_env(cs);
202
203 #if defined(TARGET_ABI32) || !defined(TARGET_SPARC64)
204 uint32_t tmp;
205
206 tmp = ldl_p(mem_buf);
207
208 /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
209 switch (n) {
210 case 0:
211 env->y = tmp;
212 break;
213 case 1:
214 cpu_put_psr(env, tmp);
215 break;
216 case 2:
217 env->wim = tmp;
218 break;
219 case 3:
220 env->tbr = tmp;
221 break;
222 case 4:
223 env->pc = tmp;
224 break;
225 case 5:
226 env->npc = tmp;
227 break;
228 case 6:
229 cpu_put_fsr(env, tmp);
230 break;
231 default:
232 return 0;
233 }
234 return 4;
235 #else
236 uint64_t tmp;
237
238 tmp = ldq_p(mem_buf);
239
240 switch (n) {
241 case 0:
242 env->pc = tmp;
243 break;
244 case 1:
245 env->npc = tmp;
246 break;
247 case 2:
248 cpu_put_ccr(env, tmp >> 32);
249 env->asi = (tmp >> 24) & 0xff;
250 env->pstate = (tmp >> 8) & 0xfff;
251 cpu_put_cwp64(env, tmp & 0xff);
252 break;
253 case 3:
254 cpu_put_fsr(env, tmp);
255 break;
256 case 4:
257 env->fprs = tmp;
258 break;
259 case 5:
260 env->y = tmp;
261 break;
262 default:
263 return 0;
264 }
265 return 8;
266 #endif
267 }
268
269 void sparc_cpu_register_gdb_regs(CPUState *cs)
270 {
271 #if defined(TARGET_ABI32) || !defined(TARGET_SPARC64)
272 gdb_register_coprocessor(cs, sparc_fpu_gdb_read_register,
273 sparc_fpu_gdb_write_register,
274 gdb_find_static_feature("sparc32-fpu.xml"));
275 gdb_register_coprocessor(cs, sparc_cp0_gdb_read_register,
276 sparc_cp0_gdb_write_register,
277 gdb_find_static_feature("sparc32-cp0.xml"));
278 #else
279 gdb_register_coprocessor(cs, sparc_fpu_gdb_read_register,
280 sparc_fpu_gdb_write_register,
281 gdb_find_static_feature("sparc64-fpu.xml"));
282 gdb_register_coprocessor(cs, sparc_cp0_gdb_read_register,
283 sparc_cp0_gdb_write_register,
284 gdb_find_static_feature("sparc64-cp0.xml"));
285 #endif
286 }