| 1 | /* |
| 2 | * Misc Sparc helpers |
| 3 | * |
| 4 | * Copyright (c) 2003-2005 Fabrice Bellard |
| 5 | * |
| 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2.1 of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU Lesser General Public |
| 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
| 18 | */ |
| 19 | |
| 20 | #include "qemu/osdep.h" |
| 21 | #include "cpu.h" |
| 22 | #include "qemu/timer.h" |
| 23 | #include "qemu/host-utils.h" |
| 24 | #include "accel/tcg/cpu-loop.h" |
| 25 | #include "exec/cpu-common.h" |
| 26 | #include "exec/helper-proto.h" |
| 27 | |
| 28 | void cpu_raise_exception_ra(CPUSPARCState *env, int tt, uintptr_t ra) |
| 29 | { |
| 30 | CPUState *cs = env_cpu(env); |
| 31 | |
| 32 | cs->exception_index = tt; |
| 33 | cpu_loop_exit_restore(cs, ra); |
| 34 | } |
| 35 | |
| 36 | void helper_raise_exception(CPUSPARCState *env, int tt) |
| 37 | { |
| 38 | CPUState *cs = env_cpu(env); |
| 39 | |
| 40 | cs->exception_index = tt; |
| 41 | cpu_loop_exit(cs); |
| 42 | } |
| 43 | |
| 44 | void helper_debug(CPUSPARCState *env) |
| 45 | { |
| 46 | CPUState *cs = env_cpu(env); |
| 47 | |
| 48 | cs->exception_index = EXCP_DEBUG; |
| 49 | cpu_loop_exit(cs); |
| 50 | } |
| 51 | |
| 52 | #ifdef TARGET_SPARC64 |
| 53 | void helper_tick_set_count(void *opaque, uint64_t count) |
| 54 | { |
| 55 | #if !defined(CONFIG_USER_ONLY) |
| 56 | cpu_tick_set_count(opaque, count); |
| 57 | #endif |
| 58 | } |
| 59 | |
| 60 | uint64_t helper_tick_get_count(CPUSPARCState *env, void *opaque, int mem_idx) |
| 61 | { |
| 62 | #if !defined(CONFIG_USER_ONLY) |
| 63 | CPUTimer *timer = opaque; |
| 64 | |
| 65 | if (timer->npt && mem_idx < MMU_KERNEL_IDX) { |
| 66 | cpu_raise_exception_ra(env, TT_PRIV_INSN, GETPC()); |
| 67 | } |
| 68 | |
| 69 | return cpu_tick_get_count(timer); |
| 70 | #else |
| 71 | /* In user-mode, QEMU_CLOCK_VIRTUAL doesn't exist. |
| 72 | Just pass through the host cpu clock ticks. */ |
| 73 | return cpu_get_host_ticks(); |
| 74 | #endif |
| 75 | } |
| 76 | |
| 77 | void helper_tick_set_limit(void *opaque, uint64_t limit) |
| 78 | { |
| 79 | #if !defined(CONFIG_USER_ONLY) |
| 80 | cpu_tick_set_limit(opaque, limit); |
| 81 | #endif |
| 82 | } |
| 83 | #endif |
| 84 | |
| 85 | uint64_t helper_udiv(CPUSPARCState *env, target_ulong a, target_ulong b) |
| 86 | { |
| 87 | uint64_t a64 = (uint32_t)a | ((uint64_t)env->y << 32); |
| 88 | uint32_t b32 = b; |
| 89 | uint32_t r; |
| 90 | |
| 91 | if (b32 == 0) { |
| 92 | cpu_raise_exception_ra(env, TT_DIV_ZERO, GETPC()); |
| 93 | } |
| 94 | |
| 95 | a64 /= b32; |
| 96 | r = a64; |
| 97 | if (unlikely(a64 > UINT32_MAX)) { |
| 98 | return -1; /* r = UINT32_MAX, v = 1 */ |
| 99 | } |
| 100 | return r; |
| 101 | } |
| 102 | |
| 103 | uint64_t helper_sdiv(CPUSPARCState *env, target_ulong a, target_ulong b) |
| 104 | { |
| 105 | int64_t a64 = (uint32_t)a | ((uint64_t)env->y << 32); |
| 106 | int32_t b32 = b; |
| 107 | int32_t r; |
| 108 | |
| 109 | if (b32 == 0) { |
| 110 | cpu_raise_exception_ra(env, TT_DIV_ZERO, GETPC()); |
| 111 | } |
| 112 | |
| 113 | if (unlikely(a64 == INT64_MIN)) { |
| 114 | /* |
| 115 | * Special case INT64_MIN / -1 is required to avoid trap on x86 host. |
| 116 | * However, with a dividend of INT64_MIN, there is no 32-bit divisor |
| 117 | * which can yield a 32-bit result: |
| 118 | * INT64_MIN / INT32_MIN = 0x1_0000_0000 |
| 119 | * INT64_MIN / INT32_MAX = -0x1_0000_0002 |
| 120 | * Therefore we know we must overflow and saturate. |
| 121 | */ |
| 122 | return (uint32_t)(b32 < 0 ? INT32_MAX : INT32_MIN) | (-1ull << 32); |
| 123 | } |
| 124 | |
| 125 | a64 /= b32; |
| 126 | r = a64; |
| 127 | if (unlikely(r != a64)) { |
| 128 | return (uint32_t)(a64 < 0 ? INT32_MIN : INT32_MAX) | (-1ull << 32); |
| 129 | } |
| 130 | return (uint32_t)r; |
| 131 | } |
| 132 | |
| 133 | target_ulong helper_taddcctv(CPUSPARCState *env, target_ulong src1, |
| 134 | target_ulong src2) |
| 135 | { |
| 136 | target_ulong dst, v; |
| 137 | |
| 138 | /* Tag overflow occurs if either input has bits 0 or 1 set. */ |
| 139 | if ((src1 | src2) & 3) { |
| 140 | goto tag_overflow; |
| 141 | } |
| 142 | |
| 143 | dst = src1 + src2; |
| 144 | |
| 145 | /* Tag overflow occurs if the addition overflows. */ |
| 146 | v = ~(src1 ^ src2) & (src1 ^ dst); |
| 147 | if (v & (1u << 31)) { |
| 148 | goto tag_overflow; |
| 149 | } |
| 150 | |
| 151 | /* Only modify the CC after any exceptions have been generated. */ |
| 152 | env->cc_V = v; |
| 153 | env->cc_N = dst; |
| 154 | env->icc_Z = dst; |
| 155 | #ifdef TARGET_SPARC64 |
| 156 | env->xcc_Z = dst; |
| 157 | env->icc_C = dst ^ src1 ^ src2; |
| 158 | env->xcc_C = dst < src1; |
| 159 | #else |
| 160 | env->icc_C = dst < src1; |
| 161 | #endif |
| 162 | |
| 163 | return dst; |
| 164 | |
| 165 | tag_overflow: |
| 166 | cpu_raise_exception_ra(env, TT_TOVF, GETPC()); |
| 167 | } |
| 168 | |
| 169 | target_ulong helper_tsubcctv(CPUSPARCState *env, target_ulong src1, |
| 170 | target_ulong src2) |
| 171 | { |
| 172 | target_ulong dst, v; |
| 173 | |
| 174 | /* Tag overflow occurs if either input has bits 0 or 1 set. */ |
| 175 | if ((src1 | src2) & 3) { |
| 176 | goto tag_overflow; |
| 177 | } |
| 178 | |
| 179 | dst = src1 - src2; |
| 180 | |
| 181 | /* Tag overflow occurs if the subtraction overflows. */ |
| 182 | v = (src1 ^ src2) & (src1 ^ dst); |
| 183 | if (v & (1u << 31)) { |
| 184 | goto tag_overflow; |
| 185 | } |
| 186 | |
| 187 | /* Only modify the CC after any exceptions have been generated. */ |
| 188 | env->cc_V = v; |
| 189 | env->cc_N = dst; |
| 190 | env->icc_Z = dst; |
| 191 | #ifdef TARGET_SPARC64 |
| 192 | env->xcc_Z = dst; |
| 193 | env->icc_C = dst ^ src1 ^ src2; |
| 194 | env->xcc_C = src1 < src2; |
| 195 | #else |
| 196 | env->icc_C = src1 < src2; |
| 197 | #endif |
| 198 | |
| 199 | return dst; |
| 200 | |
| 201 | tag_overflow: |
| 202 | cpu_raise_exception_ra(env, TT_TOVF, GETPC()); |
| 203 | } |
| 204 | |
| 205 | #ifndef TARGET_SPARC64 |
| 206 | void helper_power_down(CPUSPARCState *env) |
| 207 | { |
| 208 | CPUState *cs = env_cpu(env); |
| 209 | |
| 210 | cs->halted = 1; |
| 211 | cs->exception_index = EXCP_HLT; |
| 212 | env->pc = env->npc; |
| 213 | env->npc = env->pc + 4; |
| 214 | cpu_loop_exit(cs); |
| 215 | } |
| 216 | |
| 217 | target_ulong helper_rdasr17(CPUSPARCState *env) |
| 218 | { |
| 219 | CPUState *cs = env_cpu(env); |
| 220 | target_ulong val; |
| 221 | |
| 222 | /* |
| 223 | * TODO: There are many more fields to be filled, |
| 224 | * some of which are writable. |
| 225 | */ |
| 226 | val = env->def.nwindows - 1; /* [4:0] NWIN */ |
| 227 | val |= 1 << 8; /* [8] V8 */ |
| 228 | val |= (cs->cpu_index) << 28; /* [31:28] INDEX */ |
| 229 | |
| 230 | return val; |
| 231 | } |
| 232 | #endif |