| 1 | # SPDX-License-Identifier: LGPL-2.0-or-later |
| 2 | # |
| 3 | # Sparc instruction decode definitions. |
| 4 | # Copyright (c) 2023 Richard Henderson <rth@twiddle.net> |
| 5 | |
| 6 | ## |
| 7 | ## Major Opcodes 00 and 01 -- branches, call, and sethi. |
| 8 | ## |
| 9 | |
| 10 | &bcc i a cond cc |
| 11 | BPcc 00 a:1 cond:4 001 cc:1 0 - i:s19 &bcc |
| 12 | Bicc 00 a:1 cond:4 010 i:s22 &bcc cc=0 |
| 13 | FBPfcc 00 a:1 cond:4 101 cc:2 - i:s19 &bcc |
| 14 | FBfcc 00 a:1 cond:4 110 i:s22 &bcc cc=0 |
| 15 | |
| 16 | %d16 20:s2 0:14 |
| 17 | BPr 00 a:1 0 cond:3 011 .. - rs1:5 .............. i=%d16 |
| 18 | |
| 19 | NCP 00 - ---- 111 ---------------------- # CBcc |
| 20 | |
| 21 | SETHI 00 rd:5 100 i:22 |
| 22 | |
| 23 | CALL 01 i:s30 |
| 24 | |
| 25 | ## |
| 26 | ## Major Opcode 10 -- integer, floating-point, vis, and system insns. |
| 27 | ## |
| 28 | |
| 29 | %dfp_rd 25:5 !function=extract_dfpreg |
| 30 | %dfp_rs1 14:5 !function=extract_dfpreg |
| 31 | %dfp_rs2 0:5 !function=extract_dfpreg |
| 32 | %dfp_rs3 9:5 !function=extract_dfpreg |
| 33 | |
| 34 | %qfp_rd 25:5 !function=extract_qfpreg |
| 35 | %qfp_rs1 14:5 !function=extract_qfpreg |
| 36 | %qfp_rs2 0:5 !function=extract_qfpreg |
| 37 | |
| 38 | &r_r_ri rd rs1 rs2_or_imm imm:bool |
| 39 | @n_r_ri .. ..... ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri rd=0 |
| 40 | @r_r_ri .. rd:5 ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri |
| 41 | |
| 42 | &r_r_ri_cc rd rs1 rs2_or_imm imm:bool cc:bool |
| 43 | @r_r_ri_cc .. rd:5 . cc:1 .... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri_cc |
| 44 | @r_r_ri_cc0 .. rd:5 ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri_cc cc=0 |
| 45 | @r_r_ri_cc1 .. rd:5 ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri_cc cc=1 |
| 46 | |
| 47 | &r_r_r rd rs1 rs2 |
| 48 | @r_r_r .. rd:5 ...... rs1:5 . ........ rs2:5 &r_r_r |
| 49 | @d_r_r .. ..... ...... rs1:5 . ........ rs2:5 \ |
| 50 | &r_r_r rd=%dfp_rd |
| 51 | @r_d_d .. rd:5 ...... ..... . ........ ..... \ |
| 52 | &r_r_r rs1=%dfp_rs1 rs2=%dfp_rs2 |
| 53 | @d_r_d .. ..... ...... rs1:5 . ........ ..... \ |
| 54 | &r_r_r rd=%dfp_rd rs2=%dfp_rs2 |
| 55 | @d_d_d .. ..... ...... ..... . ........ ..... \ |
| 56 | &r_r_r rd=%dfp_rd rs1=%dfp_rs1 rs2=%dfp_rs2 |
| 57 | @q_q_q .. ..... ...... ..... . ........ ..... \ |
| 58 | &r_r_r rd=%qfp_rd rs1=%qfp_rs1 rs2=%qfp_rs2 |
| 59 | @q_d_d .. ..... ...... ..... . ........ ..... \ |
| 60 | &r_r_r rd=%qfp_rd rs1=%dfp_rs1 rs2=%dfp_rs2 |
| 61 | |
| 62 | @r_r_r_swap .. rd:5 ...... rs2:5 . ........ rs1:5 &r_r_r |
| 63 | @d_d_d_swap .. ..... ...... ..... . ........ ..... \ |
| 64 | &r_r_r rd=%dfp_rd rs1=%dfp_rs2 rs2=%dfp_rs1 |
| 65 | |
| 66 | &r_r rd rs |
| 67 | @r_r1 .. rd:5 ...... rs:5 . ........ ..... &r_r |
| 68 | @r_r2 .. rd:5 ...... ..... . ........ rs:5 &r_r |
| 69 | @r_d2 .. rd:5 ...... ..... . ........ ..... &r_r rs=%dfp_rs2 |
| 70 | @r_q2 .. rd:5 ...... ..... . ........ ..... &r_r rs=%qfp_rs2 |
| 71 | @d_r2 .. ..... ...... ..... . ........ rs:5 &r_r rd=%dfp_rd |
| 72 | @q_r2 .. ..... ...... ..... . ........ rs:5 &r_r rd=%qfp_rd |
| 73 | @d_d1 .. ..... ...... ..... . ........ ..... \ |
| 74 | &r_r rd=%dfp_rd rs=%dfp_rs1 |
| 75 | @d_d2 .. ..... ...... ..... . ........ ..... \ |
| 76 | &r_r rd=%dfp_rd rs=%dfp_rs2 |
| 77 | @d_q2 .. ..... ...... ..... . ........ ..... \ |
| 78 | &r_r rd=%dfp_rd rs=%qfp_rs2 |
| 79 | @q_q2 .. ..... ...... ..... . ........ ..... \ |
| 80 | &r_r rd=%qfp_rd rs=%qfp_rs2 |
| 81 | @q_d2 .. ..... ...... ..... . ........ ..... \ |
| 82 | &r_r rd=%qfp_rd rs=%dfp_rs2 |
| 83 | |
| 84 | &r_r_r_r rd rs1 rs2 rs3 |
| 85 | @r_r_r_r .. rd:5 ...... rs1:5 rs3:5 .... rs2:5 &r_r_r_r |
| 86 | @d_d_d_d .. ..... ...... ..... ..... .... ..... \ |
| 87 | &r_r_r_r rd=%dfp_rd rs1=%dfp_rs1 rs2=%dfp_rs2 rs3=%dfp_rs3 |
| 88 | |
| 89 | { |
| 90 | [ |
| 91 | STBAR_v9 10 00000 101000 01111 0 0000000000000 |
| 92 | MEMBAR 10 00000 101000 01111 1 000000 cmask:3 mmask:4 |
| 93 | |
| 94 | RDY_v9 10 rd:5 101000 00000 0 0000000000000 |
| 95 | RDCCR 10 rd:5 101000 00010 0 0000000000000 |
| 96 | RDASI 10 rd:5 101000 00011 0 0000000000000 |
| 97 | RDTICK 10 rd:5 101000 00100 0 0000000000000 |
| 98 | RDPC 10 rd:5 101000 00101 0 0000000000000 |
| 99 | RDFPRS 10 rd:5 101000 00110 0 0000000000000 |
| 100 | { |
| 101 | RDASR17 10 rd:5 101000 10001 0 0000000000000 |
| 102 | RDPIC 10 rd:5 101000 10001 0 0000000000000 |
| 103 | } |
| 104 | RDGSR 10 rd:5 101000 10011 0 0000000000000 |
| 105 | RDSOFTINT 10 rd:5 101000 10110 0 0000000000000 |
| 106 | RDTICK_CMPR 10 rd:5 101000 10111 0 0000000000000 |
| 107 | RDSTICK 10 rd:5 101000 11000 0 0000000000000 |
| 108 | RDSTICK_CMPR 10 rd:5 101000 11001 0 0000000000000 |
| 109 | RDSTRAND_STATUS 10 rd:5 101000 11010 0 0000000000000 |
| 110 | ] |
| 111 | |
| 112 | # The v8 manual, section B.30 STBAR instruction, says |
| 113 | # bits [12:0] are ignored, but bit 13 must be 0. |
| 114 | # However, section B.28 Read State Register Instruction has a |
| 115 | # comment that RDASR with rs1 = 15, rd = 0 is STBAR. Here, |
| 116 | # bit 13 is also ignored and rd != 0 is merely reserved. |
| 117 | # |
| 118 | # Solaris 8 executes v9 MEMBAR instruction 0x8143e008 during boot. |
| 119 | # This confirms that bit 13 is ignored, as 0x8143c000 is STBAR. |
| 120 | STBAR_v8 10 ----- 101000 01111 - ------------- |
| 121 | |
| 122 | # For v7, bits [18:0] are ignored. |
| 123 | # For v8, bits [18:14], aka rs1, are repurposed and rs1 = 0 is RDY, |
| 124 | # and other values are RDASR. However, the v8 manual explicitly |
| 125 | # says that rs1 in 1..14 yield undefined results and do not cause |
| 126 | # an illegal instruction trap, and rs1 in 16..31 are available for |
| 127 | # implementation specific usage. |
| 128 | # Implement not causing an illegal instruction trap for v8 by |
| 129 | # continuing to interpret unused values per v7, i.e. as RDY. |
| 130 | RDY_v7 10 rd:5 101000 ----- - ------------- |
| 131 | } |
| 132 | |
| 133 | { |
| 134 | [ |
| 135 | WRY 10 00000 110000 ..... . ............. @n_r_ri |
| 136 | WRCCR 10 00010 110000 ..... . ............. @n_r_ri |
| 137 | WRASI 10 00011 110000 ..... . ............. @n_r_ri |
| 138 | WRFPRS 10 00110 110000 ..... . ............. @n_r_ri |
| 139 | WRPCR 10 10000 110000 01000 0 0000000000000 |
| 140 | WRPIC 10 10001 110000 01000 0 0000000000000 |
| 141 | { |
| 142 | WRGSR 10 10011 110000 ..... . ............. @n_r_ri |
| 143 | WRPOWERDOWN 10 10011 110000 ..... . ............. @n_r_ri |
| 144 | } |
| 145 | WRSOFTINT_SET 10 10100 110000 ..... . ............. @n_r_ri |
| 146 | WRSOFTINT_CLR 10 10101 110000 ..... . ............. @n_r_ri |
| 147 | WRSOFTINT 10 10110 110000 ..... . ............. @n_r_ri |
| 148 | WRTICK_CMPR 10 10111 110000 ..... . ............. @n_r_ri |
| 149 | WRSTICK 10 11000 110000 ..... . ............. @n_r_ri |
| 150 | WRSTICK_CMPR 10 11001 110000 ..... . ............. @n_r_ri |
| 151 | WRMWAIT 10 11100 110000 ..... . ............. @n_r_ri |
| 152 | ] |
| 153 | # Before v8, rs1==0 was WRY, and the rest executed as nop. |
| 154 | [ |
| 155 | NOP_v7 10 ----- 110000 ----- 0 00000000 ----- |
| 156 | NOP_v7 10 ----- 110000 ----- 1 -------- ----- |
| 157 | ] |
| 158 | } |
| 159 | |
| 160 | { |
| 161 | [ |
| 162 | RDHPR_hpstate 10 rd:5 101001 00000 0 0000000000000 |
| 163 | RDHPR_htstate 10 rd:5 101001 00001 0 0000000000000 |
| 164 | RDHPR_hintp 10 rd:5 101001 00011 0 0000000000000 |
| 165 | RDHPR_htba 10 rd:5 101001 00101 0 0000000000000 |
| 166 | RDHPR_hver 10 rd:5 101001 00110 0 0000000000000 |
| 167 | RDHPR_hstick_cmpr 10 rd:5 101001 11111 0 0000000000000 |
| 168 | ] |
| 169 | RDPSR 10 rd:5 101001 ----- - ------------- |
| 170 | } |
| 171 | |
| 172 | { |
| 173 | WRPSR 10 00000 110001 ..... . ............. @n_r_ri |
| 174 | SAVED 10 00000 110001 00000 0 0000000000000 |
| 175 | } |
| 176 | RESTORED 10 00001 110001 00000 0 0000000000000 |
| 177 | # UA2005 ALLCLEAN |
| 178 | # UA2005 OTHERW |
| 179 | # UA2005 NORMALW |
| 180 | # UA2005 INVALW |
| 181 | |
| 182 | { |
| 183 | [ |
| 184 | RDPR_tpc 10 rd:5 101010 00000 0 0000000000000 |
| 185 | RDPR_tnpc 10 rd:5 101010 00001 0 0000000000000 |
| 186 | RDPR_tstate 10 rd:5 101010 00010 0 0000000000000 |
| 187 | RDPR_tt 10 rd:5 101010 00011 0 0000000000000 |
| 188 | RDPR_tick 10 rd:5 101010 00100 0 0000000000000 |
| 189 | RDPR_tba 10 rd:5 101010 00101 0 0000000000000 |
| 190 | RDPR_pstate 10 rd:5 101010 00110 0 0000000000000 |
| 191 | RDPR_tl 10 rd:5 101010 00111 0 0000000000000 |
| 192 | RDPR_pil 10 rd:5 101010 01000 0 0000000000000 |
| 193 | RDPR_cwp 10 rd:5 101010 01001 0 0000000000000 |
| 194 | RDPR_cansave 10 rd:5 101010 01010 0 0000000000000 |
| 195 | RDPR_canrestore 10 rd:5 101010 01011 0 0000000000000 |
| 196 | RDPR_cleanwin 10 rd:5 101010 01100 0 0000000000000 |
| 197 | RDPR_otherwin 10 rd:5 101010 01101 0 0000000000000 |
| 198 | RDPR_wstate 10 rd:5 101010 01110 0 0000000000000 |
| 199 | RDPR_gl 10 rd:5 101010 10000 0 0000000000000 |
| 200 | RDPR_strand_status 10 rd:5 101010 11010 0 0000000000000 |
| 201 | RDPR_ver 10 rd:5 101010 11111 0 0000000000000 |
| 202 | ] |
| 203 | RDWIM 10 rd:5 101010 ----- - ------------- |
| 204 | } |
| 205 | |
| 206 | { |
| 207 | WRWIM 10 00000 110010 ..... . ............. @n_r_ri |
| 208 | WRPR_tpc 10 00000 110010 ..... . ............. @n_r_ri |
| 209 | } |
| 210 | WRPR_tnpc 10 00001 110010 ..... . ............. @n_r_ri |
| 211 | WRPR_tstate 10 00010 110010 ..... . ............. @n_r_ri |
| 212 | WRPR_tt 10 00011 110010 ..... . ............. @n_r_ri |
| 213 | WRPR_tick 10 00100 110010 ..... . ............. @n_r_ri |
| 214 | WRPR_tba 10 00101 110010 ..... . ............. @n_r_ri |
| 215 | WRPR_pstate 10 00110 110010 ..... . ............. @n_r_ri |
| 216 | WRPR_tl 10 00111 110010 ..... . ............. @n_r_ri |
| 217 | WRPR_pil 10 01000 110010 ..... . ............. @n_r_ri |
| 218 | WRPR_cwp 10 01001 110010 ..... . ............. @n_r_ri |
| 219 | WRPR_cansave 10 01010 110010 ..... . ............. @n_r_ri |
| 220 | WRPR_canrestore 10 01011 110010 ..... . ............. @n_r_ri |
| 221 | WRPR_cleanwin 10 01100 110010 ..... . ............. @n_r_ri |
| 222 | WRPR_otherwin 10 01101 110010 ..... . ............. @n_r_ri |
| 223 | WRPR_wstate 10 01110 110010 ..... . ............. @n_r_ri |
| 224 | WRPR_gl 10 10000 110010 ..... . ............. @n_r_ri |
| 225 | WRPR_strand_status 10 11010 110010 ..... . ............. @n_r_ri |
| 226 | |
| 227 | { |
| 228 | FLUSHW 10 00000 101011 00000 0 0000000000000 |
| 229 | RDTBR 10 rd:5 101011 ----- - ------------- |
| 230 | } |
| 231 | |
| 232 | { |
| 233 | WRTBR 10 00000 110011 ..... . ............. @n_r_ri |
| 234 | WRHPR_hpstate 10 00000 110011 ..... . ............. @n_r_ri |
| 235 | } |
| 236 | WRHPR_htstate 10 00001 110011 ..... . ............. @n_r_ri |
| 237 | WRHPR_hintp 10 00011 110011 ..... . ............. @n_r_ri |
| 238 | WRHPR_htba 10 00101 110011 ..... . ............. @n_r_ri |
| 239 | WRHPR_hstick_cmpr 10 11111 110011 ..... . ............. @n_r_ri |
| 240 | |
| 241 | ADD 10 ..... 0.0000 ..... . ............. @r_r_ri_cc |
| 242 | AND 10 ..... 0.0001 ..... . ............. @r_r_ri_cc |
| 243 | OR 10 ..... 0.0010 ..... . ............. @r_r_ri_cc |
| 244 | XOR 10 ..... 0.0011 ..... . ............. @r_r_ri_cc |
| 245 | SUB 10 ..... 0.0100 ..... . ............. @r_r_ri_cc |
| 246 | ANDN 10 ..... 0.0101 ..... . ............. @r_r_ri_cc |
| 247 | ORN 10 ..... 0.0110 ..... . ............. @r_r_ri_cc |
| 248 | XORN 10 ..... 0.0111 ..... . ............. @r_r_ri_cc |
| 249 | ADDC 10 ..... 0.1000 ..... . ............. @r_r_ri_cc |
| 250 | SUBC 10 ..... 0.1100 ..... . ............. @r_r_ri_cc |
| 251 | |
| 252 | MULX 10 ..... 001001 ..... . ............. @r_r_ri_cc0 |
| 253 | UMUL 10 ..... 0.1010 ..... . ............. @r_r_ri_cc |
| 254 | SMUL 10 ..... 0.1011 ..... . ............. @r_r_ri_cc |
| 255 | MULScc 10 ..... 100100 ..... . ............. @r_r_ri_cc1 |
| 256 | |
| 257 | UDIVX 10 ..... 001101 ..... . ............. @r_r_ri |
| 258 | SDIVX 10 ..... 101101 ..... . ............. @r_r_ri |
| 259 | UDIV 10 ..... 001110 ..... . ............. @r_r_ri |
| 260 | UDIVcc 10 ..... 011110 ..... . ............. @r_r_ri_cc1 |
| 261 | SDIV 10 ..... 0.1111 ..... . ............. @r_r_ri_cc |
| 262 | |
| 263 | TADDcc 10 ..... 100000 ..... . ............. @r_r_ri_cc1 |
| 264 | TSUBcc 10 ..... 100001 ..... . ............. @r_r_ri_cc1 |
| 265 | TADDccTV 10 ..... 100010 ..... . ............. @r_r_ri_cc1 |
| 266 | TSUBccTV 10 ..... 100011 ..... . ............. @r_r_ri_cc1 |
| 267 | |
| 268 | POPC 10 rd:5 101110 00000 imm:1 rs2_or_imm:s13 \ |
| 269 | &r_r_ri_cc rs1=0 cc=0 |
| 270 | |
| 271 | &shiftr rd rs1 rs2 x:bool |
| 272 | @shiftr .. rd:5 ...... rs1:5 . x:1 ....... rs2:5 &shiftr |
| 273 | |
| 274 | SLL_r 10 ..... 100101 ..... 0 . 0000000 ..... @shiftr |
| 275 | SRL_r 10 ..... 100110 ..... 0 . 0000000 ..... @shiftr |
| 276 | SRA_r 10 ..... 100111 ..... 0 . 0000000 ..... @shiftr |
| 277 | |
| 278 | &shifti rd rs1 i x:bool |
| 279 | @shifti .. rd:5 ...... rs1:5 . x:1 ...... i:6 &shifti |
| 280 | |
| 281 | SLL_i 10 ..... 100101 ..... 1 . 000000 ...... @shifti |
| 282 | SRL_i 10 ..... 100110 ..... 1 . 000000 ...... @shifti |
| 283 | SRA_i 10 ..... 100111 ..... 1 . 000000 ...... @shifti |
| 284 | |
| 285 | Tcc_r 10 0 cond:4 111010 rs1:5 0 cc:1 0000000 rs2:5 |
| 286 | { |
| 287 | # For v7, the entire simm13 field is present, but masked to 7 bits. |
| 288 | # For v8, [12:7] are reserved. However, a compatibility note for |
| 289 | # the Tcc insn in the v9 manual suggests that the v8 reserved field |
| 290 | # was ignored and did not produce traps. |
| 291 | Tcc_i_v7 10 0 cond:4 111010 rs1:5 1 ------ i:7 |
| 292 | |
| 293 | # For v9, bits [12:11] are cc1 and cc0 (and cc0 must be 0). |
| 294 | # Bits [10:8] are reserved and the OSA2011 manual says they must be 0. |
| 295 | Tcc_i_v9 10 0 cond:4 111010 rs1:5 1 cc:1 0 000 i:8 |
| 296 | } |
| 297 | |
| 298 | MOVcc 10 rd:5 101100 1 cond:4 imm:1 cc:1 0 rs2_or_imm:s11 |
| 299 | MOVfcc 10 rd:5 101100 0 cond:4 imm:1 cc:2 rs2_or_imm:s11 |
| 300 | MOVR 10 rd:5 101111 rs1:5 imm:1 cond:3 rs2_or_imm:s10 |
| 301 | |
| 302 | JMPL 10 ..... 111000 ..... . ............. @r_r_ri |
| 303 | { |
| 304 | RETT 10 00000 111001 ..... . ............. @n_r_ri |
| 305 | RETURN 10 00000 111001 ..... . ............. @n_r_ri |
| 306 | } |
| 307 | NOP 10 00000 111011 ----- 0 00000000----- # FLUSH reg+reg |
| 308 | NOP 10 00000 111011 ----- 1 ------------- # FLUSH reg+imm |
| 309 | SAVE 10 ..... 111100 ..... . ............. @r_r_ri |
| 310 | RESTORE 10 ..... 111101 ..... . ............. @r_r_ri |
| 311 | |
| 312 | DONE 10 00000 111110 00000 0 0000000000000 |
| 313 | RETRY 10 00001 111110 00000 0 0000000000000 |
| 314 | |
| 315 | FMOVs 10 ..... 110100 00000 0 0000 0001 ..... @r_r2 |
| 316 | FMOVd 10 ..... 110100 00000 0 0000 0010 ..... @d_d2 |
| 317 | FMOVq 10 ..... 110100 00000 0 0000 0011 ..... @q_q2 |
| 318 | FNEGs 10 ..... 110100 00000 0 0000 0101 ..... @r_r2 |
| 319 | FNEGd 10 ..... 110100 00000 0 0000 0110 ..... @d_d2 |
| 320 | FNEGq 10 ..... 110100 00000 0 0000 0111 ..... @q_q2 |
| 321 | FABSs 10 ..... 110100 00000 0 0000 1001 ..... @r_r2 |
| 322 | FABSd 10 ..... 110100 00000 0 0000 1010 ..... @d_d2 |
| 323 | FABSq 10 ..... 110100 00000 0 0000 1011 ..... @q_q2 |
| 324 | FSQRTs 10 ..... 110100 00000 0 0010 1001 ..... @r_r2 |
| 325 | FSQRTd 10 ..... 110100 00000 0 0010 1010 ..... @d_d2 |
| 326 | FSQRTq 10 ..... 110100 00000 0 0010 1011 ..... @q_q2 |
| 327 | FADDs 10 ..... 110100 ..... 0 0100 0001 ..... @r_r_r |
| 328 | FADDd 10 ..... 110100 ..... 0 0100 0010 ..... @d_d_d |
| 329 | FADDq 10 ..... 110100 ..... 0 0100 0011 ..... @q_q_q |
| 330 | FSUBs 10 ..... 110100 ..... 0 0100 0101 ..... @r_r_r |
| 331 | FSUBd 10 ..... 110100 ..... 0 0100 0110 ..... @d_d_d |
| 332 | FSUBq 10 ..... 110100 ..... 0 0100 0111 ..... @q_q_q |
| 333 | FMULs 10 ..... 110100 ..... 0 0100 1001 ..... @r_r_r |
| 334 | FMULd 10 ..... 110100 ..... 0 0100 1010 ..... @d_d_d |
| 335 | FMULq 10 ..... 110100 ..... 0 0100 1011 ..... @q_q_q |
| 336 | FDIVs 10 ..... 110100 ..... 0 0100 1101 ..... @r_r_r |
| 337 | FDIVd 10 ..... 110100 ..... 0 0100 1110 ..... @d_d_d |
| 338 | FDIVq 10 ..... 110100 ..... 0 0100 1111 ..... @q_q_q |
| 339 | FNADDs 10 ..... 110100 ..... 0 0101 0001 ..... @r_r_r |
| 340 | FNADDd 10 ..... 110100 ..... 0 0101 0010 ..... @d_d_d |
| 341 | FNMULs 10 ..... 110100 ..... 0 0101 1001 ..... @r_r_r |
| 342 | FNMULd 10 ..... 110100 ..... 0 0101 1010 ..... @d_d_d |
| 343 | FHADDs 10 ..... 110100 ..... 0 0110 0001 ..... @r_r_r |
| 344 | FHADDd 10 ..... 110100 ..... 0 0110 0010 ..... @d_d_d |
| 345 | FHSUBs 10 ..... 110100 ..... 0 0110 0101 ..... @r_r_r |
| 346 | FHSUBd 10 ..... 110100 ..... 0 0110 0110 ..... @d_d_d |
| 347 | FsMULd 10 ..... 110100 ..... 0 0110 1001 ..... @d_r_r |
| 348 | FdMULq 10 ..... 110100 ..... 0 0110 1110 ..... @q_d_d |
| 349 | FNHADDs 10 ..... 110100 ..... 0 0111 0001 ..... @r_r_r |
| 350 | FNHADDd 10 ..... 110100 ..... 0 0111 0010 ..... @d_d_d |
| 351 | FNsMULd 10 ..... 110100 ..... 0 0111 1001 ..... @d_r_r |
| 352 | FsTOx 10 ..... 110100 00000 0 1000 0001 ..... @d_r2 |
| 353 | FdTOx 10 ..... 110100 00000 0 1000 0010 ..... @d_d2 |
| 354 | FqTOx 10 ..... 110100 00000 0 1000 0011 ..... @d_q2 |
| 355 | FxTOs 10 ..... 110100 00000 0 1000 0100 ..... @r_d2 |
| 356 | FxTOd 10 ..... 110100 00000 0 1000 1000 ..... @d_d2 |
| 357 | FxTOq 10 ..... 110100 00000 0 1000 1100 ..... @q_d2 |
| 358 | FiTOs 10 ..... 110100 00000 0 1100 0100 ..... @r_r2 |
| 359 | FdTOs 10 ..... 110100 00000 0 1100 0110 ..... @r_d2 |
| 360 | FqTOs 10 ..... 110100 00000 0 1100 0111 ..... @r_q2 |
| 361 | FiTOd 10 ..... 110100 00000 0 1100 1000 ..... @d_r2 |
| 362 | FsTOd 10 ..... 110100 00000 0 1100 1001 ..... @d_r2 |
| 363 | FqTOd 10 ..... 110100 00000 0 1100 1011 ..... @d_q2 |
| 364 | FiTOq 10 ..... 110100 00000 0 1100 1100 ..... @q_r2 |
| 365 | FsTOq 10 ..... 110100 00000 0 1100 1101 ..... @q_r2 |
| 366 | FdTOq 10 ..... 110100 00000 0 1100 1110 ..... @q_d2 |
| 367 | FsTOi 10 ..... 110100 00000 0 1101 0001 ..... @r_r2 |
| 368 | FdTOi 10 ..... 110100 00000 0 1101 0010 ..... @r_d2 |
| 369 | FqTOi 10 ..... 110100 00000 0 1101 0011 ..... @r_q2 |
| 370 | |
| 371 | FMOVscc 10 rd:5 110101 0 cond:4 1 cc:1 0 000001 rs2:5 |
| 372 | FMOVdcc 10 ..... 110101 0 cond:4 1 cc:1 0 000010 ..... \ |
| 373 | rd=%dfp_rd rs2=%dfp_rs2 |
| 374 | FMOVqcc 10 ..... 110101 0 cond:4 1 cc:1 0 000011 ..... \ |
| 375 | rd=%qfp_rd rs2=%qfp_rs2 |
| 376 | |
| 377 | FMOVsfcc 10 rd:5 110101 0 cond:4 0 cc:2 000001 rs2:5 |
| 378 | FMOVdfcc 10 ..... 110101 0 cond:4 0 cc:2 000010 ..... \ |
| 379 | rd=%dfp_rd rs2=%dfp_rs2 |
| 380 | FMOVqfcc 10 ..... 110101 0 cond:4 0 cc:2 000011 ..... \ |
| 381 | rd=%qfp_rd rs2=%qfp_rs2 |
| 382 | |
| 383 | FMOVRs 10 rd:5 110101 rs1:5 0 cond:3 00101 rs2:5 |
| 384 | FMOVRd 10 ..... 110101 rs1:5 0 cond:3 00110 ..... \ |
| 385 | rd=%dfp_rd rs2=%dfp_rs2 |
| 386 | FMOVRq 10 ..... 110101 rs1:5 0 cond:3 00111 ..... \ |
| 387 | rd=%qfp_rd rs2=%qfp_rs2 |
| 388 | |
| 389 | FCMPs 10 000 cc:2 110101 rs1:5 0 0101 0001 rs2:5 |
| 390 | FCMPd 10 000 cc:2 110101 ..... 0 0101 0010 ..... \ |
| 391 | rs1=%dfp_rs1 rs2=%dfp_rs2 |
| 392 | FCMPq 10 000 cc:2 110101 ..... 0 0101 0011 ..... \ |
| 393 | rs1=%qfp_rs1 rs2=%qfp_rs2 |
| 394 | FCMPEs 10 000 cc:2 110101 rs1:5 0 0101 0101 rs2:5 |
| 395 | FCMPEd 10 000 cc:2 110101 ..... 0 0101 0110 ..... \ |
| 396 | rs1=%dfp_rs1 rs2=%dfp_rs2 |
| 397 | FCMPEq 10 000 cc:2 110101 ..... 0 0101 0111 ..... \ |
| 398 | rs1=%qfp_rs1 rs2=%qfp_rs2 |
| 399 | |
| 400 | { |
| 401 | [ |
| 402 | EDGE8cc 10 ..... 110110 ..... 0 0000 0000 ..... @r_r_r |
| 403 | EDGE8N 10 ..... 110110 ..... 0 0000 0001 ..... @r_r_r |
| 404 | EDGE8Lcc 10 ..... 110110 ..... 0 0000 0010 ..... @r_r_r |
| 405 | EDGE8LN 10 ..... 110110 ..... 0 0000 0011 ..... @r_r_r |
| 406 | EDGE16cc 10 ..... 110110 ..... 0 0000 0100 ..... @r_r_r |
| 407 | EDGE16N 10 ..... 110110 ..... 0 0000 0101 ..... @r_r_r |
| 408 | EDGE16Lcc 10 ..... 110110 ..... 0 0000 0110 ..... @r_r_r |
| 409 | EDGE16LN 10 ..... 110110 ..... 0 0000 0111 ..... @r_r_r |
| 410 | EDGE32cc 10 ..... 110110 ..... 0 0000 1000 ..... @r_r_r |
| 411 | EDGE32N 10 ..... 110110 ..... 0 0000 1001 ..... @r_r_r |
| 412 | EDGE32Lcc 10 ..... 110110 ..... 0 0000 1010 ..... @r_r_r |
| 413 | EDGE32LN 10 ..... 110110 ..... 0 0000 1011 ..... @r_r_r |
| 414 | |
| 415 | ARRAY8 10 ..... 110110 ..... 0 0001 0000 ..... @r_r_r |
| 416 | ARRAY16 10 ..... 110110 ..... 0 0001 0010 ..... @r_r_r |
| 417 | ARRAY32 10 ..... 110110 ..... 0 0001 0100 ..... @r_r_r |
| 418 | |
| 419 | ADDXC 10 ..... 110110 ..... 0 0001 0001 ..... @r_r_r |
| 420 | ADDXCcc 10 ..... 110110 ..... 0 0001 0011 ..... @r_r_r |
| 421 | UMULXHI 10 ..... 110110 ..... 0 0001 0110 ..... @r_r_r |
| 422 | LZCNT 10 ..... 110110 00000 0 0001 0111 ..... @r_r2 |
| 423 | XMULX 10 ..... 110110 ..... 1 0001 0101 ..... @r_r_r |
| 424 | XMULXHI 10 ..... 110110 ..... 1 0001 0110 ..... @r_r_r |
| 425 | |
| 426 | ALIGNADDR 10 ..... 110110 ..... 0 0001 1000 ..... @r_r_r |
| 427 | ALIGNADDRL 10 ..... 110110 ..... 0 0001 1010 ..... @r_r_r |
| 428 | |
| 429 | BMASK 10 ..... 110110 ..... 0 0001 1001 ..... @r_r_r |
| 430 | |
| 431 | CMASK8 10 00000 110110 00000 0 0001 1011 rs2:5 |
| 432 | CMASK16 10 00000 110110 00000 0 0001 1101 rs2:5 |
| 433 | CMASK32 10 00000 110110 00000 0 0001 1111 rs2:5 |
| 434 | |
| 435 | FPCMPLE16 10 ..... 110110 ..... 0 0010 0000 ..... @r_d_d |
| 436 | FPCMPNE16 10 ..... 110110 ..... 0 0010 0010 ..... @r_d_d |
| 437 | FPCMPGT16 10 ..... 110110 ..... 0 0010 1000 ..... @r_d_d |
| 438 | FPCMPEQ16 10 ..... 110110 ..... 0 0010 1010 ..... @r_d_d |
| 439 | FPCMPLE32 10 ..... 110110 ..... 0 0010 0100 ..... @r_d_d |
| 440 | FPCMPNE32 10 ..... 110110 ..... 0 0010 0110 ..... @r_d_d |
| 441 | FPCMPGT32 10 ..... 110110 ..... 0 0010 1100 ..... @r_d_d |
| 442 | FPCMPEQ32 10 ..... 110110 ..... 0 0010 1110 ..... @r_d_d |
| 443 | |
| 444 | FSLL16 10 ..... 110110 ..... 0 0010 0001 ..... @d_d_d |
| 445 | FSRL16 10 ..... 110110 ..... 0 0010 0011 ..... @d_d_d |
| 446 | FSLAS16 10 ..... 110110 ..... 0 0010 1001 ..... @d_d_d |
| 447 | FSRA16 10 ..... 110110 ..... 0 0010 1011 ..... @d_d_d |
| 448 | FSLL32 10 ..... 110110 ..... 0 0010 0101 ..... @d_d_d |
| 449 | FSRL32 10 ..... 110110 ..... 0 0010 0111 ..... @d_d_d |
| 450 | FSLAS32 10 ..... 110110 ..... 0 0010 1101 ..... @d_d_d |
| 451 | FSRA32 10 ..... 110110 ..... 0 0010 1111 ..... @d_d_d |
| 452 | |
| 453 | FPCMPULE8 10 ..... 110110 ..... 1 0010 0000 ..... @r_d_d |
| 454 | FPCMPUGT8 10 ..... 110110 ..... 1 0010 1000 ..... @r_d_d |
| 455 | FPCMPNE8 10 ..... 110110 ..... 1 0010 0010 ..... @r_d_d |
| 456 | FPCMPEQ8 10 ..... 110110 ..... 1 0010 1010 ..... @r_d_d |
| 457 | FPCMPLE8 10 ..... 110110 ..... 0 0011 0100 ..... @r_d_d |
| 458 | FPCMPGT8 10 ..... 110110 ..... 0 0011 1100 ..... @r_d_d |
| 459 | FPCMPULE16 10 ..... 110110 ..... 1 0010 1110 ..... @r_d_d |
| 460 | FPCMPUGT16 10 ..... 110110 ..... 1 0010 1011 ..... @r_d_d |
| 461 | FPCMPULE32 10 ..... 110110 ..... 1 0010 1111 ..... @r_d_d |
| 462 | FPCMPUGT32 10 ..... 110110 ..... 1 0010 1100 ..... @r_d_d |
| 463 | |
| 464 | FMUL8x16 10 ..... 110110 ..... 0 0011 0001 ..... @d_r_d |
| 465 | FMUL8x16AU 10 ..... 110110 ..... 0 0011 0011 ..... @d_r_r |
| 466 | FMUL8x16AL 10 ..... 110110 ..... 0 0011 0101 ..... @d_r_r |
| 467 | FMUL8SUx16 10 ..... 110110 ..... 0 0011 0110 ..... @d_d_d |
| 468 | FMUL8ULx16 10 ..... 110110 ..... 0 0011 0111 ..... @d_d_d |
| 469 | FMULD8SUx16 10 ..... 110110 ..... 0 0011 1000 ..... @d_r_r |
| 470 | FMULD8ULx16 10 ..... 110110 ..... 0 0011 1001 ..... @d_r_r |
| 471 | FPACK32 10 ..... 110110 ..... 0 0011 1010 ..... @d_d_d |
| 472 | FPACK16 10 ..... 110110 00000 0 0011 1011 ..... @r_d2 |
| 473 | FPACKFIX 10 ..... 110110 00000 0 0011 1101 ..... @r_d2 |
| 474 | PDIST 10 ..... 110110 ..... 0 0011 1110 ..... \ |
| 475 | &r_r_r_r rd=%dfp_rd rs1=%dfp_rd rs2=%dfp_rs1 rs3=%dfp_rs2 |
| 476 | PDISTN 10 ..... 110110 ..... 0 0011 1111 ..... @r_d_d |
| 477 | |
| 478 | FMEAN16 10 ..... 110110 ..... 0 0100 0000 ..... @d_d_d |
| 479 | SUBXC 10 ..... 110110 ..... 0 0100 0001 ..... @r_r_r |
| 480 | SUBXCcc 10 ..... 110110 ..... 0 0100 0011 ..... @r_r_r |
| 481 | FCHKSM16 10 ..... 110110 ..... 0 0100 0100 ..... @d_d_d |
| 482 | FALIGNDATAg 10 ..... 110110 ..... 0 0100 1000 ..... @d_d_d |
| 483 | FPMERGE 10 ..... 110110 ..... 0 0100 1011 ..... @d_r_r |
| 484 | BSHUFFLE 10 ..... 110110 ..... 0 0100 1100 ..... @d_d_d |
| 485 | FEXPAND 10 ..... 110110 00000 0 0100 1101 ..... @d_r2 |
| 486 | FALIGNDATAi 10 ..... 110110 ..... 0 0100 1001 ..... @d_r_d |
| 487 | |
| 488 | FSRCd 10 ..... 110110 ..... 0 0111 0100 00000 @d_d1 # FSRC1d |
| 489 | FSRCs 10 ..... 110110 ..... 0 0111 0101 00000 @r_r1 # FSRC1s |
| 490 | FSRCd 10 ..... 110110 00000 0 0111 1000 ..... @d_d2 # FSRC2d |
| 491 | FSRCs 10 ..... 110110 00000 0 0111 1001 ..... @r_r2 # FSRC2s |
| 492 | FNOTd 10 ..... 110110 ..... 0 0110 1010 00000 @d_d1 # FNOT1d |
| 493 | FNOTs 10 ..... 110110 ..... 0 0110 1011 00000 @r_r1 # FNOT1s |
| 494 | FNOTd 10 ..... 110110 00000 0 0110 0110 ..... @d_d2 # FNOT2d |
| 495 | FNOTs 10 ..... 110110 00000 0 0110 0111 ..... @r_r2 # FNOT2s |
| 496 | |
| 497 | FPADD16 10 ..... 110110 ..... 0 0101 0000 ..... @d_d_d |
| 498 | FPADD16s 10 ..... 110110 ..... 0 0101 0001 ..... @r_r_r |
| 499 | FPADD32 10 ..... 110110 ..... 0 0101 0010 ..... @d_d_d |
| 500 | FPADD32s 10 ..... 110110 ..... 0 0101 0011 ..... @r_r_r |
| 501 | FPADD64 10 ..... 110110 ..... 0 0100 0010 ..... @d_d_d |
| 502 | FPSUB16 10 ..... 110110 ..... 0 0101 0100 ..... @d_d_d |
| 503 | FPSUB16s 10 ..... 110110 ..... 0 0101 0101 ..... @r_r_r |
| 504 | FPSUB32 10 ..... 110110 ..... 0 0101 0110 ..... @d_d_d |
| 505 | FPSUB32s 10 ..... 110110 ..... 0 0101 0111 ..... @r_r_r |
| 506 | FPSUB64 10 ..... 110110 ..... 0 0100 0110 ..... @d_d_d |
| 507 | |
| 508 | FPADDS16 10 ..... 110110 ..... 0 0101 1000 ..... @d_d_d |
| 509 | FPADDS16s 10 ..... 110110 ..... 0 0101 1001 ..... @r_r_r |
| 510 | FPADDS32 10 ..... 110110 ..... 0 0101 1010 ..... @d_d_d |
| 511 | FPADDS32s 10 ..... 110110 ..... 0 0101 1011 ..... @r_r_r |
| 512 | FPSUBS16 10 ..... 110110 ..... 0 0101 1100 ..... @d_d_d |
| 513 | FPSUBS16s 10 ..... 110110 ..... 0 0101 1101 ..... @r_r_r |
| 514 | FPSUBS32 10 ..... 110110 ..... 0 0101 1110 ..... @d_d_d |
| 515 | FPSUBS32s 10 ..... 110110 ..... 0 0101 1111 ..... @r_r_r |
| 516 | |
| 517 | FNORd 10 ..... 110110 ..... 0 0110 0010 ..... @d_d_d |
| 518 | FNORs 10 ..... 110110 ..... 0 0110 0011 ..... @r_r_r |
| 519 | FANDNOTd 10 ..... 110110 ..... 0 0110 0100 ..... @d_d_d # FANDNOT2d |
| 520 | FANDNOTs 10 ..... 110110 ..... 0 0110 0101 ..... @r_r_r # FANDNOT2s |
| 521 | FANDNOTd 10 ..... 110110 ..... 0 0110 1000 ..... @d_d_d_swap # ... 1d |
| 522 | FANDNOTs 10 ..... 110110 ..... 0 0110 1001 ..... @r_r_r_swap # ... 1s |
| 523 | FXORd 10 ..... 110110 ..... 0 0110 1100 ..... @d_d_d |
| 524 | FXORs 10 ..... 110110 ..... 0 0110 1101 ..... @r_r_r |
| 525 | FNANDd 10 ..... 110110 ..... 0 0110 1110 ..... @d_d_d |
| 526 | FNANDs 10 ..... 110110 ..... 0 0110 1111 ..... @r_r_r |
| 527 | FANDd 10 ..... 110110 ..... 0 0111 0000 ..... @d_d_d |
| 528 | FANDs 10 ..... 110110 ..... 0 0111 0001 ..... @r_r_r |
| 529 | FXNORd 10 ..... 110110 ..... 0 0111 0010 ..... @d_d_d |
| 530 | FXNORs 10 ..... 110110 ..... 0 0111 0011 ..... @r_r_r |
| 531 | FORNOTd 10 ..... 110110 ..... 0 0111 0110 ..... @d_d_d # FORNOT2d |
| 532 | FORNOTs 10 ..... 110110 ..... 0 0111 0111 ..... @r_r_r # FORNOT2s |
| 533 | FORNOTd 10 ..... 110110 ..... 0 0111 1010 ..... @d_d_d_swap # ... 1d |
| 534 | FORNOTs 10 ..... 110110 ..... 0 0111 1011 ..... @r_r_r_swap # ... 1s |
| 535 | FORd 10 ..... 110110 ..... 0 0111 1100 ..... @d_d_d |
| 536 | FORs 10 ..... 110110 ..... 0 0111 1101 ..... @r_r_r |
| 537 | |
| 538 | FZEROd 10 ..... 110110 00000 0 0110 0000 00000 rd=%dfp_rd |
| 539 | FZEROs 10 rd:5 110110 00000 0 0110 0001 00000 |
| 540 | FONEd 10 ..... 110110 00000 0 0111 1110 00000 rd=%dfp_rd |
| 541 | FONEs 10 rd:5 110110 00000 0 0111 1111 00000 |
| 542 | |
| 543 | MOVsTOuw 10 ..... 110110 00000 1 0001 0001 ..... @r_r2 |
| 544 | MOVsTOsw 10 ..... 110110 00000 1 0001 0011 ..... @r_r2 |
| 545 | MOVwTOs 10 ..... 110110 00000 1 0001 1001 ..... @r_r2 |
| 546 | MOVdTOx 10 ..... 110110 00000 1 0001 0000 ..... @r_d2 |
| 547 | MOVxTOd 10 ..... 110110 00000 1 0001 1000 ..... @d_r2 |
| 548 | |
| 549 | FPADD8 10 ..... 110110 ..... 1 0010 0100 ..... @d_d_d |
| 550 | FPADDS8 10 ..... 110110 ..... 1 0010 0110 ..... @d_d_d |
| 551 | FPADDUS8 10 ..... 110110 ..... 1 0010 0111 ..... @d_d_d |
| 552 | FPADDUS16 10 ..... 110110 ..... 1 0010 0011 ..... @d_d_d |
| 553 | FPSUB8 10 ..... 110110 ..... 1 0101 0100 ..... @d_d_d |
| 554 | FPSUBS8 10 ..... 110110 ..... 1 0101 0110 ..... @d_d_d |
| 555 | FPSUBUS8 10 ..... 110110 ..... 1 0101 0111 ..... @d_d_d |
| 556 | FPSUBUS16 10 ..... 110110 ..... 1 0101 0011 ..... @d_d_d |
| 557 | |
| 558 | FPMIN8 10 ..... 110110 ..... 1 0001 1010 ..... @d_d_d |
| 559 | FPMIN16 10 ..... 110110 ..... 1 0001 1011 ..... @d_d_d |
| 560 | FPMIN32 10 ..... 110110 ..... 1 0001 1100 ..... @d_d_d |
| 561 | FPMINU8 10 ..... 110110 ..... 1 0101 1010 ..... @d_d_d |
| 562 | FPMINU16 10 ..... 110110 ..... 1 0101 1011 ..... @d_d_d |
| 563 | FPMINU32 10 ..... 110110 ..... 1 0101 1100 ..... @d_d_d |
| 564 | |
| 565 | FPMAX8 10 ..... 110110 ..... 1 0001 1101 ..... @d_d_d |
| 566 | FPMAX16 10 ..... 110110 ..... 1 0001 1110 ..... @d_d_d |
| 567 | FPMAX32 10 ..... 110110 ..... 1 0001 1111 ..... @d_d_d |
| 568 | FPMAXU8 10 ..... 110110 ..... 1 0101 1101 ..... @d_d_d |
| 569 | FPMAXU16 10 ..... 110110 ..... 1 0101 1110 ..... @d_d_d |
| 570 | FPMAXU32 10 ..... 110110 ..... 1 0101 1111 ..... @d_d_d |
| 571 | |
| 572 | FLCMPs 10 000 cc:2 110110 rs1:5 1 0101 0001 rs2:5 |
| 573 | FLCMPd 10 000 cc:2 110110 ..... 1 0101 0010 ..... \ |
| 574 | rs1=%dfp_rs1 rs2=%dfp_rs2 |
| 575 | ] |
| 576 | NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1 |
| 577 | } |
| 578 | |
| 579 | { |
| 580 | [ |
| 581 | FMADDs 10 ..... 110111 ..... ..... 0001 ..... @r_r_r_r |
| 582 | FMADDd 10 ..... 110111 ..... ..... 0010 ..... @d_d_d_d |
| 583 | FMSUBs 10 ..... 110111 ..... ..... 0101 ..... @r_r_r_r |
| 584 | FMSUBd 10 ..... 110111 ..... ..... 0110 ..... @d_d_d_d |
| 585 | FNMSUBs 10 ..... 110111 ..... ..... 1001 ..... @r_r_r_r |
| 586 | FNMSUBd 10 ..... 110111 ..... ..... 1010 ..... @d_d_d_d |
| 587 | FNMADDs 10 ..... 110111 ..... ..... 1101 ..... @r_r_r_r |
| 588 | FNMADDd 10 ..... 110111 ..... ..... 1110 ..... @d_d_d_d |
| 589 | |
| 590 | FPMADDX 10 ..... 110111 ..... ..... 0000 ..... @d_d_d_d |
| 591 | FPMADDXHI 10 ..... 110111 ..... ..... 0100 ..... @d_d_d_d |
| 592 | ] |
| 593 | NCP 10 ----- 110111 ----- --------- ----- # v8 CPop2 |
| 594 | } |
| 595 | |
| 596 | ## |
| 597 | ## Major Opcode 11 -- load and store instructions |
| 598 | ## |
| 599 | |
| 600 | &r_r_ri_asi rd rs1 rs2_or_imm asi imm:bool |
| 601 | @r_r_ri_na .. rd:5 ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri_asi asi=-1 |
| 602 | @d_r_ri_na .. ..... ...... rs1:5 imm:1 rs2_or_imm:s13 \ |
| 603 | &r_r_ri_asi rd=%dfp_rd asi=-1 |
| 604 | @q_r_ri_na .. ..... ...... rs1:5 imm:1 rs2_or_imm:s13 \ |
| 605 | &r_r_ri_asi rd=%qfp_rd asi=-1 |
| 606 | |
| 607 | @r_r_r_asi .. rd:5 ...... rs1:5 0 asi:8 rs2_or_imm:5 &r_r_ri_asi imm=0 |
| 608 | @r_r_i_asi .. rd:5 ...... rs1:5 1 rs2_or_imm:s13 \ |
| 609 | &r_r_ri_asi imm=1 asi=-2 |
| 610 | @d_r_r_asi .. ..... ...... rs1:5 0 asi:8 rs2_or_imm:5 \ |
| 611 | &r_r_ri_asi rd=%dfp_rd imm=0 |
| 612 | @d_r_i_asi .. ..... ...... rs1:5 1 rs2_or_imm:s13 \ |
| 613 | &r_r_ri_asi rd=%dfp_rd imm=1 asi=-2 |
| 614 | @q_r_r_asi .. ..... ...... rs1:5 0 asi:8 rs2_or_imm:5 \ |
| 615 | &r_r_ri_asi rd=%qfp_rd imm=0 |
| 616 | @q_r_i_asi .. ..... ...... rs1:5 1 rs2_or_imm:s13 \ |
| 617 | &r_r_ri_asi rd=%qfp_rd imm=1 asi=-2 |
| 618 | @casa_imm .. rd:5 ...... rs1:5 1 00000000 rs2_or_imm:5 \ |
| 619 | &r_r_ri_asi imm=1 asi=-2 |
| 620 | |
| 621 | LDUW 11 ..... 000000 ..... . ............. @r_r_ri_na |
| 622 | LDUB 11 ..... 000001 ..... . ............. @r_r_ri_na |
| 623 | LDUH 11 ..... 000010 ..... . ............. @r_r_ri_na |
| 624 | LDD 11 ..... 000011 ..... . ............. @r_r_ri_na |
| 625 | LDSW 11 ..... 001000 ..... . ............. @r_r_ri_na |
| 626 | LDSB 11 ..... 001001 ..... . ............. @r_r_ri_na |
| 627 | LDSH 11 ..... 001010 ..... . ............. @r_r_ri_na |
| 628 | LDX 11 ..... 001011 ..... . ............. @r_r_ri_na |
| 629 | |
| 630 | STW 11 ..... 000100 ..... . ............. @r_r_ri_na |
| 631 | STB 11 ..... 000101 ..... . ............. @r_r_ri_na |
| 632 | STH 11 ..... 000110 ..... . ............. @r_r_ri_na |
| 633 | STD 11 ..... 000111 ..... . ............. @r_r_ri_na |
| 634 | STX 11 ..... 001110 ..... . ............. @r_r_ri_na |
| 635 | |
| 636 | LDUW 11 ..... 010000 ..... . ............. @r_r_r_asi # LDUWA |
| 637 | LDUW 11 ..... 010000 ..... . ............. @r_r_i_asi # LDUWA |
| 638 | LDUB 11 ..... 010001 ..... . ............. @r_r_r_asi # LDUBA |
| 639 | LDUB 11 ..... 010001 ..... . ............. @r_r_i_asi # LDUBA |
| 640 | LDUH 11 ..... 010010 ..... . ............. @r_r_r_asi # LDUHA |
| 641 | LDUH 11 ..... 010010 ..... . ............. @r_r_i_asi # LDUHA |
| 642 | LDD 11 ..... 010011 ..... . ............. @r_r_r_asi # LDDA |
| 643 | LDD 11 ..... 010011 ..... . ............. @r_r_i_asi # LDDA |
| 644 | LDX 11 ..... 011011 ..... . ............. @r_r_r_asi # LDXA |
| 645 | LDX 11 ..... 011011 ..... . ............. @r_r_i_asi # LDXA |
| 646 | LDSB 11 ..... 011001 ..... . ............. @r_r_r_asi # LDSBA |
| 647 | LDSB 11 ..... 011001 ..... . ............. @r_r_i_asi # LDSBA |
| 648 | LDSH 11 ..... 011010 ..... . ............. @r_r_r_asi # LDSHA |
| 649 | LDSH 11 ..... 011010 ..... . ............. @r_r_i_asi # LDSHA |
| 650 | LDSW 11 ..... 011000 ..... . ............. @r_r_r_asi # LDSWA |
| 651 | LDSW 11 ..... 011000 ..... . ............. @r_r_i_asi # LDSWA |
| 652 | |
| 653 | STW 11 ..... 010100 ..... . ............. @r_r_r_asi # STWA |
| 654 | STW 11 ..... 010100 ..... . ............. @r_r_i_asi # STWA |
| 655 | STB 11 ..... 010101 ..... . ............. @r_r_r_asi # STBA |
| 656 | STB 11 ..... 010101 ..... . ............. @r_r_i_asi # STBA |
| 657 | STH 11 ..... 010110 ..... . ............. @r_r_r_asi # STHA |
| 658 | STH 11 ..... 010110 ..... . ............. @r_r_i_asi # STHA |
| 659 | STD 11 ..... 010111 ..... . ............. @r_r_r_asi # STDA |
| 660 | STD 11 ..... 010111 ..... . ............. @r_r_i_asi # STDA |
| 661 | STX 11 ..... 011110 ..... . ............. @r_r_r_asi # STXA |
| 662 | STX 11 ..... 011110 ..... . ............. @r_r_i_asi # STXA |
| 663 | |
| 664 | LDF 11 ..... 100000 ..... . ............. @r_r_ri_na |
| 665 | LDFSR 11 00000 100001 ..... . ............. @n_r_ri |
| 666 | LDXFSR 11 00001 100001 ..... . ............. @n_r_ri |
| 667 | LDXEFSR 11 00011 100001 ..... . ............. @n_r_ri |
| 668 | LDQF 11 ..... 100010 ..... . ............. @q_r_ri_na |
| 669 | LDDF 11 ..... 100011 ..... . ............. @d_r_ri_na |
| 670 | |
| 671 | STF 11 ..... 100100 ..... . ............. @r_r_ri_na |
| 672 | STFSR 11 00000 100101 ..... . ............. @n_r_ri |
| 673 | STXFSR 11 00001 100101 ..... . ............. @n_r_ri |
| 674 | { |
| 675 | STQF 11 ..... 100110 ..... . ............. @q_r_ri_na # v9 |
| 676 | STDFQ 11 ..... 100110 ..... . ............. @r_r_ri # v7,v8 |
| 677 | } |
| 678 | STDF 11 ..... 100111 ..... . ............. @d_r_ri_na |
| 679 | |
| 680 | LDSTUB 11 ..... 001101 ..... . ............. @r_r_ri_na |
| 681 | LDSTUB 11 ..... 011101 ..... . ............. @r_r_r_asi # LDSTUBA |
| 682 | LDSTUB 11 ..... 011101 ..... . ............. @r_r_i_asi # LDSTUBA |
| 683 | |
| 684 | SWAP 11 ..... 001111 ..... . ............. @r_r_ri_na |
| 685 | SWAP 11 ..... 011111 ..... . ............. @r_r_r_asi # SWAPA |
| 686 | SWAP 11 ..... 011111 ..... . ............. @r_r_i_asi # SWAPA |
| 687 | |
| 688 | CASA 11 ..... 111100 ..... . ............. @r_r_r_asi |
| 689 | CASA 11 ..... 111100 ..... . ............. @casa_imm |
| 690 | CASXA 11 ..... 111110 ..... . ............. @r_r_r_asi |
| 691 | CASXA 11 ..... 111110 ..... . ............. @casa_imm |
| 692 | |
| 693 | NOP_v9 11 ----- 101101 ----- 0 00000000 ----- # PREFETCH |
| 694 | NOP_v9 11 ----- 101101 ----- 1 ------------- # PREFETCH |
| 695 | NOP_v9 11 ----- 111101 ----- - ------------- # PREFETCHA |
| 696 | |
| 697 | { |
| 698 | [ |
| 699 | LDFA 11 ..... 110000 ..... . ............. @r_r_r_asi |
| 700 | LDFA 11 ..... 110000 ..... . ............. @r_r_i_asi |
| 701 | ] |
| 702 | NCP 11 ----- 110000 ----- --------- ----- # v8 LDC |
| 703 | } |
| 704 | NCP 11 ----- 110001 ----- --------- ----- # v8 LDCSR |
| 705 | LDQFA 11 ..... 110010 ..... . ............. @q_r_r_asi |
| 706 | LDQFA 11 ..... 110010 ..... . ............. @q_r_i_asi |
| 707 | { |
| 708 | [ |
| 709 | LDDFA 11 ..... 110011 ..... . ............. @d_r_r_asi |
| 710 | LDDFA 11 ..... 110011 ..... . ............. @d_r_i_asi |
| 711 | ] |
| 712 | NCP 11 ----- 110011 ----- --------- ----- # v8 LDDC |
| 713 | } |
| 714 | |
| 715 | { |
| 716 | [ |
| 717 | STFA 11 ..... 110100 ..... . ............. @r_r_r_asi |
| 718 | STFA 11 ..... 110100 ..... . ............. @r_r_i_asi |
| 719 | ] |
| 720 | NCP 11 ----- 110100 ----- --------- ----- # v8 STC |
| 721 | } |
| 722 | NCP 11 ----- 110101 ----- --------- ----- # v8 STCSR |
| 723 | { |
| 724 | [ |
| 725 | STQFA 11 ..... 110110 ..... . ............. @q_r_r_asi |
| 726 | STQFA 11 ..... 110110 ..... . ............. @q_r_i_asi |
| 727 | ] |
| 728 | NCP 11 ----- 110110 ----- --------- ----- # v8 STDCQ |
| 729 | } |
| 730 | { |
| 731 | [ |
| 732 | STDFA 11 ..... 110111 ..... . ............. @d_r_r_asi |
| 733 | STDFA 11 ..... 110111 ..... . ............. @d_r_i_asi |
| 734 | ] |
| 735 | NCP 11 ----- 110111 ----- --------- ----- # v8 STDC |
| 736 | } |