| 1 | /* |
| 2 | * Sparc32 interrupt helpers |
| 3 | * |
| 4 | * Copyright (c) 2003-2005 Fabrice Bellard |
| 5 | * |
| 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2.1 of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU Lesser General Public |
| 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
| 18 | */ |
| 19 | |
| 20 | #include "qemu/osdep.h" |
| 21 | #include "qemu/main-loop.h" |
| 22 | #include "cpu.h" |
| 23 | #include "trace.h" |
| 24 | #include "accel/tcg/cpu-ldst.h" |
| 25 | #include "exec/log.h" |
| 26 | #include "system/runstate.h" |
| 27 | #include "qemu/plugin.h" |
| 28 | |
| 29 | static const char * const excp_names[0x80] = { |
| 30 | [TT_TFAULT] = "Instruction Access Fault", |
| 31 | [TT_ILL_INSN] = "Illegal Instruction", |
| 32 | [TT_PRIV_INSN] = "Privileged Instruction", |
| 33 | [TT_NFPU_INSN] = "FPU Disabled", |
| 34 | [TT_WIN_OVF] = "Window Overflow", |
| 35 | [TT_WIN_UNF] = "Window Underflow", |
| 36 | [TT_UNALIGNED] = "Unaligned Memory Access", |
| 37 | [TT_FP_EXCP] = "FPU Exception", |
| 38 | [TT_DFAULT] = "Data Access Fault", |
| 39 | [TT_TOVF] = "Tag Overflow", |
| 40 | [TT_EXTINT | 0x1] = "External Interrupt 1", |
| 41 | [TT_EXTINT | 0x2] = "External Interrupt 2", |
| 42 | [TT_EXTINT | 0x3] = "External Interrupt 3", |
| 43 | [TT_EXTINT | 0x4] = "External Interrupt 4", |
| 44 | [TT_EXTINT | 0x5] = "External Interrupt 5", |
| 45 | [TT_EXTINT | 0x6] = "External Interrupt 6", |
| 46 | [TT_EXTINT | 0x7] = "External Interrupt 7", |
| 47 | [TT_EXTINT | 0x8] = "External Interrupt 8", |
| 48 | [TT_EXTINT | 0x9] = "External Interrupt 9", |
| 49 | [TT_EXTINT | 0xa] = "External Interrupt 10", |
| 50 | [TT_EXTINT | 0xb] = "External Interrupt 11", |
| 51 | [TT_EXTINT | 0xc] = "External Interrupt 12", |
| 52 | [TT_EXTINT | 0xd] = "External Interrupt 13", |
| 53 | [TT_EXTINT | 0xe] = "External Interrupt 14", |
| 54 | [TT_EXTINT | 0xf] = "External Interrupt 15", |
| 55 | [TT_CODE_ACCESS] = "Instruction Access Error", |
| 56 | [TT_DATA_ACCESS] = "Data Access Error", |
| 57 | [TT_DIV_ZERO] = "Division By Zero", |
| 58 | [TT_NCP_INSN] = "Coprocessor Disabled", |
| 59 | }; |
| 60 | |
| 61 | static const char *excp_name_str(int32_t exception_index) |
| 62 | { |
| 63 | if (exception_index < 0 || exception_index >= ARRAY_SIZE(excp_names)) { |
| 64 | return "Unknown"; |
| 65 | } |
| 66 | return excp_names[exception_index]; |
| 67 | } |
| 68 | |
| 69 | #if !defined(CONFIG_USER_ONLY) |
| 70 | void cpu_check_irqs(CPUSPARCState *env) |
| 71 | { |
| 72 | CPUState *cs; |
| 73 | |
| 74 | /* We should be holding the BQL before we mess with IRQs */ |
| 75 | g_assert(bql_locked()); |
| 76 | |
| 77 | if (env->pil_in && (env->interrupt_index == 0 || |
| 78 | (env->interrupt_index & ~15) == TT_EXTINT)) { |
| 79 | unsigned int i; |
| 80 | |
| 81 | for (i = 15; i > 0; i--) { |
| 82 | if (env->pil_in & (1 << i)) { |
| 83 | int old_interrupt = env->interrupt_index; |
| 84 | |
| 85 | env->interrupt_index = TT_EXTINT | i; |
| 86 | if (old_interrupt != env->interrupt_index) { |
| 87 | cs = env_cpu(env); |
| 88 | trace_sun4m_cpu_interrupt(i); |
| 89 | cpu_interrupt(cs, CPU_INTERRUPT_HARD); |
| 90 | } |
| 91 | break; |
| 92 | } |
| 93 | } |
| 94 | } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) { |
| 95 | cs = env_cpu(env); |
| 96 | trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15); |
| 97 | env->interrupt_index = 0; |
| 98 | cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); |
| 99 | } |
| 100 | } |
| 101 | #endif |
| 102 | |
| 103 | void sparc_cpu_do_interrupt(CPUState *cs) |
| 104 | { |
| 105 | CPUSPARCState *env = cpu_env(cs); |
| 106 | int cwp, intno = cs->exception_index; |
| 107 | |
| 108 | if (qemu_loglevel_mask(CPU_LOG_INT)) { |
| 109 | static int count; |
| 110 | const char *name; |
| 111 | |
| 112 | if (intno < 0 || intno >= 0x100) { |
| 113 | name = "Unknown"; |
| 114 | } else if (intno >= 0x80) { |
| 115 | name = "Trap Instruction"; |
| 116 | } else { |
| 117 | name = excp_name_str(intno); |
| 118 | } |
| 119 | |
| 120 | qemu_log("%6d: %s (v=%02x)\n", count, name, intno); |
| 121 | log_cpu_state(cs, 0); |
| 122 | count++; |
| 123 | } |
| 124 | #ifndef CONFIG_USER_ONLY |
| 125 | if (env->psret == 0) { |
| 126 | if (cs->exception_index == 0x80 && |
| 127 | env->def.features & CPU_FEATURE_TA0_SHUTDOWN) { |
| 128 | qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); |
| 129 | } else { |
| 130 | cpu_abort(cs, "Trap 0x%02x (%s) while interrupts disabled, " |
| 131 | "Error state", |
| 132 | cs->exception_index, excp_name_str(cs->exception_index)); |
| 133 | } |
| 134 | return; |
| 135 | } |
| 136 | if (intno == TT_FP_EXCP) { |
| 137 | /* |
| 138 | * The sparc32 fpu has three states related to exception handling. |
| 139 | * The FPop that signals an exception transitions from fp_execute |
| 140 | * to fp_exception_pending. A subsequent FPop transitions from |
| 141 | * fp_exception_pending to fp_exception, which forces the trap. |
| 142 | * |
| 143 | * If the queue is not empty, this trap is due to execution of an |
| 144 | * illegal FPop while in fp_exception state. Here we are to |
| 145 | * re-enter fp_exception_pending state without queuing the insn. |
| 146 | * |
| 147 | * We do not model the fp_exception_pending state, but instead |
| 148 | * skip directly to fp_exception state. We advance pc/npc to |
| 149 | * mimic delayed trap delivery as if by the subsequent insn. |
| 150 | */ |
| 151 | if (!env->fsr_qne) { |
| 152 | MemOpIdx oi = make_memop_idx(MO_BEUL, cpu_mmu_index(cs, true)); |
| 153 | |
| 154 | env->fsr_qne = FSR_QNE; |
| 155 | env->fq.s.addr = env->pc; |
| 156 | env->fq.s.insn = cpu_ldl_code_mmu(env, env->pc, oi, 0); |
| 157 | } |
| 158 | env->pc = env->npc; |
| 159 | env->npc = env->npc + 4; |
| 160 | } |
| 161 | #endif |
| 162 | env->psret = 0; |
| 163 | cwp = cpu_cwp_dec(env, env->cwp - 1); |
| 164 | cpu_set_cwp(env, cwp); |
| 165 | env->regwptr[9] = env->pc; |
| 166 | env->regwptr[10] = env->npc; |
| 167 | env->psrps = env->psrs; |
| 168 | env->psrs = 1; |
| 169 | env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4); |
| 170 | env->pc = env->tbr; |
| 171 | env->npc = env->pc + 4; |
| 172 | cs->exception_index = -1; |
| 173 | |
| 174 | #if !defined(CONFIG_USER_ONLY) |
| 175 | /* IRQ acknowledgment */ |
| 176 | if ((intno & ~15) == TT_EXTINT && env->qemu_irq_ack != NULL) { |
| 177 | env->qemu_irq_ack(env, intno); |
| 178 | } |
| 179 | #endif |
| 180 | |
| 181 | if (intno == TT_EXTINT) { |
| 182 | qemu_plugin_vcpu_interrupt_cb(cs, env->regwptr[9]); |
| 183 | } else { |
| 184 | qemu_plugin_vcpu_exception_cb(cs, env->regwptr[9]); |
| 185 | } |
| 186 | } |