| 1 | /* |
| 2 | * Sparc64 interrupt helpers |
| 3 | * |
| 4 | * Copyright (c) 2003-2005 Fabrice Bellard |
| 5 | * |
| 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2.1 of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU Lesser General Public |
| 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
| 18 | */ |
| 19 | |
| 20 | #include "qemu/osdep.h" |
| 21 | #include "qemu/main-loop.h" |
| 22 | #include "cpu.h" |
| 23 | #include "exec/cpu-common.h" |
| 24 | #include "exec/helper-proto.h" |
| 25 | #include "exec/log.h" |
| 26 | #include "trace.h" |
| 27 | #include "qemu/plugin.h" |
| 28 | |
| 29 | #define DEBUG_PCALL |
| 30 | |
| 31 | #ifdef DEBUG_PCALL |
| 32 | static const char * const excp_names[0x80] = { |
| 33 | [TT_TFAULT] = "Instruction Access Fault", |
| 34 | [TT_TMISS] = "Instruction Access MMU Miss", |
| 35 | [TT_CODE_ACCESS] = "Instruction Access Error", |
| 36 | [TT_ILL_INSN] = "Illegal Instruction", |
| 37 | [TT_PRIV_INSN] = "Privileged Instruction", |
| 38 | [TT_NFPU_INSN] = "FPU Disabled", |
| 39 | [TT_FP_EXCP] = "FPU Exception", |
| 40 | [TT_TOVF] = "Tag Overflow", |
| 41 | [TT_CLRWIN] = "Clean Windows", |
| 42 | [TT_DIV_ZERO] = "Division By Zero", |
| 43 | [TT_DFAULT] = "Data Access Fault", |
| 44 | [TT_DMISS] = "Data Access MMU Miss", |
| 45 | [TT_DATA_ACCESS] = "Data Access Error", |
| 46 | [TT_DPROT] = "Data Protection Error", |
| 47 | [TT_UNALIGNED] = "Unaligned Memory Access", |
| 48 | [TT_PRIV_ACT] = "Privileged Action", |
| 49 | [TT_EXTINT | 0x1] = "External Interrupt 1", |
| 50 | [TT_EXTINT | 0x2] = "External Interrupt 2", |
| 51 | [TT_EXTINT | 0x3] = "External Interrupt 3", |
| 52 | [TT_EXTINT | 0x4] = "External Interrupt 4", |
| 53 | [TT_EXTINT | 0x5] = "External Interrupt 5", |
| 54 | [TT_EXTINT | 0x6] = "External Interrupt 6", |
| 55 | [TT_EXTINT | 0x7] = "External Interrupt 7", |
| 56 | [TT_EXTINT | 0x8] = "External Interrupt 8", |
| 57 | [TT_EXTINT | 0x9] = "External Interrupt 9", |
| 58 | [TT_EXTINT | 0xa] = "External Interrupt 10", |
| 59 | [TT_EXTINT | 0xb] = "External Interrupt 11", |
| 60 | [TT_EXTINT | 0xc] = "External Interrupt 12", |
| 61 | [TT_EXTINT | 0xd] = "External Interrupt 13", |
| 62 | [TT_EXTINT | 0xe] = "External Interrupt 14", |
| 63 | [TT_EXTINT | 0xf] = "External Interrupt 15", |
| 64 | }; |
| 65 | #endif |
| 66 | |
| 67 | #if !defined(CONFIG_USER_ONLY) |
| 68 | void cpu_check_irqs(CPUSPARCState *env) |
| 69 | { |
| 70 | CPUState *cs; |
| 71 | uint32_t pil = env->pil_in | |
| 72 | (env->softint & ~(SOFTINT_TIMER | SOFTINT_STIMER)); |
| 73 | |
| 74 | /* We should be holding the BQL before we mess with IRQs */ |
| 75 | g_assert(bql_locked()); |
| 76 | |
| 77 | /* TT_IVEC has a higher priority (16) than TT_EXTINT (31..17) */ |
| 78 | if (env->ivec_status & 0x20) { |
| 79 | return; |
| 80 | } |
| 81 | cs = env_cpu(env); |
| 82 | /* |
| 83 | * check if TM or SM in SOFTINT are set |
| 84 | * setting these also causes interrupt 14 |
| 85 | */ |
| 86 | if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) { |
| 87 | pil |= 1 << 14; |
| 88 | } |
| 89 | |
| 90 | /* |
| 91 | * The bit corresponding to psrpil is (1<< psrpil), |
| 92 | * the next bit is (2 << psrpil). |
| 93 | */ |
| 94 | if (pil < (2 << env->psrpil)) { |
| 95 | if (cpu_test_interrupt(cs, CPU_INTERRUPT_HARD)) { |
| 96 | trace_sparc64_cpu_check_irqs_reset_irq(env->interrupt_index); |
| 97 | env->interrupt_index = 0; |
| 98 | cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); |
| 99 | } |
| 100 | return; |
| 101 | } |
| 102 | |
| 103 | if (cpu_interrupts_enabled(env)) { |
| 104 | |
| 105 | unsigned int i; |
| 106 | |
| 107 | for (i = 15; i > env->psrpil; i--) { |
| 108 | if (pil & (1 << i)) { |
| 109 | int old_interrupt = env->interrupt_index; |
| 110 | int new_interrupt = TT_EXTINT | i; |
| 111 | |
| 112 | if (unlikely(env->tl > 0 && cpu_tsptr(env)->tt > new_interrupt |
| 113 | && ((cpu_tsptr(env)->tt & 0x1f0) == TT_EXTINT))) { |
| 114 | trace_sparc64_cpu_check_irqs_noset_irq(env->tl, |
| 115 | cpu_tsptr(env)->tt, |
| 116 | new_interrupt); |
| 117 | } else if (old_interrupt != new_interrupt) { |
| 118 | env->interrupt_index = new_interrupt; |
| 119 | trace_sparc64_cpu_check_irqs_set_irq(i, old_interrupt, |
| 120 | new_interrupt); |
| 121 | cpu_interrupt(cs, CPU_INTERRUPT_HARD); |
| 122 | } |
| 123 | break; |
| 124 | } |
| 125 | } |
| 126 | } else if (cpu_test_interrupt(cs, CPU_INTERRUPT_HARD)) { |
| 127 | trace_sparc64_cpu_check_irqs_disabled(pil, env->pil_in, env->softint, |
| 128 | env->interrupt_index); |
| 129 | env->interrupt_index = 0; |
| 130 | cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); |
| 131 | } |
| 132 | } |
| 133 | #endif |
| 134 | |
| 135 | void sparc_cpu_do_interrupt(CPUState *cs) |
| 136 | { |
| 137 | CPUSPARCState *env = cpu_env(cs); |
| 138 | int intno = cs->exception_index; |
| 139 | trap_state *tsptr; |
| 140 | |
| 141 | #ifdef DEBUG_PCALL |
| 142 | if (qemu_loglevel_mask(CPU_LOG_INT)) { |
| 143 | static int count; |
| 144 | const char *name; |
| 145 | |
| 146 | if (intno < 0 || intno >= 0x1ff) { |
| 147 | name = "Unknown"; |
| 148 | } else if (intno >= 0x180) { |
| 149 | name = "Hyperprivileged Trap Instruction"; |
| 150 | } else if (intno >= 0x100) { |
| 151 | name = "Trap Instruction"; |
| 152 | } else if (intno >= 0xc0) { |
| 153 | name = "Window Fill"; |
| 154 | } else if (intno >= 0x80) { |
| 155 | name = "Window Spill"; |
| 156 | } else { |
| 157 | name = excp_names[intno]; |
| 158 | if (!name) { |
| 159 | name = "Unknown"; |
| 160 | } |
| 161 | } |
| 162 | |
| 163 | qemu_log("%6d: %s (v=%04x)\n", count, name, intno); |
| 164 | log_cpu_state(cs, 0); |
| 165 | #if 0 |
| 166 | { |
| 167 | int i; |
| 168 | uint8_t *ptr; |
| 169 | |
| 170 | qemu_log(" code="); |
| 171 | ptr = (uint8_t *)env->pc; |
| 172 | for (i = 0; i < 16; i++) { |
| 173 | qemu_log(" %02x", ldub(ptr + i)); |
| 174 | } |
| 175 | qemu_log("\n"); |
| 176 | } |
| 177 | #endif |
| 178 | count++; |
| 179 | } |
| 180 | #endif |
| 181 | #if !defined(CONFIG_USER_ONLY) |
| 182 | if (env->tl >= env->maxtl) { |
| 183 | cpu_abort(cs, "Trap 0x%04x while trap level (%d) >= MAXTL (%d)," |
| 184 | " Error state", cs->exception_index, env->tl, env->maxtl); |
| 185 | return; |
| 186 | } |
| 187 | #endif |
| 188 | if (env->tl < env->maxtl - 1) { |
| 189 | env->tl++; |
| 190 | } else { |
| 191 | env->pstate |= PS_RED; |
| 192 | if (env->tl < env->maxtl) { |
| 193 | env->tl++; |
| 194 | } |
| 195 | } |
| 196 | tsptr = cpu_tsptr(env); |
| 197 | |
| 198 | tsptr->tstate = sparc64_tstate(env); |
| 199 | tsptr->tpc = env->pc; |
| 200 | tsptr->tnpc = env->npc; |
| 201 | tsptr->tt = intno; |
| 202 | |
| 203 | if (cpu_has_hypervisor(env)) { |
| 204 | env->htstate[env->tl] = env->hpstate; |
| 205 | /* XXX OpenSPARC T1 - UltraSPARC T3 have MAXPTL=2 |
| 206 | but this may change in the future */ |
| 207 | if (env->tl > 2) { |
| 208 | env->hpstate |= HS_PRIV; |
| 209 | } |
| 210 | } |
| 211 | |
| 212 | if (env->def.features & CPU_FEATURE_GL) { |
| 213 | cpu_gl_switch_gregs(env, env->gl + 1); |
| 214 | env->gl++; |
| 215 | } |
| 216 | |
| 217 | switch (intno) { |
| 218 | case TT_IVEC: |
| 219 | if (!cpu_has_hypervisor(env)) { |
| 220 | cpu_change_pstate(env, PS_PEF | PS_PRIV | PS_IG); |
| 221 | } |
| 222 | break; |
| 223 | case TT_TFAULT: |
| 224 | case TT_DFAULT: |
| 225 | case TT_TMISS ... TT_TMISS + 3: |
| 226 | case TT_DMISS ... TT_DMISS + 3: |
| 227 | case TT_DPROT ... TT_DPROT + 3: |
| 228 | if (cpu_has_hypervisor(env)) { |
| 229 | env->hpstate |= HS_PRIV; |
| 230 | env->pstate = PS_PEF | PS_PRIV; |
| 231 | } else { |
| 232 | cpu_change_pstate(env, PS_PEF | PS_PRIV | PS_MG); |
| 233 | } |
| 234 | break; |
| 235 | case TT_INSN_REAL_TRANSLATION_MISS ... TT_DATA_REAL_TRANSLATION_MISS: |
| 236 | case TT_HTRAP ... TT_HTRAP + 127: |
| 237 | env->hpstate |= HS_PRIV; |
| 238 | break; |
| 239 | default: |
| 240 | cpu_change_pstate(env, PS_PEF | PS_PRIV | PS_AG); |
| 241 | break; |
| 242 | } |
| 243 | |
| 244 | if (intno == TT_CLRWIN) { |
| 245 | cpu_set_cwp(env, cpu_cwp_dec(env, env->cwp - 1)); |
| 246 | } else if ((intno & 0x1c0) == TT_SPILL) { |
| 247 | cpu_set_cwp(env, cpu_cwp_dec(env, env->cwp - env->cansave - 2)); |
| 248 | } else if ((intno & 0x1c0) == TT_FILL) { |
| 249 | cpu_set_cwp(env, cpu_cwp_inc(env, env->cwp + 1)); |
| 250 | } |
| 251 | |
| 252 | if (cpu_hypervisor_mode(env)) { |
| 253 | env->pc = (env->htba & ~0x3fffULL) | (intno << 5); |
| 254 | } else { |
| 255 | env->pc = env->tbr & ~0x7fffULL; |
| 256 | env->pc |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5); |
| 257 | } |
| 258 | env->npc = env->pc + 4; |
| 259 | cs->exception_index = -1; |
| 260 | |
| 261 | switch (intno) { |
| 262 | case TT_EXTINT: |
| 263 | case TT_IVEC: |
| 264 | qemu_plugin_vcpu_interrupt_cb(cs, tsptr->tpc); |
| 265 | break; |
| 266 | default: |
| 267 | qemu_plugin_vcpu_exception_cb(cs, tsptr->tpc); |
| 268 | } |
| 269 | } |
| 270 | |
| 271 | trap_state *cpu_tsptr(CPUSPARCState* env) |
| 272 | { |
| 273 | return &env->ts[env->tl & MAXTL_MASK]; |
| 274 | } |
| 275 | |
| 276 | static bool do_modify_softint(CPUSPARCState *env, uint32_t value) |
| 277 | { |
| 278 | if (env->softint != value) { |
| 279 | env->softint = value; |
| 280 | #if !defined(CONFIG_USER_ONLY) |
| 281 | if (cpu_interrupts_enabled(env)) { |
| 282 | bql_lock(); |
| 283 | cpu_check_irqs(env); |
| 284 | bql_unlock(); |
| 285 | } |
| 286 | #endif |
| 287 | return true; |
| 288 | } |
| 289 | return false; |
| 290 | } |
| 291 | |
| 292 | void helper_set_softint(CPUSPARCState *env, uint64_t value) |
| 293 | { |
| 294 | if (do_modify_softint(env, env->softint | (uint32_t)value)) { |
| 295 | trace_int_helper_set_softint(env->softint); |
| 296 | } |
| 297 | } |
| 298 | |
| 299 | void helper_clear_softint(CPUSPARCState *env, uint64_t value) |
| 300 | { |
| 301 | if (do_modify_softint(env, env->softint & (uint32_t)~value)) { |
| 302 | trace_int_helper_clear_softint(env->softint); |
| 303 | } |
| 304 | } |
| 305 | |
| 306 | void helper_write_softint(CPUSPARCState *env, uint64_t value) |
| 307 | { |
| 308 | if (do_modify_softint(env, (uint32_t)value)) { |
| 309 | trace_int_helper_write_softint(env->softint); |
| 310 | } |
| 311 | } |