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1 /* Xtensa configuration-specific ISA information.
2 Copyright 2003, 2004, 2005 Free Software Foundation, Inc.
3
4 This file is part of BFD, the Binary File Descriptor library.
5
6 This program is free software; you can redistribute it and/or
7 modify it under the terms of the GNU General Public License as
8 published by the Free Software Foundation; either version 2 of the
9 License, or (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, see
18 <https://www.gnu.org/licenses/>. */
19
20 #include "qemu/osdep.h"
21 #include "xtensa-isa.h"
22 #include "xtensa-isa-internal.h"
23
24
25 /* Sysregs. */
26
27 static xtensa_sysreg_internal sysregs[] = {
28 { "LBEG", 0, 0 },
29 { "LEND", 1, 0 },
30 { "LCOUNT", 2, 0 },
31 { "ACCLO", 16, 0 },
32 { "ACCHI", 17, 0 },
33 { "M0", 32, 0 },
34 { "M1", 33, 0 },
35 { "M2", 34, 0 },
36 { "M3", 35, 0 },
37 { "PTEVADDR", 83, 0 },
38 { "MMID", 89, 0 },
39 { "DDR", 104, 0 },
40 { "176", 176, 0 },
41 { "208", 208, 0 },
42 { "INTERRUPT", 226, 0 },
43 { "INTCLEAR", 227, 0 },
44 { "CCOUNT", 234, 0 },
45 { "PRID", 235, 0 },
46 { "ICOUNT", 236, 0 },
47 { "CCOMPARE0", 240, 0 },
48 { "CCOMPARE1", 241, 0 },
49 { "CCOMPARE2", 242, 0 },
50 { "VECBASE", 231, 0 },
51 { "EPC1", 177, 0 },
52 { "EPC2", 178, 0 },
53 { "EPC3", 179, 0 },
54 { "EPC4", 180, 0 },
55 { "EPC5", 181, 0 },
56 { "EPC6", 182, 0 },
57 { "EPC7", 183, 0 },
58 { "EXCSAVE1", 209, 0 },
59 { "EXCSAVE2", 210, 0 },
60 { "EXCSAVE3", 211, 0 },
61 { "EXCSAVE4", 212, 0 },
62 { "EXCSAVE5", 213, 0 },
63 { "EXCSAVE6", 214, 0 },
64 { "EXCSAVE7", 215, 0 },
65 { "EPS2", 194, 0 },
66 { "EPS3", 195, 0 },
67 { "EPS4", 196, 0 },
68 { "EPS5", 197, 0 },
69 { "EPS6", 198, 0 },
70 { "EPS7", 199, 0 },
71 { "EXCCAUSE", 232, 0 },
72 { "DEPC", 192, 0 },
73 { "EXCVADDR", 238, 0 },
74 { "WINDOWBASE", 72, 0 },
75 { "WINDOWSTART", 73, 0 },
76 { "SAR", 3, 0 },
77 { "LITBASE", 5, 0 },
78 { "PS", 230, 0 },
79 { "MISC0", 244, 0 },
80 { "MISC1", 245, 0 },
81 { "INTENABLE", 228, 0 },
82 { "DBREAKA0", 144, 0 },
83 { "DBREAKC0", 160, 0 },
84 { "DBREAKA1", 145, 0 },
85 { "DBREAKC1", 161, 0 },
86 { "IBREAKA0", 128, 0 },
87 { "IBREAKA1", 129, 0 },
88 { "IBREAKENABLE", 96, 0 },
89 { "ICOUNTLEVEL", 237, 0 },
90 { "DEBUGCAUSE", 233, 0 },
91 { "RASID", 90, 0 },
92 { "ITLBCFG", 91, 0 },
93 { "DTLBCFG", 92, 0 },
94 { "CPENABLE", 224, 0 },
95 { "SCOMPARE1", 12, 0 },
96 { "THREADPTR", 231, 1 },
97 { "EXPSTATE", 230, 1 }
98 };
99
100 #define NUM_SYSREGS 70
101 #define MAX_SPECIAL_REG 245
102 #define MAX_USER_REG 231
103
104
105 /* Processor states. */
106
107 static xtensa_state_internal states[] = {
108 { "LCOUNT", 32, 0 },
109 { "PC", 32, 0 },
110 { "ICOUNT", 32, 0 },
111 { "DDR", 32, 0 },
112 { "INTERRUPT", 22, 0 },
113 { "CCOUNT", 32, 0 },
114 { "XTSYNC", 1, 0 },
115 { "VECBASE", 22, 0 },
116 { "EPC1", 32, 0 },
117 { "EPC2", 32, 0 },
118 { "EPC3", 32, 0 },
119 { "EPC4", 32, 0 },
120 { "EPC5", 32, 0 },
121 { "EPC6", 32, 0 },
122 { "EPC7", 32, 0 },
123 { "EXCSAVE1", 32, 0 },
124 { "EXCSAVE2", 32, 0 },
125 { "EXCSAVE3", 32, 0 },
126 { "EXCSAVE4", 32, 0 },
127 { "EXCSAVE5", 32, 0 },
128 { "EXCSAVE6", 32, 0 },
129 { "EXCSAVE7", 32, 0 },
130 { "EPS2", 15, 0 },
131 { "EPS3", 15, 0 },
132 { "EPS4", 15, 0 },
133 { "EPS5", 15, 0 },
134 { "EPS6", 15, 0 },
135 { "EPS7", 15, 0 },
136 { "EXCCAUSE", 6, 0 },
137 { "PSINTLEVEL", 4, 0 },
138 { "PSUM", 1, 0 },
139 { "PSWOE", 1, 0 },
140 { "PSRING", 2, 0 },
141 { "PSEXCM", 1, 0 },
142 { "DEPC", 32, 0 },
143 { "EXCVADDR", 32, 0 },
144 { "WindowBase", 3, 0 },
145 { "WindowStart", 8, 0 },
146 { "PSCALLINC", 2, 0 },
147 { "PSOWB", 4, 0 },
148 { "LBEG", 32, 0 },
149 { "LEND", 32, 0 },
150 { "SAR", 6, 0 },
151 { "THREADPTR", 32, 0 },
152 { "LITBADDR", 20, 0 },
153 { "LITBEN", 1, 0 },
154 { "MISC0", 32, 0 },
155 { "MISC1", 32, 0 },
156 { "ACC", 40, 0 },
157 { "InOCDMode", 1, 0 },
158 { "INTENABLE", 22, 0 },
159 { "DBREAKA0", 32, 0 },
160 { "DBREAKC0", 8, 0 },
161 { "DBREAKA1", 32, 0 },
162 { "DBREAKC1", 8, 0 },
163 { "IBREAKA0", 32, 0 },
164 { "IBREAKA1", 32, 0 },
165 { "IBREAKENABLE", 2, 0 },
166 { "ICOUNTLEVEL", 4, 0 },
167 { "DEBUGCAUSE", 6, 0 },
168 { "DBNUM", 4, 0 },
169 { "CCOMPARE0", 32, 0 },
170 { "CCOMPARE1", 32, 0 },
171 { "CCOMPARE2", 32, 0 },
172 { "ASID3", 8, 0 },
173 { "ASID2", 8, 0 },
174 { "ASID1", 8, 0 },
175 { "INSTPGSZID4", 2, 0 },
176 { "DATAPGSZID4", 2, 0 },
177 { "PTBASE", 10, 0 },
178 { "CPENABLE", 8, 0 },
179 { "SCOMPARE1", 32, 0 },
180 { "EXPSTATE", 32, XTENSA_STATE_IS_EXPORTED }
181 };
182
183 #define NUM_STATES 73
184
185 /* Macros for xtensa_state numbers (for use in iclasses because the
186 state numbers are not available when the iclass table is generated). */
187
188 #define STATE_LCOUNT 0
189 #define STATE_PC 1
190 #define STATE_ICOUNT 2
191 #define STATE_DDR 3
192 #define STATE_INTERRUPT 4
193 #define STATE_CCOUNT 5
194 #define STATE_XTSYNC 6
195 #define STATE_VECBASE 7
196 #define STATE_EPC1 8
197 #define STATE_EPC2 9
198 #define STATE_EPC3 10
199 #define STATE_EPC4 11
200 #define STATE_EPC5 12
201 #define STATE_EPC6 13
202 #define STATE_EPC7 14
203 #define STATE_EXCSAVE1 15
204 #define STATE_EXCSAVE2 16
205 #define STATE_EXCSAVE3 17
206 #define STATE_EXCSAVE4 18
207 #define STATE_EXCSAVE5 19
208 #define STATE_EXCSAVE6 20
209 #define STATE_EXCSAVE7 21
210 #define STATE_EPS2 22
211 #define STATE_EPS3 23
212 #define STATE_EPS4 24
213 #define STATE_EPS5 25
214 #define STATE_EPS6 26
215 #define STATE_EPS7 27
216 #define STATE_EXCCAUSE 28
217 #define STATE_PSINTLEVEL 29
218 #define STATE_PSUM 30
219 #define STATE_PSWOE 31
220 #define STATE_PSRING 32
221 #define STATE_PSEXCM 33
222 #define STATE_DEPC 34
223 #define STATE_EXCVADDR 35
224 #define STATE_WindowBase 36
225 #define STATE_WindowStart 37
226 #define STATE_PSCALLINC 38
227 #define STATE_PSOWB 39
228 #define STATE_LBEG 40
229 #define STATE_LEND 41
230 #define STATE_SAR 42
231 #define STATE_THREADPTR 43
232 #define STATE_LITBADDR 44
233 #define STATE_LITBEN 45
234 #define STATE_MISC0 46
235 #define STATE_MISC1 47
236 #define STATE_ACC 48
237 #define STATE_InOCDMode 49
238 #define STATE_INTENABLE 50
239 #define STATE_DBREAKA0 51
240 #define STATE_DBREAKC0 52
241 #define STATE_DBREAKA1 53
242 #define STATE_DBREAKC1 54
243 #define STATE_IBREAKA0 55
244 #define STATE_IBREAKA1 56
245 #define STATE_IBREAKENABLE 57
246 #define STATE_ICOUNTLEVEL 58
247 #define STATE_DEBUGCAUSE 59
248 #define STATE_DBNUM 60
249 #define STATE_CCOMPARE0 61
250 #define STATE_CCOMPARE1 62
251 #define STATE_CCOMPARE2 63
252 #define STATE_ASID3 64
253 #define STATE_ASID2 65
254 #define STATE_ASID1 66
255 #define STATE_INSTPGSZID4 67
256 #define STATE_DATAPGSZID4 68
257 #define STATE_PTBASE 69
258 #define STATE_CPENABLE 70
259 #define STATE_SCOMPARE1 71
260 #define STATE_EXPSTATE 72
261
262
263 /* Field definitions. */
264
265 static unsigned
266 Field_t_Slot_inst_get (const xtensa_insnbuf insn)
267 {
268 unsigned tie_t = 0;
269 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
270 return tie_t;
271 }
272
273 static void
274 Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
275 {
276 uint32 tie_t;
277 tie_t = (val << 28) >> 28;
278 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
279 }
280
281 static unsigned
282 Field_t_Slot_inst16a_get (const xtensa_insnbuf insn)
283 {
284 unsigned tie_t = 0;
285 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
286 return tie_t;
287 }
288
289 static void
290 Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
291 {
292 uint32 tie_t;
293 tie_t = (val << 28) >> 28;
294 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
295 }
296
297 static unsigned
298 Field_t_Slot_inst16b_get (const xtensa_insnbuf insn)
299 {
300 unsigned tie_t = 0;
301 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
302 return tie_t;
303 }
304
305 static void
306 Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
307 {
308 uint32 tie_t;
309 tie_t = (val << 28) >> 28;
310 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
311 }
312
313 static unsigned
314 Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn)
315 {
316 unsigned tie_t = 0;
317 tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
318 return tie_t;
319 }
320
321 static void
322 Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
323 {
324 uint32 tie_t;
325 tie_t = (val << 31) >> 31;
326 insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
327 }
328
329 static unsigned
330 Field_bbi_Slot_inst_get (const xtensa_insnbuf insn)
331 {
332 unsigned tie_t = 0;
333 tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
334 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
335 return tie_t;
336 }
337
338 static void
339 Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
340 {
341 uint32 tie_t;
342 tie_t = (val << 28) >> 28;
343 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
344 tie_t = (val << 27) >> 31;
345 insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
346 }
347
348 static unsigned
349 Field_imm12_Slot_inst_get (const xtensa_insnbuf insn)
350 {
351 unsigned tie_t = 0;
352 tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20);
353 return tie_t;
354 }
355
356 static void
357 Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
358 {
359 uint32 tie_t;
360 tie_t = (val << 20) >> 20;
361 insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12);
362 }
363
364 static unsigned
365 Field_imm8_Slot_inst_get (const xtensa_insnbuf insn)
366 {
367 unsigned tie_t = 0;
368 tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
369 return tie_t;
370 }
371
372 static void
373 Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
374 {
375 uint32 tie_t;
376 tie_t = (val << 24) >> 24;
377 insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
378 }
379
380 static unsigned
381 Field_s_Slot_inst_get (const xtensa_insnbuf insn)
382 {
383 unsigned tie_t = 0;
384 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
385 return tie_t;
386 }
387
388 static void
389 Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
390 {
391 uint32 tie_t;
392 tie_t = (val << 28) >> 28;
393 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
394 }
395
396 static unsigned
397 Field_s_Slot_inst16a_get (const xtensa_insnbuf insn)
398 {
399 unsigned tie_t = 0;
400 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
401 return tie_t;
402 }
403
404 static void
405 Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
406 {
407 uint32 tie_t;
408 tie_t = (val << 28) >> 28;
409 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
410 }
411
412 static unsigned
413 Field_s_Slot_inst16b_get (const xtensa_insnbuf insn)
414 {
415 unsigned tie_t = 0;
416 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
417 return tie_t;
418 }
419
420 static void
421 Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
422 {
423 uint32 tie_t;
424 tie_t = (val << 28) >> 28;
425 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
426 }
427
428 static unsigned
429 Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn)
430 {
431 unsigned tie_t = 0;
432 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
433 tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
434 return tie_t;
435 }
436
437 static void
438 Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
439 {
440 uint32 tie_t;
441 tie_t = (val << 24) >> 24;
442 insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
443 tie_t = (val << 20) >> 28;
444 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
445 }
446
447 static unsigned
448 Field_imm16_Slot_inst_get (const xtensa_insnbuf insn)
449 {
450 unsigned tie_t = 0;
451 tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16);
452 return tie_t;
453 }
454
455 static void
456 Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
457 {
458 uint32 tie_t;
459 tie_t = (val << 16) >> 16;
460 insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8);
461 }
462
463 static unsigned
464 Field_m_Slot_inst_get (const xtensa_insnbuf insn)
465 {
466 unsigned tie_t = 0;
467 tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
468 return tie_t;
469 }
470
471 static void
472 Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
473 {
474 uint32 tie_t;
475 tie_t = (val << 30) >> 30;
476 insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
477 }
478
479 static unsigned
480 Field_n_Slot_inst_get (const xtensa_insnbuf insn)
481 {
482 unsigned tie_t = 0;
483 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
484 return tie_t;
485 }
486
487 static void
488 Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
489 {
490 uint32 tie_t;
491 tie_t = (val << 30) >> 30;
492 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
493 }
494
495 static unsigned
496 Field_offset_Slot_inst_get (const xtensa_insnbuf insn)
497 {
498 unsigned tie_t = 0;
499 tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
500 return tie_t;
501 }
502
503 static void
504 Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
505 {
506 uint32 tie_t;
507 tie_t = (val << 14) >> 14;
508 insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
509 }
510
511 static unsigned
512 Field_op0_Slot_inst_get (const xtensa_insnbuf insn)
513 {
514 unsigned tie_t = 0;
515 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
516 return tie_t;
517 }
518
519 static void
520 Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
521 {
522 uint32 tie_t;
523 tie_t = (val << 28) >> 28;
524 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
525 }
526
527 static unsigned
528 Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn)
529 {
530 unsigned tie_t = 0;
531 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
532 return tie_t;
533 }
534
535 static void
536 Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
537 {
538 uint32 tie_t;
539 tie_t = (val << 28) >> 28;
540 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
541 }
542
543 static unsigned
544 Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn)
545 {
546 unsigned tie_t = 0;
547 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
548 return tie_t;
549 }
550
551 static void
552 Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
553 {
554 uint32 tie_t;
555 tie_t = (val << 28) >> 28;
556 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
557 }
558
559 static unsigned
560 Field_op1_Slot_inst_get (const xtensa_insnbuf insn)
561 {
562 unsigned tie_t = 0;
563 tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
564 return tie_t;
565 }
566
567 static void
568 Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
569 {
570 uint32 tie_t;
571 tie_t = (val << 28) >> 28;
572 insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
573 }
574
575 static unsigned
576 Field_op2_Slot_inst_get (const xtensa_insnbuf insn)
577 {
578 unsigned tie_t = 0;
579 tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28);
580 return tie_t;
581 }
582
583 static void
584 Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
585 {
586 uint32 tie_t;
587 tie_t = (val << 28) >> 28;
588 insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20);
589 }
590
591 static unsigned
592 Field_r_Slot_inst_get (const xtensa_insnbuf insn)
593 {
594 unsigned tie_t = 0;
595 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
596 return tie_t;
597 }
598
599 static void
600 Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
601 {
602 uint32 tie_t;
603 tie_t = (val << 28) >> 28;
604 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
605 }
606
607 static unsigned
608 Field_r_Slot_inst16a_get (const xtensa_insnbuf insn)
609 {
610 unsigned tie_t = 0;
611 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
612 return tie_t;
613 }
614
615 static void
616 Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
617 {
618 uint32 tie_t;
619 tie_t = (val << 28) >> 28;
620 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
621 }
622
623 static unsigned
624 Field_r_Slot_inst16b_get (const xtensa_insnbuf insn)
625 {
626 unsigned tie_t = 0;
627 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
628 return tie_t;
629 }
630
631 static void
632 Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
633 {
634 uint32 tie_t;
635 tie_t = (val << 28) >> 28;
636 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
637 }
638
639 static unsigned
640 Field_sa4_Slot_inst_get (const xtensa_insnbuf insn)
641 {
642 unsigned tie_t = 0;
643 tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
644 return tie_t;
645 }
646
647 static void
648 Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
649 {
650 uint32 tie_t;
651 tie_t = (val << 31) >> 31;
652 insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
653 }
654
655 static unsigned
656 Field_sae4_Slot_inst_get (const xtensa_insnbuf insn)
657 {
658 unsigned tie_t = 0;
659 tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
660 return tie_t;
661 }
662
663 static void
664 Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
665 {
666 uint32 tie_t;
667 tie_t = (val << 31) >> 31;
668 insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
669 }
670
671 static unsigned
672 Field_sae_Slot_inst_get (const xtensa_insnbuf insn)
673 {
674 unsigned tie_t = 0;
675 tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
676 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
677 return tie_t;
678 }
679
680 static void
681 Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
682 {
683 uint32 tie_t;
684 tie_t = (val << 28) >> 28;
685 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
686 tie_t = (val << 27) >> 31;
687 insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
688 }
689
690 static unsigned
691 Field_sal_Slot_inst_get (const xtensa_insnbuf insn)
692 {
693 unsigned tie_t = 0;
694 tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
695 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
696 return tie_t;
697 }
698
699 static void
700 Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
701 {
702 uint32 tie_t;
703 tie_t = (val << 28) >> 28;
704 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
705 tie_t = (val << 27) >> 31;
706 insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
707 }
708
709 static unsigned
710 Field_sargt_Slot_inst_get (const xtensa_insnbuf insn)
711 {
712 unsigned tie_t = 0;
713 tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
714 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
715 return tie_t;
716 }
717
718 static void
719 Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
720 {
721 uint32 tie_t;
722 tie_t = (val << 28) >> 28;
723 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
724 tie_t = (val << 27) >> 31;
725 insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
726 }
727
728 static unsigned
729 Field_sas4_Slot_inst_get (const xtensa_insnbuf insn)
730 {
731 unsigned tie_t = 0;
732 tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
733 return tie_t;
734 }
735
736 static void
737 Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
738 {
739 uint32 tie_t;
740 tie_t = (val << 31) >> 31;
741 insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
742 }
743
744 static unsigned
745 Field_sas_Slot_inst_get (const xtensa_insnbuf insn)
746 {
747 unsigned tie_t = 0;
748 tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
749 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
750 return tie_t;
751 }
752
753 static void
754 Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
755 {
756 uint32 tie_t;
757 tie_t = (val << 28) >> 28;
758 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
759 tie_t = (val << 27) >> 31;
760 insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
761 }
762
763 static unsigned
764 Field_sr_Slot_inst_get (const xtensa_insnbuf insn)
765 {
766 unsigned tie_t = 0;
767 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
768 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
769 return tie_t;
770 }
771
772 static void
773 Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
774 {
775 uint32 tie_t;
776 tie_t = (val << 28) >> 28;
777 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
778 tie_t = (val << 24) >> 28;
779 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
780 }
781
782 static unsigned
783 Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn)
784 {
785 unsigned tie_t = 0;
786 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
787 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
788 return tie_t;
789 }
790
791 static void
792 Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
793 {
794 uint32 tie_t;
795 tie_t = (val << 28) >> 28;
796 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
797 tie_t = (val << 24) >> 28;
798 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
799 }
800
801 static unsigned
802 Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn)
803 {
804 unsigned tie_t = 0;
805 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
806 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
807 return tie_t;
808 }
809
810 static void
811 Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
812 {
813 uint32 tie_t;
814 tie_t = (val << 28) >> 28;
815 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
816 tie_t = (val << 24) >> 28;
817 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
818 }
819
820 static unsigned
821 Field_st_Slot_inst_get (const xtensa_insnbuf insn)
822 {
823 unsigned tie_t = 0;
824 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
825 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
826 return tie_t;
827 }
828
829 static void
830 Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
831 {
832 uint32 tie_t;
833 tie_t = (val << 28) >> 28;
834 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
835 tie_t = (val << 24) >> 28;
836 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
837 }
838
839 static unsigned
840 Field_st_Slot_inst16a_get (const xtensa_insnbuf insn)
841 {
842 unsigned tie_t = 0;
843 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
844 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
845 return tie_t;
846 }
847
848 static void
849 Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
850 {
851 uint32 tie_t;
852 tie_t = (val << 28) >> 28;
853 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
854 tie_t = (val << 24) >> 28;
855 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
856 }
857
858 static unsigned
859 Field_st_Slot_inst16b_get (const xtensa_insnbuf insn)
860 {
861 unsigned tie_t = 0;
862 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
863 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
864 return tie_t;
865 }
866
867 static void
868 Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
869 {
870 uint32 tie_t;
871 tie_t = (val << 28) >> 28;
872 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
873 tie_t = (val << 24) >> 28;
874 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
875 }
876
877 static unsigned
878 Field_thi3_Slot_inst_get (const xtensa_insnbuf insn)
879 {
880 unsigned tie_t = 0;
881 tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
882 return tie_t;
883 }
884
885 static void
886 Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
887 {
888 uint32 tie_t;
889 tie_t = (val << 29) >> 29;
890 insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
891 }
892
893 static unsigned
894 Field_imm4_Slot_inst_get (const xtensa_insnbuf insn)
895 {
896 unsigned tie_t = 0;
897 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
898 return tie_t;
899 }
900
901 static void
902 Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
903 {
904 uint32 tie_t;
905 tie_t = (val << 28) >> 28;
906 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
907 }
908
909 static unsigned
910 Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn)
911 {
912 unsigned tie_t = 0;
913 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
914 return tie_t;
915 }
916
917 static void
918 Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
919 {
920 uint32 tie_t;
921 tie_t = (val << 28) >> 28;
922 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
923 }
924
925 static unsigned
926 Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn)
927 {
928 unsigned tie_t = 0;
929 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
930 return tie_t;
931 }
932
933 static void
934 Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
935 {
936 uint32 tie_t;
937 tie_t = (val << 28) >> 28;
938 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
939 }
940
941 static unsigned
942 Field_mn_Slot_inst_get (const xtensa_insnbuf insn)
943 {
944 unsigned tie_t = 0;
945 tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
946 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
947 return tie_t;
948 }
949
950 static void
951 Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
952 {
953 uint32 tie_t;
954 tie_t = (val << 30) >> 30;
955 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
956 tie_t = (val << 28) >> 30;
957 insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
958 }
959
960 static unsigned
961 Field_i_Slot_inst16a_get (const xtensa_insnbuf insn)
962 {
963 unsigned tie_t = 0;
964 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
965 return tie_t;
966 }
967
968 static void
969 Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
970 {
971 uint32 tie_t;
972 tie_t = (val << 31) >> 31;
973 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
974 }
975
976 static unsigned
977 Field_i_Slot_inst16b_get (const xtensa_insnbuf insn)
978 {
979 unsigned tie_t = 0;
980 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
981 return tie_t;
982 }
983
984 static void
985 Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
986 {
987 uint32 tie_t;
988 tie_t = (val << 31) >> 31;
989 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
990 }
991
992 static unsigned
993 Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn)
994 {
995 unsigned tie_t = 0;
996 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
997 return tie_t;
998 }
999
1000 static void
1001 Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1002 {
1003 uint32 tie_t;
1004 tie_t = (val << 28) >> 28;
1005 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1006 }
1007
1008 static unsigned
1009 Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn)
1010 {
1011 unsigned tie_t = 0;
1012 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1013 return tie_t;
1014 }
1015
1016 static void
1017 Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1018 {
1019 uint32 tie_t;
1020 tie_t = (val << 28) >> 28;
1021 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1022 }
1023
1024 static unsigned
1025 Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn)
1026 {
1027 unsigned tie_t = 0;
1028 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1029 return tie_t;
1030 }
1031
1032 static void
1033 Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1034 {
1035 uint32 tie_t;
1036 tie_t = (val << 30) >> 30;
1037 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1038 }
1039
1040 static unsigned
1041 Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn)
1042 {
1043 unsigned tie_t = 0;
1044 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1045 return tie_t;
1046 }
1047
1048 static void
1049 Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1050 {
1051 uint32 tie_t;
1052 tie_t = (val << 30) >> 30;
1053 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1054 }
1055
1056 static unsigned
1057 Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn)
1058 {
1059 unsigned tie_t = 0;
1060 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1061 return tie_t;
1062 }
1063
1064 static void
1065 Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1066 {
1067 uint32 tie_t;
1068 tie_t = (val << 28) >> 28;
1069 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1070 }
1071
1072 static unsigned
1073 Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn)
1074 {
1075 unsigned tie_t = 0;
1076 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1077 return tie_t;
1078 }
1079
1080 static void
1081 Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1082 {
1083 uint32 tie_t;
1084 tie_t = (val << 28) >> 28;
1085 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1086 }
1087
1088 static unsigned
1089 Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn)
1090 {
1091 unsigned tie_t = 0;
1092 tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
1093 return tie_t;
1094 }
1095
1096 static void
1097 Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1098 {
1099 uint32 tie_t;
1100 tie_t = (val << 29) >> 29;
1101 insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
1102 }
1103
1104 static unsigned
1105 Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn)
1106 {
1107 unsigned tie_t = 0;
1108 tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
1109 return tie_t;
1110 }
1111
1112 static void
1113 Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1114 {
1115 uint32 tie_t;
1116 tie_t = (val << 29) >> 29;
1117 insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
1118 }
1119
1120 static unsigned
1121 Field_z_Slot_inst16a_get (const xtensa_insnbuf insn)
1122 {
1123 unsigned tie_t = 0;
1124 tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
1125 return tie_t;
1126 }
1127
1128 static void
1129 Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1130 {
1131 uint32 tie_t;
1132 tie_t = (val << 31) >> 31;
1133 insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
1134 }
1135
1136 static unsigned
1137 Field_z_Slot_inst16b_get (const xtensa_insnbuf insn)
1138 {
1139 unsigned tie_t = 0;
1140 tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
1141 return tie_t;
1142 }
1143
1144 static void
1145 Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1146 {
1147 uint32 tie_t;
1148 tie_t = (val << 31) >> 31;
1149 insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
1150 }
1151
1152 static unsigned
1153 Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn)
1154 {
1155 unsigned tie_t = 0;
1156 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1157 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1158 return tie_t;
1159 }
1160
1161 static void
1162 Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1163 {
1164 uint32 tie_t;
1165 tie_t = (val << 28) >> 28;
1166 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1167 tie_t = (val << 26) >> 30;
1168 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1169 }
1170
1171 static unsigned
1172 Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn)
1173 {
1174 unsigned tie_t = 0;
1175 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1176 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1177 return tie_t;
1178 }
1179
1180 static void
1181 Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1182 {
1183 uint32 tie_t;
1184 tie_t = (val << 28) >> 28;
1185 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1186 tie_t = (val << 26) >> 30;
1187 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1188 }
1189
1190 static unsigned
1191 Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn)
1192 {
1193 unsigned tie_t = 0;
1194 tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
1195 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1196 return tie_t;
1197 }
1198
1199 static void
1200 Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1201 {
1202 uint32 tie_t;
1203 tie_t = (val << 28) >> 28;
1204 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1205 tie_t = (val << 25) >> 29;
1206 insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
1207 }
1208
1209 static unsigned
1210 Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn)
1211 {
1212 unsigned tie_t = 0;
1213 tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
1214 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1215 return tie_t;
1216 }
1217
1218 static void
1219 Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1220 {
1221 uint32 tie_t;
1222 tie_t = (val << 28) >> 28;
1223 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1224 tie_t = (val << 25) >> 29;
1225 insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
1226 }
1227
1228 static unsigned
1229 Field_r3_Slot_inst_get (const xtensa_insnbuf insn)
1230 {
1231 unsigned tie_t = 0;
1232 tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
1233 return tie_t;
1234 }
1235
1236 static void
1237 Field_r3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1238 {
1239 uint32 tie_t;
1240 tie_t = (val << 31) >> 31;
1241 insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
1242 }
1243
1244 static unsigned
1245 Field_rbit2_Slot_inst_get (const xtensa_insnbuf insn)
1246 {
1247 unsigned tie_t = 0;
1248 tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
1249 return tie_t;
1250 }
1251
1252 static void
1253 Field_rbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1254 {
1255 uint32 tie_t;
1256 tie_t = (val << 31) >> 31;
1257 insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
1258 }
1259
1260 static unsigned
1261 Field_rhi_Slot_inst_get (const xtensa_insnbuf insn)
1262 {
1263 unsigned tie_t = 0;
1264 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
1265 return tie_t;
1266 }
1267
1268 static void
1269 Field_rhi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1270 {
1271 uint32 tie_t;
1272 tie_t = (val << 30) >> 30;
1273 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
1274 }
1275
1276 static unsigned
1277 Field_t3_Slot_inst_get (const xtensa_insnbuf insn)
1278 {
1279 unsigned tie_t = 0;
1280 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
1281 return tie_t;
1282 }
1283
1284 static void
1285 Field_t3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1286 {
1287 uint32 tie_t;
1288 tie_t = (val << 31) >> 31;
1289 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
1290 }
1291
1292 static unsigned
1293 Field_tbit2_Slot_inst_get (const xtensa_insnbuf insn)
1294 {
1295 unsigned tie_t = 0;
1296 tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
1297 return tie_t;
1298 }
1299
1300 static void
1301 Field_tbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1302 {
1303 uint32 tie_t;
1304 tie_t = (val << 31) >> 31;
1305 insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
1306 }
1307
1308 static unsigned
1309 Field_tlo_Slot_inst_get (const xtensa_insnbuf insn)
1310 {
1311 unsigned tie_t = 0;
1312 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1313 return tie_t;
1314 }
1315
1316 static void
1317 Field_tlo_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1318 {
1319 uint32 tie_t;
1320 tie_t = (val << 30) >> 30;
1321 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1322 }
1323
1324 static unsigned
1325 Field_w_Slot_inst_get (const xtensa_insnbuf insn)
1326 {
1327 unsigned tie_t = 0;
1328 tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30);
1329 return tie_t;
1330 }
1331
1332 static void
1333 Field_w_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1334 {
1335 uint32 tie_t;
1336 tie_t = (val << 30) >> 30;
1337 insn[0] = (insn[0] & ~0x3000) | (tie_t << 12);
1338 }
1339
1340 static unsigned
1341 Field_y_Slot_inst_get (const xtensa_insnbuf insn)
1342 {
1343 unsigned tie_t = 0;
1344 tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
1345 return tie_t;
1346 }
1347
1348 static void
1349 Field_y_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1350 {
1351 uint32 tie_t;
1352 tie_t = (val << 31) >> 31;
1353 insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
1354 }
1355
1356 static unsigned
1357 Field_x_Slot_inst_get (const xtensa_insnbuf insn)
1358 {
1359 unsigned tie_t = 0;
1360 tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
1361 return tie_t;
1362 }
1363
1364 static void
1365 Field_x_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1366 {
1367 uint32 tie_t;
1368 tie_t = (val << 31) >> 31;
1369 insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
1370 }
1371
1372 static unsigned
1373 Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn)
1374 {
1375 unsigned tie_t = 0;
1376 tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17);
1377 return tie_t;
1378 }
1379
1380 static void
1381 Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1382 {
1383 uint32 tie_t;
1384 tie_t = (val << 17) >> 17;
1385 insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9);
1386 }
1387
1388 static unsigned
1389 Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn)
1390 {
1391 unsigned tie_t = 0;
1392 tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
1393 return tie_t;
1394 }
1395
1396 static void
1397 Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1398 {
1399 uint32 tie_t;
1400 tie_t = (val << 14) >> 14;
1401 insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
1402 }
1403
1404 static unsigned
1405 Field_bitindex_Slot_inst_get (const xtensa_insnbuf insn)
1406 {
1407 unsigned tie_t = 0;
1408 tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
1409 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1410 return tie_t;
1411 }
1412
1413 static void
1414 Field_bitindex_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1415 {
1416 uint32 tie_t;
1417 tie_t = (val << 28) >> 28;
1418 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1419 tie_t = (val << 27) >> 31;
1420 insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
1421 }
1422
1423 static unsigned
1424 Field_bitindex_Slot_inst16a_get (const xtensa_insnbuf insn)
1425 {
1426 unsigned tie_t = 0;
1427 tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
1428 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1429 return tie_t;
1430 }
1431
1432 static void
1433 Field_bitindex_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1434 {
1435 uint32 tie_t;
1436 tie_t = (val << 28) >> 28;
1437 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1438 tie_t = (val << 27) >> 31;
1439 insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
1440 }
1441
1442 static unsigned
1443 Field_bitindex_Slot_inst16b_get (const xtensa_insnbuf insn)
1444 {
1445 unsigned tie_t = 0;
1446 tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
1447 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1448 return tie_t;
1449 }
1450
1451 static void
1452 Field_bitindex_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1453 {
1454 uint32 tie_t;
1455 tie_t = (val << 28) >> 28;
1456 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1457 tie_t = (val << 27) >> 31;
1458 insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
1459 }
1460
1461 static unsigned
1462 Field_s3to1_Slot_inst_get (const xtensa_insnbuf insn)
1463 {
1464 unsigned tie_t = 0;
1465 tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
1466 return tie_t;
1467 }
1468
1469 static void
1470 Field_s3to1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1471 {
1472 uint32 tie_t;
1473 tie_t = (val << 29) >> 29;
1474 insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
1475 }
1476
1477 static unsigned
1478 Field_s3to1_Slot_inst16a_get (const xtensa_insnbuf insn)
1479 {
1480 unsigned tie_t = 0;
1481 tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
1482 return tie_t;
1483 }
1484
1485 static void
1486 Field_s3to1_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1487 {
1488 uint32 tie_t;
1489 tie_t = (val << 29) >> 29;
1490 insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
1491 }
1492
1493 static unsigned
1494 Field_s3to1_Slot_inst16b_get (const xtensa_insnbuf insn)
1495 {
1496 unsigned tie_t = 0;
1497 tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
1498 return tie_t;
1499 }
1500
1501 static void
1502 Field_s3to1_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1503 {
1504 uint32 tie_t;
1505 tie_t = (val << 29) >> 29;
1506 insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
1507 }
1508
1509 static void
1510 Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED,
1511 uint32 val ATTRIBUTE_UNUSED)
1512 {
1513 /* Do nothing. */
1514 }
1515
1516 static unsigned
1517 Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1518 {
1519 return 0;
1520 }
1521
1522 static unsigned
1523 Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1524 {
1525 return 4;
1526 }
1527
1528 static unsigned
1529 Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1530 {
1531 return 8;
1532 }
1533
1534 static unsigned
1535 Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1536 {
1537 return 12;
1538 }
1539
1540 static unsigned
1541 Implicit_Field_mr0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1542 {
1543 return 0;
1544 }
1545
1546 static unsigned
1547 Implicit_Field_mr1_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1548 {
1549 return 1;
1550 }
1551
1552 static unsigned
1553 Implicit_Field_mr2_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1554 {
1555 return 2;
1556 }
1557
1558 static unsigned
1559 Implicit_Field_mr3_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1560 {
1561 return 3;
1562 }
1563
1564
1565 /* Functional units. */
1566
1567 static xtensa_funcUnit_internal funcUnits[] = {
1568
1569 };
1570
1571
1572 /* Register files. */
1573
1574 static xtensa_regfile_internal regfiles[] = {
1575 { "AR", "a", 0, 32, 32 },
1576 { "MR", "m", 1, 32, 4 }
1577 };
1578
1579
1580 /* Interfaces. */
1581
1582 static xtensa_interface_internal interfaces[] = {
1583 { "IMPWIRE", 32, 0, 0, 'i' }
1584 };
1585
1586
1587 /* Constant tables. */
1588
1589 /* constant table ai4c */
1590 static const unsigned CONST_TBL_ai4c_0[] = {
1591 0xffffffff,
1592 0x1,
1593 0x2,
1594 0x3,
1595 0x4,
1596 0x5,
1597 0x6,
1598 0x7,
1599 0x8,
1600 0x9,
1601 0xa,
1602 0xb,
1603 0xc,
1604 0xd,
1605 0xe,
1606 0xf,
1607 0
1608 };
1609
1610 /* constant table b4c */
1611 static const unsigned CONST_TBL_b4c_0[] = {
1612 0xffffffff,
1613 0x1,
1614 0x2,
1615 0x3,
1616 0x4,
1617 0x5,
1618 0x6,
1619 0x7,
1620 0x8,
1621 0xa,
1622 0xc,
1623 0x10,
1624 0x20,
1625 0x40,
1626 0x80,
1627 0x100,
1628 0
1629 };
1630
1631 /* constant table b4cu */
1632 static const unsigned CONST_TBL_b4cu_0[] = {
1633 0x8000,
1634 0x10000,
1635 0x2,
1636 0x3,
1637 0x4,
1638 0x5,
1639 0x6,
1640 0x7,
1641 0x8,
1642 0xa,
1643 0xc,
1644 0x10,
1645 0x20,
1646 0x40,
1647 0x80,
1648 0x100,
1649 0
1650 };
1651
1652
1653 /* Instruction operands. */
1654
1655 static int
1656 Operand_soffsetx4_decode (uint32 *valp)
1657 {
1658 unsigned soffsetx4_0, offset_0;
1659 offset_0 = *valp & 0x3ffff;
1660 soffsetx4_0 = 0x4 + ((((int) offset_0 << 14) >> 14) << 2);
1661 *valp = soffsetx4_0;
1662 return 0;
1663 }
1664
1665 static int
1666 Operand_soffsetx4_encode (uint32 *valp)
1667 {
1668 unsigned offset_0, soffsetx4_0;
1669 soffsetx4_0 = *valp;
1670 offset_0 = ((soffsetx4_0 - 0x4) >> 2) & 0x3ffff;
1671 *valp = offset_0;
1672 return 0;
1673 }
1674
1675 static int
1676 Operand_soffsetx4_ator (uint32 *valp, uint32 pc)
1677 {
1678 *valp -= (pc & ~0x3);
1679 return 0;
1680 }
1681
1682 static int
1683 Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc)
1684 {
1685 *valp += (pc & ~0x3);
1686 return 0;
1687 }
1688
1689 static int
1690 Operand_uimm12x8_decode (uint32 *valp)
1691 {
1692 unsigned uimm12x8_0, imm12_0;
1693 imm12_0 = *valp & 0xfff;
1694 uimm12x8_0 = imm12_0 << 3;
1695 *valp = uimm12x8_0;
1696 return 0;
1697 }
1698
1699 static int
1700 Operand_uimm12x8_encode (uint32 *valp)
1701 {
1702 unsigned imm12_0, uimm12x8_0;
1703 uimm12x8_0 = *valp;
1704 imm12_0 = ((uimm12x8_0 >> 3) & 0xfff);
1705 *valp = imm12_0;
1706 return 0;
1707 }
1708
1709 static int
1710 Operand_simm4_decode (uint32 *valp)
1711 {
1712 unsigned simm4_0, mn_0;
1713 mn_0 = *valp & 0xf;
1714 simm4_0 = ((int) mn_0 << 28) >> 28;
1715 *valp = simm4_0;
1716 return 0;
1717 }
1718
1719 static int
1720 Operand_simm4_encode (uint32 *valp)
1721 {
1722 unsigned mn_0, simm4_0;
1723 simm4_0 = *valp;
1724 mn_0 = (simm4_0 & 0xf);
1725 *valp = mn_0;
1726 return 0;
1727 }
1728
1729 static int
1730 Operand_arr_decode (uint32 *valp ATTRIBUTE_UNUSED)
1731 {
1732 return 0;
1733 }
1734
1735 static int
1736 Operand_arr_encode (uint32 *valp)
1737 {
1738 return (*valp & ~0xf) != 0;
1739 }
1740
1741 static int
1742 Operand_ars_decode (uint32 *valp ATTRIBUTE_UNUSED)
1743 {
1744 return 0;
1745 }
1746
1747 static int
1748 Operand_ars_encode (uint32 *valp)
1749 {
1750 return (*valp & ~0xf) != 0;
1751 }
1752
1753 static int
1754 Operand_art_decode (uint32 *valp ATTRIBUTE_UNUSED)
1755 {
1756 return 0;
1757 }
1758
1759 static int
1760 Operand_art_encode (uint32 *valp)
1761 {
1762 return (*valp & ~0xf) != 0;
1763 }
1764
1765 static int
1766 Operand_ar0_decode (uint32 *valp ATTRIBUTE_UNUSED)
1767 {
1768 return 0;
1769 }
1770
1771 static int
1772 Operand_ar0_encode (uint32 *valp)
1773 {
1774 return (*valp & ~0x1f) != 0;
1775 }
1776
1777 static int
1778 Operand_ar4_decode (uint32 *valp ATTRIBUTE_UNUSED)
1779 {
1780 return 0;
1781 }
1782
1783 static int
1784 Operand_ar4_encode (uint32 *valp)
1785 {
1786 return (*valp & ~0x1f) != 0;
1787 }
1788
1789 static int
1790 Operand_ar8_decode (uint32 *valp ATTRIBUTE_UNUSED)
1791 {
1792 return 0;
1793 }
1794
1795 static int
1796 Operand_ar8_encode (uint32 *valp)
1797 {
1798 return (*valp & ~0x1f) != 0;
1799 }
1800
1801 static int
1802 Operand_ar12_decode (uint32 *valp ATTRIBUTE_UNUSED)
1803 {
1804 return 0;
1805 }
1806
1807 static int
1808 Operand_ar12_encode (uint32 *valp)
1809 {
1810 return (*valp & ~0x1f) != 0;
1811 }
1812
1813 static int
1814 Operand_ars_entry_decode (uint32 *valp ATTRIBUTE_UNUSED)
1815 {
1816 return 0;
1817 }
1818
1819 static int
1820 Operand_ars_entry_encode (uint32 *valp)
1821 {
1822 return (*valp & ~0x1f) != 0;
1823 }
1824
1825 static int
1826 Operand_immrx4_decode (uint32 *valp)
1827 {
1828 unsigned immrx4_0, r_0;
1829 r_0 = *valp & 0xf;
1830 immrx4_0 = (((0xfffffff) << 4) | r_0) << 2;
1831 *valp = immrx4_0;
1832 return 0;
1833 }
1834
1835 static int
1836 Operand_immrx4_encode (uint32 *valp)
1837 {
1838 unsigned r_0, immrx4_0;
1839 immrx4_0 = *valp;
1840 r_0 = ((immrx4_0 >> 2) & 0xf);
1841 *valp = r_0;
1842 return 0;
1843 }
1844
1845 static int
1846 Operand_lsi4x4_decode (uint32 *valp)
1847 {
1848 unsigned lsi4x4_0, r_0;
1849 r_0 = *valp & 0xf;
1850 lsi4x4_0 = r_0 << 2;
1851 *valp = lsi4x4_0;
1852 return 0;
1853 }
1854
1855 static int
1856 Operand_lsi4x4_encode (uint32 *valp)
1857 {
1858 unsigned r_0, lsi4x4_0;
1859 lsi4x4_0 = *valp;
1860 r_0 = ((lsi4x4_0 >> 2) & 0xf);
1861 *valp = r_0;
1862 return 0;
1863 }
1864
1865 static int
1866 Operand_simm7_decode (uint32 *valp)
1867 {
1868 unsigned simm7_0, imm7_0;
1869 imm7_0 = *valp & 0x7f;
1870 simm7_0 = ((((-((((imm7_0 >> 6) & 1)) & (((imm7_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | imm7_0;
1871 *valp = simm7_0;
1872 return 0;
1873 }
1874
1875 static int
1876 Operand_simm7_encode (uint32 *valp)
1877 {
1878 unsigned imm7_0, simm7_0;
1879 simm7_0 = *valp;
1880 imm7_0 = (simm7_0 & 0x7f);
1881 *valp = imm7_0;
1882 return 0;
1883 }
1884
1885 static int
1886 Operand_uimm6_decode (uint32 *valp)
1887 {
1888 unsigned uimm6_0, imm6_0;
1889 imm6_0 = *valp & 0x3f;
1890 uimm6_0 = 0x4 + (((0) << 6) | imm6_0);
1891 *valp = uimm6_0;
1892 return 0;
1893 }
1894
1895 static int
1896 Operand_uimm6_encode (uint32 *valp)
1897 {
1898 unsigned imm6_0, uimm6_0;
1899 uimm6_0 = *valp;
1900 imm6_0 = (uimm6_0 - 0x4) & 0x3f;
1901 *valp = imm6_0;
1902 return 0;
1903 }
1904
1905 static int
1906 Operand_uimm6_ator (uint32 *valp, uint32 pc)
1907 {
1908 *valp -= pc;
1909 return 0;
1910 }
1911
1912 static int
1913 Operand_uimm6_rtoa (uint32 *valp, uint32 pc)
1914 {
1915 *valp += pc;
1916 return 0;
1917 }
1918
1919 static int
1920 Operand_ai4const_decode (uint32 *valp)
1921 {
1922 unsigned ai4const_0, t_0;
1923 t_0 = *valp & 0xf;
1924 ai4const_0 = CONST_TBL_ai4c_0[t_0 & 0xf];
1925 *valp = ai4const_0;
1926 return 0;
1927 }
1928
1929 static int
1930 Operand_ai4const_encode (uint32 *valp)
1931 {
1932 unsigned t_0, ai4const_0;
1933 ai4const_0 = *valp;
1934 switch (ai4const_0)
1935 {
1936 case 0xffffffff: t_0 = 0; break;
1937 case 0x1: t_0 = 0x1; break;
1938 case 0x2: t_0 = 0x2; break;
1939 case 0x3: t_0 = 0x3; break;
1940 case 0x4: t_0 = 0x4; break;
1941 case 0x5: t_0 = 0x5; break;
1942 case 0x6: t_0 = 0x6; break;
1943 case 0x7: t_0 = 0x7; break;
1944 case 0x8: t_0 = 0x8; break;
1945 case 0x9: t_0 = 0x9; break;
1946 case 0xa: t_0 = 0xa; break;
1947 case 0xb: t_0 = 0xb; break;
1948 case 0xc: t_0 = 0xc; break;
1949 case 0xd: t_0 = 0xd; break;
1950 case 0xe: t_0 = 0xe; break;
1951 default: t_0 = 0xf; break;
1952 }
1953 *valp = t_0;
1954 return 0;
1955 }
1956
1957 static int
1958 Operand_b4const_decode (uint32 *valp)
1959 {
1960 unsigned b4const_0, r_0;
1961 r_0 = *valp & 0xf;
1962 b4const_0 = CONST_TBL_b4c_0[r_0 & 0xf];
1963 *valp = b4const_0;
1964 return 0;
1965 }
1966
1967 static int
1968 Operand_b4const_encode (uint32 *valp)
1969 {
1970 unsigned r_0, b4const_0;
1971 b4const_0 = *valp;
1972 switch (b4const_0)
1973 {
1974 case 0xffffffff: r_0 = 0; break;
1975 case 0x1: r_0 = 0x1; break;
1976 case 0x2: r_0 = 0x2; break;
1977 case 0x3: r_0 = 0x3; break;
1978 case 0x4: r_0 = 0x4; break;
1979 case 0x5: r_0 = 0x5; break;
1980 case 0x6: r_0 = 0x6; break;
1981 case 0x7: r_0 = 0x7; break;
1982 case 0x8: r_0 = 0x8; break;
1983 case 0xa: r_0 = 0x9; break;
1984 case 0xc: r_0 = 0xa; break;
1985 case 0x10: r_0 = 0xb; break;
1986 case 0x20: r_0 = 0xc; break;
1987 case 0x40: r_0 = 0xd; break;
1988 case 0x80: r_0 = 0xe; break;
1989 default: r_0 = 0xf; break;
1990 }
1991 *valp = r_0;
1992 return 0;
1993 }
1994
1995 static int
1996 Operand_b4constu_decode (uint32 *valp)
1997 {
1998 unsigned b4constu_0, r_0;
1999 r_0 = *valp & 0xf;
2000 b4constu_0 = CONST_TBL_b4cu_0[r_0 & 0xf];
2001 *valp = b4constu_0;
2002 return 0;
2003 }
2004
2005 static int
2006 Operand_b4constu_encode (uint32 *valp)
2007 {
2008 unsigned r_0, b4constu_0;
2009 b4constu_0 = *valp;
2010 switch (b4constu_0)
2011 {
2012 case 0x8000: r_0 = 0; break;
2013 case 0x10000: r_0 = 0x1; break;
2014 case 0x2: r_0 = 0x2; break;
2015 case 0x3: r_0 = 0x3; break;
2016 case 0x4: r_0 = 0x4; break;
2017 case 0x5: r_0 = 0x5; break;
2018 case 0x6: r_0 = 0x6; break;
2019 case 0x7: r_0 = 0x7; break;
2020 case 0x8: r_0 = 0x8; break;
2021 case 0xa: r_0 = 0x9; break;
2022 case 0xc: r_0 = 0xa; break;
2023 case 0x10: r_0 = 0xb; break;
2024 case 0x20: r_0 = 0xc; break;
2025 case 0x40: r_0 = 0xd; break;
2026 case 0x80: r_0 = 0xe; break;
2027 default: r_0 = 0xf; break;
2028 }
2029 *valp = r_0;
2030 return 0;
2031 }
2032
2033 static int
2034 Operand_uimm8_decode (uint32 *valp)
2035 {
2036 unsigned uimm8_0, imm8_0;
2037 imm8_0 = *valp & 0xff;
2038 uimm8_0 = imm8_0;
2039 *valp = uimm8_0;
2040 return 0;
2041 }
2042
2043 static int
2044 Operand_uimm8_encode (uint32 *valp)
2045 {
2046 unsigned imm8_0, uimm8_0;
2047 uimm8_0 = *valp;
2048 imm8_0 = (uimm8_0 & 0xff);
2049 *valp = imm8_0;
2050 return 0;
2051 }
2052
2053 static int
2054 Operand_uimm8x2_decode (uint32 *valp)
2055 {
2056 unsigned uimm8x2_0, imm8_0;
2057 imm8_0 = *valp & 0xff;
2058 uimm8x2_0 = imm8_0 << 1;
2059 *valp = uimm8x2_0;
2060 return 0;
2061 }
2062
2063 static int
2064 Operand_uimm8x2_encode (uint32 *valp)
2065 {
2066 unsigned imm8_0, uimm8x2_0;
2067 uimm8x2_0 = *valp;
2068 imm8_0 = ((uimm8x2_0 >> 1) & 0xff);
2069 *valp = imm8_0;
2070 return 0;
2071 }
2072
2073 static int
2074 Operand_uimm8x4_decode (uint32 *valp)
2075 {
2076 unsigned uimm8x4_0, imm8_0;
2077 imm8_0 = *valp & 0xff;
2078 uimm8x4_0 = imm8_0 << 2;
2079 *valp = uimm8x4_0;
2080 return 0;
2081 }
2082
2083 static int
2084 Operand_uimm8x4_encode (uint32 *valp)
2085 {
2086 unsigned imm8_0, uimm8x4_0;
2087 uimm8x4_0 = *valp;
2088 imm8_0 = ((uimm8x4_0 >> 2) & 0xff);
2089 *valp = imm8_0;
2090 return 0;
2091 }
2092
2093 static int
2094 Operand_uimm4x16_decode (uint32 *valp)
2095 {
2096 unsigned uimm4x16_0, op2_0;
2097 op2_0 = *valp & 0xf;
2098 uimm4x16_0 = op2_0 << 4;
2099 *valp = uimm4x16_0;
2100 return 0;
2101 }
2102
2103 static int
2104 Operand_uimm4x16_encode (uint32 *valp)
2105 {
2106 unsigned op2_0, uimm4x16_0;
2107 uimm4x16_0 = *valp;
2108 op2_0 = ((uimm4x16_0 >> 4) & 0xf);
2109 *valp = op2_0;
2110 return 0;
2111 }
2112
2113 static int
2114 Operand_simm8_decode (uint32 *valp)
2115 {
2116 unsigned simm8_0, imm8_0;
2117 imm8_0 = *valp & 0xff;
2118 simm8_0 = ((int) imm8_0 << 24) >> 24;
2119 *valp = simm8_0;
2120 return 0;
2121 }
2122
2123 static int
2124 Operand_simm8_encode (uint32 *valp)
2125 {
2126 unsigned imm8_0, simm8_0;
2127 simm8_0 = *valp;
2128 imm8_0 = (simm8_0 & 0xff);
2129 *valp = imm8_0;
2130 return 0;
2131 }
2132
2133 static int
2134 Operand_simm8x256_decode (uint32 *valp)
2135 {
2136 unsigned simm8x256_0, imm8_0;
2137 imm8_0 = *valp & 0xff;
2138 simm8x256_0 = (((int) imm8_0 << 24) >> 24) << 8;
2139 *valp = simm8x256_0;
2140 return 0;
2141 }
2142
2143 static int
2144 Operand_simm8x256_encode (uint32 *valp)
2145 {
2146 unsigned imm8_0, simm8x256_0;
2147 simm8x256_0 = *valp;
2148 imm8_0 = ((simm8x256_0 >> 8) & 0xff);
2149 *valp = imm8_0;
2150 return 0;
2151 }
2152
2153 static int
2154 Operand_simm12b_decode (uint32 *valp)
2155 {
2156 unsigned simm12b_0, imm12b_0;
2157 imm12b_0 = *valp & 0xfff;
2158 simm12b_0 = ((int) imm12b_0 << 20) >> 20;
2159 *valp = simm12b_0;
2160 return 0;
2161 }
2162
2163 static int
2164 Operand_simm12b_encode (uint32 *valp)
2165 {
2166 unsigned imm12b_0, simm12b_0;
2167 simm12b_0 = *valp;
2168 imm12b_0 = (simm12b_0 & 0xfff);
2169 *valp = imm12b_0;
2170 return 0;
2171 }
2172
2173 static int
2174 Operand_msalp32_decode (uint32 *valp)
2175 {
2176 unsigned msalp32_0, sal_0;
2177 sal_0 = *valp & 0x1f;
2178 msalp32_0 = 0x20 - sal_0;
2179 *valp = msalp32_0;
2180 return 0;
2181 }
2182
2183 static int
2184 Operand_msalp32_encode (uint32 *valp)
2185 {
2186 unsigned sal_0, msalp32_0;
2187 msalp32_0 = *valp;
2188 sal_0 = (0x20 - msalp32_0) & 0x1f;
2189 *valp = sal_0;
2190 return 0;
2191 }
2192
2193 static int
2194 Operand_op2p1_decode (uint32 *valp)
2195 {
2196 unsigned op2p1_0, op2_0;
2197 op2_0 = *valp & 0xf;
2198 op2p1_0 = op2_0 + 0x1;
2199 *valp = op2p1_0;
2200 return 0;
2201 }
2202
2203 static int
2204 Operand_op2p1_encode (uint32 *valp)
2205 {
2206 unsigned op2_0, op2p1_0;
2207 op2p1_0 = *valp;
2208 op2_0 = (op2p1_0 - 0x1) & 0xf;
2209 *valp = op2_0;
2210 return 0;
2211 }
2212
2213 static int
2214 Operand_label8_decode (uint32 *valp)
2215 {
2216 unsigned label8_0, imm8_0;
2217 imm8_0 = *valp & 0xff;
2218 label8_0 = 0x4 + (((int) imm8_0 << 24) >> 24);
2219 *valp = label8_0;
2220 return 0;
2221 }
2222
2223 static int
2224 Operand_label8_encode (uint32 *valp)
2225 {
2226 unsigned imm8_0, label8_0;
2227 label8_0 = *valp;
2228 imm8_0 = (label8_0 - 0x4) & 0xff;
2229 *valp = imm8_0;
2230 return 0;
2231 }
2232
2233 static int
2234 Operand_label8_ator (uint32 *valp, uint32 pc)
2235 {
2236 *valp -= pc;
2237 return 0;
2238 }
2239
2240 static int
2241 Operand_label8_rtoa (uint32 *valp, uint32 pc)
2242 {
2243 *valp += pc;
2244 return 0;
2245 }
2246
2247 static int
2248 Operand_ulabel8_decode (uint32 *valp)
2249 {
2250 unsigned ulabel8_0, imm8_0;
2251 imm8_0 = *valp & 0xff;
2252 ulabel8_0 = 0x4 + (((0) << 8) | imm8_0);
2253 *valp = ulabel8_0;
2254 return 0;
2255 }
2256
2257 static int
2258 Operand_ulabel8_encode (uint32 *valp)
2259 {
2260 unsigned imm8_0, ulabel8_0;
2261 ulabel8_0 = *valp;
2262 imm8_0 = (ulabel8_0 - 0x4) & 0xff;
2263 *valp = imm8_0;
2264 return 0;
2265 }
2266
2267 static int
2268 Operand_ulabel8_ator (uint32 *valp, uint32 pc)
2269 {
2270 *valp -= pc;
2271 return 0;
2272 }
2273
2274 static int
2275 Operand_ulabel8_rtoa (uint32 *valp, uint32 pc)
2276 {
2277 *valp += pc;
2278 return 0;
2279 }
2280
2281 static int
2282 Operand_label12_decode (uint32 *valp)
2283 {
2284 unsigned label12_0, imm12_0;
2285 imm12_0 = *valp & 0xfff;
2286 label12_0 = 0x4 + (((int) imm12_0 << 20) >> 20);
2287 *valp = label12_0;
2288 return 0;
2289 }
2290
2291 static int
2292 Operand_label12_encode (uint32 *valp)
2293 {
2294 unsigned imm12_0, label12_0;
2295 label12_0 = *valp;
2296 imm12_0 = (label12_0 - 0x4) & 0xfff;
2297 *valp = imm12_0;
2298 return 0;
2299 }
2300
2301 static int
2302 Operand_label12_ator (uint32 *valp, uint32 pc)
2303 {
2304 *valp -= pc;
2305 return 0;
2306 }
2307
2308 static int
2309 Operand_label12_rtoa (uint32 *valp, uint32 pc)
2310 {
2311 *valp += pc;
2312 return 0;
2313 }
2314
2315 static int
2316 Operand_soffset_decode (uint32 *valp)
2317 {
2318 unsigned soffset_0, offset_0;
2319 offset_0 = *valp & 0x3ffff;
2320 soffset_0 = 0x4 + (((int) offset_0 << 14) >> 14);
2321 *valp = soffset_0;
2322 return 0;
2323 }
2324
2325 static int
2326 Operand_soffset_encode (uint32 *valp)
2327 {
2328 unsigned offset_0, soffset_0;
2329 soffset_0 = *valp;
2330 offset_0 = (soffset_0 - 0x4) & 0x3ffff;
2331 *valp = offset_0;
2332 return 0;
2333 }
2334
2335 static int
2336 Operand_soffset_ator (uint32 *valp, uint32 pc)
2337 {
2338 *valp -= pc;
2339 return 0;
2340 }
2341
2342 static int
2343 Operand_soffset_rtoa (uint32 *valp, uint32 pc)
2344 {
2345 *valp += pc;
2346 return 0;
2347 }
2348
2349 static int
2350 Operand_uimm16x4_decode (uint32 *valp)
2351 {
2352 unsigned uimm16x4_0, imm16_0;
2353 imm16_0 = *valp & 0xffff;
2354 uimm16x4_0 = (((0xffff) << 16) | imm16_0) << 2;
2355 *valp = uimm16x4_0;
2356 return 0;
2357 }
2358
2359 static int
2360 Operand_uimm16x4_encode (uint32 *valp)
2361 {
2362 unsigned imm16_0, uimm16x4_0;
2363 uimm16x4_0 = *valp;
2364 imm16_0 = (uimm16x4_0 >> 2) & 0xffff;
2365 *valp = imm16_0;
2366 return 0;
2367 }
2368
2369 static int
2370 Operand_uimm16x4_ator (uint32 *valp, uint32 pc)
2371 {
2372 *valp -= ((pc + 3) & ~0x3);
2373 return 0;
2374 }
2375
2376 static int
2377 Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc)
2378 {
2379 *valp += ((pc + 3) & ~0x3);
2380 return 0;
2381 }
2382
2383 static int
2384 Operand_mx_decode (uint32 *valp ATTRIBUTE_UNUSED)
2385 {
2386 return 0;
2387 }
2388
2389 static int
2390 Operand_mx_encode (uint32 *valp)
2391 {
2392 return (*valp & ~0x3) != 0;
2393 }
2394
2395 static int
2396 Operand_my_decode (uint32 *valp)
2397 {
2398 *valp += 2;
2399 return 0;
2400 }
2401
2402 static int
2403 Operand_my_encode (uint32 *valp)
2404 {
2405 int error;
2406 error = ((*valp & ~0x3) != 0) || ((*valp & 0x2) == 0);
2407 *valp = *valp & 1;
2408 return error;
2409 }
2410
2411 static int
2412 Operand_mw_decode (uint32 *valp ATTRIBUTE_UNUSED)
2413 {
2414 return 0;
2415 }
2416
2417 static int
2418 Operand_mw_encode (uint32 *valp)
2419 {
2420 return (*valp & ~0x3) != 0;
2421 }
2422
2423 static int
2424 Operand_mr0_decode (uint32 *valp ATTRIBUTE_UNUSED)
2425 {
2426 return 0;
2427 }
2428
2429 static int
2430 Operand_mr0_encode (uint32 *valp)
2431 {
2432 return (*valp & ~0x3) != 0;
2433 }
2434
2435 static int
2436 Operand_mr1_decode (uint32 *valp ATTRIBUTE_UNUSED)
2437 {
2438 return 0;
2439 }
2440
2441 static int
2442 Operand_mr1_encode (uint32 *valp)
2443 {
2444 return (*valp & ~0x3) != 0;
2445 }
2446
2447 static int
2448 Operand_mr2_decode (uint32 *valp ATTRIBUTE_UNUSED)
2449 {
2450 return 0;
2451 }
2452
2453 static int
2454 Operand_mr2_encode (uint32 *valp)
2455 {
2456 return (*valp & ~0x3) != 0;
2457 }
2458
2459 static int
2460 Operand_mr3_decode (uint32 *valp ATTRIBUTE_UNUSED)
2461 {
2462 return 0;
2463 }
2464
2465 static int
2466 Operand_mr3_encode (uint32 *valp)
2467 {
2468 return (*valp & ~0x3) != 0;
2469 }
2470
2471 static int
2472 Operand_immt_decode (uint32 *valp)
2473 {
2474 unsigned immt_0, t_0;
2475 t_0 = *valp & 0xf;
2476 immt_0 = t_0;
2477 *valp = immt_0;
2478 return 0;
2479 }
2480
2481 static int
2482 Operand_immt_encode (uint32 *valp)
2483 {
2484 unsigned t_0, immt_0;
2485 immt_0 = *valp;
2486 t_0 = immt_0 & 0xf;
2487 *valp = t_0;
2488 return 0;
2489 }
2490
2491 static int
2492 Operand_imms_decode (uint32 *valp)
2493 {
2494 unsigned imms_0, s_0;
2495 s_0 = *valp & 0xf;
2496 imms_0 = s_0;
2497 *valp = imms_0;
2498 return 0;
2499 }
2500
2501 static int
2502 Operand_imms_encode (uint32 *valp)
2503 {
2504 unsigned s_0, imms_0;
2505 imms_0 = *valp;
2506 s_0 = imms_0 & 0xf;
2507 *valp = s_0;
2508 return 0;
2509 }
2510
2511 static int
2512 Operand_tp7_decode (uint32 *valp)
2513 {
2514 unsigned tp7_0, t_0;
2515 t_0 = *valp & 0xf;
2516 tp7_0 = t_0 + 0x7;
2517 *valp = tp7_0;
2518 return 0;
2519 }
2520
2521 static int
2522 Operand_tp7_encode (uint32 *valp)
2523 {
2524 unsigned t_0, tp7_0;
2525 tp7_0 = *valp;
2526 t_0 = (tp7_0 - 0x7) & 0xf;
2527 *valp = t_0;
2528 return 0;
2529 }
2530
2531 static int
2532 Operand_xt_wbr15_label_decode (uint32 *valp)
2533 {
2534 unsigned xt_wbr15_label_0, xt_wbr15_imm_0;
2535 xt_wbr15_imm_0 = *valp & 0x7fff;
2536 xt_wbr15_label_0 = 0x4 + (((int) xt_wbr15_imm_0 << 17) >> 17);
2537 *valp = xt_wbr15_label_0;
2538 return 0;
2539 }
2540
2541 static int
2542 Operand_xt_wbr15_label_encode (uint32 *valp)
2543 {
2544 unsigned xt_wbr15_imm_0, xt_wbr15_label_0;
2545 xt_wbr15_label_0 = *valp;
2546 xt_wbr15_imm_0 = (xt_wbr15_label_0 - 0x4) & 0x7fff;
2547 *valp = xt_wbr15_imm_0;
2548 return 0;
2549 }
2550
2551 static int
2552 Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc)
2553 {
2554 *valp -= pc;
2555 return 0;
2556 }
2557
2558 static int
2559 Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc)
2560 {
2561 *valp += pc;
2562 return 0;
2563 }
2564
2565 static int
2566 Operand_xt_wbr18_label_decode (uint32 *valp)
2567 {
2568 unsigned xt_wbr18_label_0, xt_wbr18_imm_0;
2569 xt_wbr18_imm_0 = *valp & 0x3ffff;
2570 xt_wbr18_label_0 = 0x4 + (((int) xt_wbr18_imm_0 << 14) >> 14);
2571 *valp = xt_wbr18_label_0;
2572 return 0;
2573 }
2574
2575 static int
2576 Operand_xt_wbr18_label_encode (uint32 *valp)
2577 {
2578 unsigned xt_wbr18_imm_0, xt_wbr18_label_0;
2579 xt_wbr18_label_0 = *valp;
2580 xt_wbr18_imm_0 = (xt_wbr18_label_0 - 0x4) & 0x3ffff;
2581 *valp = xt_wbr18_imm_0;
2582 return 0;
2583 }
2584
2585 static int
2586 Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc)
2587 {
2588 *valp -= pc;
2589 return 0;
2590 }
2591
2592 static int
2593 Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc)
2594 {
2595 *valp += pc;
2596 return 0;
2597 }
2598
2599 static xtensa_operand_internal operands[] = {
2600 { "soffsetx4", 10, -1, 0,
2601 XTENSA_OPERAND_IS_PCRELATIVE,
2602 Operand_soffsetx4_encode, Operand_soffsetx4_decode,
2603 Operand_soffsetx4_ator, Operand_soffsetx4_rtoa },
2604 { "uimm12x8", 3, -1, 0,
2605 0,
2606 Operand_uimm12x8_encode, Operand_uimm12x8_decode,
2607 0, 0 },
2608 { "simm4", 26, -1, 0,
2609 0,
2610 Operand_simm4_encode, Operand_simm4_decode,
2611 0, 0 },
2612 { "arr", 14, 0, 1,
2613 XTENSA_OPERAND_IS_REGISTER,
2614 Operand_arr_encode, Operand_arr_decode,
2615 0, 0 },
2616 { "ars", 5, 0, 1,
2617 XTENSA_OPERAND_IS_REGISTER,
2618 Operand_ars_encode, Operand_ars_decode,
2619 0, 0 },
2620 { "*ars_invisible", 5, 0, 1,
2621 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2622 Operand_ars_encode, Operand_ars_decode,
2623 0, 0 },
2624 { "art", 0, 0, 1,
2625 XTENSA_OPERAND_IS_REGISTER,
2626 Operand_art_encode, Operand_art_decode,
2627 0, 0 },
2628 { "ar0", 48, 0, 1,
2629 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2630 Operand_ar0_encode, Operand_ar0_decode,
2631 0, 0 },
2632 { "ar4", 49, 0, 1,
2633 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2634 Operand_ar4_encode, Operand_ar4_decode,
2635 0, 0 },
2636 { "ar8", 50, 0, 1,
2637 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2638 Operand_ar8_encode, Operand_ar8_decode,
2639 0, 0 },
2640 { "ar12", 51, 0, 1,
2641 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2642 Operand_ar12_encode, Operand_ar12_decode,
2643 0, 0 },
2644 { "ars_entry", 5, 0, 1,
2645 XTENSA_OPERAND_IS_REGISTER,
2646 Operand_ars_entry_encode, Operand_ars_entry_decode,
2647 0, 0 },
2648 { "immrx4", 14, -1, 0,
2649 0,
2650 Operand_immrx4_encode, Operand_immrx4_decode,
2651 0, 0 },
2652 { "lsi4x4", 14, -1, 0,
2653 0,
2654 Operand_lsi4x4_encode, Operand_lsi4x4_decode,
2655 0, 0 },
2656 { "simm7", 34, -1, 0,
2657 0,
2658 Operand_simm7_encode, Operand_simm7_decode,
2659 0, 0 },
2660 { "uimm6", 33, -1, 0,
2661 XTENSA_OPERAND_IS_PCRELATIVE,
2662 Operand_uimm6_encode, Operand_uimm6_decode,
2663 Operand_uimm6_ator, Operand_uimm6_rtoa },
2664 { "ai4const", 0, -1, 0,
2665 0,
2666 Operand_ai4const_encode, Operand_ai4const_decode,
2667 0, 0 },
2668 { "b4const", 14, -1, 0,
2669 0,
2670 Operand_b4const_encode, Operand_b4const_decode,
2671 0, 0 },
2672 { "b4constu", 14, -1, 0,
2673 0,
2674 Operand_b4constu_encode, Operand_b4constu_decode,
2675 0, 0 },
2676 { "uimm8", 4, -1, 0,
2677 0,
2678 Operand_uimm8_encode, Operand_uimm8_decode,
2679 0, 0 },
2680 { "uimm8x2", 4, -1, 0,
2681 0,
2682 Operand_uimm8x2_encode, Operand_uimm8x2_decode,
2683 0, 0 },
2684 { "uimm8x4", 4, -1, 0,
2685 0,
2686 Operand_uimm8x4_encode, Operand_uimm8x4_decode,
2687 0, 0 },
2688 { "uimm4x16", 13, -1, 0,
2689 0,
2690 Operand_uimm4x16_encode, Operand_uimm4x16_decode,
2691 0, 0 },
2692 { "simm8", 4, -1, 0,
2693 0,
2694 Operand_simm8_encode, Operand_simm8_decode,
2695 0, 0 },
2696 { "simm8x256", 4, -1, 0,
2697 0,
2698 Operand_simm8x256_encode, Operand_simm8x256_decode,
2699 0, 0 },
2700 { "simm12b", 6, -1, 0,
2701 0,
2702 Operand_simm12b_encode, Operand_simm12b_decode,
2703 0, 0 },
2704 { "msalp32", 18, -1, 0,
2705 0,
2706 Operand_msalp32_encode, Operand_msalp32_decode,
2707 0, 0 },
2708 { "op2p1", 13, -1, 0,
2709 0,
2710 Operand_op2p1_encode, Operand_op2p1_decode,
2711 0, 0 },
2712 { "label8", 4, -1, 0,
2713 XTENSA_OPERAND_IS_PCRELATIVE,
2714 Operand_label8_encode, Operand_label8_decode,
2715 Operand_label8_ator, Operand_label8_rtoa },
2716 { "ulabel8", 4, -1, 0,
2717 XTENSA_OPERAND_IS_PCRELATIVE,
2718 Operand_ulabel8_encode, Operand_ulabel8_decode,
2719 Operand_ulabel8_ator, Operand_ulabel8_rtoa },
2720 { "label12", 3, -1, 0,
2721 XTENSA_OPERAND_IS_PCRELATIVE,
2722 Operand_label12_encode, Operand_label12_decode,
2723 Operand_label12_ator, Operand_label12_rtoa },
2724 { "soffset", 10, -1, 0,
2725 XTENSA_OPERAND_IS_PCRELATIVE,
2726 Operand_soffset_encode, Operand_soffset_decode,
2727 Operand_soffset_ator, Operand_soffset_rtoa },
2728 { "uimm16x4", 7, -1, 0,
2729 XTENSA_OPERAND_IS_PCRELATIVE,
2730 Operand_uimm16x4_encode, Operand_uimm16x4_decode,
2731 Operand_uimm16x4_ator, Operand_uimm16x4_rtoa },
2732 { "mx", 43, 1, 1,
2733 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN,
2734 Operand_mx_encode, Operand_mx_decode,
2735 0, 0 },
2736 { "my", 42, 1, 1,
2737 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN,
2738 Operand_my_encode, Operand_my_decode,
2739 0, 0 },
2740 { "mw", 41, 1, 1,
2741 XTENSA_OPERAND_IS_REGISTER,
2742 Operand_mw_encode, Operand_mw_decode,
2743 0, 0 },
2744 { "mr0", 52, 1, 1,
2745 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2746 Operand_mr0_encode, Operand_mr0_decode,
2747 0, 0 },
2748 { "mr1", 53, 1, 1,
2749 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2750 Operand_mr1_encode, Operand_mr1_decode,
2751 0, 0 },
2752 { "mr2", 54, 1, 1,
2753 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2754 Operand_mr2_encode, Operand_mr2_decode,
2755 0, 0 },
2756 { "mr3", 55, 1, 1,
2757 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2758 Operand_mr3_encode, Operand_mr3_decode,
2759 0, 0 },
2760 { "immt", 0, -1, 0,
2761 0,
2762 Operand_immt_encode, Operand_immt_decode,
2763 0, 0 },
2764 { "imms", 5, -1, 0,
2765 0,
2766 Operand_imms_encode, Operand_imms_decode,
2767 0, 0 },
2768 { "tp7", 0, -1, 0,
2769 0,
2770 Operand_tp7_encode, Operand_tp7_decode,
2771 0, 0 },
2772 { "xt_wbr15_label", 44, -1, 0,
2773 XTENSA_OPERAND_IS_PCRELATIVE,
2774 Operand_xt_wbr15_label_encode, Operand_xt_wbr15_label_decode,
2775 Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa },
2776 { "xt_wbr18_label", 45, -1, 0,
2777 XTENSA_OPERAND_IS_PCRELATIVE,
2778 Operand_xt_wbr18_label_encode, Operand_xt_wbr18_label_decode,
2779 Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa },
2780 { "t", 0, -1, 0, 0, 0, 0, 0, 0 },
2781 { "bbi4", 1, -1, 0, 0, 0, 0, 0, 0 },
2782 { "bbi", 2, -1, 0, 0, 0, 0, 0, 0 },
2783 { "imm12", 3, -1, 0, 0, 0, 0, 0, 0 },
2784 { "imm8", 4, -1, 0, 0, 0, 0, 0, 0 },
2785 { "s", 5, -1, 0, 0, 0, 0, 0, 0 },
2786 { "imm12b", 6, -1, 0, 0, 0, 0, 0, 0 },
2787 { "imm16", 7, -1, 0, 0, 0, 0, 0, 0 },
2788 { "m", 8, -1, 0, 0, 0, 0, 0, 0 },
2789 { "n", 9, -1, 0, 0, 0, 0, 0, 0 },
2790 { "offset", 10, -1, 0, 0, 0, 0, 0, 0 },
2791 { "op0", 11, -1, 0, 0, 0, 0, 0, 0 },
2792 { "op1", 12, -1, 0, 0, 0, 0, 0, 0 },
2793 { "op2", 13, -1, 0, 0, 0, 0, 0, 0 },
2794 { "r", 14, -1, 0, 0, 0, 0, 0, 0 },
2795 { "sa4", 15, -1, 0, 0, 0, 0, 0, 0 },
2796 { "sae4", 16, -1, 0, 0, 0, 0, 0, 0 },
2797 { "sae", 17, -1, 0, 0, 0, 0, 0, 0 },
2798 { "sal", 18, -1, 0, 0, 0, 0, 0, 0 },
2799 { "sargt", 19, -1, 0, 0, 0, 0, 0, 0 },
2800 { "sas4", 20, -1, 0, 0, 0, 0, 0, 0 },
2801 { "sas", 21, -1, 0, 0, 0, 0, 0, 0 },
2802 { "sr", 22, -1, 0, 0, 0, 0, 0, 0 },
2803 { "st", 23, -1, 0, 0, 0, 0, 0, 0 },
2804 { "thi3", 24, -1, 0, 0, 0, 0, 0, 0 },
2805 { "imm4", 25, -1, 0, 0, 0, 0, 0, 0 },
2806 { "mn", 26, -1, 0, 0, 0, 0, 0, 0 },
2807 { "i", 27, -1, 0, 0, 0, 0, 0, 0 },
2808 { "imm6lo", 28, -1, 0, 0, 0, 0, 0, 0 },
2809 { "imm6hi", 29, -1, 0, 0, 0, 0, 0, 0 },
2810 { "imm7lo", 30, -1, 0, 0, 0, 0, 0, 0 },
2811 { "imm7hi", 31, -1, 0, 0, 0, 0, 0, 0 },
2812 { "z", 32, -1, 0, 0, 0, 0, 0, 0 },
2813 { "imm6", 33, -1, 0, 0, 0, 0, 0, 0 },
2814 { "imm7", 34, -1, 0, 0, 0, 0, 0, 0 },
2815 { "r3", 35, -1, 0, 0, 0, 0, 0, 0 },
2816 { "rbit2", 36, -1, 0, 0, 0, 0, 0, 0 },
2817 { "rhi", 37, -1, 0, 0, 0, 0, 0, 0 },
2818 { "t3", 38, -1, 0, 0, 0, 0, 0, 0 },
2819 { "tbit2", 39, -1, 0, 0, 0, 0, 0, 0 },
2820 { "tlo", 40, -1, 0, 0, 0, 0, 0, 0 },
2821 { "w", 41, -1, 0, 0, 0, 0, 0, 0 },
2822 { "y", 42, -1, 0, 0, 0, 0, 0, 0 },
2823 { "x", 43, -1, 0, 0, 0, 0, 0, 0 },
2824 { "xt_wbr15_imm", 44, -1, 0, 0, 0, 0, 0, 0 },
2825 { "xt_wbr18_imm", 45, -1, 0, 0, 0, 0, 0, 0 },
2826 { "bitindex", 46, -1, 0, 0, 0, 0, 0, 0 },
2827 { "s3to1", 47, -1, 0, 0, 0, 0, 0, 0 }
2828 };
2829
2830
2831 /* Iclass table. */
2832
2833 static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = {
2834 { { STATE_PSRING }, 'i' },
2835 { { STATE_PSEXCM }, 'm' },
2836 { { STATE_EPC1 }, 'i' }
2837 };
2838
2839 static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = {
2840 { { STATE_PSEXCM }, 'i' },
2841 { { STATE_PSRING }, 'i' },
2842 { { STATE_DEPC }, 'i' }
2843 };
2844
2845 static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = {
2846 { { 0 /* soffsetx4 */ }, 'i' },
2847 { { 10 /* ar12 */ }, 'o' }
2848 };
2849
2850 static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = {
2851 { { STATE_PSCALLINC }, 'o' }
2852 };
2853
2854 static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = {
2855 { { 0 /* soffsetx4 */ }, 'i' },
2856 { { 9 /* ar8 */ }, 'o' }
2857 };
2858
2859 static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = {
2860 { { STATE_PSCALLINC }, 'o' }
2861 };
2862
2863 static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = {
2864 { { 0 /* soffsetx4 */ }, 'i' },
2865 { { 8 /* ar4 */ }, 'o' }
2866 };
2867
2868 static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = {
2869 { { STATE_PSCALLINC }, 'o' }
2870 };
2871
2872 static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = {
2873 { { 4 /* ars */ }, 'i' },
2874 { { 10 /* ar12 */ }, 'o' }
2875 };
2876
2877 static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = {
2878 { { STATE_PSCALLINC }, 'o' }
2879 };
2880
2881 static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = {
2882 { { 4 /* ars */ }, 'i' },
2883 { { 9 /* ar8 */ }, 'o' }
2884 };
2885
2886 static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = {
2887 { { STATE_PSCALLINC }, 'o' }
2888 };
2889
2890 static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = {
2891 { { 4 /* ars */ }, 'i' },
2892 { { 8 /* ar4 */ }, 'o' }
2893 };
2894
2895 static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = {
2896 { { STATE_PSCALLINC }, 'o' }
2897 };
2898
2899 static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = {
2900 { { 11 /* ars_entry */ }, 's' },
2901 { { 4 /* ars */ }, 'i' },
2902 { { 1 /* uimm12x8 */ }, 'i' }
2903 };
2904
2905 static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = {
2906 { { STATE_PSCALLINC }, 'i' },
2907 { { STATE_PSEXCM }, 'i' },
2908 { { STATE_PSWOE }, 'i' },
2909 { { STATE_WindowBase }, 'm' },
2910 { { STATE_WindowStart }, 'm' }
2911 };
2912
2913 static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = {
2914 { { 6 /* art */ }, 'o' },
2915 { { 4 /* ars */ }, 'i' }
2916 };
2917
2918 static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = {
2919 { { STATE_WindowBase }, 'i' },
2920 { { STATE_WindowStart }, 'i' }
2921 };
2922
2923 static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = {
2924 { { 2 /* simm4 */ }, 'i' }
2925 };
2926
2927 static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = {
2928 { { STATE_PSEXCM }, 'i' },
2929 { { STATE_PSRING }, 'i' },
2930 { { STATE_WindowBase }, 'm' }
2931 };
2932
2933 static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = {
2934 { { 5 /* *ars_invisible */ }, 'i' }
2935 };
2936
2937 static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = {
2938 { { STATE_WindowBase }, 'm' },
2939 { { STATE_WindowStart }, 'm' },
2940 { { STATE_PSEXCM }, 'i' },
2941 { { STATE_PSWOE }, 'i' }
2942 };
2943
2944 static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = {
2945 { { STATE_EPC1 }, 'i' },
2946 { { STATE_PSEXCM }, 'm' },
2947 { { STATE_PSRING }, 'i' },
2948 { { STATE_WindowBase }, 'm' },
2949 { { STATE_WindowStart }, 'm' },
2950 { { STATE_PSOWB }, 'i' }
2951 };
2952
2953 static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = {
2954 { { 6 /* art */ }, 'o' },
2955 { { 4 /* ars */ }, 'i' },
2956 { { 12 /* immrx4 */ }, 'i' }
2957 };
2958
2959 static xtensa_arg_internal Iclass_xt_iclass_l32e_stateArgs[] = {
2960 { { STATE_PSEXCM }, 'i' },
2961 { { STATE_PSRING }, 'i' }
2962 };
2963
2964 static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = {
2965 { { 6 /* art */ }, 'i' },
2966 { { 4 /* ars */ }, 'i' },
2967 { { 12 /* immrx4 */ }, 'i' }
2968 };
2969
2970 static xtensa_arg_internal Iclass_xt_iclass_s32e_stateArgs[] = {
2971 { { STATE_PSEXCM }, 'i' },
2972 { { STATE_PSRING }, 'i' }
2973 };
2974
2975 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = {
2976 { { 6 /* art */ }, 'o' }
2977 };
2978
2979 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = {
2980 { { STATE_PSEXCM }, 'i' },
2981 { { STATE_PSRING }, 'i' },
2982 { { STATE_WindowBase }, 'i' }
2983 };
2984
2985 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = {
2986 { { 6 /* art */ }, 'i' }
2987 };
2988
2989 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = {
2990 { { STATE_PSEXCM }, 'i' },
2991 { { STATE_PSRING }, 'i' },
2992 { { STATE_WindowBase }, 'o' }
2993 };
2994
2995 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = {
2996 { { 6 /* art */ }, 'm' }
2997 };
2998
2999 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = {
3000 { { STATE_PSEXCM }, 'i' },
3001 { { STATE_PSRING }, 'i' },
3002 { { STATE_WindowBase }, 'm' }
3003 };
3004
3005 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = {
3006 { { 6 /* art */ }, 'o' }
3007 };
3008
3009 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = {
3010 { { STATE_PSEXCM }, 'i' },
3011 { { STATE_PSRING }, 'i' },
3012 { { STATE_WindowStart }, 'i' }
3013 };
3014
3015 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = {
3016 { { 6 /* art */ }, 'i' }
3017 };
3018
3019 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = {
3020 { { STATE_PSEXCM }, 'i' },
3021 { { STATE_PSRING }, 'i' },
3022 { { STATE_WindowStart }, 'o' }
3023 };
3024
3025 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = {
3026 { { 6 /* art */ }, 'm' }
3027 };
3028
3029 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = {
3030 { { STATE_PSEXCM }, 'i' },
3031 { { STATE_PSRING }, 'i' },
3032 { { STATE_WindowStart }, 'm' }
3033 };
3034
3035 static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = {
3036 { { 3 /* arr */ }, 'o' },
3037 { { 4 /* ars */ }, 'i' },
3038 { { 6 /* art */ }, 'i' }
3039 };
3040
3041 static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = {
3042 { { 3 /* arr */ }, 'o' },
3043 { { 4 /* ars */ }, 'i' },
3044 { { 16 /* ai4const */ }, 'i' }
3045 };
3046
3047 static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = {
3048 { { 4 /* ars */ }, 'i' },
3049 { { 15 /* uimm6 */ }, 'i' }
3050 };
3051
3052 static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = {
3053 { { 6 /* art */ }, 'o' },
3054 { { 4 /* ars */ }, 'i' },
3055 { { 13 /* lsi4x4 */ }, 'i' }
3056 };
3057
3058 static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = {
3059 { { 6 /* art */ }, 'o' },
3060 { { 4 /* ars */ }, 'i' }
3061 };
3062
3063 static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = {
3064 { { 4 /* ars */ }, 'o' },
3065 { { 14 /* simm7 */ }, 'i' }
3066 };
3067
3068 static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = {
3069 { { 5 /* *ars_invisible */ }, 'i' }
3070 };
3071
3072 static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = {
3073 { { 6 /* art */ }, 'i' },
3074 { { 4 /* ars */ }, 'i' },
3075 { { 13 /* lsi4x4 */ }, 'i' }
3076 };
3077
3078 static xtensa_arg_internal Iclass_rur_threadptr_args[] = {
3079 { { 3 /* arr */ }, 'o' }
3080 };
3081
3082 static xtensa_arg_internal Iclass_rur_threadptr_stateArgs[] = {
3083 { { STATE_THREADPTR }, 'i' }
3084 };
3085
3086 static xtensa_arg_internal Iclass_wur_threadptr_args[] = {
3087 { { 6 /* art */ }, 'i' }
3088 };
3089
3090 static xtensa_arg_internal Iclass_wur_threadptr_stateArgs[] = {
3091 { { STATE_THREADPTR }, 'o' }
3092 };
3093
3094 static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = {
3095 { { 6 /* art */ }, 'o' },
3096 { { 4 /* ars */ }, 'i' },
3097 { { 23 /* simm8 */ }, 'i' }
3098 };
3099
3100 static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = {
3101 { { 6 /* art */ }, 'o' },
3102 { { 4 /* ars */ }, 'i' },
3103 { { 24 /* simm8x256 */ }, 'i' }
3104 };
3105
3106 static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = {
3107 { { 3 /* arr */ }, 'o' },
3108 { { 4 /* ars */ }, 'i' },
3109 { { 6 /* art */ }, 'i' }
3110 };
3111
3112 static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = {
3113 { { 3 /* arr */ }, 'o' },
3114 { { 4 /* ars */ }, 'i' },
3115 { { 6 /* art */ }, 'i' }
3116 };
3117
3118 static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = {
3119 { { 4 /* ars */ }, 'i' },
3120 { { 17 /* b4const */ }, 'i' },
3121 { { 28 /* label8 */ }, 'i' }
3122 };
3123
3124 static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = {
3125 { { 4 /* ars */ }, 'i' },
3126 { { 47 /* bbi */ }, 'i' },
3127 { { 28 /* label8 */ }, 'i' }
3128 };
3129
3130 static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = {
3131 { { 4 /* ars */ }, 'i' },
3132 { { 18 /* b4constu */ }, 'i' },
3133 { { 28 /* label8 */ }, 'i' }
3134 };
3135
3136 static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = {
3137 { { 4 /* ars */ }, 'i' },
3138 { { 6 /* art */ }, 'i' },
3139 { { 28 /* label8 */ }, 'i' }
3140 };
3141
3142 static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = {
3143 { { 4 /* ars */ }, 'i' },
3144 { { 30 /* label12 */ }, 'i' }
3145 };
3146
3147 static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = {
3148 { { 0 /* soffsetx4 */ }, 'i' },
3149 { { 7 /* ar0 */ }, 'o' }
3150 };
3151
3152 static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = {
3153 { { 4 /* ars */ }, 'i' },
3154 { { 7 /* ar0 */ }, 'o' }
3155 };
3156
3157 static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = {
3158 { { 3 /* arr */ }, 'o' },
3159 { { 6 /* art */ }, 'i' },
3160 { { 62 /* sae */ }, 'i' },
3161 { { 27 /* op2p1 */ }, 'i' }
3162 };
3163
3164 static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = {
3165 { { 31 /* soffset */ }, 'i' }
3166 };
3167
3168 static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = {
3169 { { 4 /* ars */ }, 'i' }
3170 };
3171
3172 static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = {
3173 { { 6 /* art */ }, 'o' },
3174 { { 4 /* ars */ }, 'i' },
3175 { { 20 /* uimm8x2 */ }, 'i' }
3176 };
3177
3178 static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = {
3179 { { 6 /* art */ }, 'o' },
3180 { { 4 /* ars */ }, 'i' },
3181 { { 20 /* uimm8x2 */ }, 'i' }
3182 };
3183
3184 static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = {
3185 { { 6 /* art */ }, 'o' },
3186 { { 4 /* ars */ }, 'i' },
3187 { { 21 /* uimm8x4 */ }, 'i' }
3188 };
3189
3190 static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = {
3191 { { 6 /* art */ }, 'o' },
3192 { { 32 /* uimm16x4 */ }, 'i' }
3193 };
3194
3195 static xtensa_arg_internal Iclass_xt_iclass_l32r_stateArgs[] = {
3196 { { STATE_LITBADDR }, 'i' },
3197 { { STATE_LITBEN }, 'i' }
3198 };
3199
3200 static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = {
3201 { { 6 /* art */ }, 'o' },
3202 { { 4 /* ars */ }, 'i' },
3203 { { 19 /* uimm8 */ }, 'i' }
3204 };
3205
3206 static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = {
3207 { { 4 /* ars */ }, 'i' },
3208 { { 29 /* ulabel8 */ }, 'i' }
3209 };
3210
3211 static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = {
3212 { { STATE_LBEG }, 'o' },
3213 { { STATE_LEND }, 'o' },
3214 { { STATE_LCOUNT }, 'o' }
3215 };
3216
3217 static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = {
3218 { { 4 /* ars */ }, 'i' },
3219 { { 29 /* ulabel8 */ }, 'i' }
3220 };
3221
3222 static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = {
3223 { { STATE_LBEG }, 'o' },
3224 { { STATE_LEND }, 'o' },
3225 { { STATE_LCOUNT }, 'o' }
3226 };
3227
3228 static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = {
3229 { { 6 /* art */ }, 'o' },
3230 { { 25 /* simm12b */ }, 'i' }
3231 };
3232
3233 static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = {
3234 { { 3 /* arr */ }, 'm' },
3235 { { 4 /* ars */ }, 'i' },
3236 { { 6 /* art */ }, 'i' }
3237 };
3238
3239 static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = {
3240 { { 3 /* arr */ }, 'o' },
3241 { { 6 /* art */ }, 'i' }
3242 };
3243
3244 static xtensa_arg_internal Iclass_xt_iclass_return_args[] = {
3245 { { 5 /* *ars_invisible */ }, 'i' }
3246 };
3247
3248 static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = {
3249 { { 6 /* art */ }, 'i' },
3250 { { 4 /* ars */ }, 'i' },
3251 { { 20 /* uimm8x2 */ }, 'i' }
3252 };
3253
3254 static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = {
3255 { { 6 /* art */ }, 'i' },
3256 { { 4 /* ars */ }, 'i' },
3257 { { 21 /* uimm8x4 */ }, 'i' }
3258 };
3259
3260 static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = {
3261 { { 6 /* art */ }, 'i' },
3262 { { 4 /* ars */ }, 'i' },
3263 { { 19 /* uimm8 */ }, 'i' }
3264 };
3265
3266 static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = {
3267 { { 4 /* ars */ }, 'i' }
3268 };
3269
3270 static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = {
3271 { { STATE_SAR }, 'o' }
3272 };
3273
3274 static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = {
3275 { { 66 /* sas */ }, 'i' }
3276 };
3277
3278 static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = {
3279 { { STATE_SAR }, 'o' }
3280 };
3281
3282 static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = {
3283 { { 3 /* arr */ }, 'o' },
3284 { { 4 /* ars */ }, 'i' }
3285 };
3286
3287 static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = {
3288 { { STATE_SAR }, 'i' }
3289 };
3290
3291 static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = {
3292 { { 3 /* arr */ }, 'o' },
3293 { { 4 /* ars */ }, 'i' },
3294 { { 6 /* art */ }, 'i' }
3295 };
3296
3297 static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = {
3298 { { STATE_SAR }, 'i' }
3299 };
3300
3301 static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = {
3302 { { 3 /* arr */ }, 'o' },
3303 { { 6 /* art */ }, 'i' }
3304 };
3305
3306 static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = {
3307 { { STATE_SAR }, 'i' }
3308 };
3309
3310 static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = {
3311 { { 3 /* arr */ }, 'o' },
3312 { { 4 /* ars */ }, 'i' },
3313 { { 26 /* msalp32 */ }, 'i' }
3314 };
3315
3316 static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = {
3317 { { 3 /* arr */ }, 'o' },
3318 { { 6 /* art */ }, 'i' },
3319 { { 64 /* sargt */ }, 'i' }
3320 };
3321
3322 static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = {
3323 { { 3 /* arr */ }, 'o' },
3324 { { 6 /* art */ }, 'i' },
3325 { { 50 /* s */ }, 'i' }
3326 };
3327
3328 static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = {
3329 { { STATE_XTSYNC }, 'i' }
3330 };
3331
3332 static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = {
3333 { { 6 /* art */ }, 'o' },
3334 { { 50 /* s */ }, 'i' }
3335 };
3336
3337 static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = {
3338 { { STATE_PSWOE }, 'i' },
3339 { { STATE_PSCALLINC }, 'i' },
3340 { { STATE_PSOWB }, 'i' },
3341 { { STATE_PSRING }, 'i' },
3342 { { STATE_PSUM }, 'i' },
3343 { { STATE_PSEXCM }, 'i' },
3344 { { STATE_PSINTLEVEL }, 'm' }
3345 };
3346
3347 static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = {
3348 { { 6 /* art */ }, 'o' }
3349 };
3350
3351 static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = {
3352 { { STATE_LEND }, 'i' }
3353 };
3354
3355 static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = {
3356 { { 6 /* art */ }, 'i' }
3357 };
3358
3359 static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = {
3360 { { STATE_LEND }, 'o' }
3361 };
3362
3363 static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = {
3364 { { 6 /* art */ }, 'm' }
3365 };
3366
3367 static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = {
3368 { { STATE_LEND }, 'm' }
3369 };
3370
3371 static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = {
3372 { { 6 /* art */ }, 'o' }
3373 };
3374
3375 static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = {
3376 { { STATE_LCOUNT }, 'i' }
3377 };
3378
3379 static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = {
3380 { { 6 /* art */ }, 'i' }
3381 };
3382
3383 static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = {
3384 { { STATE_XTSYNC }, 'o' },
3385 { { STATE_LCOUNT }, 'o' }
3386 };
3387
3388 static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = {
3389 { { 6 /* art */ }, 'm' }
3390 };
3391
3392 static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = {
3393 { { STATE_XTSYNC }, 'o' },
3394 { { STATE_LCOUNT }, 'm' }
3395 };
3396
3397 static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = {
3398 { { 6 /* art */ }, 'o' }
3399 };
3400
3401 static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = {
3402 { { STATE_LBEG }, 'i' }
3403 };
3404
3405 static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = {
3406 { { 6 /* art */ }, 'i' }
3407 };
3408
3409 static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = {
3410 { { STATE_LBEG }, 'o' }
3411 };
3412
3413 static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = {
3414 { { 6 /* art */ }, 'm' }
3415 };
3416
3417 static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = {
3418 { { STATE_LBEG }, 'm' }
3419 };
3420
3421 static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = {
3422 { { 6 /* art */ }, 'o' }
3423 };
3424
3425 static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = {
3426 { { STATE_SAR }, 'i' }
3427 };
3428
3429 static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = {
3430 { { 6 /* art */ }, 'i' }
3431 };
3432
3433 static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = {
3434 { { STATE_SAR }, 'o' },
3435 { { STATE_XTSYNC }, 'o' }
3436 };
3437
3438 static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = {
3439 { { 6 /* art */ }, 'm' }
3440 };
3441
3442 static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = {
3443 { { STATE_SAR }, 'm' }
3444 };
3445
3446 static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = {
3447 { { 6 /* art */ }, 'o' }
3448 };
3449
3450 static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_stateArgs[] = {
3451 { { STATE_LITBADDR }, 'i' },
3452 { { STATE_LITBEN }, 'i' }
3453 };
3454
3455 static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = {
3456 { { 6 /* art */ }, 'i' }
3457 };
3458
3459 static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_stateArgs[] = {
3460 { { STATE_LITBADDR }, 'o' },
3461 { { STATE_LITBEN }, 'o' }
3462 };
3463
3464 static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = {
3465 { { 6 /* art */ }, 'm' }
3466 };
3467
3468 static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_stateArgs[] = {
3469 { { STATE_LITBADDR }, 'm' },
3470 { { STATE_LITBEN }, 'm' }
3471 };
3472
3473 static xtensa_arg_internal Iclass_xt_iclass_rsr_176_args[] = {
3474 { { 6 /* art */ }, 'o' }
3475 };
3476
3477 static xtensa_arg_internal Iclass_xt_iclass_rsr_176_stateArgs[] = {
3478 { { STATE_PSEXCM }, 'i' },
3479 { { STATE_PSRING }, 'i' }
3480 };
3481
3482 static xtensa_arg_internal Iclass_xt_iclass_rsr_208_args[] = {
3483 { { 6 /* art */ }, 'o' }
3484 };
3485
3486 static xtensa_arg_internal Iclass_xt_iclass_rsr_208_stateArgs[] = {
3487 { { STATE_PSEXCM }, 'i' },
3488 { { STATE_PSRING }, 'i' }
3489 };
3490
3491 static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = {
3492 { { 6 /* art */ }, 'o' }
3493 };
3494
3495 static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = {
3496 { { STATE_PSWOE }, 'i' },
3497 { { STATE_PSCALLINC }, 'i' },
3498 { { STATE_PSOWB }, 'i' },
3499 { { STATE_PSRING }, 'i' },
3500 { { STATE_PSUM }, 'i' },
3501 { { STATE_PSEXCM }, 'i' },
3502 { { STATE_PSINTLEVEL }, 'i' }
3503 };
3504
3505 static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = {
3506 { { 6 /* art */ }, 'i' }
3507 };
3508
3509 static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = {
3510 { { STATE_PSWOE }, 'o' },
3511 { { STATE_PSCALLINC }, 'o' },
3512 { { STATE_PSOWB }, 'o' },
3513 { { STATE_PSRING }, 'm' },
3514 { { STATE_PSUM }, 'o' },
3515 { { STATE_PSEXCM }, 'm' },
3516 { { STATE_PSINTLEVEL }, 'o' }
3517 };
3518
3519 static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = {
3520 { { 6 /* art */ }, 'm' }
3521 };
3522
3523 static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = {
3524 { { STATE_PSWOE }, 'm' },
3525 { { STATE_PSCALLINC }, 'm' },
3526 { { STATE_PSOWB }, 'm' },
3527 { { STATE_PSRING }, 'm' },
3528 { { STATE_PSUM }, 'm' },
3529 { { STATE_PSEXCM }, 'm' },
3530 { { STATE_PSINTLEVEL }, 'm' }
3531 };
3532
3533 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = {
3534 { { 6 /* art */ }, 'o' }
3535 };
3536
3537 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = {
3538 { { STATE_PSEXCM }, 'i' },
3539 { { STATE_PSRING }, 'i' },
3540 { { STATE_EPC1 }, 'i' }
3541 };
3542
3543 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = {
3544 { { 6 /* art */ }, 'i' }
3545 };
3546
3547 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = {
3548 { { STATE_PSEXCM }, 'i' },
3549 { { STATE_PSRING }, 'i' },
3550 { { STATE_EPC1 }, 'o' }
3551 };
3552
3553 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = {
3554 { { 6 /* art */ }, 'm' }
3555 };
3556
3557 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = {
3558 { { STATE_PSEXCM }, 'i' },
3559 { { STATE_PSRING }, 'i' },
3560 { { STATE_EPC1 }, 'm' }
3561 };
3562
3563 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = {
3564 { { 6 /* art */ }, 'o' }
3565 };
3566
3567 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = {
3568 { { STATE_PSEXCM }, 'i' },
3569 { { STATE_PSRING }, 'i' },
3570 { { STATE_EXCSAVE1 }, 'i' }
3571 };
3572
3573 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = {
3574 { { 6 /* art */ }, 'i' }
3575 };
3576
3577 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = {
3578 { { STATE_PSEXCM }, 'i' },
3579 { { STATE_PSRING }, 'i' },
3580 { { STATE_EXCSAVE1 }, 'o' }
3581 };
3582
3583 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = {
3584 { { 6 /* art */ }, 'm' }
3585 };
3586
3587 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = {
3588 { { STATE_PSEXCM }, 'i' },
3589 { { STATE_PSRING }, 'i' },
3590 { { STATE_EXCSAVE1 }, 'm' }
3591 };
3592
3593 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = {
3594 { { 6 /* art */ }, 'o' }
3595 };
3596
3597 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = {
3598 { { STATE_PSEXCM }, 'i' },
3599 { { STATE_PSRING }, 'i' },
3600 { { STATE_EPC2 }, 'i' }
3601 };
3602
3603 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = {
3604 { { 6 /* art */ }, 'i' }
3605 };
3606
3607 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = {
3608 { { STATE_PSEXCM }, 'i' },
3609 { { STATE_PSRING }, 'i' },
3610 { { STATE_EPC2 }, 'o' }
3611 };
3612
3613 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = {
3614 { { 6 /* art */ }, 'm' }
3615 };
3616
3617 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = {
3618 { { STATE_PSEXCM }, 'i' },
3619 { { STATE_PSRING }, 'i' },
3620 { { STATE_EPC2 }, 'm' }
3621 };
3622
3623 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = {
3624 { { 6 /* art */ }, 'o' }
3625 };
3626
3627 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = {
3628 { { STATE_PSEXCM }, 'i' },
3629 { { STATE_PSRING }, 'i' },
3630 { { STATE_EXCSAVE2 }, 'i' }
3631 };
3632
3633 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = {
3634 { { 6 /* art */ }, 'i' }
3635 };
3636
3637 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = {
3638 { { STATE_PSEXCM }, 'i' },
3639 { { STATE_PSRING }, 'i' },
3640 { { STATE_EXCSAVE2 }, 'o' }
3641 };
3642
3643 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = {
3644 { { 6 /* art */ }, 'm' }
3645 };
3646
3647 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = {
3648 { { STATE_PSEXCM }, 'i' },
3649 { { STATE_PSRING }, 'i' },
3650 { { STATE_EXCSAVE2 }, 'm' }
3651 };
3652
3653 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = {
3654 { { 6 /* art */ }, 'o' }
3655 };
3656
3657 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = {
3658 { { STATE_PSEXCM }, 'i' },
3659 { { STATE_PSRING }, 'i' },
3660 { { STATE_EPC3 }, 'i' }
3661 };
3662
3663 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = {
3664 { { 6 /* art */ }, 'i' }
3665 };
3666
3667 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = {
3668 { { STATE_PSEXCM }, 'i' },
3669 { { STATE_PSRING }, 'i' },
3670 { { STATE_EPC3 }, 'o' }
3671 };
3672
3673 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = {
3674 { { 6 /* art */ }, 'm' }
3675 };
3676
3677 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = {
3678 { { STATE_PSEXCM }, 'i' },
3679 { { STATE_PSRING }, 'i' },
3680 { { STATE_EPC3 }, 'm' }
3681 };
3682
3683 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = {
3684 { { 6 /* art */ }, 'o' }
3685 };
3686
3687 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = {
3688 { { STATE_PSEXCM }, 'i' },
3689 { { STATE_PSRING }, 'i' },
3690 { { STATE_EXCSAVE3 }, 'i' }
3691 };
3692
3693 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = {
3694 { { 6 /* art */ }, 'i' }
3695 };
3696
3697 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = {
3698 { { STATE_PSEXCM }, 'i' },
3699 { { STATE_PSRING }, 'i' },
3700 { { STATE_EXCSAVE3 }, 'o' }
3701 };
3702
3703 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = {
3704 { { 6 /* art */ }, 'm' }
3705 };
3706
3707 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = {
3708 { { STATE_PSEXCM }, 'i' },
3709 { { STATE_PSRING }, 'i' },
3710 { { STATE_EXCSAVE3 }, 'm' }
3711 };
3712
3713 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = {
3714 { { 6 /* art */ }, 'o' }
3715 };
3716
3717 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = {
3718 { { STATE_PSEXCM }, 'i' },
3719 { { STATE_PSRING }, 'i' },
3720 { { STATE_EPC4 }, 'i' }
3721 };
3722
3723 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = {
3724 { { 6 /* art */ }, 'i' }
3725 };
3726
3727 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = {
3728 { { STATE_PSEXCM }, 'i' },
3729 { { STATE_PSRING }, 'i' },
3730 { { STATE_EPC4 }, 'o' }
3731 };
3732
3733 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = {
3734 { { 6 /* art */ }, 'm' }
3735 };
3736
3737 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = {
3738 { { STATE_PSEXCM }, 'i' },
3739 { { STATE_PSRING }, 'i' },
3740 { { STATE_EPC4 }, 'm' }
3741 };
3742
3743 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = {
3744 { { 6 /* art */ }, 'o' }
3745 };
3746
3747 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = {
3748 { { STATE_PSEXCM }, 'i' },
3749 { { STATE_PSRING }, 'i' },
3750 { { STATE_EXCSAVE4 }, 'i' }
3751 };
3752
3753 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = {
3754 { { 6 /* art */ }, 'i' }
3755 };
3756
3757 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = {
3758 { { STATE_PSEXCM }, 'i' },
3759 { { STATE_PSRING }, 'i' },
3760 { { STATE_EXCSAVE4 }, 'o' }
3761 };
3762
3763 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = {
3764 { { 6 /* art */ }, 'm' }
3765 };
3766
3767 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = {
3768 { { STATE_PSEXCM }, 'i' },
3769 { { STATE_PSRING }, 'i' },
3770 { { STATE_EXCSAVE4 }, 'm' }
3771 };
3772
3773 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_args[] = {
3774 { { 6 /* art */ }, 'o' }
3775 };
3776
3777 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_stateArgs[] = {
3778 { { STATE_PSEXCM }, 'i' },
3779 { { STATE_PSRING }, 'i' },
3780 { { STATE_EPC5 }, 'i' }
3781 };
3782
3783 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_args[] = {
3784 { { 6 /* art */ }, 'i' }
3785 };
3786
3787 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_stateArgs[] = {
3788 { { STATE_PSEXCM }, 'i' },
3789 { { STATE_PSRING }, 'i' },
3790 { { STATE_EPC5 }, 'o' }
3791 };
3792
3793 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_args[] = {
3794 { { 6 /* art */ }, 'm' }
3795 };
3796
3797 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_stateArgs[] = {
3798 { { STATE_PSEXCM }, 'i' },
3799 { { STATE_PSRING }, 'i' },
3800 { { STATE_EPC5 }, 'm' }
3801 };
3802
3803 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_args[] = {
3804 { { 6 /* art */ }, 'o' }
3805 };
3806
3807 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_stateArgs[] = {
3808 { { STATE_PSEXCM }, 'i' },
3809 { { STATE_PSRING }, 'i' },
3810 { { STATE_EXCSAVE5 }, 'i' }
3811 };
3812
3813 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_args[] = {
3814 { { 6 /* art */ }, 'i' }
3815 };
3816
3817 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_stateArgs[] = {
3818 { { STATE_PSEXCM }, 'i' },
3819 { { STATE_PSRING }, 'i' },
3820 { { STATE_EXCSAVE5 }, 'o' }
3821 };
3822
3823 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_args[] = {
3824 { { 6 /* art */ }, 'm' }
3825 };
3826
3827 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_stateArgs[] = {
3828 { { STATE_PSEXCM }, 'i' },
3829 { { STATE_PSRING }, 'i' },
3830 { { STATE_EXCSAVE5 }, 'm' }
3831 };
3832
3833 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_args[] = {
3834 { { 6 /* art */ }, 'o' }
3835 };
3836
3837 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_stateArgs[] = {
3838 { { STATE_PSEXCM }, 'i' },
3839 { { STATE_PSRING }, 'i' },
3840 { { STATE_EPC6 }, 'i' }
3841 };
3842
3843 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_args[] = {
3844 { { 6 /* art */ }, 'i' }
3845 };
3846
3847 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_stateArgs[] = {
3848 { { STATE_PSEXCM }, 'i' },
3849 { { STATE_PSRING }, 'i' },
3850 { { STATE_EPC6 }, 'o' }
3851 };
3852
3853 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_args[] = {
3854 { { 6 /* art */ }, 'm' }
3855 };
3856
3857 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_stateArgs[] = {
3858 { { STATE_PSEXCM }, 'i' },
3859 { { STATE_PSRING }, 'i' },
3860 { { STATE_EPC6 }, 'm' }
3861 };
3862
3863 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_args[] = {
3864 { { 6 /* art */ }, 'o' }
3865 };
3866
3867 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_stateArgs[] = {
3868 { { STATE_PSEXCM }, 'i' },
3869 { { STATE_PSRING }, 'i' },
3870 { { STATE_EXCSAVE6 }, 'i' }
3871 };
3872
3873 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_args[] = {
3874 { { 6 /* art */ }, 'i' }
3875 };
3876
3877 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_stateArgs[] = {
3878 { { STATE_PSEXCM }, 'i' },
3879 { { STATE_PSRING }, 'i' },
3880 { { STATE_EXCSAVE6 }, 'o' }
3881 };
3882
3883 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_args[] = {
3884 { { 6 /* art */ }, 'm' }
3885 };
3886
3887 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_stateArgs[] = {
3888 { { STATE_PSEXCM }, 'i' },
3889 { { STATE_PSRING }, 'i' },
3890 { { STATE_EXCSAVE6 }, 'm' }
3891 };
3892
3893 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_args[] = {
3894 { { 6 /* art */ }, 'o' }
3895 };
3896
3897 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_stateArgs[] = {
3898 { { STATE_PSEXCM }, 'i' },
3899 { { STATE_PSRING }, 'i' },
3900 { { STATE_EPC7 }, 'i' }
3901 };
3902
3903 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_args[] = {
3904 { { 6 /* art */ }, 'i' }
3905 };
3906
3907 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_stateArgs[] = {
3908 { { STATE_PSEXCM }, 'i' },
3909 { { STATE_PSRING }, 'i' },
3910 { { STATE_EPC7 }, 'o' }
3911 };
3912
3913 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_args[] = {
3914 { { 6 /* art */ }, 'm' }
3915 };
3916
3917 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_stateArgs[] = {
3918 { { STATE_PSEXCM }, 'i' },
3919 { { STATE_PSRING }, 'i' },
3920 { { STATE_EPC7 }, 'm' }
3921 };
3922
3923 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_args[] = {
3924 { { 6 /* art */ }, 'o' }
3925 };
3926
3927 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_stateArgs[] = {
3928 { { STATE_PSEXCM }, 'i' },
3929 { { STATE_PSRING }, 'i' },
3930 { { STATE_EXCSAVE7 }, 'i' }
3931 };
3932
3933 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_args[] = {
3934 { { 6 /* art */ }, 'i' }
3935 };
3936
3937 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_stateArgs[] = {
3938 { { STATE_PSEXCM }, 'i' },
3939 { { STATE_PSRING }, 'i' },
3940 { { STATE_EXCSAVE7 }, 'o' }
3941 };
3942
3943 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_args[] = {
3944 { { 6 /* art */ }, 'm' }
3945 };
3946
3947 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_stateArgs[] = {
3948 { { STATE_PSEXCM }, 'i' },
3949 { { STATE_PSRING }, 'i' },
3950 { { STATE_EXCSAVE7 }, 'm' }
3951 };
3952
3953 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = {
3954 { { 6 /* art */ }, 'o' }
3955 };
3956
3957 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = {
3958 { { STATE_PSEXCM }, 'i' },
3959 { { STATE_PSRING }, 'i' },
3960 { { STATE_EPS2 }, 'i' }
3961 };
3962
3963 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = {
3964 { { 6 /* art */ }, 'i' }
3965 };
3966
3967 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = {
3968 { { STATE_PSEXCM }, 'i' },
3969 { { STATE_PSRING }, 'i' },
3970 { { STATE_EPS2 }, 'o' }
3971 };
3972
3973 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = {
3974 { { 6 /* art */ }, 'm' }
3975 };
3976
3977 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = {
3978 { { STATE_PSEXCM }, 'i' },
3979 { { STATE_PSRING }, 'i' },
3980 { { STATE_EPS2 }, 'm' }
3981 };
3982
3983 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = {
3984 { { 6 /* art */ }, 'o' }
3985 };
3986
3987 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = {
3988 { { STATE_PSEXCM }, 'i' },
3989 { { STATE_PSRING }, 'i' },
3990 { { STATE_EPS3 }, 'i' }
3991 };
3992
3993 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = {
3994 { { 6 /* art */ }, 'i' }
3995 };
3996
3997 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = {
3998 { { STATE_PSEXCM }, 'i' },
3999 { { STATE_PSRING }, 'i' },
4000 { { STATE_EPS3 }, 'o' }
4001 };
4002
4003 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = {
4004 { { 6 /* art */ }, 'm' }
4005 };
4006
4007 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = {
4008 { { STATE_PSEXCM }, 'i' },
4009 { { STATE_PSRING }, 'i' },
4010 { { STATE_EPS3 }, 'm' }
4011 };
4012
4013 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = {
4014 { { 6 /* art */ }, 'o' }
4015 };
4016
4017 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = {
4018 { { STATE_PSEXCM }, 'i' },
4019 { { STATE_PSRING }, 'i' },
4020 { { STATE_EPS4 }, 'i' }
4021 };
4022
4023 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = {
4024 { { 6 /* art */ }, 'i' }
4025 };
4026
4027 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = {
4028 { { STATE_PSEXCM }, 'i' },
4029 { { STATE_PSRING }, 'i' },
4030 { { STATE_EPS4 }, 'o' }
4031 };
4032
4033 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = {
4034 { { 6 /* art */ }, 'm' }
4035 };
4036
4037 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = {
4038 { { STATE_PSEXCM }, 'i' },
4039 { { STATE_PSRING }, 'i' },
4040 { { STATE_EPS4 }, 'm' }
4041 };
4042
4043 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_args[] = {
4044 { { 6 /* art */ }, 'o' }
4045 };
4046
4047 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_stateArgs[] = {
4048 { { STATE_PSEXCM }, 'i' },
4049 { { STATE_PSRING }, 'i' },
4050 { { STATE_EPS5 }, 'i' }
4051 };
4052
4053 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_args[] = {
4054 { { 6 /* art */ }, 'i' }
4055 };
4056
4057 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_stateArgs[] = {
4058 { { STATE_PSEXCM }, 'i' },
4059 { { STATE_PSRING }, 'i' },
4060 { { STATE_EPS5 }, 'o' }
4061 };
4062
4063 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_args[] = {
4064 { { 6 /* art */ }, 'm' }
4065 };
4066
4067 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_stateArgs[] = {
4068 { { STATE_PSEXCM }, 'i' },
4069 { { STATE_PSRING }, 'i' },
4070 { { STATE_EPS5 }, 'm' }
4071 };
4072
4073 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_args[] = {
4074 { { 6 /* art */ }, 'o' }
4075 };
4076
4077 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_stateArgs[] = {
4078 { { STATE_PSEXCM }, 'i' },
4079 { { STATE_PSRING }, 'i' },
4080 { { STATE_EPS6 }, 'i' }
4081 };
4082
4083 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_args[] = {
4084 { { 6 /* art */ }, 'i' }
4085 };
4086
4087 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_stateArgs[] = {
4088 { { STATE_PSEXCM }, 'i' },
4089 { { STATE_PSRING }, 'i' },
4090 { { STATE_EPS6 }, 'o' }
4091 };
4092
4093 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_args[] = {
4094 { { 6 /* art */ }, 'm' }
4095 };
4096
4097 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_stateArgs[] = {
4098 { { STATE_PSEXCM }, 'i' },
4099 { { STATE_PSRING }, 'i' },
4100 { { STATE_EPS6 }, 'm' }
4101 };
4102
4103 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_args[] = {
4104 { { 6 /* art */ }, 'o' }
4105 };
4106
4107 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_stateArgs[] = {
4108 { { STATE_PSEXCM }, 'i' },
4109 { { STATE_PSRING }, 'i' },
4110 { { STATE_EPS7 }, 'i' }
4111 };
4112
4113 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_args[] = {
4114 { { 6 /* art */ }, 'i' }
4115 };
4116
4117 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_stateArgs[] = {
4118 { { STATE_PSEXCM }, 'i' },
4119 { { STATE_PSRING }, 'i' },
4120 { { STATE_EPS7 }, 'o' }
4121 };
4122
4123 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_args[] = {
4124 { { 6 /* art */ }, 'm' }
4125 };
4126
4127 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_stateArgs[] = {
4128 { { STATE_PSEXCM }, 'i' },
4129 { { STATE_PSRING }, 'i' },
4130 { { STATE_EPS7 }, 'm' }
4131 };
4132
4133 static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = {
4134 { { 6 /* art */ }, 'o' }
4135 };
4136
4137 static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = {
4138 { { STATE_PSEXCM }, 'i' },
4139 { { STATE_PSRING }, 'i' },
4140 { { STATE_EXCVADDR }, 'i' }
4141 };
4142
4143 static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = {
4144 { { 6 /* art */ }, 'i' }
4145 };
4146
4147 static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = {
4148 { { STATE_PSEXCM }, 'i' },
4149 { { STATE_PSRING }, 'i' },
4150 { { STATE_EXCVADDR }, 'o' }
4151 };
4152
4153 static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = {
4154 { { 6 /* art */ }, 'm' }
4155 };
4156
4157 static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = {
4158 { { STATE_PSEXCM }, 'i' },
4159 { { STATE_PSRING }, 'i' },
4160 { { STATE_EXCVADDR }, 'm' }
4161 };
4162
4163 static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = {
4164 { { 6 /* art */ }, 'o' }
4165 };
4166
4167 static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = {
4168 { { STATE_PSEXCM }, 'i' },
4169 { { STATE_PSRING }, 'i' },
4170 { { STATE_DEPC }, 'i' }
4171 };
4172
4173 static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = {
4174 { { 6 /* art */ }, 'i' }
4175 };
4176
4177 static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = {
4178 { { STATE_PSEXCM }, 'i' },
4179 { { STATE_PSRING }, 'i' },
4180 { { STATE_DEPC }, 'o' }
4181 };
4182
4183 static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = {
4184 { { 6 /* art */ }, 'm' }
4185 };
4186
4187 static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = {
4188 { { STATE_PSEXCM }, 'i' },
4189 { { STATE_PSRING }, 'i' },
4190 { { STATE_DEPC }, 'm' }
4191 };
4192
4193 static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = {
4194 { { 6 /* art */ }, 'o' }
4195 };
4196
4197 static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = {
4198 { { STATE_PSEXCM }, 'i' },
4199 { { STATE_PSRING }, 'i' },
4200 { { STATE_EXCCAUSE }, 'i' },
4201 { { STATE_XTSYNC }, 'i' }
4202 };
4203
4204 static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = {
4205 { { 6 /* art */ }, 'i' }
4206 };
4207
4208 static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = {
4209 { { STATE_PSEXCM }, 'i' },
4210 { { STATE_PSRING }, 'i' },
4211 { { STATE_EXCCAUSE }, 'o' }
4212 };
4213
4214 static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = {
4215 { { 6 /* art */ }, 'm' }
4216 };
4217
4218 static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = {
4219 { { STATE_PSEXCM }, 'i' },
4220 { { STATE_PSRING }, 'i' },
4221 { { STATE_EXCCAUSE }, 'm' }
4222 };
4223
4224 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = {
4225 { { 6 /* art */ }, 'o' }
4226 };
4227
4228 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = {
4229 { { STATE_PSEXCM }, 'i' },
4230 { { STATE_PSRING }, 'i' },
4231 { { STATE_MISC0 }, 'i' }
4232 };
4233
4234 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = {
4235 { { 6 /* art */ }, 'i' }
4236 };
4237
4238 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = {
4239 { { STATE_PSEXCM }, 'i' },
4240 { { STATE_PSRING }, 'i' },
4241 { { STATE_MISC0 }, 'o' }
4242 };
4243
4244 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = {
4245 { { 6 /* art */ }, 'm' }
4246 };
4247
4248 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = {
4249 { { STATE_PSEXCM }, 'i' },
4250 { { STATE_PSRING }, 'i' },
4251 { { STATE_MISC0 }, 'm' }
4252 };
4253
4254 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = {
4255 { { 6 /* art */ }, 'o' }
4256 };
4257
4258 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = {
4259 { { STATE_PSEXCM }, 'i' },
4260 { { STATE_PSRING }, 'i' },
4261 { { STATE_MISC1 }, 'i' }
4262 };
4263
4264 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = {
4265 { { 6 /* art */ }, 'i' }
4266 };
4267
4268 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = {
4269 { { STATE_PSEXCM }, 'i' },
4270 { { STATE_PSRING }, 'i' },
4271 { { STATE_MISC1 }, 'o' }
4272 };
4273
4274 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = {
4275 { { 6 /* art */ }, 'm' }
4276 };
4277
4278 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = {
4279 { { STATE_PSEXCM }, 'i' },
4280 { { STATE_PSRING }, 'i' },
4281 { { STATE_MISC1 }, 'm' }
4282 };
4283
4284 static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = {
4285 { { 6 /* art */ }, 'o' }
4286 };
4287
4288 static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_stateArgs[] = {
4289 { { STATE_PSEXCM }, 'i' },
4290 { { STATE_PSRING }, 'i' }
4291 };
4292
4293 static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = {
4294 { { 6 /* art */ }, 'o' }
4295 };
4296
4297 static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = {
4298 { { STATE_PSEXCM }, 'i' },
4299 { { STATE_PSRING }, 'i' },
4300 { { STATE_VECBASE }, 'i' }
4301 };
4302
4303 static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = {
4304 { { 6 /* art */ }, 'i' }
4305 };
4306
4307 static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = {
4308 { { STATE_PSEXCM }, 'i' },
4309 { { STATE_PSRING }, 'i' },
4310 { { STATE_VECBASE }, 'o' }
4311 };
4312
4313 static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = {
4314 { { 6 /* art */ }, 'm' }
4315 };
4316
4317 static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = {
4318 { { STATE_PSEXCM }, 'i' },
4319 { { STATE_PSRING }, 'i' },
4320 { { STATE_VECBASE }, 'm' }
4321 };
4322
4323 static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_args[] = {
4324 { { 4 /* ars */ }, 'i' },
4325 { { 6 /* art */ }, 'i' }
4326 };
4327
4328 static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_stateArgs[] = {
4329 { { STATE_ACC }, 'o' }
4330 };
4331
4332 static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_args[] = {
4333 { { 4 /* ars */ }, 'i' },
4334 { { 34 /* my */ }, 'i' }
4335 };
4336
4337 static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_stateArgs[] = {
4338 { { STATE_ACC }, 'o' }
4339 };
4340
4341 static xtensa_arg_internal Iclass_xt_iclass_mac16_da_args[] = {
4342 { { 33 /* mx */ }, 'i' },
4343 { { 6 /* art */ }, 'i' }
4344 };
4345
4346 static xtensa_arg_internal Iclass_xt_iclass_mac16_da_stateArgs[] = {
4347 { { STATE_ACC }, 'o' }
4348 };
4349
4350 static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_args[] = {
4351 { { 33 /* mx */ }, 'i' },
4352 { { 34 /* my */ }, 'i' }
4353 };
4354
4355 static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_stateArgs[] = {
4356 { { STATE_ACC }, 'o' }
4357 };
4358
4359 static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_args[] = {
4360 { { 4 /* ars */ }, 'i' },
4361 { { 6 /* art */ }, 'i' }
4362 };
4363
4364 static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_stateArgs[] = {
4365 { { STATE_ACC }, 'm' }
4366 };
4367
4368 static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_args[] = {
4369 { { 4 /* ars */ }, 'i' },
4370 { { 34 /* my */ }, 'i' }
4371 };
4372
4373 static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_stateArgs[] = {
4374 { { STATE_ACC }, 'm' }
4375 };
4376
4377 static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_args[] = {
4378 { { 33 /* mx */ }, 'i' },
4379 { { 6 /* art */ }, 'i' }
4380 };
4381
4382 static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_stateArgs[] = {
4383 { { STATE_ACC }, 'm' }
4384 };
4385
4386 static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_args[] = {
4387 { { 33 /* mx */ }, 'i' },
4388 { { 34 /* my */ }, 'i' }
4389 };
4390
4391 static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_stateArgs[] = {
4392 { { STATE_ACC }, 'm' }
4393 };
4394
4395 static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_args[] = {
4396 { { 35 /* mw */ }, 'o' },
4397 { { 4 /* ars */ }, 'm' },
4398 { { 33 /* mx */ }, 'i' },
4399 { { 6 /* art */ }, 'i' }
4400 };
4401
4402 static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_stateArgs[] = {
4403 { { STATE_ACC }, 'm' }
4404 };
4405
4406 static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_args[] = {
4407 { { 35 /* mw */ }, 'o' },
4408 { { 4 /* ars */ }, 'm' },
4409 { { 33 /* mx */ }, 'i' },
4410 { { 34 /* my */ }, 'i' }
4411 };
4412
4413 static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_stateArgs[] = {
4414 { { STATE_ACC }, 'm' }
4415 };
4416
4417 static xtensa_arg_internal Iclass_xt_iclass_mac16_l_args[] = {
4418 { { 35 /* mw */ }, 'o' },
4419 { { 4 /* ars */ }, 'm' }
4420 };
4421
4422 static xtensa_arg_internal Iclass_xt_iclass_mul16_args[] = {
4423 { { 3 /* arr */ }, 'o' },
4424 { { 4 /* ars */ }, 'i' },
4425 { { 6 /* art */ }, 'i' }
4426 };
4427
4428 static xtensa_arg_internal Iclass_xt_iclass_rsr_m0_args[] = {
4429 { { 6 /* art */ }, 'o' },
4430 { { 36 /* mr0 */ }, 'i' }
4431 };
4432
4433 static xtensa_arg_internal Iclass_xt_iclass_wsr_m0_args[] = {
4434 { { 6 /* art */ }, 'i' },
4435 { { 36 /* mr0 */ }, 'o' }
4436 };
4437
4438 static xtensa_arg_internal Iclass_xt_iclass_xsr_m0_args[] = {
4439 { { 6 /* art */ }, 'm' },
4440 { { 36 /* mr0 */ }, 'm' }
4441 };
4442
4443 static xtensa_arg_internal Iclass_xt_iclass_rsr_m1_args[] = {
4444 { { 6 /* art */ }, 'o' },
4445 { { 37 /* mr1 */ }, 'i' }
4446 };
4447
4448 static xtensa_arg_internal Iclass_xt_iclass_wsr_m1_args[] = {
4449 { { 6 /* art */ }, 'i' },
4450 { { 37 /* mr1 */ }, 'o' }
4451 };
4452
4453 static xtensa_arg_internal Iclass_xt_iclass_xsr_m1_args[] = {
4454 { { 6 /* art */ }, 'm' },
4455 { { 37 /* mr1 */ }, 'm' }
4456 };
4457
4458 static xtensa_arg_internal Iclass_xt_iclass_rsr_m2_args[] = {
4459 { { 6 /* art */ }, 'o' },
4460 { { 38 /* mr2 */ }, 'i' }
4461 };
4462
4463 static xtensa_arg_internal Iclass_xt_iclass_wsr_m2_args[] = {
4464 { { 6 /* art */ }, 'i' },
4465 { { 38 /* mr2 */ }, 'o' }
4466 };
4467
4468 static xtensa_arg_internal Iclass_xt_iclass_xsr_m2_args[] = {
4469 { { 6 /* art */ }, 'm' },
4470 { { 38 /* mr2 */ }, 'm' }
4471 };
4472
4473 static xtensa_arg_internal Iclass_xt_iclass_rsr_m3_args[] = {
4474 { { 6 /* art */ }, 'o' },
4475 { { 39 /* mr3 */ }, 'i' }
4476 };
4477
4478 static xtensa_arg_internal Iclass_xt_iclass_wsr_m3_args[] = {
4479 { { 6 /* art */ }, 'i' },
4480 { { 39 /* mr3 */ }, 'o' }
4481 };
4482
4483 static xtensa_arg_internal Iclass_xt_iclass_xsr_m3_args[] = {
4484 { { 6 /* art */ }, 'm' },
4485 { { 39 /* mr3 */ }, 'm' }
4486 };
4487
4488 static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_args[] = {
4489 { { 6 /* art */ }, 'o' }
4490 };
4491
4492 static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_stateArgs[] = {
4493 { { STATE_ACC }, 'i' }
4494 };
4495
4496 static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_args[] = {
4497 { { 6 /* art */ }, 'i' }
4498 };
4499
4500 static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_stateArgs[] = {
4501 { { STATE_ACC }, 'm' }
4502 };
4503
4504 static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_args[] = {
4505 { { 6 /* art */ }, 'm' }
4506 };
4507
4508 static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_stateArgs[] = {
4509 { { STATE_ACC }, 'm' }
4510 };
4511
4512 static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_args[] = {
4513 { { 6 /* art */ }, 'o' }
4514 };
4515
4516 static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_stateArgs[] = {
4517 { { STATE_ACC }, 'i' }
4518 };
4519
4520 static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_args[] = {
4521 { { 6 /* art */ }, 'i' }
4522 };
4523
4524 static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_stateArgs[] = {
4525 { { STATE_ACC }, 'm' }
4526 };
4527
4528 static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_args[] = {
4529 { { 6 /* art */ }, 'm' }
4530 };
4531
4532 static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_stateArgs[] = {
4533 { { STATE_ACC }, 'm' }
4534 };
4535
4536 static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = {
4537 { { 50 /* s */ }, 'i' }
4538 };
4539
4540 static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = {
4541 { { STATE_PSWOE }, 'o' },
4542 { { STATE_PSCALLINC }, 'o' },
4543 { { STATE_PSOWB }, 'o' },
4544 { { STATE_PSRING }, 'm' },
4545 { { STATE_PSUM }, 'o' },
4546 { { STATE_PSEXCM }, 'm' },
4547 { { STATE_PSINTLEVEL }, 'o' },
4548 { { STATE_EPC1 }, 'i' },
4549 { { STATE_EPC2 }, 'i' },
4550 { { STATE_EPC3 }, 'i' },
4551 { { STATE_EPC4 }, 'i' },
4552 { { STATE_EPC5 }, 'i' },
4553 { { STATE_EPC6 }, 'i' },
4554 { { STATE_EPC7 }, 'i' },
4555 { { STATE_EPS2 }, 'i' },
4556 { { STATE_EPS3 }, 'i' },
4557 { { STATE_EPS4 }, 'i' },
4558 { { STATE_EPS5 }, 'i' },
4559 { { STATE_EPS6 }, 'i' },
4560 { { STATE_EPS7 }, 'i' },
4561 { { STATE_InOCDMode }, 'm' }
4562 };
4563
4564 static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = {
4565 { { 50 /* s */ }, 'i' }
4566 };
4567
4568 static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = {
4569 { { STATE_PSEXCM }, 'i' },
4570 { { STATE_PSRING }, 'i' },
4571 { { STATE_PSINTLEVEL }, 'o' }
4572 };
4573
4574 static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = {
4575 { { 6 /* art */ }, 'o' }
4576 };
4577
4578 static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = {
4579 { { STATE_PSEXCM }, 'i' },
4580 { { STATE_PSRING }, 'i' },
4581 { { STATE_INTERRUPT }, 'i' }
4582 };
4583
4584 static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = {
4585 { { 6 /* art */ }, 'i' }
4586 };
4587
4588 static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = {
4589 { { STATE_PSEXCM }, 'i' },
4590 { { STATE_PSRING }, 'i' },
4591 { { STATE_XTSYNC }, 'o' },
4592 { { STATE_INTERRUPT }, 'm' }
4593 };
4594
4595 static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = {
4596 { { 6 /* art */ }, 'i' }
4597 };
4598
4599 static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = {
4600 { { STATE_PSEXCM }, 'i' },
4601 { { STATE_PSRING }, 'i' },
4602 { { STATE_XTSYNC }, 'o' },
4603 { { STATE_INTERRUPT }, 'm' }
4604 };
4605
4606 static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = {
4607 { { 6 /* art */ }, 'o' }
4608 };
4609
4610 static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = {
4611 { { STATE_PSEXCM }, 'i' },
4612 { { STATE_PSRING }, 'i' },
4613 { { STATE_INTENABLE }, 'i' }
4614 };
4615
4616 static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = {
4617 { { 6 /* art */ }, 'i' }
4618 };
4619
4620 static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = {
4621 { { STATE_PSEXCM }, 'i' },
4622 { { STATE_PSRING }, 'i' },
4623 { { STATE_INTENABLE }, 'o' }
4624 };
4625
4626 static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = {
4627 { { 6 /* art */ }, 'm' }
4628 };
4629
4630 static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = {
4631 { { STATE_PSEXCM }, 'i' },
4632 { { STATE_PSRING }, 'i' },
4633 { { STATE_INTENABLE }, 'm' }
4634 };
4635
4636 static xtensa_arg_internal Iclass_xt_iclass_break_args[] = {
4637 { { 41 /* imms */ }, 'i' },
4638 { { 40 /* immt */ }, 'i' }
4639 };
4640
4641 static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = {
4642 { { STATE_PSEXCM }, 'i' },
4643 { { STATE_PSINTLEVEL }, 'i' }
4644 };
4645
4646 static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = {
4647 { { 41 /* imms */ }, 'i' }
4648 };
4649
4650 static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = {
4651 { { STATE_PSEXCM }, 'i' },
4652 { { STATE_PSINTLEVEL }, 'i' }
4653 };
4654
4655 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = {
4656 { { 6 /* art */ }, 'o' }
4657 };
4658
4659 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = {
4660 { { STATE_PSEXCM }, 'i' },
4661 { { STATE_PSRING }, 'i' },
4662 { { STATE_DBREAKA0 }, 'i' }
4663 };
4664
4665 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = {
4666 { { 6 /* art */ }, 'i' }
4667 };
4668
4669 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = {
4670 { { STATE_PSEXCM }, 'i' },
4671 { { STATE_PSRING }, 'i' },
4672 { { STATE_DBREAKA0 }, 'o' },
4673 { { STATE_XTSYNC }, 'o' }
4674 };
4675
4676 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = {
4677 { { 6 /* art */ }, 'm' }
4678 };
4679
4680 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = {
4681 { { STATE_PSEXCM }, 'i' },
4682 { { STATE_PSRING }, 'i' },
4683 { { STATE_DBREAKA0 }, 'm' },
4684 { { STATE_XTSYNC }, 'o' }
4685 };
4686
4687 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = {
4688 { { 6 /* art */ }, 'o' }
4689 };
4690
4691 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = {
4692 { { STATE_PSEXCM }, 'i' },
4693 { { STATE_PSRING }, 'i' },
4694 { { STATE_DBREAKC0 }, 'i' }
4695 };
4696
4697 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = {
4698 { { 6 /* art */ }, 'i' }
4699 };
4700
4701 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = {
4702 { { STATE_PSEXCM }, 'i' },
4703 { { STATE_PSRING }, 'i' },
4704 { { STATE_DBREAKC0 }, 'o' },
4705 { { STATE_XTSYNC }, 'o' }
4706 };
4707
4708 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = {
4709 { { 6 /* art */ }, 'm' }
4710 };
4711
4712 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = {
4713 { { STATE_PSEXCM }, 'i' },
4714 { { STATE_PSRING }, 'i' },
4715 { { STATE_DBREAKC0 }, 'm' },
4716 { { STATE_XTSYNC }, 'o' }
4717 };
4718
4719 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = {
4720 { { 6 /* art */ }, 'o' }
4721 };
4722
4723 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = {
4724 { { STATE_PSEXCM }, 'i' },
4725 { { STATE_PSRING }, 'i' },
4726 { { STATE_DBREAKA1 }, 'i' }
4727 };
4728
4729 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = {
4730 { { 6 /* art */ }, 'i' }
4731 };
4732
4733 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = {
4734 { { STATE_PSEXCM }, 'i' },
4735 { { STATE_PSRING }, 'i' },
4736 { { STATE_DBREAKA1 }, 'o' },
4737 { { STATE_XTSYNC }, 'o' }
4738 };
4739
4740 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = {
4741 { { 6 /* art */ }, 'm' }
4742 };
4743
4744 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = {
4745 { { STATE_PSEXCM }, 'i' },
4746 { { STATE_PSRING }, 'i' },
4747 { { STATE_DBREAKA1 }, 'm' },
4748 { { STATE_XTSYNC }, 'o' }
4749 };
4750
4751 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = {
4752 { { 6 /* art */ }, 'o' }
4753 };
4754
4755 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = {
4756 { { STATE_PSEXCM }, 'i' },
4757 { { STATE_PSRING }, 'i' },
4758 { { STATE_DBREAKC1 }, 'i' }
4759 };
4760
4761 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = {
4762 { { 6 /* art */ }, 'i' }
4763 };
4764
4765 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = {
4766 { { STATE_PSEXCM }, 'i' },
4767 { { STATE_PSRING }, 'i' },
4768 { { STATE_DBREAKC1 }, 'o' },
4769 { { STATE_XTSYNC }, 'o' }
4770 };
4771
4772 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = {
4773 { { 6 /* art */ }, 'm' }
4774 };
4775
4776 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = {
4777 { { STATE_PSEXCM }, 'i' },
4778 { { STATE_PSRING }, 'i' },
4779 { { STATE_DBREAKC1 }, 'm' },
4780 { { STATE_XTSYNC }, 'o' }
4781 };
4782
4783 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = {
4784 { { 6 /* art */ }, 'o' }
4785 };
4786
4787 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = {
4788 { { STATE_PSEXCM }, 'i' },
4789 { { STATE_PSRING }, 'i' },
4790 { { STATE_IBREAKA0 }, 'i' }
4791 };
4792
4793 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = {
4794 { { 6 /* art */ }, 'i' }
4795 };
4796
4797 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = {
4798 { { STATE_PSEXCM }, 'i' },
4799 { { STATE_PSRING }, 'i' },
4800 { { STATE_IBREAKA0 }, 'o' }
4801 };
4802
4803 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = {
4804 { { 6 /* art */ }, 'm' }
4805 };
4806
4807 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = {
4808 { { STATE_PSEXCM }, 'i' },
4809 { { STATE_PSRING }, 'i' },
4810 { { STATE_IBREAKA0 }, 'm' }
4811 };
4812
4813 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = {
4814 { { 6 /* art */ }, 'o' }
4815 };
4816
4817 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = {
4818 { { STATE_PSEXCM }, 'i' },
4819 { { STATE_PSRING }, 'i' },
4820 { { STATE_IBREAKA1 }, 'i' }
4821 };
4822
4823 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = {
4824 { { 6 /* art */ }, 'i' }
4825 };
4826
4827 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = {
4828 { { STATE_PSEXCM }, 'i' },
4829 { { STATE_PSRING }, 'i' },
4830 { { STATE_IBREAKA1 }, 'o' }
4831 };
4832
4833 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = {
4834 { { 6 /* art */ }, 'm' }
4835 };
4836
4837 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = {
4838 { { STATE_PSEXCM }, 'i' },
4839 { { STATE_PSRING }, 'i' },
4840 { { STATE_IBREAKA1 }, 'm' }
4841 };
4842
4843 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = {
4844 { { 6 /* art */ }, 'o' }
4845 };
4846
4847 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = {
4848 { { STATE_PSEXCM }, 'i' },
4849 { { STATE_PSRING }, 'i' },
4850 { { STATE_IBREAKENABLE }, 'i' }
4851 };
4852
4853 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = {
4854 { { 6 /* art */ }, 'i' }
4855 };
4856
4857 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = {
4858 { { STATE_PSEXCM }, 'i' },
4859 { { STATE_PSRING }, 'i' },
4860 { { STATE_IBREAKENABLE }, 'o' }
4861 };
4862
4863 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = {
4864 { { 6 /* art */ }, 'm' }
4865 };
4866
4867 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = {
4868 { { STATE_PSEXCM }, 'i' },
4869 { { STATE_PSRING }, 'i' },
4870 { { STATE_IBREAKENABLE }, 'm' }
4871 };
4872
4873 static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = {
4874 { { 6 /* art */ }, 'o' }
4875 };
4876
4877 static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = {
4878 { { STATE_PSEXCM }, 'i' },
4879 { { STATE_PSRING }, 'i' },
4880 { { STATE_DEBUGCAUSE }, 'i' },
4881 { { STATE_DBNUM }, 'i' }
4882 };
4883
4884 static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = {
4885 { { 6 /* art */ }, 'i' }
4886 };
4887
4888 static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = {
4889 { { STATE_PSEXCM }, 'i' },
4890 { { STATE_PSRING }, 'i' },
4891 { { STATE_DEBUGCAUSE }, 'o' },
4892 { { STATE_DBNUM }, 'o' }
4893 };
4894
4895 static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = {
4896 { { 6 /* art */ }, 'm' }
4897 };
4898
4899 static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = {
4900 { { STATE_PSEXCM }, 'i' },
4901 { { STATE_PSRING }, 'i' },
4902 { { STATE_DEBUGCAUSE }, 'm' },
4903 { { STATE_DBNUM }, 'm' }
4904 };
4905
4906 static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = {
4907 { { 6 /* art */ }, 'o' }
4908 };
4909
4910 static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = {
4911 { { STATE_PSEXCM }, 'i' },
4912 { { STATE_PSRING }, 'i' },
4913 { { STATE_ICOUNT }, 'i' }
4914 };
4915
4916 static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = {
4917 { { 6 /* art */ }, 'i' }
4918 };
4919
4920 static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = {
4921 { { STATE_PSEXCM }, 'i' },
4922 { { STATE_PSRING }, 'i' },
4923 { { STATE_XTSYNC }, 'o' },
4924 { { STATE_ICOUNT }, 'o' }
4925 };
4926
4927 static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = {
4928 { { 6 /* art */ }, 'm' }
4929 };
4930
4931 static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = {
4932 { { STATE_PSEXCM }, 'i' },
4933 { { STATE_PSRING }, 'i' },
4934 { { STATE_XTSYNC }, 'o' },
4935 { { STATE_ICOUNT }, 'm' }
4936 };
4937
4938 static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = {
4939 { { 6 /* art */ }, 'o' }
4940 };
4941
4942 static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = {
4943 { { STATE_PSEXCM }, 'i' },
4944 { { STATE_PSRING }, 'i' },
4945 { { STATE_ICOUNTLEVEL }, 'i' }
4946 };
4947
4948 static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = {
4949 { { 6 /* art */ }, 'i' }
4950 };
4951
4952 static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = {
4953 { { STATE_PSEXCM }, 'i' },
4954 { { STATE_PSRING }, 'i' },
4955 { { STATE_ICOUNTLEVEL }, 'o' }
4956 };
4957
4958 static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = {
4959 { { 6 /* art */ }, 'm' }
4960 };
4961
4962 static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = {
4963 { { STATE_PSEXCM }, 'i' },
4964 { { STATE_PSRING }, 'i' },
4965 { { STATE_ICOUNTLEVEL }, 'm' }
4966 };
4967
4968 static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = {
4969 { { 6 /* art */ }, 'o' }
4970 };
4971
4972 static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = {
4973 { { STATE_PSEXCM }, 'i' },
4974 { { STATE_PSRING }, 'i' },
4975 { { STATE_DDR }, 'i' }
4976 };
4977
4978 static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = {
4979 { { 6 /* art */ }, 'i' }
4980 };
4981
4982 static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = {
4983 { { STATE_PSEXCM }, 'i' },
4984 { { STATE_PSRING }, 'i' },
4985 { { STATE_XTSYNC }, 'o' },
4986 { { STATE_DDR }, 'o' }
4987 };
4988
4989 static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = {
4990 { { 6 /* art */ }, 'm' }
4991 };
4992
4993 static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = {
4994 { { STATE_PSEXCM }, 'i' },
4995 { { STATE_PSRING }, 'i' },
4996 { { STATE_XTSYNC }, 'o' },
4997 { { STATE_DDR }, 'm' }
4998 };
4999
5000 static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = {
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