@samitouri / QOSamiQemu
Code Commits Issues Pulls Sessions CI/CD
master
master
inc 15,205 lines 352 KB
Raw
1 /* Xtensa configuration-specific ISA information.
2
3 Customer ID=4869; Build=0x2cfec; Copyright (c) 2003-2010 Tensilica Inc.
4
5 Permission is hereby granted, free of charge, to any person obtaining
6 a copy of this software and associated documentation files (the
7 "Software"), to deal in the Software without restriction, including
8 without limitation the rights to use, copy, modify, merge, publish,
9 distribute, sublicense, and/or sell copies of the Software, and to
10 permit persons to whom the Software is furnished to do so, subject to
11 the following conditions:
12
13 The above copyright notice and this permission notice shall be included
14 in all copies or substantial portions of the Software.
15
16 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
17 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
19 IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
20 CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
23
24 #include "qemu/osdep.h"
25 #include "xtensa-isa.h"
26 #include "xtensa-isa-internal.h"
27
28
29 /* Sysregs. */
30
31 static xtensa_sysreg_internal sysregs[] = {
32 { "LBEG", 0, 0 },
33 { "LEND", 1, 0 },
34 { "LCOUNT", 2, 0 },
35 { "ACCLO", 16, 0 },
36 { "ACCHI", 17, 0 },
37 { "M0", 32, 0 },
38 { "M1", 33, 0 },
39 { "M2", 34, 0 },
40 { "M3", 35, 0 },
41 { "PTEVADDR", 83, 0 },
42 { "MMID", 89, 0 },
43 { "DDR", 104, 0 },
44 { "176", 176, 0 },
45 { "208", 208, 0 },
46 { "INTERRUPT", 226, 0 },
47 { "INTCLEAR", 227, 0 },
48 { "CCOUNT", 234, 0 },
49 { "PRID", 235, 0 },
50 { "ICOUNT", 236, 0 },
51 { "CCOMPARE0", 240, 0 },
52 { "CCOMPARE1", 241, 0 },
53 { "CCOMPARE2", 242, 0 },
54 { "VECBASE", 231, 0 },
55 { "EPC1", 177, 0 },
56 { "EPC2", 178, 0 },
57 { "EPC3", 179, 0 },
58 { "EPC4", 180, 0 },
59 { "EPC5", 181, 0 },
60 { "EPC6", 182, 0 },
61 { "EPC7", 183, 0 },
62 { "EXCSAVE1", 209, 0 },
63 { "EXCSAVE2", 210, 0 },
64 { "EXCSAVE3", 211, 0 },
65 { "EXCSAVE4", 212, 0 },
66 { "EXCSAVE5", 213, 0 },
67 { "EXCSAVE6", 214, 0 },
68 { "EXCSAVE7", 215, 0 },
69 { "EPS2", 194, 0 },
70 { "EPS3", 195, 0 },
71 { "EPS4", 196, 0 },
72 { "EPS5", 197, 0 },
73 { "EPS6", 198, 0 },
74 { "EPS7", 199, 0 },
75 { "EXCCAUSE", 232, 0 },
76 { "DEPC", 192, 0 },
77 { "EXCVADDR", 238, 0 },
78 { "WINDOWBASE", 72, 0 },
79 { "WINDOWSTART", 73, 0 },
80 { "SAR", 3, 0 },
81 { "LITBASE", 5, 0 },
82 { "PS", 230, 0 },
83 { "MISC0", 244, 0 },
84 { "MISC1", 245, 0 },
85 { "INTENABLE", 228, 0 },
86 { "DBREAKA0", 144, 0 },
87 { "DBREAKC0", 160, 0 },
88 { "DBREAKA1", 145, 0 },
89 { "DBREAKC1", 161, 0 },
90 { "IBREAKA0", 128, 0 },
91 { "IBREAKA1", 129, 0 },
92 { "IBREAKENABLE", 96, 0 },
93 { "ICOUNTLEVEL", 237, 0 },
94 { "DEBUGCAUSE", 233, 0 },
95 { "RASID", 90, 0 },
96 { "ITLBCFG", 91, 0 },
97 { "DTLBCFG", 92, 0 },
98 { "CPENABLE", 224, 0 },
99 { "SCOMPARE1", 12, 0 },
100 { "ATOMCTL", 99, 0 },
101 { "THREADPTR", 231, 1 },
102 { "EXPSTATE", 230, 1 }
103 };
104
105 #define NUM_SYSREGS 71
106 #define MAX_SPECIAL_REG 245
107 #define MAX_USER_REG 231
108
109
110 /* Processor states. */
111
112 static xtensa_state_internal states[] = {
113 { "LCOUNT", 32, 0 },
114 { "PC", 32, 0 },
115 { "ICOUNT", 32, 0 },
116 { "DDR", 32, 0 },
117 { "INTERRUPT", 22, 0 },
118 { "CCOUNT", 32, 0 },
119 { "XTSYNC", 1, 0 },
120 { "VECBASE", 22, 0 },
121 { "EPC1", 32, 0 },
122 { "EPC2", 32, 0 },
123 { "EPC3", 32, 0 },
124 { "EPC4", 32, 0 },
125 { "EPC5", 32, 0 },
126 { "EPC6", 32, 0 },
127 { "EPC7", 32, 0 },
128 { "EXCSAVE1", 32, 0 },
129 { "EXCSAVE2", 32, 0 },
130 { "EXCSAVE3", 32, 0 },
131 { "EXCSAVE4", 32, 0 },
132 { "EXCSAVE5", 32, 0 },
133 { "EXCSAVE6", 32, 0 },
134 { "EXCSAVE7", 32, 0 },
135 { "EPS2", 15, 0 },
136 { "EPS3", 15, 0 },
137 { "EPS4", 15, 0 },
138 { "EPS5", 15, 0 },
139 { "EPS6", 15, 0 },
140 { "EPS7", 15, 0 },
141 { "EXCCAUSE", 6, 0 },
142 { "PSINTLEVEL", 4, 0 },
143 { "PSUM", 1, 0 },
144 { "PSWOE", 1, 0 },
145 { "PSRING", 2, 0 },
146 { "PSEXCM", 1, 0 },
147 { "DEPC", 32, 0 },
148 { "EXCVADDR", 32, 0 },
149 { "WindowBase", 3, 0 },
150 { "WindowStart", 8, 0 },
151 { "PSCALLINC", 2, 0 },
152 { "PSOWB", 4, 0 },
153 { "LBEG", 32, 0 },
154 { "LEND", 32, 0 },
155 { "SAR", 6, 0 },
156 { "THREADPTR", 32, 0 },
157 { "LITBADDR", 20, 0 },
158 { "LITBEN", 1, 0 },
159 { "MISC0", 32, 0 },
160 { "MISC1", 32, 0 },
161 { "ACC", 40, 0 },
162 { "InOCDMode", 1, 0 },
163 { "INTENABLE", 22, 0 },
164 { "DBREAKA0", 32, 0 },
165 { "DBREAKC0", 8, 0 },
166 { "DBREAKA1", 32, 0 },
167 { "DBREAKC1", 8, 0 },
168 { "IBREAKA0", 32, 0 },
169 { "IBREAKA1", 32, 0 },
170 { "IBREAKENABLE", 2, 0 },
171 { "ICOUNTLEVEL", 4, 0 },
172 { "DEBUGCAUSE", 6, 0 },
173 { "DBNUM", 4, 0 },
174 { "CCOMPARE0", 32, 0 },
175 { "CCOMPARE1", 32, 0 },
176 { "CCOMPARE2", 32, 0 },
177 { "ASID3", 8, 0 },
178 { "ASID2", 8, 0 },
179 { "ASID1", 8, 0 },
180 { "INSTPGSZID6", 1, 0 },
181 { "INSTPGSZID5", 1, 0 },
182 { "INSTPGSZID4", 2, 0 },
183 { "DATAPGSZID6", 1, 0 },
184 { "DATAPGSZID5", 1, 0 },
185 { "DATAPGSZID4", 2, 0 },
186 { "PTBASE", 10, 0 },
187 { "CPENABLE", 8, 0 },
188 { "SCOMPARE1", 32, 0 },
189 { "ATOMCTL", 6, 0 },
190 { "EXPSTATE", 32, XTENSA_STATE_IS_EXPORTED }
191 };
192
193 #define NUM_STATES 78
194
195 enum xtensa_state_id {
196 STATE_LCOUNT,
197 STATE_PC,
198 STATE_ICOUNT,
199 STATE_DDR,
200 STATE_INTERRUPT,
201 STATE_CCOUNT,
202 STATE_XTSYNC,
203 STATE_VECBASE,
204 STATE_EPC1,
205 STATE_EPC2,
206 STATE_EPC3,
207 STATE_EPC4,
208 STATE_EPC5,
209 STATE_EPC6,
210 STATE_EPC7,
211 STATE_EXCSAVE1,
212 STATE_EXCSAVE2,
213 STATE_EXCSAVE3,
214 STATE_EXCSAVE4,
215 STATE_EXCSAVE5,
216 STATE_EXCSAVE6,
217 STATE_EXCSAVE7,
218 STATE_EPS2,
219 STATE_EPS3,
220 STATE_EPS4,
221 STATE_EPS5,
222 STATE_EPS6,
223 STATE_EPS7,
224 STATE_EXCCAUSE,
225 STATE_PSINTLEVEL,
226 STATE_PSUM,
227 STATE_PSWOE,
228 STATE_PSRING,
229 STATE_PSEXCM,
230 STATE_DEPC,
231 STATE_EXCVADDR,
232 STATE_WindowBase,
233 STATE_WindowStart,
234 STATE_PSCALLINC,
235 STATE_PSOWB,
236 STATE_LBEG,
237 STATE_LEND,
238 STATE_SAR,
239 STATE_THREADPTR,
240 STATE_LITBADDR,
241 STATE_LITBEN,
242 STATE_MISC0,
243 STATE_MISC1,
244 STATE_ACC,
245 STATE_InOCDMode,
246 STATE_INTENABLE,
247 STATE_DBREAKA0,
248 STATE_DBREAKC0,
249 STATE_DBREAKA1,
250 STATE_DBREAKC1,
251 STATE_IBREAKA0,
252 STATE_IBREAKA1,
253 STATE_IBREAKENABLE,
254 STATE_ICOUNTLEVEL,
255 STATE_DEBUGCAUSE,
256 STATE_DBNUM,
257 STATE_CCOMPARE0,
258 STATE_CCOMPARE1,
259 STATE_CCOMPARE2,
260 STATE_ASID3,
261 STATE_ASID2,
262 STATE_ASID1,
263 STATE_INSTPGSZID6,
264 STATE_INSTPGSZID5,
265 STATE_INSTPGSZID4,
266 STATE_DATAPGSZID6,
267 STATE_DATAPGSZID5,
268 STATE_DATAPGSZID4,
269 STATE_PTBASE,
270 STATE_CPENABLE,
271 STATE_SCOMPARE1,
272 STATE_ATOMCTL,
273 STATE_EXPSTATE
274 };
275
276
277 /* Field definitions. */
278
279 static unsigned
280 Field_t_Slot_inst_get (const xtensa_insnbuf insn)
281 {
282 unsigned tie_t = 0;
283 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
284 return tie_t;
285 }
286
287 static void
288 Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
289 {
290 uint32 tie_t;
291 tie_t = (val << 28) >> 28;
292 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
293 }
294
295 static unsigned
296 Field_s_Slot_inst_get (const xtensa_insnbuf insn)
297 {
298 unsigned tie_t = 0;
299 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
300 return tie_t;
301 }
302
303 static void
304 Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
305 {
306 uint32 tie_t;
307 tie_t = (val << 28) >> 28;
308 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
309 }
310
311 static unsigned
312 Field_r_Slot_inst_get (const xtensa_insnbuf insn)
313 {
314 unsigned tie_t = 0;
315 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
316 return tie_t;
317 }
318
319 static void
320 Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
321 {
322 uint32 tie_t;
323 tie_t = (val << 28) >> 28;
324 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
325 }
326
327 static unsigned
328 Field_op2_Slot_inst_get (const xtensa_insnbuf insn)
329 {
330 unsigned tie_t = 0;
331 tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28);
332 return tie_t;
333 }
334
335 static void
336 Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
337 {
338 uint32 tie_t;
339 tie_t = (val << 28) >> 28;
340 insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20);
341 }
342
343 static unsigned
344 Field_op1_Slot_inst_get (const xtensa_insnbuf insn)
345 {
346 unsigned tie_t = 0;
347 tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
348 return tie_t;
349 }
350
351 static void
352 Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
353 {
354 uint32 tie_t;
355 tie_t = (val << 28) >> 28;
356 insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
357 }
358
359 static unsigned
360 Field_op0_Slot_inst_get (const xtensa_insnbuf insn)
361 {
362 unsigned tie_t = 0;
363 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
364 return tie_t;
365 }
366
367 static void
368 Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
369 {
370 uint32 tie_t;
371 tie_t = (val << 28) >> 28;
372 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
373 }
374
375 static unsigned
376 Field_n_Slot_inst_get (const xtensa_insnbuf insn)
377 {
378 unsigned tie_t = 0;
379 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
380 return tie_t;
381 }
382
383 static void
384 Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
385 {
386 uint32 tie_t;
387 tie_t = (val << 30) >> 30;
388 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
389 }
390
391 static unsigned
392 Field_m_Slot_inst_get (const xtensa_insnbuf insn)
393 {
394 unsigned tie_t = 0;
395 tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
396 return tie_t;
397 }
398
399 static void
400 Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
401 {
402 uint32 tie_t;
403 tie_t = (val << 30) >> 30;
404 insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
405 }
406
407 static unsigned
408 Field_sr_Slot_inst_get (const xtensa_insnbuf insn)
409 {
410 unsigned tie_t = 0;
411 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
412 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
413 return tie_t;
414 }
415
416 static void
417 Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
418 {
419 uint32 tie_t;
420 tie_t = (val << 28) >> 28;
421 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
422 tie_t = (val << 24) >> 28;
423 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
424 }
425
426 static unsigned
427 Field_st_Slot_inst_get (const xtensa_insnbuf insn)
428 {
429 unsigned tie_t = 0;
430 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
431 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
432 return tie_t;
433 }
434
435 static void
436 Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
437 {
438 uint32 tie_t;
439 tie_t = (val << 28) >> 28;
440 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
441 tie_t = (val << 24) >> 28;
442 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
443 }
444
445 static unsigned
446 Field_thi3_Slot_inst_get (const xtensa_insnbuf insn)
447 {
448 unsigned tie_t = 0;
449 tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
450 return tie_t;
451 }
452
453 static void
454 Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
455 {
456 uint32 tie_t;
457 tie_t = (val << 29) >> 29;
458 insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
459 }
460
461 static unsigned
462 Field_t3_Slot_inst_get (const xtensa_insnbuf insn)
463 {
464 unsigned tie_t = 0;
465 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
466 return tie_t;
467 }
468
469 static void
470 Field_t3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
471 {
472 uint32 tie_t;
473 tie_t = (val << 31) >> 31;
474 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
475 }
476
477 static unsigned
478 Field_tlo_Slot_inst_get (const xtensa_insnbuf insn)
479 {
480 unsigned tie_t = 0;
481 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
482 return tie_t;
483 }
484
485 static void
486 Field_tlo_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
487 {
488 uint32 tie_t;
489 tie_t = (val << 30) >> 30;
490 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
491 }
492
493 static unsigned
494 Field_w_Slot_inst_get (const xtensa_insnbuf insn)
495 {
496 unsigned tie_t = 0;
497 tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30);
498 return tie_t;
499 }
500
501 static void
502 Field_w_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
503 {
504 uint32 tie_t;
505 tie_t = (val << 30) >> 30;
506 insn[0] = (insn[0] & ~0x3000) | (tie_t << 12);
507 }
508
509 static unsigned
510 Field_r3_Slot_inst_get (const xtensa_insnbuf insn)
511 {
512 unsigned tie_t = 0;
513 tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
514 return tie_t;
515 }
516
517 static void
518 Field_r3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
519 {
520 uint32 tie_t;
521 tie_t = (val << 31) >> 31;
522 insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
523 }
524
525 static unsigned
526 Field_rhi_Slot_inst_get (const xtensa_insnbuf insn)
527 {
528 unsigned tie_t = 0;
529 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
530 return tie_t;
531 }
532
533 static void
534 Field_rhi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
535 {
536 uint32 tie_t;
537 tie_t = (val << 30) >> 30;
538 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
539 }
540
541 static unsigned
542 Field_s3to1_Slot_inst_get (const xtensa_insnbuf insn)
543 {
544 unsigned tie_t = 0;
545 tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
546 return tie_t;
547 }
548
549 static void
550 Field_s3to1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
551 {
552 uint32 tie_t;
553 tie_t = (val << 29) >> 29;
554 insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
555 }
556
557 static unsigned
558 Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn)
559 {
560 unsigned tie_t = 0;
561 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
562 return tie_t;
563 }
564
565 static void
566 Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
567 {
568 uint32 tie_t;
569 tie_t = (val << 28) >> 28;
570 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
571 }
572
573 static unsigned
574 Field_t_Slot_inst16b_get (const xtensa_insnbuf insn)
575 {
576 unsigned tie_t = 0;
577 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
578 return tie_t;
579 }
580
581 static void
582 Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
583 {
584 uint32 tie_t;
585 tie_t = (val << 28) >> 28;
586 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
587 }
588
589 static unsigned
590 Field_r_Slot_inst16b_get (const xtensa_insnbuf insn)
591 {
592 unsigned tie_t = 0;
593 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
594 return tie_t;
595 }
596
597 static void
598 Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
599 {
600 uint32 tie_t;
601 tie_t = (val << 28) >> 28;
602 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
603 }
604
605 static unsigned
606 Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn)
607 {
608 unsigned tie_t = 0;
609 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
610 return tie_t;
611 }
612
613 static void
614 Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
615 {
616 uint32 tie_t;
617 tie_t = (val << 28) >> 28;
618 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
619 }
620
621 static unsigned
622 Field_z_Slot_inst16b_get (const xtensa_insnbuf insn)
623 {
624 unsigned tie_t = 0;
625 tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
626 return tie_t;
627 }
628
629 static void
630 Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
631 {
632 uint32 tie_t;
633 tie_t = (val << 31) >> 31;
634 insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
635 }
636
637 static unsigned
638 Field_i_Slot_inst16b_get (const xtensa_insnbuf insn)
639 {
640 unsigned tie_t = 0;
641 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
642 return tie_t;
643 }
644
645 static void
646 Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
647 {
648 uint32 tie_t;
649 tie_t = (val << 31) >> 31;
650 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
651 }
652
653 static unsigned
654 Field_s_Slot_inst16b_get (const xtensa_insnbuf insn)
655 {
656 unsigned tie_t = 0;
657 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
658 return tie_t;
659 }
660
661 static void
662 Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
663 {
664 uint32 tie_t;
665 tie_t = (val << 28) >> 28;
666 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
667 }
668
669 static unsigned
670 Field_t_Slot_inst16a_get (const xtensa_insnbuf insn)
671 {
672 unsigned tie_t = 0;
673 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
674 return tie_t;
675 }
676
677 static void
678 Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
679 {
680 uint32 tie_t;
681 tie_t = (val << 28) >> 28;
682 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
683 }
684
685 static unsigned
686 Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn)
687 {
688 unsigned tie_t = 0;
689 tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
690 return tie_t;
691 }
692
693 static void
694 Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
695 {
696 uint32 tie_t;
697 tie_t = (val << 31) >> 31;
698 insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
699 }
700
701 static unsigned
702 Field_bbi_Slot_inst_get (const xtensa_insnbuf insn)
703 {
704 unsigned tie_t = 0;
705 tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
706 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
707 return tie_t;
708 }
709
710 static void
711 Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
712 {
713 uint32 tie_t;
714 tie_t = (val << 28) >> 28;
715 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
716 tie_t = (val << 27) >> 31;
717 insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
718 }
719
720 static unsigned
721 Field_imm12_Slot_inst_get (const xtensa_insnbuf insn)
722 {
723 unsigned tie_t = 0;
724 tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20);
725 return tie_t;
726 }
727
728 static void
729 Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
730 {
731 uint32 tie_t;
732 tie_t = (val << 20) >> 20;
733 insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12);
734 }
735
736 static unsigned
737 Field_imm8_Slot_inst_get (const xtensa_insnbuf insn)
738 {
739 unsigned tie_t = 0;
740 tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
741 return tie_t;
742 }
743
744 static void
745 Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
746 {
747 uint32 tie_t;
748 tie_t = (val << 24) >> 24;
749 insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
750 }
751
752 static unsigned
753 Field_s_Slot_inst16a_get (const xtensa_insnbuf insn)
754 {
755 unsigned tie_t = 0;
756 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
757 return tie_t;
758 }
759
760 static void
761 Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
762 {
763 uint32 tie_t;
764 tie_t = (val << 28) >> 28;
765 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
766 }
767
768 static unsigned
769 Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn)
770 {
771 unsigned tie_t = 0;
772 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
773 tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
774 return tie_t;
775 }
776
777 static void
778 Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
779 {
780 uint32 tie_t;
781 tie_t = (val << 24) >> 24;
782 insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
783 tie_t = (val << 20) >> 28;
784 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
785 }
786
787 static unsigned
788 Field_imm16_Slot_inst_get (const xtensa_insnbuf insn)
789 {
790 unsigned tie_t = 0;
791 tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16);
792 return tie_t;
793 }
794
795 static void
796 Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
797 {
798 uint32 tie_t;
799 tie_t = (val << 16) >> 16;
800 insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8);
801 }
802
803 static unsigned
804 Field_offset_Slot_inst_get (const xtensa_insnbuf insn)
805 {
806 unsigned tie_t = 0;
807 tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
808 return tie_t;
809 }
810
811 static void
812 Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
813 {
814 uint32 tie_t;
815 tie_t = (val << 14) >> 14;
816 insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
817 }
818
819 static unsigned
820 Field_r_Slot_inst16a_get (const xtensa_insnbuf insn)
821 {
822 unsigned tie_t = 0;
823 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
824 return tie_t;
825 }
826
827 static void
828 Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
829 {
830 uint32 tie_t;
831 tie_t = (val << 28) >> 28;
832 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
833 }
834
835 static unsigned
836 Field_sa4_Slot_inst_get (const xtensa_insnbuf insn)
837 {
838 unsigned tie_t = 0;
839 tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
840 return tie_t;
841 }
842
843 static void
844 Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
845 {
846 uint32 tie_t;
847 tie_t = (val << 31) >> 31;
848 insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
849 }
850
851 static unsigned
852 Field_sae4_Slot_inst_get (const xtensa_insnbuf insn)
853 {
854 unsigned tie_t = 0;
855 tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
856 return tie_t;
857 }
858
859 static void
860 Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
861 {
862 uint32 tie_t;
863 tie_t = (val << 31) >> 31;
864 insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
865 }
866
867 static unsigned
868 Field_sae_Slot_inst_get (const xtensa_insnbuf insn)
869 {
870 unsigned tie_t = 0;
871 tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
872 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
873 return tie_t;
874 }
875
876 static void
877 Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
878 {
879 uint32 tie_t;
880 tie_t = (val << 28) >> 28;
881 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
882 tie_t = (val << 27) >> 31;
883 insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
884 }
885
886 static unsigned
887 Field_sal_Slot_inst_get (const xtensa_insnbuf insn)
888 {
889 unsigned tie_t = 0;
890 tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
891 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
892 return tie_t;
893 }
894
895 static void
896 Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
897 {
898 uint32 tie_t;
899 tie_t = (val << 28) >> 28;
900 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
901 tie_t = (val << 27) >> 31;
902 insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
903 }
904
905 static unsigned
906 Field_sargt_Slot_inst_get (const xtensa_insnbuf insn)
907 {
908 unsigned tie_t = 0;
909 tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
910 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
911 return tie_t;
912 }
913
914 static void
915 Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
916 {
917 uint32 tie_t;
918 tie_t = (val << 28) >> 28;
919 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
920 tie_t = (val << 27) >> 31;
921 insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
922 }
923
924 static unsigned
925 Field_sas4_Slot_inst_get (const xtensa_insnbuf insn)
926 {
927 unsigned tie_t = 0;
928 tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
929 return tie_t;
930 }
931
932 static void
933 Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
934 {
935 uint32 tie_t;
936 tie_t = (val << 31) >> 31;
937 insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
938 }
939
940 static unsigned
941 Field_sas_Slot_inst_get (const xtensa_insnbuf insn)
942 {
943 unsigned tie_t = 0;
944 tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
945 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
946 return tie_t;
947 }
948
949 static void
950 Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
951 {
952 uint32 tie_t;
953 tie_t = (val << 28) >> 28;
954 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
955 tie_t = (val << 27) >> 31;
956 insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
957 }
958
959 static unsigned
960 Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn)
961 {
962 unsigned tie_t = 0;
963 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
964 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
965 return tie_t;
966 }
967
968 static void
969 Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
970 {
971 uint32 tie_t;
972 tie_t = (val << 28) >> 28;
973 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
974 tie_t = (val << 24) >> 28;
975 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
976 }
977
978 static unsigned
979 Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn)
980 {
981 unsigned tie_t = 0;
982 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
983 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
984 return tie_t;
985 }
986
987 static void
988 Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
989 {
990 uint32 tie_t;
991 tie_t = (val << 28) >> 28;
992 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
993 tie_t = (val << 24) >> 28;
994 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
995 }
996
997 static unsigned
998 Field_st_Slot_inst16a_get (const xtensa_insnbuf insn)
999 {
1000 unsigned tie_t = 0;
1001 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
1002 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1003 return tie_t;
1004 }
1005
1006 static void
1007 Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1008 {
1009 uint32 tie_t;
1010 tie_t = (val << 28) >> 28;
1011 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1012 tie_t = (val << 24) >> 28;
1013 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1014 }
1015
1016 static unsigned
1017 Field_st_Slot_inst16b_get (const xtensa_insnbuf insn)
1018 {
1019 unsigned tie_t = 0;
1020 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
1021 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1022 return tie_t;
1023 }
1024
1025 static void
1026 Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1027 {
1028 uint32 tie_t;
1029 tie_t = (val << 28) >> 28;
1030 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1031 tie_t = (val << 24) >> 28;
1032 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1033 }
1034
1035 static unsigned
1036 Field_imm4_Slot_inst_get (const xtensa_insnbuf insn)
1037 {
1038 unsigned tie_t = 0;
1039 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1040 return tie_t;
1041 }
1042
1043 static void
1044 Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1045 {
1046 uint32 tie_t;
1047 tie_t = (val << 28) >> 28;
1048 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1049 }
1050
1051 static unsigned
1052 Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn)
1053 {
1054 unsigned tie_t = 0;
1055 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1056 return tie_t;
1057 }
1058
1059 static void
1060 Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1061 {
1062 uint32 tie_t;
1063 tie_t = (val << 28) >> 28;
1064 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1065 }
1066
1067 static unsigned
1068 Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn)
1069 {
1070 unsigned tie_t = 0;
1071 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1072 return tie_t;
1073 }
1074
1075 static void
1076 Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1077 {
1078 uint32 tie_t;
1079 tie_t = (val << 28) >> 28;
1080 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1081 }
1082
1083 static unsigned
1084 Field_mn_Slot_inst_get (const xtensa_insnbuf insn)
1085 {
1086 unsigned tie_t = 0;
1087 tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
1088 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1089 return tie_t;
1090 }
1091
1092 static void
1093 Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1094 {
1095 uint32 tie_t;
1096 tie_t = (val << 30) >> 30;
1097 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1098 tie_t = (val << 28) >> 30;
1099 insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
1100 }
1101
1102 static unsigned
1103 Field_i_Slot_inst16a_get (const xtensa_insnbuf insn)
1104 {
1105 unsigned tie_t = 0;
1106 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
1107 return tie_t;
1108 }
1109
1110 static void
1111 Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1112 {
1113 uint32 tie_t;
1114 tie_t = (val << 31) >> 31;
1115 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
1116 }
1117
1118 static unsigned
1119 Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn)
1120 {
1121 unsigned tie_t = 0;
1122 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1123 return tie_t;
1124 }
1125
1126 static void
1127 Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1128 {
1129 uint32 tie_t;
1130 tie_t = (val << 28) >> 28;
1131 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1132 }
1133
1134 static unsigned
1135 Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn)
1136 {
1137 unsigned tie_t = 0;
1138 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1139 return tie_t;
1140 }
1141
1142 static void
1143 Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1144 {
1145 uint32 tie_t;
1146 tie_t = (val << 28) >> 28;
1147 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1148 }
1149
1150 static unsigned
1151 Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn)
1152 {
1153 unsigned tie_t = 0;
1154 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1155 return tie_t;
1156 }
1157
1158 static void
1159 Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1160 {
1161 uint32 tie_t;
1162 tie_t = (val << 30) >> 30;
1163 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1164 }
1165
1166 static unsigned
1167 Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn)
1168 {
1169 unsigned tie_t = 0;
1170 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1171 return tie_t;
1172 }
1173
1174 static void
1175 Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1176 {
1177 uint32 tie_t;
1178 tie_t = (val << 30) >> 30;
1179 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1180 }
1181
1182 static unsigned
1183 Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn)
1184 {
1185 unsigned tie_t = 0;
1186 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1187 return tie_t;
1188 }
1189
1190 static void
1191 Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1192 {
1193 uint32 tie_t;
1194 tie_t = (val << 28) >> 28;
1195 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1196 }
1197
1198 static unsigned
1199 Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn)
1200 {
1201 unsigned tie_t = 0;
1202 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1203 return tie_t;
1204 }
1205
1206 static void
1207 Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1208 {
1209 uint32 tie_t;
1210 tie_t = (val << 28) >> 28;
1211 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1212 }
1213
1214 static unsigned
1215 Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn)
1216 {
1217 unsigned tie_t = 0;
1218 tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
1219 return tie_t;
1220 }
1221
1222 static void
1223 Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1224 {
1225 uint32 tie_t;
1226 tie_t = (val << 29) >> 29;
1227 insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
1228 }
1229
1230 static unsigned
1231 Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn)
1232 {
1233 unsigned tie_t = 0;
1234 tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
1235 return tie_t;
1236 }
1237
1238 static void
1239 Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1240 {
1241 uint32 tie_t;
1242 tie_t = (val << 29) >> 29;
1243 insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
1244 }
1245
1246 static unsigned
1247 Field_z_Slot_inst16a_get (const xtensa_insnbuf insn)
1248 {
1249 unsigned tie_t = 0;
1250 tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
1251 return tie_t;
1252 }
1253
1254 static void
1255 Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1256 {
1257 uint32 tie_t;
1258 tie_t = (val << 31) >> 31;
1259 insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
1260 }
1261
1262 static unsigned
1263 Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn)
1264 {
1265 unsigned tie_t = 0;
1266 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1267 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1268 return tie_t;
1269 }
1270
1271 static void
1272 Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1273 {
1274 uint32 tie_t;
1275 tie_t = (val << 28) >> 28;
1276 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1277 tie_t = (val << 26) >> 30;
1278 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1279 }
1280
1281 static unsigned
1282 Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn)
1283 {
1284 unsigned tie_t = 0;
1285 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1286 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1287 return tie_t;
1288 }
1289
1290 static void
1291 Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1292 {
1293 uint32 tie_t;
1294 tie_t = (val << 28) >> 28;
1295 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1296 tie_t = (val << 26) >> 30;
1297 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1298 }
1299
1300 static unsigned
1301 Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn)
1302 {
1303 unsigned tie_t = 0;
1304 tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
1305 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1306 return tie_t;
1307 }
1308
1309 static void
1310 Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1311 {
1312 uint32 tie_t;
1313 tie_t = (val << 28) >> 28;
1314 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1315 tie_t = (val << 25) >> 29;
1316 insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
1317 }
1318
1319 static unsigned
1320 Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn)
1321 {
1322 unsigned tie_t = 0;
1323 tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
1324 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1325 return tie_t;
1326 }
1327
1328 static void
1329 Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1330 {
1331 uint32 tie_t;
1332 tie_t = (val << 28) >> 28;
1333 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1334 tie_t = (val << 25) >> 29;
1335 insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
1336 }
1337
1338 static unsigned
1339 Field_rbit2_Slot_inst_get (const xtensa_insnbuf insn)
1340 {
1341 unsigned tie_t = 0;
1342 tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
1343 return tie_t;
1344 }
1345
1346 static void
1347 Field_rbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1348 {
1349 uint32 tie_t;
1350 tie_t = (val << 31) >> 31;
1351 insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
1352 }
1353
1354 static unsigned
1355 Field_tbit2_Slot_inst_get (const xtensa_insnbuf insn)
1356 {
1357 unsigned tie_t = 0;
1358 tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
1359 return tie_t;
1360 }
1361
1362 static void
1363 Field_tbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1364 {
1365 uint32 tie_t;
1366 tie_t = (val << 31) >> 31;
1367 insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
1368 }
1369
1370 static unsigned
1371 Field_y_Slot_inst_get (const xtensa_insnbuf insn)
1372 {
1373 unsigned tie_t = 0;
1374 tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
1375 return tie_t;
1376 }
1377
1378 static void
1379 Field_y_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1380 {
1381 uint32 tie_t;
1382 tie_t = (val << 31) >> 31;
1383 insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
1384 }
1385
1386 static unsigned
1387 Field_x_Slot_inst_get (const xtensa_insnbuf insn)
1388 {
1389 unsigned tie_t = 0;
1390 tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
1391 return tie_t;
1392 }
1393
1394 static void
1395 Field_x_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1396 {
1397 uint32 tie_t;
1398 tie_t = (val << 31) >> 31;
1399 insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
1400 }
1401
1402 static unsigned
1403 Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn)
1404 {
1405 unsigned tie_t = 0;
1406 tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17);
1407 return tie_t;
1408 }
1409
1410 static void
1411 Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1412 {
1413 uint32 tie_t;
1414 tie_t = (val << 17) >> 17;
1415 insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9);
1416 }
1417
1418 static unsigned
1419 Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn)
1420 {
1421 unsigned tie_t = 0;
1422 tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
1423 return tie_t;
1424 }
1425
1426 static void
1427 Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1428 {
1429 uint32 tie_t;
1430 tie_t = (val << 14) >> 14;
1431 insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
1432 }
1433
1434 static unsigned
1435 Field_bitindex_Slot_inst_get (const xtensa_insnbuf insn)
1436 {
1437 unsigned tie_t = 0;
1438 tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
1439 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1440 return tie_t;
1441 }
1442
1443 static void
1444 Field_bitindex_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1445 {
1446 uint32 tie_t;
1447 tie_t = (val << 28) >> 28;
1448 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1449 tie_t = (val << 27) >> 31;
1450 insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
1451 }
1452
1453 static unsigned
1454 Field_bitindex_Slot_inst16a_get (const xtensa_insnbuf insn)
1455 {
1456 unsigned tie_t = 0;
1457 tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
1458 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1459 return tie_t;
1460 }
1461
1462 static void
1463 Field_bitindex_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1464 {
1465 uint32 tie_t;
1466 tie_t = (val << 28) >> 28;
1467 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1468 tie_t = (val << 27) >> 31;
1469 insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
1470 }
1471
1472 static unsigned
1473 Field_bitindex_Slot_inst16b_get (const xtensa_insnbuf insn)
1474 {
1475 unsigned tie_t = 0;
1476 tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
1477 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1478 return tie_t;
1479 }
1480
1481 static void
1482 Field_bitindex_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1483 {
1484 uint32 tie_t;
1485 tie_t = (val << 28) >> 28;
1486 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1487 tie_t = (val << 27) >> 31;
1488 insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
1489 }
1490
1491 static unsigned
1492 Field_s3to1_Slot_inst16a_get (const xtensa_insnbuf insn)
1493 {
1494 unsigned tie_t = 0;
1495 tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
1496 return tie_t;
1497 }
1498
1499 static void
1500 Field_s3to1_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1501 {
1502 uint32 tie_t;
1503 tie_t = (val << 29) >> 29;
1504 insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
1505 }
1506
1507 static unsigned
1508 Field_s3to1_Slot_inst16b_get (const xtensa_insnbuf insn)
1509 {
1510 unsigned tie_t = 0;
1511 tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
1512 return tie_t;
1513 }
1514
1515 static void
1516 Field_s3to1_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1517 {
1518 uint32 tie_t;
1519 tie_t = (val << 29) >> 29;
1520 insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
1521 }
1522
1523 static void
1524 Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED,
1525 uint32 val ATTRIBUTE_UNUSED)
1526 {
1527 /* Do nothing. */
1528 }
1529
1530 static unsigned
1531 Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1532 {
1533 return 0;
1534 }
1535
1536 static unsigned
1537 Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1538 {
1539 return 4;
1540 }
1541
1542 static unsigned
1543 Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1544 {
1545 return 8;
1546 }
1547
1548 static unsigned
1549 Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1550 {
1551 return 12;
1552 }
1553
1554 static unsigned
1555 Implicit_Field_mr0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1556 {
1557 return 0;
1558 }
1559
1560 static unsigned
1561 Implicit_Field_mr1_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1562 {
1563 return 1;
1564 }
1565
1566 static unsigned
1567 Implicit_Field_mr2_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1568 {
1569 return 2;
1570 }
1571
1572 static unsigned
1573 Implicit_Field_mr3_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1574 {
1575 return 3;
1576 }
1577
1578 enum xtensa_field_id {
1579 FIELD_t,
1580 FIELD_bbi4,
1581 FIELD_bbi,
1582 FIELD_imm12,
1583 FIELD_imm8,
1584 FIELD_s,
1585 FIELD_imm12b,
1586 FIELD_imm16,
1587 FIELD_m,
1588 FIELD_n,
1589 FIELD_offset,
1590 FIELD_op0,
1591 FIELD_op1,
1592 FIELD_op2,
1593 FIELD_r,
1594 FIELD_sa4,
1595 FIELD_sae4,
1596 FIELD_sae,
1597 FIELD_sal,
1598 FIELD_sargt,
1599 FIELD_sas4,
1600 FIELD_sas,
1601 FIELD_sr,
1602 FIELD_st,
1603 FIELD_thi3,
1604 FIELD_imm4,
1605 FIELD_mn,
1606 FIELD_i,
1607 FIELD_imm6lo,
1608 FIELD_imm6hi,
1609 FIELD_imm7lo,
1610 FIELD_imm7hi,
1611 FIELD_z,
1612 FIELD_imm6,
1613 FIELD_imm7,
1614 FIELD_r3,
1615 FIELD_rbit2,
1616 FIELD_rhi,
1617 FIELD_t3,
1618 FIELD_tbit2,
1619 FIELD_tlo,
1620 FIELD_w,
1621 FIELD_y,
1622 FIELD_x,
1623 FIELD_xt_wbr15_imm,
1624 FIELD_xt_wbr18_imm,
1625 FIELD_bitindex,
1626 FIELD_s3to1,
1627 FIELD__ar0,
1628 FIELD__ar4,
1629 FIELD__ar8,
1630 FIELD__ar12,
1631 FIELD__mr0,
1632 FIELD__mr1,
1633 FIELD__mr2,
1634 FIELD__mr3
1635 };
1636
1637
1638 /* Functional units. */
1639
1640 static xtensa_funcUnit_internal funcUnits[] = {
1641
1642 };
1643
1644
1645 /* Register files. */
1646
1647 enum xtensa_regfile_id {
1648 REGFILE_AR,
1649 REGFILE_MR
1650 };
1651
1652 static xtensa_regfile_internal regfiles[] = {
1653 { "AR", "a", REGFILE_AR, 32, 32 },
1654 { "MR", "m", REGFILE_MR, 32, 4 }
1655 };
1656
1657
1658 /* Interfaces. */
1659
1660 static xtensa_interface_internal interfaces[] = {
1661 { "IMPWIRE", 32, 0, 0, 'i' }
1662 };
1663
1664 enum xtensa_interface_id {
1665 INTERFACE_IMPWIRE
1666 };
1667
1668
1669 /* Constant tables. */
1670
1671 /* constant table ai4c */
1672 static const unsigned CONST_TBL_ai4c_0[] = {
1673 0xffffffff,
1674 0x1,
1675 0x2,
1676 0x3,
1677 0x4,
1678 0x5,
1679 0x6,
1680 0x7,
1681 0x8,
1682 0x9,
1683 0xa,
1684 0xb,
1685 0xc,
1686 0xd,
1687 0xe,
1688 0xf,
1689 0
1690 };
1691
1692 /* constant table b4c */
1693 static const unsigned CONST_TBL_b4c_0[] = {
1694 0xffffffff,
1695 0x1,
1696 0x2,
1697 0x3,
1698 0x4,
1699 0x5,
1700 0x6,
1701 0x7,
1702 0x8,
1703 0xa,
1704 0xc,
1705 0x10,
1706 0x20,
1707 0x40,
1708 0x80,
1709 0x100,
1710 0
1711 };
1712
1713 /* constant table b4cu */
1714 static const unsigned CONST_TBL_b4cu_0[] = {
1715 0x8000,
1716 0x10000,
1717 0x2,
1718 0x3,
1719 0x4,
1720 0x5,
1721 0x6,
1722 0x7,
1723 0x8,
1724 0xa,
1725 0xc,
1726 0x10,
1727 0x20,
1728 0x40,
1729 0x80,
1730 0x100,
1731 0
1732 };
1733
1734
1735 /* Instruction operands. */
1736
1737 static int
1738 Operand_soffsetx4_decode (uint32 *valp)
1739 {
1740 unsigned soffsetx4_0, offset_0;
1741 offset_0 = *valp & 0x3ffff;
1742 soffsetx4_0 = 0x4 + ((((int) offset_0 << 14) >> 14) << 2);
1743 *valp = soffsetx4_0;
1744 return 0;
1745 }
1746
1747 static int
1748 Operand_soffsetx4_encode (uint32 *valp)
1749 {
1750 unsigned offset_0, soffsetx4_0;
1751 soffsetx4_0 = *valp;
1752 offset_0 = ((soffsetx4_0 - 0x4) >> 2) & 0x3ffff;
1753 *valp = offset_0;
1754 return 0;
1755 }
1756
1757 static int
1758 Operand_soffsetx4_ator (uint32 *valp, uint32 pc)
1759 {
1760 *valp -= (pc & ~0x3);
1761 return 0;
1762 }
1763
1764 static int
1765 Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc)
1766 {
1767 *valp += (pc & ~0x3);
1768 return 0;
1769 }
1770
1771 static int
1772 Operand_uimm12x8_decode (uint32 *valp)
1773 {
1774 unsigned uimm12x8_0, imm12_0;
1775 imm12_0 = *valp & 0xfff;
1776 uimm12x8_0 = imm12_0 << 3;
1777 *valp = uimm12x8_0;
1778 return 0;
1779 }
1780
1781 static int
1782 Operand_uimm12x8_encode (uint32 *valp)
1783 {
1784 unsigned imm12_0, uimm12x8_0;
1785 uimm12x8_0 = *valp;
1786 imm12_0 = ((uimm12x8_0 >> 3) & 0xfff);
1787 *valp = imm12_0;
1788 return 0;
1789 }
1790
1791 static int
1792 Operand_simm4_decode (uint32 *valp)
1793 {
1794 unsigned simm4_0, mn_0;
1795 mn_0 = *valp & 0xf;
1796 simm4_0 = ((int) mn_0 << 28) >> 28;
1797 *valp = simm4_0;
1798 return 0;
1799 }
1800
1801 static int
1802 Operand_simm4_encode (uint32 *valp)
1803 {
1804 unsigned mn_0, simm4_0;
1805 simm4_0 = *valp;
1806 mn_0 = (simm4_0 & 0xf);
1807 *valp = mn_0;
1808 return 0;
1809 }
1810
1811 static int
1812 Operand_arr_decode (uint32 *valp ATTRIBUTE_UNUSED)
1813 {
1814 return 0;
1815 }
1816
1817 static int
1818 Operand_arr_encode (uint32 *valp)
1819 {
1820 return (*valp & ~0xf) != 0;
1821 }
1822
1823 static int
1824 Operand_ars_decode (uint32 *valp ATTRIBUTE_UNUSED)
1825 {
1826 return 0;
1827 }
1828
1829 static int
1830 Operand_ars_encode (uint32 *valp)
1831 {
1832 return (*valp & ~0xf) != 0;
1833 }
1834
1835 static int
1836 Operand_art_decode (uint32 *valp ATTRIBUTE_UNUSED)
1837 {
1838 return 0;
1839 }
1840
1841 static int
1842 Operand_art_encode (uint32 *valp)
1843 {
1844 return (*valp & ~0xf) != 0;
1845 }
1846
1847 static int
1848 Operand_ar0_decode (uint32 *valp ATTRIBUTE_UNUSED)
1849 {
1850 return 0;
1851 }
1852
1853 static int
1854 Operand_ar0_encode (uint32 *valp)
1855 {
1856 return (*valp & ~0x1f) != 0;
1857 }
1858
1859 static int
1860 Operand_ar4_decode (uint32 *valp ATTRIBUTE_UNUSED)
1861 {
1862 return 0;
1863 }
1864
1865 static int
1866 Operand_ar4_encode (uint32 *valp)
1867 {
1868 return (*valp & ~0x1f) != 0;
1869 }
1870
1871 static int
1872 Operand_ar8_decode (uint32 *valp ATTRIBUTE_UNUSED)
1873 {
1874 return 0;
1875 }
1876
1877 static int
1878 Operand_ar8_encode (uint32 *valp)
1879 {
1880 return (*valp & ~0x1f) != 0;
1881 }
1882
1883 static int
1884 Operand_ar12_decode (uint32 *valp ATTRIBUTE_UNUSED)
1885 {
1886 return 0;
1887 }
1888
1889 static int
1890 Operand_ar12_encode (uint32 *valp)
1891 {
1892 return (*valp & ~0x1f) != 0;
1893 }
1894
1895 static int
1896 Operand_ars_entry_decode (uint32 *valp ATTRIBUTE_UNUSED)
1897 {
1898 return 0;
1899 }
1900
1901 static int
1902 Operand_ars_entry_encode (uint32 *valp)
1903 {
1904 return (*valp & ~0x1f) != 0;
1905 }
1906
1907 static int
1908 Operand_immrx4_decode (uint32 *valp)
1909 {
1910 unsigned immrx4_0, r_0;
1911 r_0 = *valp & 0xf;
1912 immrx4_0 = (((0xfffffff) << 4) | r_0) << 2;
1913 *valp = immrx4_0;
1914 return 0;
1915 }
1916
1917 static int
1918 Operand_immrx4_encode (uint32 *valp)
1919 {
1920 unsigned r_0, immrx4_0;
1921 immrx4_0 = *valp;
1922 r_0 = ((immrx4_0 >> 2) & 0xf);
1923 *valp = r_0;
1924 return 0;
1925 }
1926
1927 static int
1928 Operand_lsi4x4_decode (uint32 *valp)
1929 {
1930 unsigned lsi4x4_0, r_0;
1931 r_0 = *valp & 0xf;
1932 lsi4x4_0 = r_0 << 2;
1933 *valp = lsi4x4_0;
1934 return 0;
1935 }
1936
1937 static int
1938 Operand_lsi4x4_encode (uint32 *valp)
1939 {
1940 unsigned r_0, lsi4x4_0;
1941 lsi4x4_0 = *valp;
1942 r_0 = ((lsi4x4_0 >> 2) & 0xf);
1943 *valp = r_0;
1944 return 0;
1945 }
1946
1947 static int
1948 Operand_simm7_decode (uint32 *valp)
1949 {
1950 unsigned simm7_0, imm7_0;
1951 imm7_0 = *valp & 0x7f;
1952 simm7_0 = ((((-((((imm7_0 >> 6) & 1)) & (((imm7_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | imm7_0;
1953 *valp = simm7_0;
1954 return 0;
1955 }
1956
1957 static int
1958 Operand_simm7_encode (uint32 *valp)
1959 {
1960 unsigned imm7_0, simm7_0;
1961 simm7_0 = *valp;
1962 imm7_0 = (simm7_0 & 0x7f);
1963 *valp = imm7_0;
1964 return 0;
1965 }
1966
1967 static int
1968 Operand_uimm6_decode (uint32 *valp)
1969 {
1970 unsigned uimm6_0, imm6_0;
1971 imm6_0 = *valp & 0x3f;
1972 uimm6_0 = 0x4 + (((0) << 6) | imm6_0);
1973 *valp = uimm6_0;
1974 return 0;
1975 }
1976
1977 static int
1978 Operand_uimm6_encode (uint32 *valp)
1979 {
1980 unsigned imm6_0, uimm6_0;
1981 uimm6_0 = *valp;
1982 imm6_0 = (uimm6_0 - 0x4) & 0x3f;
1983 *valp = imm6_0;
1984 return 0;
1985 }
1986
1987 static int
1988 Operand_uimm6_ator (uint32 *valp, uint32 pc)
1989 {
1990 *valp -= pc;
1991 return 0;
1992 }
1993
1994 static int
1995 Operand_uimm6_rtoa (uint32 *valp, uint32 pc)
1996 {
1997 *valp += pc;
1998 return 0;
1999 }
2000
2001 static int
2002 Operand_ai4const_decode (uint32 *valp)
2003 {
2004 unsigned ai4const_0, t_0;
2005 t_0 = *valp & 0xf;
2006 ai4const_0 = CONST_TBL_ai4c_0[t_0 & 0xf];
2007 *valp = ai4const_0;
2008 return 0;
2009 }
2010
2011 static int
2012 Operand_ai4const_encode (uint32 *valp)
2013 {
2014 unsigned t_0, ai4const_0;
2015 ai4const_0 = *valp;
2016 switch (ai4const_0)
2017 {
2018 case 0xffffffff: t_0 = 0; break;
2019 case 0x1: t_0 = 0x1; break;
2020 case 0x2: t_0 = 0x2; break;
2021 case 0x3: t_0 = 0x3; break;
2022 case 0x4: t_0 = 0x4; break;
2023 case 0x5: t_0 = 0x5; break;
2024 case 0x6: t_0 = 0x6; break;
2025 case 0x7: t_0 = 0x7; break;
2026 case 0x8: t_0 = 0x8; break;
2027 case 0x9: t_0 = 0x9; break;
2028 case 0xa: t_0 = 0xa; break;
2029 case 0xb: t_0 = 0xb; break;
2030 case 0xc: t_0 = 0xc; break;
2031 case 0xd: t_0 = 0xd; break;
2032 case 0xe: t_0 = 0xe; break;
2033 default: t_0 = 0xf; break;
2034 }
2035 *valp = t_0;
2036 return 0;
2037 }
2038
2039 static int
2040 Operand_b4const_decode (uint32 *valp)
2041 {
2042 unsigned b4const_0, r_0;
2043 r_0 = *valp & 0xf;
2044 b4const_0 = CONST_TBL_b4c_0[r_0 & 0xf];
2045 *valp = b4const_0;
2046 return 0;
2047 }
2048
2049 static int
2050 Operand_b4const_encode (uint32 *valp)
2051 {
2052 unsigned r_0, b4const_0;
2053 b4const_0 = *valp;
2054 switch (b4const_0)
2055 {
2056 case 0xffffffff: r_0 = 0; break;
2057 case 0x1: r_0 = 0x1; break;
2058 case 0x2: r_0 = 0x2; break;
2059 case 0x3: r_0 = 0x3; break;
2060 case 0x4: r_0 = 0x4; break;
2061 case 0x5: r_0 = 0x5; break;
2062 case 0x6: r_0 = 0x6; break;
2063 case 0x7: r_0 = 0x7; break;
2064 case 0x8: r_0 = 0x8; break;
2065 case 0xa: r_0 = 0x9; break;
2066 case 0xc: r_0 = 0xa; break;
2067 case 0x10: r_0 = 0xb; break;
2068 case 0x20: r_0 = 0xc; break;
2069 case 0x40: r_0 = 0xd; break;
2070 case 0x80: r_0 = 0xe; break;
2071 default: r_0 = 0xf; break;
2072 }
2073 *valp = r_0;
2074 return 0;
2075 }
2076
2077 static int
2078 Operand_b4constu_decode (uint32 *valp)
2079 {
2080 unsigned b4constu_0, r_0;
2081 r_0 = *valp & 0xf;
2082 b4constu_0 = CONST_TBL_b4cu_0[r_0 & 0xf];
2083 *valp = b4constu_0;
2084 return 0;
2085 }
2086
2087 static int
2088 Operand_b4constu_encode (uint32 *valp)
2089 {
2090 unsigned r_0, b4constu_0;
2091 b4constu_0 = *valp;
2092 switch (b4constu_0)
2093 {
2094 case 0x8000: r_0 = 0; break;
2095 case 0x10000: r_0 = 0x1; break;
2096 case 0x2: r_0 = 0x2; break;
2097 case 0x3: r_0 = 0x3; break;
2098 case 0x4: r_0 = 0x4; break;
2099 case 0x5: r_0 = 0x5; break;
2100 case 0x6: r_0 = 0x6; break;
2101 case 0x7: r_0 = 0x7; break;
2102 case 0x8: r_0 = 0x8; break;
2103 case 0xa: r_0 = 0x9; break;
2104 case 0xc: r_0 = 0xa; break;
2105 case 0x10: r_0 = 0xb; break;
2106 case 0x20: r_0 = 0xc; break;
2107 case 0x40: r_0 = 0xd; break;
2108 case 0x80: r_0 = 0xe; break;
2109 default: r_0 = 0xf; break;
2110 }
2111 *valp = r_0;
2112 return 0;
2113 }
2114
2115 static int
2116 Operand_uimm8_decode (uint32 *valp)
2117 {
2118 unsigned uimm8_0, imm8_0;
2119 imm8_0 = *valp & 0xff;
2120 uimm8_0 = imm8_0;
2121 *valp = uimm8_0;
2122 return 0;
2123 }
2124
2125 static int
2126 Operand_uimm8_encode (uint32 *valp)
2127 {
2128 unsigned imm8_0, uimm8_0;
2129 uimm8_0 = *valp;
2130 imm8_0 = (uimm8_0 & 0xff);
2131 *valp = imm8_0;
2132 return 0;
2133 }
2134
2135 static int
2136 Operand_uimm8x2_decode (uint32 *valp)
2137 {
2138 unsigned uimm8x2_0, imm8_0;
2139 imm8_0 = *valp & 0xff;
2140 uimm8x2_0 = imm8_0 << 1;
2141 *valp = uimm8x2_0;
2142 return 0;
2143 }
2144
2145 static int
2146 Operand_uimm8x2_encode (uint32 *valp)
2147 {
2148 unsigned imm8_0, uimm8x2_0;
2149 uimm8x2_0 = *valp;
2150 imm8_0 = ((uimm8x2_0 >> 1) & 0xff);
2151 *valp = imm8_0;
2152 return 0;
2153 }
2154
2155 static int
2156 Operand_uimm8x4_decode (uint32 *valp)
2157 {
2158 unsigned uimm8x4_0, imm8_0;
2159 imm8_0 = *valp & 0xff;
2160 uimm8x4_0 = imm8_0 << 2;
2161 *valp = uimm8x4_0;
2162 return 0;
2163 }
2164
2165 static int
2166 Operand_uimm8x4_encode (uint32 *valp)
2167 {
2168 unsigned imm8_0, uimm8x4_0;
2169 uimm8x4_0 = *valp;
2170 imm8_0 = ((uimm8x4_0 >> 2) & 0xff);
2171 *valp = imm8_0;
2172 return 0;
2173 }
2174
2175 static int
2176 Operand_uimm4x16_decode (uint32 *valp)
2177 {
2178 unsigned uimm4x16_0, op2_0;
2179 op2_0 = *valp & 0xf;
2180 uimm4x16_0 = op2_0 << 4;
2181 *valp = uimm4x16_0;
2182 return 0;
2183 }
2184
2185 static int
2186 Operand_uimm4x16_encode (uint32 *valp)
2187 {
2188 unsigned op2_0, uimm4x16_0;
2189 uimm4x16_0 = *valp;
2190 op2_0 = ((uimm4x16_0 >> 4) & 0xf);
2191 *valp = op2_0;
2192 return 0;
2193 }
2194
2195 static int
2196 Operand_simm8_decode (uint32 *valp)
2197 {
2198 unsigned simm8_0, imm8_0;
2199 imm8_0 = *valp & 0xff;
2200 simm8_0 = ((int) imm8_0 << 24) >> 24;
2201 *valp = simm8_0;
2202 return 0;
2203 }
2204
2205 static int
2206 Operand_simm8_encode (uint32 *valp)
2207 {
2208 unsigned imm8_0, simm8_0;
2209 simm8_0 = *valp;
2210 imm8_0 = (simm8_0 & 0xff);
2211 *valp = imm8_0;
2212 return 0;
2213 }
2214
2215 static int
2216 Operand_simm8x256_decode (uint32 *valp)
2217 {
2218 unsigned simm8x256_0, imm8_0;
2219 imm8_0 = *valp & 0xff;
2220 simm8x256_0 = (((int) imm8_0 << 24) >> 24) << 8;
2221 *valp = simm8x256_0;
2222 return 0;
2223 }
2224
2225 static int
2226 Operand_simm8x256_encode (uint32 *valp)
2227 {
2228 unsigned imm8_0, simm8x256_0;
2229 simm8x256_0 = *valp;
2230 imm8_0 = ((simm8x256_0 >> 8) & 0xff);
2231 *valp = imm8_0;
2232 return 0;
2233 }
2234
2235 static int
2236 Operand_simm12b_decode (uint32 *valp)
2237 {
2238 unsigned simm12b_0, imm12b_0;
2239 imm12b_0 = *valp & 0xfff;
2240 simm12b_0 = ((int) imm12b_0 << 20) >> 20;
2241 *valp = simm12b_0;
2242 return 0;
2243 }
2244
2245 static int
2246 Operand_simm12b_encode (uint32 *valp)
2247 {
2248 unsigned imm12b_0, simm12b_0;
2249 simm12b_0 = *valp;
2250 imm12b_0 = (simm12b_0 & 0xfff);
2251 *valp = imm12b_0;
2252 return 0;
2253 }
2254
2255 static int
2256 Operand_msalp32_decode (uint32 *valp)
2257 {
2258 unsigned msalp32_0, sal_0;
2259 sal_0 = *valp & 0x1f;
2260 msalp32_0 = 0x20 - sal_0;
2261 *valp = msalp32_0;
2262 return 0;
2263 }
2264
2265 static int
2266 Operand_msalp32_encode (uint32 *valp)
2267 {
2268 unsigned sal_0, msalp32_0;
2269 msalp32_0 = *valp;
2270 sal_0 = (0x20 - msalp32_0) & 0x1f;
2271 *valp = sal_0;
2272 return 0;
2273 }
2274
2275 static int
2276 Operand_op2p1_decode (uint32 *valp)
2277 {
2278 unsigned op2p1_0, op2_0;
2279 op2_0 = *valp & 0xf;
2280 op2p1_0 = op2_0 + 0x1;
2281 *valp = op2p1_0;
2282 return 0;
2283 }
2284
2285 static int
2286 Operand_op2p1_encode (uint32 *valp)
2287 {
2288 unsigned op2_0, op2p1_0;
2289 op2p1_0 = *valp;
2290 op2_0 = (op2p1_0 - 0x1) & 0xf;
2291 *valp = op2_0;
2292 return 0;
2293 }
2294
2295 static int
2296 Operand_label8_decode (uint32 *valp)
2297 {
2298 unsigned label8_0, imm8_0;
2299 imm8_0 = *valp & 0xff;
2300 label8_0 = 0x4 + (((int) imm8_0 << 24) >> 24);
2301 *valp = label8_0;
2302 return 0;
2303 }
2304
2305 static int
2306 Operand_label8_encode (uint32 *valp)
2307 {
2308 unsigned imm8_0, label8_0;
2309 label8_0 = *valp;
2310 imm8_0 = (label8_0 - 0x4) & 0xff;
2311 *valp = imm8_0;
2312 return 0;
2313 }
2314
2315 static int
2316 Operand_label8_ator (uint32 *valp, uint32 pc)
2317 {
2318 *valp -= pc;
2319 return 0;
2320 }
2321
2322 static int
2323 Operand_label8_rtoa (uint32 *valp, uint32 pc)
2324 {
2325 *valp += pc;
2326 return 0;
2327 }
2328
2329 static int
2330 Operand_ulabel8_decode (uint32 *valp)
2331 {
2332 unsigned ulabel8_0, imm8_0;
2333 imm8_0 = *valp & 0xff;
2334 ulabel8_0 = 0x4 + (((0) << 8) | imm8_0);
2335 *valp = ulabel8_0;
2336 return 0;
2337 }
2338
2339 static int
2340 Operand_ulabel8_encode (uint32 *valp)
2341 {
2342 unsigned imm8_0, ulabel8_0;
2343 ulabel8_0 = *valp;
2344 imm8_0 = (ulabel8_0 - 0x4) & 0xff;
2345 *valp = imm8_0;
2346 return 0;
2347 }
2348
2349 static int
2350 Operand_ulabel8_ator (uint32 *valp, uint32 pc)
2351 {
2352 *valp -= pc;
2353 return 0;
2354 }
2355
2356 static int
2357 Operand_ulabel8_rtoa (uint32 *valp, uint32 pc)
2358 {
2359 *valp += pc;
2360 return 0;
2361 }
2362
2363 static int
2364 Operand_label12_decode (uint32 *valp)
2365 {
2366 unsigned label12_0, imm12_0;
2367 imm12_0 = *valp & 0xfff;
2368 label12_0 = 0x4 + (((int) imm12_0 << 20) >> 20);
2369 *valp = label12_0;
2370 return 0;
2371 }
2372
2373 static int
2374 Operand_label12_encode (uint32 *valp)
2375 {
2376 unsigned imm12_0, label12_0;
2377 label12_0 = *valp;
2378 imm12_0 = (label12_0 - 0x4) & 0xfff;
2379 *valp = imm12_0;
2380 return 0;
2381 }
2382
2383 static int
2384 Operand_label12_ator (uint32 *valp, uint32 pc)
2385 {
2386 *valp -= pc;
2387 return 0;
2388 }
2389
2390 static int
2391 Operand_label12_rtoa (uint32 *valp, uint32 pc)
2392 {
2393 *valp += pc;
2394 return 0;
2395 }
2396
2397 static int
2398 Operand_soffset_decode (uint32 *valp)
2399 {
2400 unsigned soffset_0, offset_0;
2401 offset_0 = *valp & 0x3ffff;
2402 soffset_0 = 0x4 + (((int) offset_0 << 14) >> 14);
2403 *valp = soffset_0;
2404 return 0;
2405 }
2406
2407 static int
2408 Operand_soffset_encode (uint32 *valp)
2409 {
2410 unsigned offset_0, soffset_0;
2411 soffset_0 = *valp;
2412 offset_0 = (soffset_0 - 0x4) & 0x3ffff;
2413 *valp = offset_0;
2414 return 0;
2415 }
2416
2417 static int
2418 Operand_soffset_ator (uint32 *valp, uint32 pc)
2419 {
2420 *valp -= pc;
2421 return 0;
2422 }
2423
2424 static int
2425 Operand_soffset_rtoa (uint32 *valp, uint32 pc)
2426 {
2427 *valp += pc;
2428 return 0;
2429 }
2430
2431 static int
2432 Operand_uimm16x4_decode (uint32 *valp)
2433 {
2434 unsigned uimm16x4_0, imm16_0;
2435 imm16_0 = *valp & 0xffff;
2436 uimm16x4_0 = (((0xffff) << 16) | imm16_0) << 2;
2437 *valp = uimm16x4_0;
2438 return 0;
2439 }
2440
2441 static int
2442 Operand_uimm16x4_encode (uint32 *valp)
2443 {
2444 unsigned imm16_0, uimm16x4_0;
2445 uimm16x4_0 = *valp;
2446 imm16_0 = (uimm16x4_0 >> 2) & 0xffff;
2447 *valp = imm16_0;
2448 return 0;
2449 }
2450
2451 static int
2452 Operand_uimm16x4_ator (uint32 *valp, uint32 pc)
2453 {
2454 *valp -= ((pc + 3) & ~0x3);
2455 return 0;
2456 }
2457
2458 static int
2459 Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc)
2460 {
2461 *valp += ((pc + 3) & ~0x3);
2462 return 0;
2463 }
2464
2465 static int
2466 Operand_mx_decode (uint32 *valp ATTRIBUTE_UNUSED)
2467 {
2468 return 0;
2469 }
2470
2471 static int
2472 Operand_mx_encode (uint32 *valp)
2473 {
2474 return (*valp & ~0x3) != 0;
2475 }
2476
2477 static int
2478 Operand_my_decode (uint32 *valp)
2479 {
2480 *valp += 2;
2481 return 0;
2482 }
2483
2484 static int
2485 Operand_my_encode (uint32 *valp)
2486 {
2487 int error;
2488 error = ((*valp & ~0x3) != 0) || ((*valp & 0x2) == 0);
2489 *valp = *valp & 1;
2490 return error;
2491 }
2492
2493 static int
2494 Operand_mw_decode (uint32 *valp ATTRIBUTE_UNUSED)
2495 {
2496 return 0;
2497 }
2498
2499 static int
2500 Operand_mw_encode (uint32 *valp)
2501 {
2502 return (*valp & ~0x3) != 0;
2503 }
2504
2505 static int
2506 Operand_mr0_decode (uint32 *valp ATTRIBUTE_UNUSED)
2507 {
2508 return 0;
2509 }
2510
2511 static int
2512 Operand_mr0_encode (uint32 *valp)
2513 {
2514 return (*valp & ~0x3) != 0;
2515 }
2516
2517 static int
2518 Operand_mr1_decode (uint32 *valp ATTRIBUTE_UNUSED)
2519 {
2520 return 0;
2521 }
2522
2523 static int
2524 Operand_mr1_encode (uint32 *valp)
2525 {
2526 return (*valp & ~0x3) != 0;
2527 }
2528
2529 static int
2530 Operand_mr2_decode (uint32 *valp ATTRIBUTE_UNUSED)
2531 {
2532 return 0;
2533 }
2534
2535 static int
2536 Operand_mr2_encode (uint32 *valp)
2537 {
2538 return (*valp & ~0x3) != 0;
2539 }
2540
2541 static int
2542 Operand_mr3_decode (uint32 *valp ATTRIBUTE_UNUSED)
2543 {
2544 return 0;
2545 }
2546
2547 static int
2548 Operand_mr3_encode (uint32 *valp)
2549 {
2550 return (*valp & ~0x3) != 0;
2551 }
2552
2553 static int
2554 Operand_immt_decode (uint32 *valp)
2555 {
2556 unsigned immt_0, t_0;
2557 t_0 = *valp & 0xf;
2558 immt_0 = t_0;
2559 *valp = immt_0;
2560 return 0;
2561 }
2562
2563 static int
2564 Operand_immt_encode (uint32 *valp)
2565 {
2566 unsigned t_0, immt_0;
2567 immt_0 = *valp;
2568 t_0 = immt_0 & 0xf;
2569 *valp = t_0;
2570 return 0;
2571 }
2572
2573 static int
2574 Operand_imms_decode (uint32 *valp)
2575 {
2576 unsigned imms_0, s_0;
2577 s_0 = *valp & 0xf;
2578 imms_0 = s_0;
2579 *valp = imms_0;
2580 return 0;
2581 }
2582
2583 static int
2584 Operand_imms_encode (uint32 *valp)
2585 {
2586 unsigned s_0, imms_0;
2587 imms_0 = *valp;
2588 s_0 = imms_0 & 0xf;
2589 *valp = s_0;
2590 return 0;
2591 }
2592
2593 static int
2594 Operand_tp7_decode (uint32 *valp)
2595 {
2596 unsigned tp7_0, t_0;
2597 t_0 = *valp & 0xf;
2598 tp7_0 = t_0 + 0x7;
2599 *valp = tp7_0;
2600 return 0;
2601 }
2602
2603 static int
2604 Operand_tp7_encode (uint32 *valp)
2605 {
2606 unsigned t_0, tp7_0;
2607 tp7_0 = *valp;
2608 t_0 = (tp7_0 - 0x7) & 0xf;
2609 *valp = t_0;
2610 return 0;
2611 }
2612
2613 static int
2614 Operand_xt_wbr15_label_decode (uint32 *valp)
2615 {
2616 unsigned xt_wbr15_label_0, xt_wbr15_imm_0;
2617 xt_wbr15_imm_0 = *valp & 0x7fff;
2618 xt_wbr15_label_0 = 0x4 + (((int) xt_wbr15_imm_0 << 17) >> 17);
2619 *valp = xt_wbr15_label_0;
2620 return 0;
2621 }
2622
2623 static int
2624 Operand_xt_wbr15_label_encode (uint32 *valp)
2625 {
2626 unsigned xt_wbr15_imm_0, xt_wbr15_label_0;
2627 xt_wbr15_label_0 = *valp;
2628 xt_wbr15_imm_0 = (xt_wbr15_label_0 - 0x4) & 0x7fff;
2629 *valp = xt_wbr15_imm_0;
2630 return 0;
2631 }
2632
2633 static int
2634 Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc)
2635 {
2636 *valp -= pc;
2637 return 0;
2638 }
2639
2640 static int
2641 Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc)
2642 {
2643 *valp += pc;
2644 return 0;
2645 }
2646
2647 static int
2648 Operand_xt_wbr18_label_decode (uint32 *valp)
2649 {
2650 unsigned xt_wbr18_label_0, xt_wbr18_imm_0;
2651 xt_wbr18_imm_0 = *valp & 0x3ffff;
2652 xt_wbr18_label_0 = 0x4 + (((int) xt_wbr18_imm_0 << 14) >> 14);
2653 *valp = xt_wbr18_label_0;
2654 return 0;
2655 }
2656
2657 static int
2658 Operand_xt_wbr18_label_encode (uint32 *valp)
2659 {
2660 unsigned xt_wbr18_imm_0, xt_wbr18_label_0;
2661 xt_wbr18_label_0 = *valp;
2662 xt_wbr18_imm_0 = (xt_wbr18_label_0 - 0x4) & 0x3ffff;
2663 *valp = xt_wbr18_imm_0;
2664 return 0;
2665 }
2666
2667 static int
2668 Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc)
2669 {
2670 *valp -= pc;
2671 return 0;
2672 }
2673
2674 static int
2675 Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc)
2676 {
2677 *valp += pc;
2678 return 0;
2679 }
2680
2681 static xtensa_operand_internal operands[] = {
2682 { "soffsetx4", FIELD_offset, -1, 0,
2683 XTENSA_OPERAND_IS_PCRELATIVE,
2684 Operand_soffsetx4_encode, Operand_soffsetx4_decode,
2685 Operand_soffsetx4_ator, Operand_soffsetx4_rtoa },
2686 { "uimm12x8", FIELD_imm12, -1, 0,
2687 0,
2688 Operand_uimm12x8_encode, Operand_uimm12x8_decode,
2689 0, 0 },
2690 { "simm4", FIELD_mn, -1, 0,
2691 0,
2692 Operand_simm4_encode, Operand_simm4_decode,
2693 0, 0 },
2694 { "arr", FIELD_r, REGFILE_AR, 1,
2695 XTENSA_OPERAND_IS_REGISTER,
2696 Operand_arr_encode, Operand_arr_decode,
2697 0, 0 },
2698 { "ars", FIELD_s, REGFILE_AR, 1,
2699 XTENSA_OPERAND_IS_REGISTER,
2700 Operand_ars_encode, Operand_ars_decode,
2701 0, 0 },
2702 { "*ars_invisible", FIELD_s, REGFILE_AR, 1,
2703 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2704 Operand_ars_encode, Operand_ars_decode,
2705 0, 0 },
2706 { "art", FIELD_t, REGFILE_AR, 1,
2707 XTENSA_OPERAND_IS_REGISTER,
2708 Operand_art_encode, Operand_art_decode,
2709 0, 0 },
2710 { "ar0", FIELD__ar0, REGFILE_AR, 1,
2711 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2712 Operand_ar0_encode, Operand_ar0_decode,
2713 0, 0 },
2714 { "ar4", FIELD__ar4, REGFILE_AR, 1,
2715 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2716 Operand_ar4_encode, Operand_ar4_decode,
2717 0, 0 },
2718 { "ar8", FIELD__ar8, REGFILE_AR, 1,
2719 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2720 Operand_ar8_encode, Operand_ar8_decode,
2721 0, 0 },
2722 { "ar12", FIELD__ar12, REGFILE_AR, 1,
2723 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2724 Operand_ar12_encode, Operand_ar12_decode,
2725 0, 0 },
2726 { "ars_entry", FIELD_s, REGFILE_AR, 1,
2727 XTENSA_OPERAND_IS_REGISTER,
2728 Operand_ars_entry_encode, Operand_ars_entry_decode,
2729 0, 0 },
2730 { "immrx4", FIELD_r, -1, 0,
2731 0,
2732 Operand_immrx4_encode, Operand_immrx4_decode,
2733 0, 0 },
2734 { "lsi4x4", FIELD_r, -1, 0,
2735 0,
2736 Operand_lsi4x4_encode, Operand_lsi4x4_decode,
2737 0, 0 },
2738 { "simm7", FIELD_imm7, -1, 0,
2739 0,
2740 Operand_simm7_encode, Operand_simm7_decode,
2741 0, 0 },
2742 { "uimm6", FIELD_imm6, -1, 0,
2743 XTENSA_OPERAND_IS_PCRELATIVE,
2744 Operand_uimm6_encode, Operand_uimm6_decode,
2745 Operand_uimm6_ator, Operand_uimm6_rtoa },
2746 { "ai4const", FIELD_t, -1, 0,
2747 0,
2748 Operand_ai4const_encode, Operand_ai4const_decode,
2749 0, 0 },
2750 { "b4const", FIELD_r, -1, 0,
2751 0,
2752 Operand_b4const_encode, Operand_b4const_decode,
2753 0, 0 },
2754 { "b4constu", FIELD_r, -1, 0,
2755 0,
2756 Operand_b4constu_encode, Operand_b4constu_decode,
2757 0, 0 },
2758 { "uimm8", FIELD_imm8, -1, 0,
2759 0,
2760 Operand_uimm8_encode, Operand_uimm8_decode,
2761 0, 0 },
2762 { "uimm8x2", FIELD_imm8, -1, 0,
2763 0,
2764 Operand_uimm8x2_encode, Operand_uimm8x2_decode,
2765 0, 0 },
2766 { "uimm8x4", FIELD_imm8, -1, 0,
2767 0,
2768 Operand_uimm8x4_encode, Operand_uimm8x4_decode,
2769 0, 0 },
2770 { "uimm4x16", FIELD_op2, -1, 0,
2771 0,
2772 Operand_uimm4x16_encode, Operand_uimm4x16_decode,
2773 0, 0 },
2774 { "simm8", FIELD_imm8, -1, 0,
2775 0,
2776 Operand_simm8_encode, Operand_simm8_decode,
2777 0, 0 },
2778 { "simm8x256", FIELD_imm8, -1, 0,
2779 0,
2780 Operand_simm8x256_encode, Operand_simm8x256_decode,
2781 0, 0 },
2782 { "simm12b", FIELD_imm12b, -1, 0,
2783 0,
2784 Operand_simm12b_encode, Operand_simm12b_decode,
2785 0, 0 },
2786 { "msalp32", FIELD_sal, -1, 0,
2787 0,
2788 Operand_msalp32_encode, Operand_msalp32_decode,
2789 0, 0 },
2790 { "op2p1", FIELD_op2, -1, 0,
2791 0,
2792 Operand_op2p1_encode, Operand_op2p1_decode,
2793 0, 0 },
2794 { "label8", FIELD_imm8, -1, 0,
2795 XTENSA_OPERAND_IS_PCRELATIVE,
2796 Operand_label8_encode, Operand_label8_decode,
2797 Operand_label8_ator, Operand_label8_rtoa },
2798 { "ulabel8", FIELD_imm8, -1, 0,
2799 XTENSA_OPERAND_IS_PCRELATIVE,
2800 Operand_ulabel8_encode, Operand_ulabel8_decode,
2801 Operand_ulabel8_ator, Operand_ulabel8_rtoa },
2802 { "label12", FIELD_imm12, -1, 0,
2803 XTENSA_OPERAND_IS_PCRELATIVE,
2804 Operand_label12_encode, Operand_label12_decode,
2805 Operand_label12_ator, Operand_label12_rtoa },
2806 { "soffset", FIELD_offset, -1, 0,
2807 XTENSA_OPERAND_IS_PCRELATIVE,
2808 Operand_soffset_encode, Operand_soffset_decode,
2809 Operand_soffset_ator, Operand_soffset_rtoa },
2810 { "uimm16x4", FIELD_imm16, -1, 0,
2811 XTENSA_OPERAND_IS_PCRELATIVE,
2812 Operand_uimm16x4_encode, Operand_uimm16x4_decode,
2813 Operand_uimm16x4_ator, Operand_uimm16x4_rtoa },
2814 { "mx", FIELD_x, REGFILE_MR, 1,
2815 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN,
2816 Operand_mx_encode, Operand_mx_decode,
2817 0, 0 },
2818 { "my", FIELD_y, REGFILE_MR, 1,
2819 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN,
2820 Operand_my_encode, Operand_my_decode,
2821 0, 0 },
2822 { "mw", FIELD_w, REGFILE_MR, 1,
2823 XTENSA_OPERAND_IS_REGISTER,
2824 Operand_mw_encode, Operand_mw_decode,
2825 0, 0 },
2826 { "mr0", FIELD__mr0, REGFILE_MR, 1,
2827 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2828 Operand_mr0_encode, Operand_mr0_decode,
2829 0, 0 },
2830 { "mr1", FIELD__mr1, REGFILE_MR, 1,
2831 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2832 Operand_mr1_encode, Operand_mr1_decode,
2833 0, 0 },
2834 { "mr2", FIELD__mr2, REGFILE_MR, 1,
2835 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2836 Operand_mr2_encode, Operand_mr2_decode,
2837 0, 0 },
2838 { "mr3", FIELD__mr3, REGFILE_MR, 1,
2839 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2840 Operand_mr3_encode, Operand_mr3_decode,
2841 0, 0 },
2842 { "immt", FIELD_t, -1, 0,
2843 0,
2844 Operand_immt_encode, Operand_immt_decode,
2845 0, 0 },
2846 { "imms", FIELD_s, -1, 0,
2847 0,
2848 Operand_imms_encode, Operand_imms_decode,
2849 0, 0 },
2850 { "tp7", FIELD_t, -1, 0,
2851 0,
2852 Operand_tp7_encode, Operand_tp7_decode,
2853 0, 0 },
2854 { "xt_wbr15_label", FIELD_xt_wbr15_imm, -1, 0,
2855 XTENSA_OPERAND_IS_PCRELATIVE,
2856 Operand_xt_wbr15_label_encode, Operand_xt_wbr15_label_decode,
2857 Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa },
2858 { "xt_wbr18_label", FIELD_xt_wbr18_imm, -1, 0,
2859 XTENSA_OPERAND_IS_PCRELATIVE,
2860 Operand_xt_wbr18_label_encode, Operand_xt_wbr18_label_decode,
2861 Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa },
2862 { "t", FIELD_t, -1, 0, 0, 0, 0, 0, 0 },
2863 { "bbi4", FIELD_bbi4, -1, 0, 0, 0, 0, 0, 0 },
2864 { "bbi", FIELD_bbi, -1, 0, 0, 0, 0, 0, 0 },
2865 { "imm12", FIELD_imm12, -1, 0, 0, 0, 0, 0, 0 },
2866 { "imm8", FIELD_imm8, -1, 0, 0, 0, 0, 0, 0 },
2867 { "s", FIELD_s, -1, 0, 0, 0, 0, 0, 0 },
2868 { "imm12b", FIELD_imm12b, -1, 0, 0, 0, 0, 0, 0 },
2869 { "imm16", FIELD_imm16, -1, 0, 0, 0, 0, 0, 0 },
2870 { "m", FIELD_m, -1, 0, 0, 0, 0, 0, 0 },
2871 { "n", FIELD_n, -1, 0, 0, 0, 0, 0, 0 },
2872 { "offset", FIELD_offset, -1, 0, 0, 0, 0, 0, 0 },
2873 { "op0", FIELD_op0, -1, 0, 0, 0, 0, 0, 0 },
2874 { "op1", FIELD_op1, -1, 0, 0, 0, 0, 0, 0 },
2875 { "op2", FIELD_op2, -1, 0, 0, 0, 0, 0, 0 },
2876 { "r", FIELD_r, -1, 0, 0, 0, 0, 0, 0 },
2877 { "sa4", FIELD_sa4, -1, 0, 0, 0, 0, 0, 0 },
2878 { "sae4", FIELD_sae4, -1, 0, 0, 0, 0, 0, 0 },
2879 { "sae", FIELD_sae, -1, 0, 0, 0, 0, 0, 0 },
2880 { "sal", FIELD_sal, -1, 0, 0, 0, 0, 0, 0 },
2881 { "sargt", FIELD_sargt, -1, 0, 0, 0, 0, 0, 0 },
2882 { "sas4", FIELD_sas4, -1, 0, 0, 0, 0, 0, 0 },
2883 { "sas", FIELD_sas, -1, 0, 0, 0, 0, 0, 0 },
2884 { "sr", FIELD_sr, -1, 0, 0, 0, 0, 0, 0 },
2885 { "st", FIELD_st, -1, 0, 0, 0, 0, 0, 0 },
2886 { "thi3", FIELD_thi3, -1, 0, 0, 0, 0, 0, 0 },
2887 { "imm4", FIELD_imm4, -1, 0, 0, 0, 0, 0, 0 },
2888 { "mn", FIELD_mn, -1, 0, 0, 0, 0, 0, 0 },
2889 { "i", FIELD_i, -1, 0, 0, 0, 0, 0, 0 },
2890 { "imm6lo", FIELD_imm6lo, -1, 0, 0, 0, 0, 0, 0 },
2891 { "imm6hi", FIELD_imm6hi, -1, 0, 0, 0, 0, 0, 0 },
2892 { "imm7lo", FIELD_imm7lo, -1, 0, 0, 0, 0, 0, 0 },
2893 { "imm7hi", FIELD_imm7hi, -1, 0, 0, 0, 0, 0, 0 },
2894 { "z", FIELD_z, -1, 0, 0, 0, 0, 0, 0 },
2895 { "imm6", FIELD_imm6, -1, 0, 0, 0, 0, 0, 0 },
2896 { "imm7", FIELD_imm7, -1, 0, 0, 0, 0, 0, 0 },
2897 { "r3", FIELD_r3, -1, 0, 0, 0, 0, 0, 0 },
2898 { "rbit2", FIELD_rbit2, -1, 0, 0, 0, 0, 0, 0 },
2899 { "rhi", FIELD_rhi, -1, 0, 0, 0, 0, 0, 0 },
2900 { "t3", FIELD_t3, -1, 0, 0, 0, 0, 0, 0 },
2901 { "tbit2", FIELD_tbit2, -1, 0, 0, 0, 0, 0, 0 },
2902 { "tlo", FIELD_tlo, -1, 0, 0, 0, 0, 0, 0 },
2903 { "w", FIELD_w, -1, 0, 0, 0, 0, 0, 0 },
2904 { "y", FIELD_y, -1, 0, 0, 0, 0, 0, 0 },
2905 { "x", FIELD_x, -1, 0, 0, 0, 0, 0, 0 },
2906 { "xt_wbr15_imm", FIELD_xt_wbr15_imm, -1, 0, 0, 0, 0, 0, 0 },
2907 { "xt_wbr18_imm", FIELD_xt_wbr18_imm, -1, 0, 0, 0, 0, 0, 0 },
2908 { "bitindex", FIELD_bitindex, -1, 0, 0, 0, 0, 0, 0 },
2909 { "s3to1", FIELD_s3to1, -1, 0, 0, 0, 0, 0, 0 }
2910 };
2911
2912 enum xtensa_operand_id {
2913 OPERAND_soffsetx4,
2914 OPERAND_uimm12x8,
2915 OPERAND_simm4,
2916 OPERAND_arr,
2917 OPERAND_ars,
2918 OPERAND__ars_invisible,
2919 OPERAND_art,
2920 OPERAND_ar0,
2921 OPERAND_ar4,
2922 OPERAND_ar8,
2923 OPERAND_ar12,
2924 OPERAND_ars_entry,
2925 OPERAND_immrx4,
2926 OPERAND_lsi4x4,
2927 OPERAND_simm7,
2928 OPERAND_uimm6,
2929 OPERAND_ai4const,
2930 OPERAND_b4const,
2931 OPERAND_b4constu,
2932 OPERAND_uimm8,
2933 OPERAND_uimm8x2,
2934 OPERAND_uimm8x4,
2935 OPERAND_uimm4x16,
2936 OPERAND_simm8,
2937 OPERAND_simm8x256,
2938 OPERAND_simm12b,
2939 OPERAND_msalp32,
2940 OPERAND_op2p1,
2941 OPERAND_label8,
2942 OPERAND_ulabel8,
2943 OPERAND_label12,
2944 OPERAND_soffset,
2945 OPERAND_uimm16x4,
2946 OPERAND_mx,
2947 OPERAND_my,
2948 OPERAND_mw,
2949 OPERAND_mr0,
2950 OPERAND_mr1,
2951 OPERAND_mr2,
2952 OPERAND_mr3,
2953 OPERAND_immt,
2954 OPERAND_imms,
2955 OPERAND_tp7,
2956 OPERAND_xt_wbr15_label,
2957 OPERAND_xt_wbr18_label,
2958 OPERAND_t,
2959 OPERAND_bbi4,
2960 OPERAND_bbi,
2961 OPERAND_imm12,
2962 OPERAND_imm8,
2963 OPERAND_s,
2964 OPERAND_imm12b,
2965 OPERAND_imm16,
2966 OPERAND_m,
2967 OPERAND_n,
2968 OPERAND_offset,
2969 OPERAND_op0,
2970 OPERAND_op1,
2971 OPERAND_op2,
2972 OPERAND_r,
2973 OPERAND_sa4,
2974 OPERAND_sae4,
2975 OPERAND_sae,
2976 OPERAND_sal,
2977 OPERAND_sargt,
2978 OPERAND_sas4,
2979 OPERAND_sas,
2980 OPERAND_sr,
2981 OPERAND_st,
2982 OPERAND_thi3,
2983 OPERAND_imm4,
2984 OPERAND_mn,
2985 OPERAND_i,
2986 OPERAND_imm6lo,
2987 OPERAND_imm6hi,
2988 OPERAND_imm7lo,
2989 OPERAND_imm7hi,
2990 OPERAND_z,
2991 OPERAND_imm6,
2992 OPERAND_imm7,
2993 OPERAND_r3,
2994 OPERAND_rbit2,
2995 OPERAND_rhi,
2996 OPERAND_t3,
2997 OPERAND_tbit2,
2998 OPERAND_tlo,
2999 OPERAND_w,
3000 OPERAND_y,
3001 OPERAND_x,
3002 OPERAND_xt_wbr15_imm,
3003 OPERAND_xt_wbr18_imm,
3004 OPERAND_bitindex,
3005 OPERAND_s3to1
3006 };
3007
3008
3009 /* Iclass table. */
3010
3011 static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = {
3012 { { STATE_PSRING }, 'i' },
3013 { { STATE_PSEXCM }, 'm' },
3014 { { STATE_EPC1 }, 'i' }
3015 };
3016
3017 static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = {
3018 { { STATE_PSEXCM }, 'i' },
3019 { { STATE_PSRING }, 'i' },
3020 { { STATE_DEPC }, 'i' }
3021 };
3022
3023 static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = {
3024 { { OPERAND_soffsetx4 }, 'i' },
3025 { { OPERAND_ar12 }, 'o' }
3026 };
3027
3028 static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = {
3029 { { STATE_PSCALLINC }, 'o' }
3030 };
3031
3032 static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = {
3033 { { OPERAND_soffsetx4 }, 'i' },
3034 { { OPERAND_ar8 }, 'o' }
3035 };
3036
3037 static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = {
3038 { { STATE_PSCALLINC }, 'o' }
3039 };
3040
3041 static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = {
3042 { { OPERAND_soffsetx4 }, 'i' },
3043 { { OPERAND_ar4 }, 'o' }
3044 };
3045
3046 static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = {
3047 { { STATE_PSCALLINC }, 'o' }
3048 };
3049
3050 static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = {
3051 { { OPERAND_ars }, 'i' },
3052 { { OPERAND_ar12 }, 'o' }
3053 };
3054
3055 static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = {
3056 { { STATE_PSCALLINC }, 'o' }
3057 };
3058
3059 static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = {
3060 { { OPERAND_ars }, 'i' },
3061 { { OPERAND_ar8 }, 'o' }
3062 };
3063
3064 static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = {
3065 { { STATE_PSCALLINC }, 'o' }
3066 };
3067
3068 static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = {
3069 { { OPERAND_ars }, 'i' },
3070 { { OPERAND_ar4 }, 'o' }
3071 };
3072
3073 static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = {
3074 { { STATE_PSCALLINC }, 'o' }
3075 };
3076
3077 static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = {
3078 { { OPERAND_ars_entry }, 's' },
3079 { { OPERAND_ars }, 'i' },
3080 { { OPERAND_uimm12x8 }, 'i' }
3081 };
3082
3083 static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = {
3084 { { STATE_PSCALLINC }, 'i' },
3085 { { STATE_PSEXCM }, 'i' },
3086 { { STATE_PSWOE }, 'i' },
3087 { { STATE_WindowBase }, 'm' },
3088 { { STATE_WindowStart }, 'm' }
3089 };
3090
3091 static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = {
3092 { { OPERAND_art }, 'o' },
3093 { { OPERAND_ars }, 'i' }
3094 };
3095
3096 static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = {
3097 { { STATE_WindowBase }, 'i' },
3098 { { STATE_WindowStart }, 'i' }
3099 };
3100
3101 static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = {
3102 { { OPERAND_simm4 }, 'i' }
3103 };
3104
3105 static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = {
3106 { { STATE_PSEXCM }, 'i' },
3107 { { STATE_PSRING }, 'i' },
3108 { { STATE_WindowBase }, 'm' }
3109 };
3110
3111 static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = {
3112 { { OPERAND__ars_invisible }, 'i' }
3113 };
3114
3115 static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = {
3116 { { STATE_WindowBase }, 'm' },
3117 { { STATE_WindowStart }, 'm' },
3118 { { STATE_PSEXCM }, 'i' },
3119 { { STATE_PSWOE }, 'i' }
3120 };
3121
3122 static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = {
3123 { { STATE_EPC1 }, 'i' },
3124 { { STATE_PSEXCM }, 'm' },
3125 { { STATE_PSRING }, 'i' },
3126 { { STATE_WindowBase }, 'm' },
3127 { { STATE_WindowStart }, 'm' },
3128 { { STATE_PSOWB }, 'i' }
3129 };
3130
3131 static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = {
3132 { { OPERAND_art }, 'o' },
3133 { { OPERAND_ars }, 'i' },
3134 { { OPERAND_immrx4 }, 'i' }
3135 };
3136
3137 static xtensa_arg_internal Iclass_xt_iclass_l32e_stateArgs[] = {
3138 { { STATE_PSEXCM }, 'i' },
3139 { { STATE_PSRING }, 'i' }
3140 };
3141
3142 static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = {
3143 { { OPERAND_art }, 'i' },
3144 { { OPERAND_ars }, 'i' },
3145 { { OPERAND_immrx4 }, 'i' }
3146 };
3147
3148 static xtensa_arg_internal Iclass_xt_iclass_s32e_stateArgs[] = {
3149 { { STATE_PSEXCM }, 'i' },
3150 { { STATE_PSRING }, 'i' }
3151 };
3152
3153 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = {
3154 { { OPERAND_art }, 'o' }
3155 };
3156
3157 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = {
3158 { { STATE_PSEXCM }, 'i' },
3159 { { STATE_PSRING }, 'i' },
3160 { { STATE_WindowBase }, 'i' }
3161 };
3162
3163 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = {
3164 { { OPERAND_art }, 'i' }
3165 };
3166
3167 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = {
3168 { { STATE_PSEXCM }, 'i' },
3169 { { STATE_PSRING }, 'i' },
3170 { { STATE_WindowBase }, 'o' }
3171 };
3172
3173 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = {
3174 { { OPERAND_art }, 'm' }
3175 };
3176
3177 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = {
3178 { { STATE_PSEXCM }, 'i' },
3179 { { STATE_PSRING }, 'i' },
3180 { { STATE_WindowBase }, 'm' }
3181 };
3182
3183 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = {
3184 { { OPERAND_art }, 'o' }
3185 };
3186
3187 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = {
3188 { { STATE_PSEXCM }, 'i' },
3189 { { STATE_PSRING }, 'i' },
3190 { { STATE_WindowStart }, 'i' }
3191 };
3192
3193 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = {
3194 { { OPERAND_art }, 'i' }
3195 };
3196
3197 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = {
3198 { { STATE_PSEXCM }, 'i' },
3199 { { STATE_PSRING }, 'i' },
3200 { { STATE_WindowStart }, 'o' }
3201 };
3202
3203 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = {
3204 { { OPERAND_art }, 'm' }
3205 };
3206
3207 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = {
3208 { { STATE_PSEXCM }, 'i' },
3209 { { STATE_PSRING }, 'i' },
3210 { { STATE_WindowStart }, 'm' }
3211 };
3212
3213 static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = {
3214 { { OPERAND_arr }, 'o' },
3215 { { OPERAND_ars }, 'i' },
3216 { { OPERAND_art }, 'i' }
3217 };
3218
3219 static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = {
3220 { { OPERAND_arr }, 'o' },
3221 { { OPERAND_ars }, 'i' },
3222 { { OPERAND_ai4const }, 'i' }
3223 };
3224
3225 static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = {
3226 { { OPERAND_ars }, 'i' },
3227 { { OPERAND_uimm6 }, 'i' }
3228 };
3229
3230 static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = {
3231 { { OPERAND_art }, 'o' },
3232 { { OPERAND_ars }, 'i' },
3233 { { OPERAND_lsi4x4 }, 'i' }
3234 };
3235
3236 static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = {
3237 { { OPERAND_art }, 'o' },
3238 { { OPERAND_ars }, 'i' }
3239 };
3240
3241 static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = {
3242 { { OPERAND_ars }, 'o' },
3243 { { OPERAND_simm7 }, 'i' }
3244 };
3245
3246 static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = {
3247 { { OPERAND__ars_invisible }, 'i' }
3248 };
3249
3250 static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = {
3251 { { OPERAND_art }, 'i' },
3252 { { OPERAND_ars }, 'i' },
3253 { { OPERAND_lsi4x4 }, 'i' }
3254 };
3255
3256 static xtensa_arg_internal Iclass_rur_threadptr_args[] = {
3257 { { OPERAND_arr }, 'o' }
3258 };
3259
3260 static xtensa_arg_internal Iclass_rur_threadptr_stateArgs[] = {
3261 { { STATE_THREADPTR }, 'i' }
3262 };
3263
3264 static xtensa_arg_internal Iclass_wur_threadptr_args[] = {
3265 { { OPERAND_art }, 'i' }
3266 };
3267
3268 static xtensa_arg_internal Iclass_wur_threadptr_stateArgs[] = {
3269 { { STATE_THREADPTR }, 'o' }
3270 };
3271
3272 static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = {
3273 { { OPERAND_art }, 'o' },
3274 { { OPERAND_ars }, 'i' },
3275 { { OPERAND_simm8 }, 'i' }
3276 };
3277
3278 static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = {
3279 { { OPERAND_art }, 'o' },
3280 { { OPERAND_ars }, 'i' },
3281 { { OPERAND_simm8x256 }, 'i' }
3282 };
3283
3284 static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = {
3285 { { OPERAND_arr }, 'o' },
3286 { { OPERAND_ars }, 'i' },
3287 { { OPERAND_art }, 'i' }
3288 };
3289
3290 static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = {
3291 { { OPERAND_arr }, 'o' },
3292 { { OPERAND_ars }, 'i' },
3293 { { OPERAND_art }, 'i' }
3294 };
3295
3296 static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = {
3297 { { OPERAND_ars }, 'i' },
3298 { { OPERAND_b4const }, 'i' },
3299 { { OPERAND_label8 }, 'i' }
3300 };
3301
3302 static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = {
3303 { { OPERAND_ars }, 'i' },
3304 { { OPERAND_bbi }, 'i' },
3305 { { OPERAND_label8 }, 'i' }
3306 };
3307
3308 static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = {
3309 { { OPERAND_ars }, 'i' },
3310 { { OPERAND_b4constu }, 'i' },
3311 { { OPERAND_label8 }, 'i' }
3312 };
3313
3314 static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = {
3315 { { OPERAND_ars }, 'i' },
3316 { { OPERAND_art }, 'i' },
3317 { { OPERAND_label8 }, 'i' }
3318 };
3319
3320 static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = {
3321 { { OPERAND_ars }, 'i' },
3322 { { OPERAND_label12 }, 'i' }
3323 };
3324
3325 static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = {
3326 { { OPERAND_soffsetx4 }, 'i' },
3327 { { OPERAND_ar0 }, 'o' }
3328 };
3329
3330 static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = {
3331 { { OPERAND_ars }, 'i' },
3332 { { OPERAND_ar0 }, 'o' }
3333 };
3334
3335 static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = {
3336 { { OPERAND_arr }, 'o' },
3337 { { OPERAND_art }, 'i' },
3338 { { OPERAND_sae }, 'i' },
3339 { { OPERAND_op2p1 }, 'i' }
3340 };
3341
3342 static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = {
3343 { { OPERAND_soffset }, 'i' }
3344 };
3345
3346 static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = {
3347 { { OPERAND_ars }, 'i' }
3348 };
3349
3350 static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = {
3351 { { OPERAND_art }, 'o' },
3352 { { OPERAND_ars }, 'i' },
3353 { { OPERAND_uimm8x2 }, 'i' }
3354 };
3355
3356 static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = {
3357 { { OPERAND_art }, 'o' },
3358 { { OPERAND_ars }, 'i' },
3359 { { OPERAND_uimm8x2 }, 'i' }
3360 };
3361
3362 static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = {
3363 { { OPERAND_art }, 'o' },
3364 { { OPERAND_ars }, 'i' },
3365 { { OPERAND_uimm8x4 }, 'i' }
3366 };
3367
3368 static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = {
3369 { { OPERAND_art }, 'o' },
3370 { { OPERAND_uimm16x4 }, 'i' }
3371 };
3372
3373 static xtensa_arg_internal Iclass_xt_iclass_l32r_stateArgs[] = {
3374 { { STATE_LITBADDR }, 'i' },
3375 { { STATE_LITBEN }, 'i' }
3376 };
3377
3378 static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = {
3379 { { OPERAND_art }, 'o' },
3380 { { OPERAND_ars }, 'i' },
3381 { { OPERAND_uimm8 }, 'i' }
3382 };
3383
3384 static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = {
3385 { { OPERAND_ars }, 'i' },
3386 { { OPERAND_ulabel8 }, 'i' }
3387 };
3388
3389 static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = {
3390 { { STATE_LBEG }, 'o' },
3391 { { STATE_LEND }, 'o' },
3392 { { STATE_LCOUNT }, 'o' }
3393 };
3394
3395 static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = {
3396 { { OPERAND_ars }, 'i' },
3397 { { OPERAND_ulabel8 }, 'i' }
3398 };
3399
3400 static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = {
3401 { { STATE_LBEG }, 'o' },
3402 { { STATE_LEND }, 'o' },
3403 { { STATE_LCOUNT }, 'o' }
3404 };
3405
3406 static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = {
3407 { { OPERAND_art }, 'o' },
3408 { { OPERAND_simm12b }, 'i' }
3409 };
3410
3411 static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = {
3412 { { OPERAND_arr }, 'm' },
3413 { { OPERAND_ars }, 'i' },
3414 { { OPERAND_art }, 'i' }
3415 };
3416
3417 static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = {
3418 { { OPERAND_arr }, 'o' },
3419 { { OPERAND_art }, 'i' }
3420 };
3421
3422 static xtensa_arg_internal Iclass_xt_iclass_return_args[] = {
3423 { { OPERAND__ars_invisible }, 'i' }
3424 };
3425
3426 static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = {
3427 { { OPERAND_art }, 'i' },
3428 { { OPERAND_ars }, 'i' },
3429 { { OPERAND_uimm8x2 }, 'i' }
3430 };
3431
3432 static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = {
3433 { { OPERAND_art }, 'i' },
3434 { { OPERAND_ars }, 'i' },
3435 { { OPERAND_uimm8x4 }, 'i' }
3436 };
3437
3438 static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = {
3439 { { OPERAND_art }, 'i' },
3440 { { OPERAND_ars }, 'i' },
3441 { { OPERAND_uimm8 }, 'i' }
3442 };
3443
3444 static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = {
3445 { { OPERAND_ars }, 'i' }
3446 };
3447
3448 static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = {
3449 { { STATE_SAR }, 'o' }
3450 };
3451
3452 static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = {
3453 { { OPERAND_sas }, 'i' }
3454 };
3455
3456 static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = {
3457 { { STATE_SAR }, 'o' }
3458 };
3459
3460 static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = {
3461 { { OPERAND_arr }, 'o' },
3462 { { OPERAND_ars }, 'i' }
3463 };
3464
3465 static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = {
3466 { { STATE_SAR }, 'i' }
3467 };
3468
3469 static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = {
3470 { { OPERAND_arr }, 'o' },
3471 { { OPERAND_ars }, 'i' },
3472 { { OPERAND_art }, 'i' }
3473 };
3474
3475 static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = {
3476 { { STATE_SAR }, 'i' }
3477 };
3478
3479 static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = {
3480 { { OPERAND_arr }, 'o' },
3481 { { OPERAND_art }, 'i' }
3482 };
3483
3484 static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = {
3485 { { STATE_SAR }, 'i' }
3486 };
3487
3488 static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = {
3489 { { OPERAND_arr }, 'o' },
3490 { { OPERAND_ars }, 'i' },
3491 { { OPERAND_msalp32 }, 'i' }
3492 };
3493
3494 static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = {
3495 { { OPERAND_arr }, 'o' },
3496 { { OPERAND_art }, 'i' },
3497 { { OPERAND_sargt }, 'i' }
3498 };
3499
3500 static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = {
3501 { { OPERAND_arr }, 'o' },
3502 { { OPERAND_art }, 'i' },
3503 { { OPERAND_s }, 'i' }
3504 };
3505
3506 static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = {
3507 { { STATE_XTSYNC }, 'i' }
3508 };
3509
3510 static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = {
3511 { { OPERAND_art }, 'o' },
3512 { { OPERAND_s }, 'i' }
3513 };
3514
3515 static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = {
3516 { { STATE_PSWOE }, 'i' },
3517 { { STATE_PSCALLINC }, 'i' },
3518 { { STATE_PSOWB }, 'i' },
3519 { { STATE_PSRING }, 'i' },
3520 { { STATE_PSUM }, 'i' },
3521 { { STATE_PSEXCM }, 'i' },
3522 { { STATE_PSINTLEVEL }, 'm' }
3523 };
3524
3525 static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = {
3526 { { OPERAND_art }, 'o' }
3527 };
3528
3529 static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = {
3530 { { STATE_LEND }, 'i' }
3531 };
3532
3533 static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = {
3534 { { OPERAND_art }, 'i' }
3535 };
3536
3537 static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = {
3538 { { STATE_LEND }, 'o' }
3539 };
3540
3541 static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = {
3542 { { OPERAND_art }, 'm' }
3543 };
3544
3545 static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = {
3546 { { STATE_LEND }, 'm' }
3547 };
3548
3549 static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = {
3550 { { OPERAND_art }, 'o' }
3551 };
3552
3553 static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = {
3554 { { STATE_LCOUNT }, 'i' }
3555 };
3556
3557 static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = {
3558 { { OPERAND_art }, 'i' }
3559 };
3560
3561 static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = {
3562 { { STATE_XTSYNC }, 'o' },
3563 { { STATE_LCOUNT }, 'o' }
3564 };
3565
3566 static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = {
3567 { { OPERAND_art }, 'm' }
3568 };
3569
3570 static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = {
3571 { { STATE_XTSYNC }, 'o' },
3572 { { STATE_LCOUNT }, 'm' }
3573 };
3574
3575 static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = {
3576 { { OPERAND_art }, 'o' }
3577 };
3578
3579 static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = {
3580 { { STATE_LBEG }, 'i' }
3581 };
3582
3583 static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = {
3584 { { OPERAND_art }, 'i' }
3585 };
3586
3587 static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = {
3588 { { STATE_LBEG }, 'o' }
3589 };
3590
3591 static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = {
3592 { { OPERAND_art }, 'm' }
3593 };
3594
3595 static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = {
3596 { { STATE_LBEG }, 'm' }
3597 };
3598
3599 static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = {
3600 { { OPERAND_art }, 'o' }
3601 };
3602
3603 static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = {
3604 { { STATE_SAR }, 'i' }
3605 };
3606
3607 static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = {
3608 { { OPERAND_art }, 'i' }
3609 };
3610
3611 static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = {
3612 { { STATE_SAR }, 'o' },
3613 { { STATE_XTSYNC }, 'o' }
3614 };
3615
3616 static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = {
3617 { { OPERAND_art }, 'm' }
3618 };
3619
3620 static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = {
3621 { { STATE_SAR }, 'm' }
3622 };
3623
3624 static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = {
3625 { { OPERAND_art }, 'o' }
3626 };
3627
3628 static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_stateArgs[] = {
3629 { { STATE_LITBADDR }, 'i' },
3630 { { STATE_LITBEN }, 'i' }
3631 };
3632
3633 static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = {
3634 { { OPERAND_art }, 'i' }
3635 };
3636
3637 static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_stateArgs[] = {
3638 { { STATE_LITBADDR }, 'o' },
3639 { { STATE_LITBEN }, 'o' }
3640 };
3641
3642 static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = {
3643 { { OPERAND_art }, 'm' }
3644 };
3645
3646 static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_stateArgs[] = {
3647 { { STATE_LITBADDR }, 'm' },
3648 { { STATE_LITBEN }, 'm' }
3649 };
3650
3651 static xtensa_arg_internal Iclass_xt_iclass_rsr_176_args[] = {
3652 { { OPERAND_art }, 'o' }
3653 };
3654
3655 static xtensa_arg_internal Iclass_xt_iclass_rsr_176_stateArgs[] = {
3656 { { STATE_PSEXCM }, 'i' },
3657 { { STATE_PSRING }, 'i' }
3658 };
3659
3660 static xtensa_arg_internal Iclass_xt_iclass_wsr_176_args[] = {
3661 { { OPERAND_art }, 'i' }
3662 };
3663
3664 static xtensa_arg_internal Iclass_xt_iclass_wsr_176_stateArgs[] = {
3665 { { STATE_PSEXCM }, 'i' },
3666 { { STATE_PSRING }, 'i' }
3667 };
3668
3669 static xtensa_arg_internal Iclass_xt_iclass_rsr_208_args[] = {
3670 { { OPERAND_art }, 'o' }
3671 };
3672
3673 static xtensa_arg_internal Iclass_xt_iclass_rsr_208_stateArgs[] = {
3674 { { STATE_PSEXCM }, 'i' },
3675 { { STATE_PSRING }, 'i' }
3676 };
3677
3678 static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = {
3679 { { OPERAND_art }, 'o' }
3680 };
3681
3682 static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = {
3683 { { STATE_PSWOE }, 'i' },
3684 { { STATE_PSCALLINC }, 'i' },
3685 { { STATE_PSOWB }, 'i' },
3686 { { STATE_PSRING }, 'i' },
3687 { { STATE_PSUM }, 'i' },
3688 { { STATE_PSEXCM }, 'i' },
3689 { { STATE_PSINTLEVEL }, 'i' }
3690 };
3691
3692 static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = {
3693 { { OPERAND_art }, 'i' }
3694 };
3695
3696 static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = {
3697 { { STATE_PSWOE }, 'o' },
3698 { { STATE_PSCALLINC }, 'o' },
3699 { { STATE_PSOWB }, 'o' },
3700 { { STATE_PSRING }, 'm' },
3701 { { STATE_PSUM }, 'o' },
3702 { { STATE_PSEXCM }, 'm' },
3703 { { STATE_PSINTLEVEL }, 'o' }
3704 };
3705
3706 static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = {
3707 { { OPERAND_art }, 'm' }
3708 };
3709
3710 static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = {
3711 { { STATE_PSWOE }, 'm' },
3712 { { STATE_PSCALLINC }, 'm' },
3713 { { STATE_PSOWB }, 'm' },
3714 { { STATE_PSRING }, 'm' },
3715 { { STATE_PSUM }, 'm' },
3716 { { STATE_PSEXCM }, 'm' },
3717 { { STATE_PSINTLEVEL }, 'm' }
3718 };
3719
3720 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = {
3721 { { OPERAND_art }, 'o' }
3722 };
3723
3724 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = {
3725 { { STATE_PSEXCM }, 'i' },
3726 { { STATE_PSRING }, 'i' },
3727 { { STATE_EPC1 }, 'i' }
3728 };
3729
3730 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = {
3731 { { OPERAND_art }, 'i' }
3732 };
3733
3734 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = {
3735 { { STATE_PSEXCM }, 'i' },
3736 { { STATE_PSRING }, 'i' },
3737 { { STATE_EPC1 }, 'o' }
3738 };
3739
3740 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = {
3741 { { OPERAND_art }, 'm' }
3742 };
3743
3744 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = {
3745 { { STATE_PSEXCM }, 'i' },
3746 { { STATE_PSRING }, 'i' },
3747 { { STATE_EPC1 }, 'm' }
3748 };
3749
3750 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = {
3751 { { OPERAND_art }, 'o' }
3752 };
3753
3754 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = {
3755 { { STATE_PSEXCM }, 'i' },
3756 { { STATE_PSRING }, 'i' },
3757 { { STATE_EXCSAVE1 }, 'i' }
3758 };
3759
3760 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = {
3761 { { OPERAND_art }, 'i' }
3762 };
3763
3764 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = {
3765 { { STATE_PSEXCM }, 'i' },
3766 { { STATE_PSRING }, 'i' },
3767 { { STATE_EXCSAVE1 }, 'o' }
3768 };
3769
3770 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = {
3771 { { OPERAND_art }, 'm' }
3772 };
3773
3774 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = {
3775 { { STATE_PSEXCM }, 'i' },
3776 { { STATE_PSRING }, 'i' },
3777 { { STATE_EXCSAVE1 }, 'm' }
3778 };
3779
3780 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = {
3781 { { OPERAND_art }, 'o' }
3782 };
3783
3784 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = {
3785 { { STATE_PSEXCM }, 'i' },
3786 { { STATE_PSRING }, 'i' },
3787 { { STATE_EPC2 }, 'i' }
3788 };
3789
3790 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = {
3791 { { OPERAND_art }, 'i' }
3792 };
3793
3794 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = {
3795 { { STATE_PSEXCM }, 'i' },
3796 { { STATE_PSRING }, 'i' },
3797 { { STATE_EPC2 }, 'o' }
3798 };
3799
3800 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = {
3801 { { OPERAND_art }, 'm' }
3802 };
3803
3804 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = {
3805 { { STATE_PSEXCM }, 'i' },
3806 { { STATE_PSRING }, 'i' },
3807 { { STATE_EPC2 }, 'm' }
3808 };
3809
3810 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = {
3811 { { OPERAND_art }, 'o' }
3812 };
3813
3814 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = {
3815 { { STATE_PSEXCM }, 'i' },
3816 { { STATE_PSRING }, 'i' },
3817 { { STATE_EXCSAVE2 }, 'i' }
3818 };
3819
3820 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = {
3821 { { OPERAND_art }, 'i' }
3822 };
3823
3824 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = {
3825 { { STATE_PSEXCM }, 'i' },
3826 { { STATE_PSRING }, 'i' },
3827 { { STATE_EXCSAVE2 }, 'o' }
3828 };
3829
3830 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = {
3831 { { OPERAND_art }, 'm' }
3832 };
3833
3834 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = {
3835 { { STATE_PSEXCM }, 'i' },
3836 { { STATE_PSRING }, 'i' },
3837 { { STATE_EXCSAVE2 }, 'm' }
3838 };
3839
3840 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = {
3841 { { OPERAND_art }, 'o' }
3842 };
3843
3844 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = {
3845 { { STATE_PSEXCM }, 'i' },
3846 { { STATE_PSRING }, 'i' },
3847 { { STATE_EPC3 }, 'i' }
3848 };
3849
3850 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = {
3851 { { OPERAND_art }, 'i' }
3852 };
3853
3854 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = {
3855 { { STATE_PSEXCM }, 'i' },
3856 { { STATE_PSRING }, 'i' },
3857 { { STATE_EPC3 }, 'o' }
3858 };
3859
3860 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = {
3861 { { OPERAND_art }, 'm' }
3862 };
3863
3864 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = {
3865 { { STATE_PSEXCM }, 'i' },
3866 { { STATE_PSRING }, 'i' },
3867 { { STATE_EPC3 }, 'm' }
3868 };
3869
3870 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = {
3871 { { OPERAND_art }, 'o' }
3872 };
3873
3874 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = {
3875 { { STATE_PSEXCM }, 'i' },
3876 { { STATE_PSRING }, 'i' },
3877 { { STATE_EXCSAVE3 }, 'i' }
3878 };
3879
3880 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = {
3881 { { OPERAND_art }, 'i' }
3882 };
3883
3884 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = {
3885 { { STATE_PSEXCM }, 'i' },
3886 { { STATE_PSRING }, 'i' },
3887 { { STATE_EXCSAVE3 }, 'o' }
3888 };
3889
3890 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = {
3891 { { OPERAND_art }, 'm' }
3892 };
3893
3894 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = {
3895 { { STATE_PSEXCM }, 'i' },
3896 { { STATE_PSRING }, 'i' },
3897 { { STATE_EXCSAVE3 }, 'm' }
3898 };
3899
3900 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = {
3901 { { OPERAND_art }, 'o' }
3902 };
3903
3904 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = {
3905 { { STATE_PSEXCM }, 'i' },
3906 { { STATE_PSRING }, 'i' },
3907 { { STATE_EPC4 }, 'i' }
3908 };
3909
3910 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = {
3911 { { OPERAND_art }, 'i' }
3912 };
3913
3914 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = {
3915 { { STATE_PSEXCM }, 'i' },
3916 { { STATE_PSRING }, 'i' },
3917 { { STATE_EPC4 }, 'o' }
3918 };
3919
3920 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = {
3921 { { OPERAND_art }, 'm' }
3922 };
3923
3924 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = {
3925 { { STATE_PSEXCM }, 'i' },
3926 { { STATE_PSRING }, 'i' },
3927 { { STATE_EPC4 }, 'm' }
3928 };
3929
3930 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = {
3931 { { OPERAND_art }, 'o' }
3932 };
3933
3934 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = {
3935 { { STATE_PSEXCM }, 'i' },
3936 { { STATE_PSRING }, 'i' },
3937 { { STATE_EXCSAVE4 }, 'i' }
3938 };
3939
3940 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = {
3941 { { OPERAND_art }, 'i' }
3942 };
3943
3944 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = {
3945 { { STATE_PSEXCM }, 'i' },
3946 { { STATE_PSRING }, 'i' },
3947 { { STATE_EXCSAVE4 }, 'o' }
3948 };
3949
3950 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = {
3951 { { OPERAND_art }, 'm' }
3952 };
3953
3954 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = {
3955 { { STATE_PSEXCM }, 'i' },
3956 { { STATE_PSRING }, 'i' },
3957 { { STATE_EXCSAVE4 }, 'm' }
3958 };
3959
3960 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_args[] = {
3961 { { OPERAND_art }, 'o' }
3962 };
3963
3964 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_stateArgs[] = {
3965 { { STATE_PSEXCM }, 'i' },
3966 { { STATE_PSRING }, 'i' },
3967 { { STATE_EPC5 }, 'i' }
3968 };
3969
3970 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_args[] = {
3971 { { OPERAND_art }, 'i' }
3972 };
3973
3974 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_stateArgs[] = {
3975 { { STATE_PSEXCM }, 'i' },
3976 { { STATE_PSRING }, 'i' },
3977 { { STATE_EPC5 }, 'o' }
3978 };
3979
3980 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_args[] = {
3981 { { OPERAND_art }, 'm' }
3982 };
3983
3984 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_stateArgs[] = {
3985 { { STATE_PSEXCM }, 'i' },
3986 { { STATE_PSRING }, 'i' },
3987 { { STATE_EPC5 }, 'm' }
3988 };
3989
3990 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_args[] = {
3991 { { OPERAND_art }, 'o' }
3992 };
3993
3994 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_stateArgs[] = {
3995 { { STATE_PSEXCM }, 'i' },
3996 { { STATE_PSRING }, 'i' },
3997 { { STATE_EXCSAVE5 }, 'i' }
3998 };
3999
4000 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_args[] = {
4001 { { OPERAND_art }, 'i' }
4002 };
4003
4004 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_stateArgs[] = {
4005 { { STATE_PSEXCM }, 'i' },
4006 { { STATE_PSRING }, 'i' },
4007 { { STATE_EXCSAVE5 }, 'o' }
4008 };
4009
4010 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_args[] = {
4011 { { OPERAND_art }, 'm' }
4012 };
4013
4014 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_stateArgs[] = {
4015 { { STATE_PSEXCM }, 'i' },
4016 { { STATE_PSRING }, 'i' },
4017 { { STATE_EXCSAVE5 }, 'm' }
4018 };
4019
4020 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_args[] = {
4021 { { OPERAND_art }, 'o' }
4022 };
4023
4024 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_stateArgs[] = {
4025 { { STATE_PSEXCM }, 'i' },
4026 { { STATE_PSRING }, 'i' },
4027 { { STATE_EPC6 }, 'i' }
4028 };
4029
4030 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_args[] = {
4031 { { OPERAND_art }, 'i' }
4032 };
4033
4034 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_stateArgs[] = {
4035 { { STATE_PSEXCM }, 'i' },
4036 { { STATE_PSRING }, 'i' },
4037 { { STATE_EPC6 }, 'o' }
4038 };
4039
4040 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_args[] = {
4041 { { OPERAND_art }, 'm' }
4042 };
4043
4044 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_stateArgs[] = {
4045 { { STATE_PSEXCM }, 'i' },
4046 { { STATE_PSRING }, 'i' },
4047 { { STATE_EPC6 }, 'm' }
4048 };
4049
4050 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_args[] = {
4051 { { OPERAND_art }, 'o' }
4052 };
4053
4054 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_stateArgs[] = {
4055 { { STATE_PSEXCM }, 'i' },
4056 { { STATE_PSRING }, 'i' },
4057 { { STATE_EXCSAVE6 }, 'i' }
4058 };
4059
4060 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_args[] = {
4061 { { OPERAND_art }, 'i' }
4062 };
4063
4064 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_stateArgs[] = {
4065 { { STATE_PSEXCM }, 'i' },
4066 { { STATE_PSRING }, 'i' },
4067 { { STATE_EXCSAVE6 }, 'o' }
4068 };
4069
4070 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_args[] = {
4071 { { OPERAND_art }, 'm' }
4072 };
4073
4074 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_stateArgs[] = {
4075 { { STATE_PSEXCM }, 'i' },
4076 { { STATE_PSRING }, 'i' },
4077 { { STATE_EXCSAVE6 }, 'm' }
4078 };
4079
4080 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_args[] = {
4081 { { OPERAND_art }, 'o' }
4082 };
4083
4084 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_stateArgs[] = {
4085 { { STATE_PSEXCM }, 'i' },
4086 { { STATE_PSRING }, 'i' },
4087 { { STATE_EPC7 }, 'i' }
4088 };
4089
4090 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_args[] = {
4091 { { OPERAND_art }, 'i' }
4092 };
4093
4094 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_stateArgs[] = {
4095 { { STATE_PSEXCM }, 'i' },
4096 { { STATE_PSRING }, 'i' },
4097 { { STATE_EPC7 }, 'o' }
4098 };
4099
4100 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_args[] = {
4101 { { OPERAND_art }, 'm' }
4102 };
4103
4104 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_stateArgs[] = {
4105 { { STATE_PSEXCM }, 'i' },
4106 { { STATE_PSRING }, 'i' },
4107 { { STATE_EPC7 }, 'm' }
4108 };
4109
4110 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_args[] = {
4111 { { OPERAND_art }, 'o' }
4112 };
4113
4114 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_stateArgs[] = {
4115 { { STATE_PSEXCM }, 'i' },
4116 { { STATE_PSRING }, 'i' },
4117 { { STATE_EXCSAVE7 }, 'i' }
4118 };
4119
4120 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_args[] = {
4121 { { OPERAND_art }, 'i' }
4122 };
4123
4124 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_stateArgs[] = {
4125 { { STATE_PSEXCM }, 'i' },
4126 { { STATE_PSRING }, 'i' },
4127 { { STATE_EXCSAVE7 }, 'o' }
4128 };
4129
4130 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_args[] = {
4131 { { OPERAND_art }, 'm' }
4132 };
4133
4134 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_stateArgs[] = {
4135 { { STATE_PSEXCM }, 'i' },
4136 { { STATE_PSRING }, 'i' },
4137 { { STATE_EXCSAVE7 }, 'm' }
4138 };
4139
4140 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = {
4141 { { OPERAND_art }, 'o' }
4142 };
4143
4144 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = {
4145 { { STATE_PSEXCM }, 'i' },
4146 { { STATE_PSRING }, 'i' },
4147 { { STATE_EPS2 }, 'i' }
4148 };
4149
4150 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = {
4151 { { OPERAND_art }, 'i' }
4152 };
4153
4154 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = {
4155 { { STATE_PSEXCM }, 'i' },
4156 { { STATE_PSRING }, 'i' },
4157 { { STATE_EPS2 }, 'o' }
4158 };
4159
4160 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = {
4161 { { OPERAND_art }, 'm' }
4162 };
4163
4164 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = {
4165 { { STATE_PSEXCM }, 'i' },
4166 { { STATE_PSRING }, 'i' },
4167 { { STATE_EPS2 }, 'm' }
4168 };
4169
4170 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = {
4171 { { OPERAND_art }, 'o' }
4172 };
4173
4174 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = {
4175 { { STATE_PSEXCM }, 'i' },
4176 { { STATE_PSRING }, 'i' },
4177 { { STATE_EPS3 }, 'i' }
4178 };
4179
4180 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = {
4181 { { OPERAND_art }, 'i' }
4182 };
4183
4184 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = {
4185 { { STATE_PSEXCM }, 'i' },
4186 { { STATE_PSRING }, 'i' },
4187 { { STATE_EPS3 }, 'o' }
4188 };
4189
4190 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = {
4191 { { OPERAND_art }, 'm' }
4192 };
4193
4194 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = {
4195 { { STATE_PSEXCM }, 'i' },
4196 { { STATE_PSRING }, 'i' },
4197 { { STATE_EPS3 }, 'm' }
4198 };
4199
4200 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = {
4201 { { OPERAND_art }, 'o' }
4202 };
4203
4204 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = {
4205 { { STATE_PSEXCM }, 'i' },
4206 { { STATE_PSRING }, 'i' },
4207 { { STATE_EPS4 }, 'i' }
4208 };
4209
4210 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = {
4211 { { OPERAND_art }, 'i' }
4212 };
4213
4214 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = {
4215 { { STATE_PSEXCM }, 'i' },
4216 { { STATE_PSRING }, 'i' },
4217 { { STATE_EPS4 }, 'o' }
4218 };
4219
4220 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = {
4221 { { OPERAND_art }, 'm' }
4222 };
4223
4224 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = {
4225 { { STATE_PSEXCM }, 'i' },
4226 { { STATE_PSRING }, 'i' },
4227 { { STATE_EPS4 }, 'm' }
4228 };
4229
4230 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_args[] = {
4231 { { OPERAND_art }, 'o' }
4232 };
4233
4234 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_stateArgs[] = {
4235 { { STATE_PSEXCM }, 'i' },
4236 { { STATE_PSRING }, 'i' },
4237 { { STATE_EPS5 }, 'i' }
4238 };
4239
4240 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_args[] = {
4241 { { OPERAND_art }, 'i' }
4242 };
4243
4244 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_stateArgs[] = {
4245 { { STATE_PSEXCM }, 'i' },
4246 { { STATE_PSRING }, 'i' },
4247 { { STATE_EPS5 }, 'o' }
4248 };
4249
4250 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_args[] = {
4251 { { OPERAND_art }, 'm' }
4252 };
4253
4254 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_stateArgs[] = {
4255 { { STATE_PSEXCM }, 'i' },
4256 { { STATE_PSRING }, 'i' },
4257 { { STATE_EPS5 }, 'm' }
4258 };
4259
4260 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_args[] = {
4261 { { OPERAND_art }, 'o' }
4262 };
4263
4264 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_stateArgs[] = {
4265 { { STATE_PSEXCM }, 'i' },
4266 { { STATE_PSRING }, 'i' },
4267 { { STATE_EPS6 }, 'i' }
4268 };
4269
4270 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_args[] = {
4271 { { OPERAND_art }, 'i' }
4272 };
4273
4274 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_stateArgs[] = {
4275 { { STATE_PSEXCM }, 'i' },
4276 { { STATE_PSRING }, 'i' },
4277 { { STATE_EPS6 }, 'o' }
4278 };
4279
4280 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_args[] = {
4281 { { OPERAND_art }, 'm' }
4282 };
4283
4284 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_stateArgs[] = {
4285 { { STATE_PSEXCM }, 'i' },
4286 { { STATE_PSRING }, 'i' },
4287 { { STATE_EPS6 }, 'm' }
4288 };
4289
4290 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_args[] = {
4291 { { OPERAND_art }, 'o' }
4292 };
4293
4294 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_stateArgs[] = {
4295 { { STATE_PSEXCM }, 'i' },
4296 { { STATE_PSRING }, 'i' },
4297 { { STATE_EPS7 }, 'i' }
4298 };
4299
4300 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_args[] = {
4301 { { OPERAND_art }, 'i' }
4302 };
4303
4304 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_stateArgs[] = {
4305 { { STATE_PSEXCM }, 'i' },
4306 { { STATE_PSRING }, 'i' },
4307 { { STATE_EPS7 }, 'o' }
4308 };
4309
4310 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_args[] = {
4311 { { OPERAND_art }, 'm' }
4312 };
4313
4314 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_stateArgs[] = {
4315 { { STATE_PSEXCM }, 'i' },
4316 { { STATE_PSRING }, 'i' },
4317 { { STATE_EPS7 }, 'm' }
4318 };
4319
4320 static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = {
4321 { { OPERAND_art }, 'o' }
4322 };
4323
4324 static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = {
4325 { { STATE_PSEXCM }, 'i' },
4326 { { STATE_PSRING }, 'i' },
4327 { { STATE_EXCVADDR }, 'i' }
4328 };
4329
4330 static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = {
4331 { { OPERAND_art }, 'i' }
4332 };
4333
4334 static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = {
4335 { { STATE_PSEXCM }, 'i' },
4336 { { STATE_PSRING }, 'i' },
4337 { { STATE_EXCVADDR }, 'o' }
4338 };
4339
4340 static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = {
4341 { { OPERAND_art }, 'm' }
4342 };
4343
4344 static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = {
4345 { { STATE_PSEXCM }, 'i' },
4346 { { STATE_PSRING }, 'i' },
4347 { { STATE_EXCVADDR }, 'm' }
4348 };
4349
4350 static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = {
4351 { { OPERAND_art }, 'o' }
4352 };
4353
4354 static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = {
4355 { { STATE_PSEXCM }, 'i' },
4356 { { STATE_PSRING }, 'i' },
4357 { { STATE_DEPC }, 'i' }
4358 };
4359
4360 static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = {
4361 { { OPERAND_art }, 'i' }
4362 };
4363
4364 static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = {
4365 { { STATE_PSEXCM }, 'i' },
4366 { { STATE_PSRING }, 'i' },
4367 { { STATE_DEPC }, 'o' }
4368 };
4369
4370 static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = {
4371 { { OPERAND_art }, 'm' }
4372 };
4373
4374 static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = {
4375 { { STATE_PSEXCM }, 'i' },
4376 { { STATE_PSRING }, 'i' },
4377 { { STATE_DEPC }, 'm' }
4378 };
4379
4380 static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = {
4381 { { OPERAND_art }, 'o' }
4382 };
4383
4384 static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = {
4385 { { STATE_PSEXCM }, 'i' },
4386 { { STATE_PSRING }, 'i' },
4387 { { STATE_EXCCAUSE }, 'i' },
4388 { { STATE_XTSYNC }, 'i' }
4389 };
4390
4391 static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = {
4392 { { OPERAND_art }, 'i' }
4393 };
4394
4395 static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = {
4396 { { STATE_PSEXCM }, 'i' },
4397 { { STATE_PSRING }, 'i' },
4398 { { STATE_EXCCAUSE }, 'o' }
4399 };
4400
4401 static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = {
4402 { { OPERAND_art }, 'm' }
4403 };
4404
4405 static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = {
4406 { { STATE_PSEXCM }, 'i' },
4407 { { STATE_PSRING }, 'i' },
4408 { { STATE_EXCCAUSE }, 'm' }
4409 };
4410
4411 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = {
4412 { { OPERAND_art }, 'o' }
4413 };
4414
4415 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = {
4416 { { STATE_PSEXCM }, 'i' },
4417 { { STATE_PSRING }, 'i' },
4418 { { STATE_MISC0 }, 'i' }
4419 };
4420
4421 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = {
4422 { { OPERAND_art }, 'i' }
4423 };
4424
4425 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = {
4426 { { STATE_PSEXCM }, 'i' },
4427 { { STATE_PSRING }, 'i' },
4428 { { STATE_MISC0 }, 'o' }
4429 };
4430
4431 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = {
4432 { { OPERAND_art }, 'm' }
4433 };
4434
4435 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = {
4436 { { STATE_PSEXCM }, 'i' },
4437 { { STATE_PSRING }, 'i' },
4438 { { STATE_MISC0 }, 'm' }
4439 };
4440
4441 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = {
4442 { { OPERAND_art }, 'o' }
4443 };
4444
4445 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = {
4446 { { STATE_PSEXCM }, 'i' },
4447 { { STATE_PSRING }, 'i' },
4448 { { STATE_MISC1 }, 'i' }
4449 };
4450
4451 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = {
4452 { { OPERAND_art }, 'i' }
4453 };
4454
4455 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = {
4456 { { STATE_PSEXCM }, 'i' },
4457 { { STATE_PSRING }, 'i' },
4458 { { STATE_MISC1 }, 'o' }
4459 };
4460
4461 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = {
4462 { { OPERAND_art }, 'm' }
4463 };
4464
4465 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = {
4466 { { STATE_PSEXCM }, 'i' },
4467 { { STATE_PSRING }, 'i' },
4468 { { STATE_MISC1 }, 'm' }
4469 };
4470
4471 static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = {
4472 { { OPERAND_art }, 'o' }
4473 };
4474
4475 static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_stateArgs[] = {
4476 { { STATE_PSEXCM }, 'i' },
4477 { { STATE_PSRING }, 'i' }
4478 };
4479
4480 static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = {
4481 { { OPERAND_art }, 'o' }
4482 };
4483
4484 static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = {
4485 { { STATE_PSEXCM }, 'i' },
4486 { { STATE_PSRING }, 'i' },
4487 { { STATE_VECBASE }, 'i' }
4488 };
4489
4490 static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = {
4491 { { OPERAND_art }, 'i' }
4492 };
4493
4494 static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = {
4495 { { STATE_PSEXCM }, 'i' },
4496 { { STATE_PSRING }, 'i' },
4497 { { STATE_VECBASE }, 'o' }
4498 };
4499
4500 static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = {
4501 { { OPERAND_art }, 'm' }
4502 };
4503
4504 static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = {
4505 { { STATE_PSEXCM }, 'i' },
4506 { { STATE_PSRING }, 'i' },
4507 { { STATE_VECBASE }, 'm' }
4508 };
4509
4510 static xtensa_arg_internal Iclass_xt_mul16_args[] = {
4511 { { OPERAND_arr }, 'o' },
4512 { { OPERAND_ars }, 'i' },
4513 { { OPERAND_art }, 'i' }
4514 };
4515
4516 static xtensa_arg_internal Iclass_xt_mul32_args[] = {
4517 { { OPERAND_arr }, 'o' },
4518 { { OPERAND_ars }, 'i' },
4519 { { OPERAND_art }, 'i' }
4520 };
4521
4522 static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_args[] = {
4523 { { OPERAND_ars }, 'i' },
4524 { { OPERAND_art }, 'i' }
4525 };
4526
4527 static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_stateArgs[] = {
4528 { { STATE_ACC }, 'o' }
4529 };
4530
4531 static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_args[] = {
4532 { { OPERAND_ars }, 'i' },
4533 { { OPERAND_my }, 'i' }
4534 };
4535
4536 static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_stateArgs[] = {
4537 { { STATE_ACC }, 'o' }
4538 };
4539
4540 static xtensa_arg_internal Iclass_xt_iclass_mac16_da_args[] = {
4541 { { OPERAND_mx }, 'i' },
4542 { { OPERAND_art }, 'i' }
4543 };
4544
4545 static xtensa_arg_internal Iclass_xt_iclass_mac16_da_stateArgs[] = {
4546 { { STATE_ACC }, 'o' }
4547 };
4548
4549 static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_args[] = {
4550 { { OPERAND_mx }, 'i' },
4551 { { OPERAND_my }, 'i' }
4552 };
4553
4554 static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_stateArgs[] = {
4555 { { STATE_ACC }, 'o' }
4556 };
4557
4558 static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_args[] = {
4559 { { OPERAND_ars }, 'i' },
4560 { { OPERAND_art }, 'i' }
4561 };
4562
4563 static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_stateArgs[] = {
4564 { { STATE_ACC }, 'm' }
4565 };
4566
4567 static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_args[] = {
4568 { { OPERAND_ars }, 'i' },
4569 { { OPERAND_my }, 'i' }
4570 };
4571
4572 static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_stateArgs[] = {
4573 { { STATE_ACC }, 'm' }
4574 };
4575
4576 static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_args[] = {
4577 { { OPERAND_mx }, 'i' },
4578 { { OPERAND_art }, 'i' }
4579 };
4580
4581 static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_stateArgs[] = {
4582 { { STATE_ACC }, 'm' }
4583 };
4584
4585 static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_args[] = {
4586 { { OPERAND_mx }, 'i' },
4587 { { OPERAND_my }, 'i' }
4588 };
4589
4590 static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_stateArgs[] = {
4591 { { STATE_ACC }, 'm' }
4592 };
4593
4594 static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_args[] = {
4595 { { OPERAND_mw }, 'o' },
4596 { { OPERAND_ars }, 'm' },
4597 { { OPERAND_mx }, 'i' },
4598 { { OPERAND_art }, 'i' }
4599 };
4600
4601 static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_stateArgs[] = {
4602 { { STATE_ACC }, 'm' }
4603 };
4604
4605 static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_args[] = {
4606 { { OPERAND_mw }, 'o' },
4607 { { OPERAND_ars }, 'm' },
4608 { { OPERAND_mx }, 'i' },
4609 { { OPERAND_my }, 'i' }
4610 };
4611
4612 static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_stateArgs[] = {
4613 { { STATE_ACC }, 'm' }
4614 };
4615
4616 static xtensa_arg_internal Iclass_xt_iclass_mac16_l_args[] = {
4617 { { OPERAND_mw }, 'o' },
4618 { { OPERAND_ars }, 'm' }
4619 };
4620
4621 static xtensa_arg_internal Iclass_xt_iclass_rsr_m0_args[] = {
4622 { { OPERAND_art }, 'o' },
4623 { { OPERAND_mr0 }, 'i' }
4624 };
4625
4626 static xtensa_arg_internal Iclass_xt_iclass_wsr_m0_args[] = {
4627 { { OPERAND_art }, 'i' },
4628 { { OPERAND_mr0 }, 'o' }
4629 };
4630
4631 static xtensa_arg_internal Iclass_xt_iclass_xsr_m0_args[] = {
4632 { { OPERAND_art }, 'm' },
4633 { { OPERAND_mr0 }, 'm' }
4634 };
4635
4636 static xtensa_arg_internal Iclass_xt_iclass_rsr_m1_args[] = {
4637 { { OPERAND_art }, 'o' },
4638 { { OPERAND_mr1 }, 'i' }
4639 };
4640
4641 static xtensa_arg_internal Iclass_xt_iclass_wsr_m1_args[] = {
4642 { { OPERAND_art }, 'i' },
4643 { { OPERAND_mr1 }, 'o' }
4644 };
4645
4646 static xtensa_arg_internal Iclass_xt_iclass_xsr_m1_args[] = {
4647 { { OPERAND_art }, 'm' },
4648 { { OPERAND_mr1 }, 'm' }
4649 };
4650
4651 static xtensa_arg_internal Iclass_xt_iclass_rsr_m2_args[] = {
4652 { { OPERAND_art }, 'o' },
4653 { { OPERAND_mr2 }, 'i' }
4654 };
4655
4656 static xtensa_arg_internal Iclass_xt_iclass_wsr_m2_args[] = {
4657 { { OPERAND_art }, 'i' },
4658 { { OPERAND_mr2 }, 'o' }
4659 };
4660
4661 static xtensa_arg_internal Iclass_xt_iclass_xsr_m2_args[] = {
4662 { { OPERAND_art }, 'm' },
4663 { { OPERAND_mr2 }, 'm' }
4664 };
4665
4666 static xtensa_arg_internal Iclass_xt_iclass_rsr_m3_args[] = {
4667 { { OPERAND_art }, 'o' },
4668 { { OPERAND_mr3 }, 'i' }
4669 };
4670
4671 static xtensa_arg_internal Iclass_xt_iclass_wsr_m3_args[] = {
4672 { { OPERAND_art }, 'i' },
4673 { { OPERAND_mr3 }, 'o' }
4674 };
4675
4676 static xtensa_arg_internal Iclass_xt_iclass_xsr_m3_args[] = {
4677 { { OPERAND_art }, 'm' },
4678 { { OPERAND_mr3 }, 'm' }
4679 };
4680
4681 static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_args[] = {
4682 { { OPERAND_art }, 'o' }
4683 };
4684
4685 static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_stateArgs[] = {
4686 { { STATE_ACC }, 'i' }
4687 };
4688
4689 static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_args[] = {
4690 { { OPERAND_art }, 'i' }
4691 };
4692
4693 static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_stateArgs[] = {
4694 { { STATE_ACC }, 'm' }
4695 };
4696
4697 static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_args[] = {
4698 { { OPERAND_art }, 'm' }
4699 };
4700
4701 static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_stateArgs[] = {
4702 { { STATE_ACC }, 'm' }
4703 };
4704
4705 static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_args[] = {
4706 { { OPERAND_art }, 'o' }
4707 };
4708
4709 static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_stateArgs[] = {
4710 { { STATE_ACC }, 'i' }
4711 };
4712
4713 static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_args[] = {
4714 { { OPERAND_art }, 'i' }
4715 };
4716
4717 static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_stateArgs[] = {
4718 { { STATE_ACC }, 'm' }
4719 };
4720
4721 static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_args[] = {
4722 { { OPERAND_art }, 'm' }
4723 };
4724
4725 static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_stateArgs[] = {
4726 { { STATE_ACC }, 'm' }
4727 };
4728
4729 static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = {
4730 { { OPERAND_s }, 'i' }
4731 };
4732
4733 static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = {
4734 { { STATE_PSWOE }, 'o' },
4735 { { STATE_PSCALLINC }, 'o' },
4736 { { STATE_PSOWB }, 'o' },
4737 { { STATE_PSRING }, 'm' },
4738 { { STATE_PSUM }, 'o' },
4739 { { STATE_PSEXCM }, 'm' },
4740 { { STATE_PSINTLEVEL }, 'o' },
4741 { { STATE_EPC1 }, 'i' },
4742 { { STATE_EPC2 }, 'i' },
4743 { { STATE_EPC3 }, 'i' },
4744 { { STATE_EPC4 }, 'i' },
4745 { { STATE_EPC5 }, 'i' },
4746 { { STATE_EPC6 }, 'i' },
4747 { { STATE_EPC7 }, 'i' },
4748 { { STATE_EPS2 }, 'i' },
4749 { { STATE_EPS3 }, 'i' },
4750 { { STATE_EPS4 }, 'i' },
4751 { { STATE_EPS5 }, 'i' },
4752 { { STATE_EPS6 }, 'i' },
4753 { { STATE_EPS7 }, 'i' },
4754 { { STATE_InOCDMode }, 'm' }
4755 };
4756
4757 static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = {
4758 { { OPERAND_s }, 'i' }
4759 };
4760
4761 static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = {
4762 { { STATE_PSEXCM }, 'i' },
4763 { { STATE_PSRING }, 'i' },
4764 { { STATE_PSINTLEVEL }, 'o' }
4765 };
4766
4767 static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = {
4768 { { OPERAND_art }, 'o' }
4769 };
4770
4771 static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = {
4772 { { STATE_PSEXCM }, 'i' },
4773 { { STATE_PSRING }, 'i' },
4774 { { STATE_INTERRUPT }, 'i' }
4775 };
4776
4777 static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = {
4778 { { OPERAND_art }, 'i' }
4779 };
4780
4781 static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = {
4782 { { STATE_PSEXCM }, 'i' },
4783 { { STATE_PSRING }, 'i' },
4784 { { STATE_XTSYNC }, 'o' },
4785 { { STATE_INTERRUPT }, 'm' }
4786 };
4787
4788 static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = {
4789 { { OPERAND_art }, 'i' }
4790 };
4791
4792 static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = {
4793 { { STATE_PSEXCM }, 'i' },
4794 { { STATE_PSRING }, 'i' },
4795 { { STATE_XTSYNC }, 'o' },
4796 { { STATE_INTERRUPT }, 'm' }
4797 };
4798
4799 static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = {
4800 { { OPERAND_art }, 'o' }
4801 };
4802
4803 static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = {
4804 { { STATE_PSEXCM }, 'i' },
4805 { { STATE_PSRING }, 'i' },
4806 { { STATE_INTENABLE }, 'i' }
4807 };
4808
4809 static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = {
4810 { { OPERAND_art }, 'i' }
4811 };
4812
4813 static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = {
4814 { { STATE_PSEXCM }, 'i' },
4815 { { STATE_PSRING }, 'i' },
4816 { { STATE_INTENABLE }, 'o' }
4817 };
4818
4819 static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = {
4820 { { OPERAND_art }, 'm' }
4821 };
4822
4823 static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = {
4824 { { STATE_PSEXCM }, 'i' },
4825 { { STATE_PSRING }, 'i' },
4826 { { STATE_INTENABLE }, 'm' }
4827 };
4828
4829 static xtensa_arg_internal Iclass_xt_iclass_break_args[] = {
4830 { { OPERAND_imms }, 'i' },
4831 { { OPERAND_immt }, 'i' }
4832 };
4833
4834 static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = {
4835 { { STATE_PSEXCM }, 'i' },
4836 { { STATE_PSINTLEVEL }, 'i' }
4837 };
4838
4839 static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = {
4840 { { OPERAND_imms }, 'i' }
4841 };
4842
4843 static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = {
4844 { { STATE_PSEXCM }, 'i' },
4845 { { STATE_PSINTLEVEL }, 'i' }
4846 };
4847
4848 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = {
4849 { { OPERAND_art }, 'o' }
4850 };
4851
4852 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = {
4853 { { STATE_PSEXCM }, 'i' },
4854 { { STATE_PSRING }, 'i' },
4855 { { STATE_DBREAKA0 }, 'i' }
4856 };
4857
4858 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = {
4859 { { OPERAND_art }, 'i' }
4860 };
4861
4862 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = {
4863 { { STATE_PSEXCM }, 'i' },
4864 { { STATE_PSRING }, 'i' },
4865 { { STATE_DBREAKA0 }, 'o' },
4866 { { STATE_XTSYNC }, 'o' }
4867 };
4868
4869 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = {
4870 { { OPERAND_art }, 'm' }
4871 };
4872
4873 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = {
4874 { { STATE_PSEXCM }, 'i' },
4875 { { STATE_PSRING }, 'i' },
4876 { { STATE_DBREAKA0 }, 'm' },
4877 { { STATE_XTSYNC }, 'o' }
4878 };
4879
4880 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = {
4881 { { OPERAND_art }, 'o' }
4882 };
4883
4884 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = {
4885 { { STATE_PSEXCM }, 'i' },
4886 { { STATE_PSRING }, 'i' },
4887 { { STATE_DBREAKC0 }, 'i' }
4888 };
4889
4890 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = {
4891 { { OPERAND_art }, 'i' }
4892 };
4893
4894 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = {
4895 { { STATE_PSEXCM }, 'i' },
4896 { { STATE_PSRING }, 'i' },
4897 { { STATE_DBREAKC0 }, 'o' },
4898 { { STATE_XTSYNC }, 'o' }
4899 };
4900
4901 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = {
4902 { { OPERAND_art }, 'm' }
4903 };
4904
4905 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = {
4906 { { STATE_PSEXCM }, 'i' },
4907 { { STATE_PSRING }, 'i' },
4908 { { STATE_DBREAKC0 }, 'm' },
4909 { { STATE_XTSYNC }, 'o' }
4910 };
4911
4912 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = {
4913 { { OPERAND_art }, 'o' }
4914 };
4915
4916 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = {
4917 { { STATE_PSEXCM }, 'i' },
4918 { { STATE_PSRING }, 'i' },
4919 { { STATE_DBREAKA1 }, 'i' }
4920 };
4921
4922 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = {
4923 { { OPERAND_art }, 'i' }
4924 };
4925
4926 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = {
4927 { { STATE_PSEXCM }, 'i' },
4928 { { STATE_PSRING }, 'i' },
4929 { { STATE_DBREAKA1 }, 'o' },
4930 { { STATE_XTSYNC }, 'o' }
4931 };
4932
4933 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = {
4934 { { OPERAND_art }, 'm' }
4935 };
4936
4937 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = {
4938 { { STATE_PSEXCM }, 'i' },
4939 { { STATE_PSRING }, 'i' },
4940 { { STATE_DBREAKA1 }, 'm' },
4941 { { STATE_XTSYNC }, 'o' }
4942 };
4943
4944 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = {
4945 { { OPERAND_art }, 'o' }
4946 };
4947
4948 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = {
4949 { { STATE_PSEXCM }, 'i' },
4950 { { STATE_PSRING }, 'i' },
4951 { { STATE_DBREAKC1 }, 'i' }
4952 };
4953
4954 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = {
4955 { { OPERAND_art }, 'i' }
4956 };
4957
4958 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = {
4959 { { STATE_PSEXCM }, 'i' },
4960 { { STATE_PSRING }, 'i' },
4961 { { STATE_DBREAKC1 }, 'o' },
4962 { { STATE_XTSYNC }, 'o' }
4963 };
4964
4965 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = {
4966 { { OPERAND_art }, 'm' }
4967 };
4968
4969 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = {
4970 { { STATE_PSEXCM }, 'i' },
4971 { { STATE_PSRING }, 'i' },
4972 { { STATE_DBREAKC1 }, 'm' },
4973 { { STATE_XTSYNC }, 'o' }
4974 };
4975
4976 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = {
4977 { { OPERAND_art }, 'o' }
4978 };
4979
4980 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = {
4981 { { STATE_PSEXCM }, 'i' },
4982 { { STATE_PSRING }, 'i' },
4983 { { STATE_IBREAKA0 }, 'i' }
4984 };
4985
4986 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = {
4987 { { OPERAND_art }, 'i' }
4988 };
4989
4990 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = {
4991 { { STATE_PSEXCM }, 'i' },
4992 { { STATE_PSRING }, 'i' },
4993 { { STATE_IBREAKA0 }, 'o' }
4994 };
4995
4996 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = {
4997 { { OPERAND_art }, 'm' }
4998 };
4999
5000 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = {
Showing first 5,000 of 15,205 lines. View raw