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1 /* Xtensa configuration-specific ISA information.
2
3 Copyright (c) 2003-2015 Tensilica Inc.
4
5 Permission is hereby granted, free of charge, to any person obtaining
6 a copy of this software and associated documentation files (the
7 "Software"), to deal in the Software without restriction, including
8 without limitation the rights to use, copy, modify, merge, publish,
9 distribute, sublicense, and/or sell copies of the Software, and to
10 permit persons to whom the Software is furnished to do so, subject to
11 the following conditions:
12
13 The above copyright notice and this permission notice shall be included
14 in all copies or substantial portions of the Software.
15
16 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
17 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
19 IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
20 CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
23
24 #include "qemu/osdep.h"
25 #include "xtensa-isa.h"
26 #include "xtensa-isa-internal.h"
27
28
29 /* Sysregs. */
30
31 static xtensa_sysreg_internal sysregs[] = {
32 { "LBEG", 0, 0 },
33 { "LEND", 1, 0 },
34 { "LCOUNT", 2, 0 },
35 { "ACCLO", 16, 0 },
36 { "ACCHI", 17, 0 },
37 { "M0", 32, 0 },
38 { "M1", 33, 0 },
39 { "M2", 34, 0 },
40 { "M3", 35, 0 },
41 { "MMID", 89, 0 },
42 { "DDR", 104, 0 },
43 { "CONFIGID0", 176, 0 },
44 { "CONFIGID1", 208, 0 },
45 { "INTERRUPT", 226, 0 },
46 { "INTCLEAR", 227, 0 },
47 { "CCOUNT", 234, 0 },
48 { "PRID", 235, 0 },
49 { "ICOUNT", 236, 0 },
50 { "CCOMPARE0", 240, 0 },
51 { "CCOMPARE1", 241, 0 },
52 { "CCOMPARE2", 242, 0 },
53 { "VECBASE", 231, 0 },
54 { "EPC1", 177, 0 },
55 { "EPC2", 178, 0 },
56 { "EPC3", 179, 0 },
57 { "EPC4", 180, 0 },
58 { "EPC5", 181, 0 },
59 { "EPC6", 182, 0 },
60 { "EPC7", 183, 0 },
61 { "EXCSAVE1", 209, 0 },
62 { "EXCSAVE2", 210, 0 },
63 { "EXCSAVE3", 211, 0 },
64 { "EXCSAVE4", 212, 0 },
65 { "EXCSAVE5", 213, 0 },
66 { "EXCSAVE6", 214, 0 },
67 { "EXCSAVE7", 215, 0 },
68 { "EPS2", 194, 0 },
69 { "EPS3", 195, 0 },
70 { "EPS4", 196, 0 },
71 { "EPS5", 197, 0 },
72 { "EPS6", 198, 0 },
73 { "EPS7", 199, 0 },
74 { "EXCCAUSE", 232, 0 },
75 { "DEPC", 192, 0 },
76 { "EXCVADDR", 238, 0 },
77 { "WINDOWBASE", 72, 0 },
78 { "WINDOWSTART", 73, 0 },
79 { "SAR", 3, 0 },
80 { "PS", 230, 0 },
81 { "MISC0", 244, 0 },
82 { "MISC1", 245, 0 },
83 { "INTENABLE", 228, 0 },
84 { "DBREAKA0", 144, 0 },
85 { "DBREAKC0", 160, 0 },
86 { "DBREAKA1", 145, 0 },
87 { "DBREAKC1", 161, 0 },
88 { "IBREAKA0", 128, 0 },
89 { "IBREAKA1", 129, 0 },
90 { "IBREAKENABLE", 96, 0 },
91 { "ICOUNTLEVEL", 237, 0 },
92 { "DEBUGCAUSE", 233, 0 },
93 { "SCOMPARE1", 12, 0 },
94 { "ATOMCTL", 99, 0 },
95 { "EXPSTATE", 230, 1 }
96 };
97
98 #define NUM_SYSREGS 64
99 #define MAX_SPECIAL_REG 245
100 #define MAX_USER_REG 230
101
102
103 /* Processor states. */
104
105 static xtensa_state_internal states[] = {
106 { "LCOUNT", 32, 0 },
107 { "PC", 32, 0 },
108 { "ICOUNT", 32, 0 },
109 { "DDR", 32, 0 },
110 { "INTERRUPT", 22, 0 },
111 { "CCOUNT", 32, 0 },
112 { "XTSYNC", 1, 0 },
113 { "VECBASE", 22, 0 },
114 { "EPC1", 32, 0 },
115 { "EPC2", 32, 0 },
116 { "EPC3", 32, 0 },
117 { "EPC4", 32, 0 },
118 { "EPC5", 32, 0 },
119 { "EPC6", 32, 0 },
120 { "EPC7", 32, 0 },
121 { "EXCSAVE1", 32, 0 },
122 { "EXCSAVE2", 32, 0 },
123 { "EXCSAVE3", 32, 0 },
124 { "EXCSAVE4", 32, 0 },
125 { "EXCSAVE5", 32, 0 },
126 { "EXCSAVE6", 32, 0 },
127 { "EXCSAVE7", 32, 0 },
128 { "EPS2", 13, 0 },
129 { "EPS3", 13, 0 },
130 { "EPS4", 13, 0 },
131 { "EPS5", 13, 0 },
132 { "EPS6", 13, 0 },
133 { "EPS7", 13, 0 },
134 { "EXCCAUSE", 6, 0 },
135 { "PSINTLEVEL", 4, 0 },
136 { "PSUM", 1, 0 },
137 { "PSWOE", 1, 0 },
138 { "PSEXCM", 1, 0 },
139 { "DEPC", 32, 0 },
140 { "EXCVADDR", 32, 0 },
141 { "WindowBase", 3, 0 },
142 { "WindowStart", 8, 0 },
143 { "PSCALLINC", 2, 0 },
144 { "PSOWB", 4, 0 },
145 { "LBEG", 32, 0 },
146 { "LEND", 32, 0 },
147 { "SAR", 6, 0 },
148 { "MISC0", 32, 0 },
149 { "MISC1", 32, 0 },
150 { "ACC", 40, 0 },
151 { "InOCDMode", 1, 0 },
152 { "INTENABLE", 22, 0 },
153 { "DBREAKA0", 32, 0 },
154 { "DBREAKC0", 8, 0 },
155 { "DBREAKA1", 32, 0 },
156 { "DBREAKC1", 8, 0 },
157 { "IBREAKA0", 32, 0 },
158 { "IBREAKA1", 32, 0 },
159 { "IBREAKENABLE", 2, 0 },
160 { "ICOUNTLEVEL", 4, 0 },
161 { "DEBUGCAUSE", 6, 0 },
162 { "DBNUM", 4, 0 },
163 { "CCOMPARE0", 32, 0 },
164 { "CCOMPARE1", 32, 0 },
165 { "CCOMPARE2", 32, 0 },
166 { "SCOMPARE1", 32, 0 },
167 { "ATOMCTL", 6, 0 },
168 { "ERI_RAW_INTERLOCK", 1, 0 },
169 { "EXPSTATE", 32, XTENSA_STATE_IS_EXPORTED }
170 };
171
172 #define NUM_STATES 64
173
174 enum xtensa_state_id {
175 STATE_LCOUNT,
176 STATE_PC,
177 STATE_ICOUNT,
178 STATE_DDR,
179 STATE_INTERRUPT,
180 STATE_CCOUNT,
181 STATE_XTSYNC,
182 STATE_VECBASE,
183 STATE_EPC1,
184 STATE_EPC2,
185 STATE_EPC3,
186 STATE_EPC4,
187 STATE_EPC5,
188 STATE_EPC6,
189 STATE_EPC7,
190 STATE_EXCSAVE1,
191 STATE_EXCSAVE2,
192 STATE_EXCSAVE3,
193 STATE_EXCSAVE4,
194 STATE_EXCSAVE5,
195 STATE_EXCSAVE6,
196 STATE_EXCSAVE7,
197 STATE_EPS2,
198 STATE_EPS3,
199 STATE_EPS4,
200 STATE_EPS5,
201 STATE_EPS6,
202 STATE_EPS7,
203 STATE_EXCCAUSE,
204 STATE_PSINTLEVEL,
205 STATE_PSUM,
206 STATE_PSWOE,
207 STATE_PSEXCM,
208 STATE_DEPC,
209 STATE_EXCVADDR,
210 STATE_WindowBase,
211 STATE_WindowStart,
212 STATE_PSCALLINC,
213 STATE_PSOWB,
214 STATE_LBEG,
215 STATE_LEND,
216 STATE_SAR,
217 STATE_MISC0,
218 STATE_MISC1,
219 STATE_ACC,
220 STATE_InOCDMode,
221 STATE_INTENABLE,
222 STATE_DBREAKA0,
223 STATE_DBREAKC0,
224 STATE_DBREAKA1,
225 STATE_DBREAKC1,
226 STATE_IBREAKA0,
227 STATE_IBREAKA1,
228 STATE_IBREAKENABLE,
229 STATE_ICOUNTLEVEL,
230 STATE_DEBUGCAUSE,
231 STATE_DBNUM,
232 STATE_CCOMPARE0,
233 STATE_CCOMPARE1,
234 STATE_CCOMPARE2,
235 STATE_SCOMPARE1,
236 STATE_ATOMCTL,
237 STATE_ERI_RAW_INTERLOCK,
238 STATE_EXPSTATE
239 };
240
241
242 /* Field definitions. */
243
244 static unsigned
245 Field_t_Slot_inst_get (const xtensa_insnbuf insn)
246 {
247 unsigned tie_t = 0;
248 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
249 return tie_t;
250 }
251
252 static void
253 Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
254 {
255 uint32 tie_t;
256 tie_t = (val << 28) >> 28;
257 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
258 }
259
260 static unsigned
261 Field_s_Slot_inst_get (const xtensa_insnbuf insn)
262 {
263 unsigned tie_t = 0;
264 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
265 return tie_t;
266 }
267
268 static void
269 Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
270 {
271 uint32 tie_t;
272 tie_t = (val << 28) >> 28;
273 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
274 }
275
276 static unsigned
277 Field_r_Slot_inst_get (const xtensa_insnbuf insn)
278 {
279 unsigned tie_t = 0;
280 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
281 return tie_t;
282 }
283
284 static void
285 Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
286 {
287 uint32 tie_t;
288 tie_t = (val << 28) >> 28;
289 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
290 }
291
292 static unsigned
293 Field_op2_Slot_inst_get (const xtensa_insnbuf insn)
294 {
295 unsigned tie_t = 0;
296 tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28);
297 return tie_t;
298 }
299
300 static void
301 Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
302 {
303 uint32 tie_t;
304 tie_t = (val << 28) >> 28;
305 insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20);
306 }
307
308 static unsigned
309 Field_op1_Slot_inst_get (const xtensa_insnbuf insn)
310 {
311 unsigned tie_t = 0;
312 tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
313 return tie_t;
314 }
315
316 static void
317 Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
318 {
319 uint32 tie_t;
320 tie_t = (val << 28) >> 28;
321 insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
322 }
323
324 static unsigned
325 Field_op0_Slot_inst_get (const xtensa_insnbuf insn)
326 {
327 unsigned tie_t = 0;
328 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
329 return tie_t;
330 }
331
332 static void
333 Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
334 {
335 uint32 tie_t;
336 tie_t = (val << 28) >> 28;
337 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
338 }
339
340 static unsigned
341 Field_n_Slot_inst_get (const xtensa_insnbuf insn)
342 {
343 unsigned tie_t = 0;
344 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
345 return tie_t;
346 }
347
348 static void
349 Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
350 {
351 uint32 tie_t;
352 tie_t = (val << 30) >> 30;
353 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
354 }
355
356 static unsigned
357 Field_m_Slot_inst_get (const xtensa_insnbuf insn)
358 {
359 unsigned tie_t = 0;
360 tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
361 return tie_t;
362 }
363
364 static void
365 Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
366 {
367 uint32 tie_t;
368 tie_t = (val << 30) >> 30;
369 insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
370 }
371
372 static unsigned
373 Field_sr_Slot_inst_get (const xtensa_insnbuf insn)
374 {
375 unsigned tie_t = 0;
376 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
377 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
378 return tie_t;
379 }
380
381 static void
382 Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
383 {
384 uint32 tie_t;
385 tie_t = (val << 28) >> 28;
386 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
387 tie_t = (val << 24) >> 28;
388 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
389 }
390
391 static unsigned
392 Field_thi3_Slot_inst_get (const xtensa_insnbuf insn)
393 {
394 unsigned tie_t = 0;
395 tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
396 return tie_t;
397 }
398
399 static void
400 Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
401 {
402 uint32 tie_t;
403 tie_t = (val << 29) >> 29;
404 insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
405 }
406
407 static unsigned
408 Field_t3_Slot_inst_get (const xtensa_insnbuf insn)
409 {
410 unsigned tie_t = 0;
411 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
412 return tie_t;
413 }
414
415 static void
416 Field_t3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
417 {
418 uint32 tie_t;
419 tie_t = (val << 31) >> 31;
420 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
421 }
422
423 static unsigned
424 Field_tlo_Slot_inst_get (const xtensa_insnbuf insn)
425 {
426 unsigned tie_t = 0;
427 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
428 return tie_t;
429 }
430
431 static void
432 Field_tlo_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
433 {
434 uint32 tie_t;
435 tie_t = (val << 30) >> 30;
436 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
437 }
438
439 static unsigned
440 Field_w_Slot_inst_get (const xtensa_insnbuf insn)
441 {
442 unsigned tie_t = 0;
443 tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30);
444 return tie_t;
445 }
446
447 static void
448 Field_w_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
449 {
450 uint32 tie_t;
451 tie_t = (val << 30) >> 30;
452 insn[0] = (insn[0] & ~0x3000) | (tie_t << 12);
453 }
454
455 static unsigned
456 Field_r3_Slot_inst_get (const xtensa_insnbuf insn)
457 {
458 unsigned tie_t = 0;
459 tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
460 return tie_t;
461 }
462
463 static void
464 Field_r3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
465 {
466 uint32 tie_t;
467 tie_t = (val << 31) >> 31;
468 insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
469 }
470
471 static unsigned
472 Field_rhi_Slot_inst_get (const xtensa_insnbuf insn)
473 {
474 unsigned tie_t = 0;
475 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
476 return tie_t;
477 }
478
479 static void
480 Field_rhi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
481 {
482 uint32 tie_t;
483 tie_t = (val << 30) >> 30;
484 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
485 }
486
487 static unsigned
488 Field_st_Slot_inst_get (const xtensa_insnbuf insn)
489 {
490 unsigned tie_t = 0;
491 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
492 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
493 return tie_t;
494 }
495
496 static void
497 Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
498 {
499 uint32 tie_t;
500 tie_t = (val << 28) >> 28;
501 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
502 tie_t = (val << 24) >> 28;
503 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
504 }
505
506 static unsigned
507 Field_s3to1_Slot_inst_get (const xtensa_insnbuf insn)
508 {
509 unsigned tie_t = 0;
510 tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
511 return tie_t;
512 }
513
514 static void
515 Field_s3to1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
516 {
517 uint32 tie_t;
518 tie_t = (val << 29) >> 29;
519 insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
520 }
521
522 static unsigned
523 Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn)
524 {
525 unsigned tie_t = 0;
526 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
527 return tie_t;
528 }
529
530 static void
531 Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
532 {
533 uint32 tie_t;
534 tie_t = (val << 28) >> 28;
535 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
536 }
537
538 static unsigned
539 Field_t_Slot_inst16b_get (const xtensa_insnbuf insn)
540 {
541 unsigned tie_t = 0;
542 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
543 return tie_t;
544 }
545
546 static void
547 Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
548 {
549 uint32 tie_t;
550 tie_t = (val << 28) >> 28;
551 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
552 }
553
554 static unsigned
555 Field_r_Slot_inst16b_get (const xtensa_insnbuf insn)
556 {
557 unsigned tie_t = 0;
558 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
559 return tie_t;
560 }
561
562 static void
563 Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
564 {
565 uint32 tie_t;
566 tie_t = (val << 28) >> 28;
567 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
568 }
569
570 static unsigned
571 Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn)
572 {
573 unsigned tie_t = 0;
574 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
575 return tie_t;
576 }
577
578 static void
579 Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
580 {
581 uint32 tie_t;
582 tie_t = (val << 28) >> 28;
583 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
584 }
585
586 static unsigned
587 Field_z_Slot_inst16b_get (const xtensa_insnbuf insn)
588 {
589 unsigned tie_t = 0;
590 tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
591 return tie_t;
592 }
593
594 static void
595 Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
596 {
597 uint32 tie_t;
598 tie_t = (val << 31) >> 31;
599 insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
600 }
601
602 static unsigned
603 Field_i_Slot_inst16b_get (const xtensa_insnbuf insn)
604 {
605 unsigned tie_t = 0;
606 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
607 return tie_t;
608 }
609
610 static void
611 Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
612 {
613 uint32 tie_t;
614 tie_t = (val << 31) >> 31;
615 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
616 }
617
618 static unsigned
619 Field_s_Slot_inst16b_get (const xtensa_insnbuf insn)
620 {
621 unsigned tie_t = 0;
622 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
623 return tie_t;
624 }
625
626 static void
627 Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
628 {
629 uint32 tie_t;
630 tie_t = (val << 28) >> 28;
631 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
632 }
633
634 static unsigned
635 Field_t_Slot_inst16a_get (const xtensa_insnbuf insn)
636 {
637 unsigned tie_t = 0;
638 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
639 return tie_t;
640 }
641
642 static void
643 Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
644 {
645 uint32 tie_t;
646 tie_t = (val << 28) >> 28;
647 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
648 }
649
650 static unsigned
651 Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn)
652 {
653 unsigned tie_t = 0;
654 tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
655 return tie_t;
656 }
657
658 static void
659 Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
660 {
661 uint32 tie_t;
662 tie_t = (val << 31) >> 31;
663 insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
664 }
665
666 static unsigned
667 Field_bbi_Slot_inst_get (const xtensa_insnbuf insn)
668 {
669 unsigned tie_t = 0;
670 tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
671 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
672 return tie_t;
673 }
674
675 static void
676 Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
677 {
678 uint32 tie_t;
679 tie_t = (val << 28) >> 28;
680 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
681 tie_t = (val << 27) >> 31;
682 insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
683 }
684
685 static unsigned
686 Field_imm12_Slot_inst_get (const xtensa_insnbuf insn)
687 {
688 unsigned tie_t = 0;
689 tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20);
690 return tie_t;
691 }
692
693 static void
694 Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
695 {
696 uint32 tie_t;
697 tie_t = (val << 20) >> 20;
698 insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12);
699 }
700
701 static unsigned
702 Field_imm8_Slot_inst_get (const xtensa_insnbuf insn)
703 {
704 unsigned tie_t = 0;
705 tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
706 return tie_t;
707 }
708
709 static void
710 Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
711 {
712 uint32 tie_t;
713 tie_t = (val << 24) >> 24;
714 insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
715 }
716
717 static unsigned
718 Field_s_Slot_inst16a_get (const xtensa_insnbuf insn)
719 {
720 unsigned tie_t = 0;
721 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
722 return tie_t;
723 }
724
725 static void
726 Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
727 {
728 uint32 tie_t;
729 tie_t = (val << 28) >> 28;
730 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
731 }
732
733 static unsigned
734 Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn)
735 {
736 unsigned tie_t = 0;
737 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
738 tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
739 return tie_t;
740 }
741
742 static void
743 Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
744 {
745 uint32 tie_t;
746 tie_t = (val << 24) >> 24;
747 insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
748 tie_t = (val << 20) >> 28;
749 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
750 }
751
752 static unsigned
753 Field_imm16_Slot_inst_get (const xtensa_insnbuf insn)
754 {
755 unsigned tie_t = 0;
756 tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16);
757 return tie_t;
758 }
759
760 static void
761 Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
762 {
763 uint32 tie_t;
764 tie_t = (val << 16) >> 16;
765 insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8);
766 }
767
768 static unsigned
769 Field_offset_Slot_inst_get (const xtensa_insnbuf insn)
770 {
771 unsigned tie_t = 0;
772 tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
773 return tie_t;
774 }
775
776 static void
777 Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
778 {
779 uint32 tie_t;
780 tie_t = (val << 14) >> 14;
781 insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
782 }
783
784 static unsigned
785 Field_r_Slot_inst16a_get (const xtensa_insnbuf insn)
786 {
787 unsigned tie_t = 0;
788 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
789 return tie_t;
790 }
791
792 static void
793 Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
794 {
795 uint32 tie_t;
796 tie_t = (val << 28) >> 28;
797 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
798 }
799
800 static unsigned
801 Field_sa4_Slot_inst_get (const xtensa_insnbuf insn)
802 {
803 unsigned tie_t = 0;
804 tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
805 return tie_t;
806 }
807
808 static void
809 Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
810 {
811 uint32 tie_t;
812 tie_t = (val << 31) >> 31;
813 insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
814 }
815
816 static unsigned
817 Field_sae4_Slot_inst_get (const xtensa_insnbuf insn)
818 {
819 unsigned tie_t = 0;
820 tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
821 return tie_t;
822 }
823
824 static void
825 Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
826 {
827 uint32 tie_t;
828 tie_t = (val << 31) >> 31;
829 insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
830 }
831
832 static unsigned
833 Field_sae_Slot_inst_get (const xtensa_insnbuf insn)
834 {
835 unsigned tie_t = 0;
836 tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
837 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
838 return tie_t;
839 }
840
841 static void
842 Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
843 {
844 uint32 tie_t;
845 tie_t = (val << 28) >> 28;
846 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
847 tie_t = (val << 27) >> 31;
848 insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
849 }
850
851 static unsigned
852 Field_sal_Slot_inst_get (const xtensa_insnbuf insn)
853 {
854 unsigned tie_t = 0;
855 tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
856 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
857 return tie_t;
858 }
859
860 static void
861 Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
862 {
863 uint32 tie_t;
864 tie_t = (val << 28) >> 28;
865 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
866 tie_t = (val << 27) >> 31;
867 insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
868 }
869
870 static unsigned
871 Field_sargt_Slot_inst_get (const xtensa_insnbuf insn)
872 {
873 unsigned tie_t = 0;
874 tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
875 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
876 return tie_t;
877 }
878
879 static void
880 Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
881 {
882 uint32 tie_t;
883 tie_t = (val << 28) >> 28;
884 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
885 tie_t = (val << 27) >> 31;
886 insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
887 }
888
889 static unsigned
890 Field_sas4_Slot_inst_get (const xtensa_insnbuf insn)
891 {
892 unsigned tie_t = 0;
893 tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
894 return tie_t;
895 }
896
897 static void
898 Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
899 {
900 uint32 tie_t;
901 tie_t = (val << 31) >> 31;
902 insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
903 }
904
905 static unsigned
906 Field_sas_Slot_inst_get (const xtensa_insnbuf insn)
907 {
908 unsigned tie_t = 0;
909 tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
910 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
911 return tie_t;
912 }
913
914 static void
915 Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
916 {
917 uint32 tie_t;
918 tie_t = (val << 28) >> 28;
919 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
920 tie_t = (val << 27) >> 31;
921 insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
922 }
923
924 static unsigned
925 Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn)
926 {
927 unsigned tie_t = 0;
928 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
929 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
930 return tie_t;
931 }
932
933 static void
934 Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
935 {
936 uint32 tie_t;
937 tie_t = (val << 28) >> 28;
938 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
939 tie_t = (val << 24) >> 28;
940 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
941 }
942
943 static unsigned
944 Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn)
945 {
946 unsigned tie_t = 0;
947 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
948 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
949 return tie_t;
950 }
951
952 static void
953 Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
954 {
955 uint32 tie_t;
956 tie_t = (val << 28) >> 28;
957 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
958 tie_t = (val << 24) >> 28;
959 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
960 }
961
962 static unsigned
963 Field_st_Slot_inst16a_get (const xtensa_insnbuf insn)
964 {
965 unsigned tie_t = 0;
966 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
967 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
968 return tie_t;
969 }
970
971 static void
972 Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
973 {
974 uint32 tie_t;
975 tie_t = (val << 28) >> 28;
976 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
977 tie_t = (val << 24) >> 28;
978 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
979 }
980
981 static unsigned
982 Field_st_Slot_inst16b_get (const xtensa_insnbuf insn)
983 {
984 unsigned tie_t = 0;
985 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
986 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
987 return tie_t;
988 }
989
990 static void
991 Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
992 {
993 uint32 tie_t;
994 tie_t = (val << 28) >> 28;
995 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
996 tie_t = (val << 24) >> 28;
997 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
998 }
999
1000 static unsigned
1001 Field_imm4_Slot_inst_get (const xtensa_insnbuf insn)
1002 {
1003 unsigned tie_t = 0;
1004 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1005 return tie_t;
1006 }
1007
1008 static void
1009 Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1010 {
1011 uint32 tie_t;
1012 tie_t = (val << 28) >> 28;
1013 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1014 }
1015
1016 static unsigned
1017 Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn)
1018 {
1019 unsigned tie_t = 0;
1020 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1021 return tie_t;
1022 }
1023
1024 static void
1025 Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1026 {
1027 uint32 tie_t;
1028 tie_t = (val << 28) >> 28;
1029 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1030 }
1031
1032 static unsigned
1033 Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn)
1034 {
1035 unsigned tie_t = 0;
1036 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1037 return tie_t;
1038 }
1039
1040 static void
1041 Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1042 {
1043 uint32 tie_t;
1044 tie_t = (val << 28) >> 28;
1045 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1046 }
1047
1048 static unsigned
1049 Field_mn_Slot_inst_get (const xtensa_insnbuf insn)
1050 {
1051 unsigned tie_t = 0;
1052 tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
1053 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1054 return tie_t;
1055 }
1056
1057 static void
1058 Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1059 {
1060 uint32 tie_t;
1061 tie_t = (val << 30) >> 30;
1062 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1063 tie_t = (val << 28) >> 30;
1064 insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
1065 }
1066
1067 static unsigned
1068 Field_i_Slot_inst16a_get (const xtensa_insnbuf insn)
1069 {
1070 unsigned tie_t = 0;
1071 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
1072 return tie_t;
1073 }
1074
1075 static void
1076 Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1077 {
1078 uint32 tie_t;
1079 tie_t = (val << 31) >> 31;
1080 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
1081 }
1082
1083 static unsigned
1084 Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn)
1085 {
1086 unsigned tie_t = 0;
1087 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1088 return tie_t;
1089 }
1090
1091 static void
1092 Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1093 {
1094 uint32 tie_t;
1095 tie_t = (val << 28) >> 28;
1096 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1097 }
1098
1099 static unsigned
1100 Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn)
1101 {
1102 unsigned tie_t = 0;
1103 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1104 return tie_t;
1105 }
1106
1107 static void
1108 Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1109 {
1110 uint32 tie_t;
1111 tie_t = (val << 28) >> 28;
1112 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1113 }
1114
1115 static unsigned
1116 Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn)
1117 {
1118 unsigned tie_t = 0;
1119 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1120 return tie_t;
1121 }
1122
1123 static void
1124 Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1125 {
1126 uint32 tie_t;
1127 tie_t = (val << 30) >> 30;
1128 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1129 }
1130
1131 static unsigned
1132 Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn)
1133 {
1134 unsigned tie_t = 0;
1135 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1136 return tie_t;
1137 }
1138
1139 static void
1140 Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1141 {
1142 uint32 tie_t;
1143 tie_t = (val << 30) >> 30;
1144 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1145 }
1146
1147 static unsigned
1148 Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn)
1149 {
1150 unsigned tie_t = 0;
1151 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1152 return tie_t;
1153 }
1154
1155 static void
1156 Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1157 {
1158 uint32 tie_t;
1159 tie_t = (val << 28) >> 28;
1160 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1161 }
1162
1163 static unsigned
1164 Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn)
1165 {
1166 unsigned tie_t = 0;
1167 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1168 return tie_t;
1169 }
1170
1171 static void
1172 Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1173 {
1174 uint32 tie_t;
1175 tie_t = (val << 28) >> 28;
1176 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1177 }
1178
1179 static unsigned
1180 Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn)
1181 {
1182 unsigned tie_t = 0;
1183 tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
1184 return tie_t;
1185 }
1186
1187 static void
1188 Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1189 {
1190 uint32 tie_t;
1191 tie_t = (val << 29) >> 29;
1192 insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
1193 }
1194
1195 static unsigned
1196 Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn)
1197 {
1198 unsigned tie_t = 0;
1199 tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
1200 return tie_t;
1201 }
1202
1203 static void
1204 Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1205 {
1206 uint32 tie_t;
1207 tie_t = (val << 29) >> 29;
1208 insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
1209 }
1210
1211 static unsigned
1212 Field_z_Slot_inst16a_get (const xtensa_insnbuf insn)
1213 {
1214 unsigned tie_t = 0;
1215 tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
1216 return tie_t;
1217 }
1218
1219 static void
1220 Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1221 {
1222 uint32 tie_t;
1223 tie_t = (val << 31) >> 31;
1224 insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
1225 }
1226
1227 static unsigned
1228 Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn)
1229 {
1230 unsigned tie_t = 0;
1231 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1232 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1233 return tie_t;
1234 }
1235
1236 static void
1237 Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1238 {
1239 uint32 tie_t;
1240 tie_t = (val << 28) >> 28;
1241 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1242 tie_t = (val << 26) >> 30;
1243 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1244 }
1245
1246 static unsigned
1247 Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn)
1248 {
1249 unsigned tie_t = 0;
1250 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1251 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1252 return tie_t;
1253 }
1254
1255 static void
1256 Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1257 {
1258 uint32 tie_t;
1259 tie_t = (val << 28) >> 28;
1260 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1261 tie_t = (val << 26) >> 30;
1262 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1263 }
1264
1265 static unsigned
1266 Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn)
1267 {
1268 unsigned tie_t = 0;
1269 tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
1270 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1271 return tie_t;
1272 }
1273
1274 static void
1275 Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1276 {
1277 uint32 tie_t;
1278 tie_t = (val << 28) >> 28;
1279 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1280 tie_t = (val << 25) >> 29;
1281 insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
1282 }
1283
1284 static unsigned
1285 Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn)
1286 {
1287 unsigned tie_t = 0;
1288 tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
1289 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1290 return tie_t;
1291 }
1292
1293 static void
1294 Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1295 {
1296 uint32 tie_t;
1297 tie_t = (val << 28) >> 28;
1298 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1299 tie_t = (val << 25) >> 29;
1300 insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
1301 }
1302
1303 static unsigned
1304 Field_rbit2_Slot_inst_get (const xtensa_insnbuf insn)
1305 {
1306 unsigned tie_t = 0;
1307 tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
1308 return tie_t;
1309 }
1310
1311 static void
1312 Field_rbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1313 {
1314 uint32 tie_t;
1315 tie_t = (val << 31) >> 31;
1316 insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
1317 }
1318
1319 static unsigned
1320 Field_tbit2_Slot_inst_get (const xtensa_insnbuf insn)
1321 {
1322 unsigned tie_t = 0;
1323 tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
1324 return tie_t;
1325 }
1326
1327 static void
1328 Field_tbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1329 {
1330 uint32 tie_t;
1331 tie_t = (val << 31) >> 31;
1332 insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
1333 }
1334
1335 static unsigned
1336 Field_y_Slot_inst_get (const xtensa_insnbuf insn)
1337 {
1338 unsigned tie_t = 0;
1339 tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
1340 return tie_t;
1341 }
1342
1343 static void
1344 Field_y_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1345 {
1346 uint32 tie_t;
1347 tie_t = (val << 31) >> 31;
1348 insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
1349 }
1350
1351 static unsigned
1352 Field_x_Slot_inst_get (const xtensa_insnbuf insn)
1353 {
1354 unsigned tie_t = 0;
1355 tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
1356 return tie_t;
1357 }
1358
1359 static void
1360 Field_x_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1361 {
1362 uint32 tie_t;
1363 tie_t = (val << 31) >> 31;
1364 insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
1365 }
1366
1367 static unsigned
1368 Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn)
1369 {
1370 unsigned tie_t = 0;
1371 tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17);
1372 return tie_t;
1373 }
1374
1375 static void
1376 Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1377 {
1378 uint32 tie_t;
1379 tie_t = (val << 17) >> 17;
1380 insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9);
1381 }
1382
1383 static unsigned
1384 Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn)
1385 {
1386 unsigned tie_t = 0;
1387 tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
1388 return tie_t;
1389 }
1390
1391 static void
1392 Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1393 {
1394 uint32 tie_t;
1395 tie_t = (val << 14) >> 14;
1396 insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
1397 }
1398
1399 static unsigned
1400 Field_bitindex_Slot_inst_get (const xtensa_insnbuf insn)
1401 {
1402 unsigned tie_t = 0;
1403 tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
1404 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1405 return tie_t;
1406 }
1407
1408 static void
1409 Field_bitindex_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1410 {
1411 uint32 tie_t;
1412 tie_t = (val << 28) >> 28;
1413 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1414 tie_t = (val << 27) >> 31;
1415 insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
1416 }
1417
1418 static unsigned
1419 Field_bitindex_Slot_inst16a_get (const xtensa_insnbuf insn)
1420 {
1421 unsigned tie_t = 0;
1422 tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
1423 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1424 return tie_t;
1425 }
1426
1427 static void
1428 Field_bitindex_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1429 {
1430 uint32 tie_t;
1431 tie_t = (val << 28) >> 28;
1432 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1433 tie_t = (val << 27) >> 31;
1434 insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
1435 }
1436
1437 static unsigned
1438 Field_bitindex_Slot_inst16b_get (const xtensa_insnbuf insn)
1439 {
1440 unsigned tie_t = 0;
1441 tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
1442 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1443 return tie_t;
1444 }
1445
1446 static void
1447 Field_bitindex_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1448 {
1449 uint32 tie_t;
1450 tie_t = (val << 28) >> 28;
1451 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1452 tie_t = (val << 27) >> 31;
1453 insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
1454 }
1455
1456 static unsigned
1457 Field_s3to1_Slot_inst16a_get (const xtensa_insnbuf insn)
1458 {
1459 unsigned tie_t = 0;
1460 tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
1461 return tie_t;
1462 }
1463
1464 static void
1465 Field_s3to1_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1466 {
1467 uint32 tie_t;
1468 tie_t = (val << 29) >> 29;
1469 insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
1470 }
1471
1472 static unsigned
1473 Field_s3to1_Slot_inst16b_get (const xtensa_insnbuf insn)
1474 {
1475 unsigned tie_t = 0;
1476 tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
1477 return tie_t;
1478 }
1479
1480 static void
1481 Field_s3to1_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1482 {
1483 uint32 tie_t;
1484 tie_t = (val << 29) >> 29;
1485 insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
1486 }
1487
1488 static void
1489 Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED,
1490 uint32 val ATTRIBUTE_UNUSED)
1491 {
1492 /* Do nothing. */
1493 }
1494
1495 static unsigned
1496 Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1497 {
1498 return 0;
1499 }
1500
1501 static unsigned
1502 Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1503 {
1504 return 4;
1505 }
1506
1507 static unsigned
1508 Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1509 {
1510 return 8;
1511 }
1512
1513 static unsigned
1514 Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1515 {
1516 return 12;
1517 }
1518
1519 static unsigned
1520 Implicit_Field_mr0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1521 {
1522 return 0;
1523 }
1524
1525 static unsigned
1526 Implicit_Field_mr1_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1527 {
1528 return 1;
1529 }
1530
1531 static unsigned
1532 Implicit_Field_mr2_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1533 {
1534 return 2;
1535 }
1536
1537 static unsigned
1538 Implicit_Field_mr3_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1539 {
1540 return 3;
1541 }
1542
1543 enum xtensa_field_id {
1544 FIELD_t,
1545 FIELD_bbi4,
1546 FIELD_bbi,
1547 FIELD_imm12,
1548 FIELD_imm8,
1549 FIELD_s,
1550 FIELD_imm12b,
1551 FIELD_imm16,
1552 FIELD_m,
1553 FIELD_n,
1554 FIELD_offset,
1555 FIELD_op0,
1556 FIELD_op1,
1557 FIELD_op2,
1558 FIELD_r,
1559 FIELD_sa4,
1560 FIELD_sae4,
1561 FIELD_sae,
1562 FIELD_sal,
1563 FIELD_sargt,
1564 FIELD_sas4,
1565 FIELD_sas,
1566 FIELD_sr,
1567 FIELD_st,
1568 FIELD_thi3,
1569 FIELD_imm4,
1570 FIELD_mn,
1571 FIELD_i,
1572 FIELD_imm6lo,
1573 FIELD_imm6hi,
1574 FIELD_imm7lo,
1575 FIELD_imm7hi,
1576 FIELD_z,
1577 FIELD_imm6,
1578 FIELD_imm7,
1579 FIELD_r3,
1580 FIELD_rbit2,
1581 FIELD_rhi,
1582 FIELD_t3,
1583 FIELD_tbit2,
1584 FIELD_tlo,
1585 FIELD_w,
1586 FIELD_y,
1587 FIELD_x,
1588 FIELD_xt_wbr15_imm,
1589 FIELD_xt_wbr18_imm,
1590 FIELD_bitindex,
1591 FIELD_s3to1,
1592 FIELD__ar0,
1593 FIELD__ar4,
1594 FIELD__ar8,
1595 FIELD__ar12,
1596 FIELD__mr0,
1597 FIELD__mr1,
1598 FIELD__mr2,
1599 FIELD__mr3
1600 };
1601
1602
1603 /* Functional units. */
1604
1605 #define funcUnits 0
1606
1607
1608 /* Register files. */
1609
1610 enum xtensa_regfile_id {
1611 REGFILE_AR,
1612 REGFILE_MR
1613 };
1614
1615 static xtensa_regfile_internal regfiles[] = {
1616 { "AR", "a", REGFILE_AR, 32, 32 },
1617 { "MR", "m", REGFILE_MR, 32, 4 }
1618 };
1619
1620
1621 /* Interfaces. */
1622
1623 static xtensa_interface_internal interfaces[] = {
1624 { "ERI_RD_Out", 14, 0, 0, 'o' },
1625 { "ERI_RD_In", 32, 0, 1, 'i' },
1626 { "ERI_RD_Rdy", 1, 0, 0, 'i' },
1627 { "ERI_WR_Out", 46, 0, 2, 'o' },
1628 { "ERI_WR_In", 1, 0, 3, 'i' },
1629 { "IMPWIRE", 32, 0, 4, 'i' }
1630 };
1631
1632 enum xtensa_interface_id {
1633 INTERFACE_ERI_RD_Out,
1634 INTERFACE_ERI_RD_In,
1635 INTERFACE_ERI_RD_Rdy,
1636 INTERFACE_ERI_WR_Out,
1637 INTERFACE_ERI_WR_In,
1638 INTERFACE_IMPWIRE
1639 };
1640
1641
1642 /* Constant tables. */
1643
1644 /* constant table ai4c */
1645 static const unsigned CONST_TBL_ai4c_0[] = {
1646 0xffffffff,
1647 0x1,
1648 0x2,
1649 0x3,
1650 0x4,
1651 0x5,
1652 0x6,
1653 0x7,
1654 0x8,
1655 0x9,
1656 0xa,
1657 0xb,
1658 0xc,
1659 0xd,
1660 0xe,
1661 0xf,
1662 0
1663 };
1664
1665 /* constant table b4c */
1666 static const unsigned CONST_TBL_b4c_0[] = {
1667 0xffffffff,
1668 0x1,
1669 0x2,
1670 0x3,
1671 0x4,
1672 0x5,
1673 0x6,
1674 0x7,
1675 0x8,
1676 0xa,
1677 0xc,
1678 0x10,
1679 0x20,
1680 0x40,
1681 0x80,
1682 0x100,
1683 0
1684 };
1685
1686 /* constant table b4cu */
1687 static const unsigned CONST_TBL_b4cu_0[] = {
1688 0x8000,
1689 0x10000,
1690 0x2,
1691 0x3,
1692 0x4,
1693 0x5,
1694 0x6,
1695 0x7,
1696 0x8,
1697 0xa,
1698 0xc,
1699 0x10,
1700 0x20,
1701 0x40,
1702 0x80,
1703 0x100,
1704 0
1705 };
1706
1707
1708 /* Instruction operands. */
1709
1710 static int
1711 OperandSem_opnd_sem_MR_0_decode (uint32 *valp)
1712 {
1713 *valp += 2;
1714 return 0;
1715 }
1716
1717 static int
1718 OperandSem_opnd_sem_MR_0_encode (uint32 *valp)
1719 {
1720 int error;
1721 error = ((*valp & ~0x3) != 0) || ((*valp & 0x2) == 0);
1722 *valp = *valp & 1;
1723 return error;
1724 }
1725
1726 static int
1727 OperandSem_opnd_sem_soffsetx4_decode (uint32 *valp)
1728 {
1729 unsigned soffsetx4_out_0;
1730 unsigned soffsetx4_in_0;
1731 soffsetx4_in_0 = *valp & 0x3ffff;
1732 soffsetx4_out_0 = 0x4 + ((((int) soffsetx4_in_0 << 14) >> 14) << 2);
1733 *valp = soffsetx4_out_0;
1734 return 0;
1735 }
1736
1737 static int
1738 OperandSem_opnd_sem_soffsetx4_encode (uint32 *valp)
1739 {
1740 unsigned soffsetx4_in_0;
1741 unsigned soffsetx4_out_0;
1742 soffsetx4_out_0 = *valp;
1743 soffsetx4_in_0 = ((soffsetx4_out_0 - 0x4) >> 2) & 0x3ffff;
1744 *valp = soffsetx4_in_0;
1745 return 0;
1746 }
1747
1748 static int
1749 OperandSem_opnd_sem_uimm12x8_decode (uint32 *valp)
1750 {
1751 unsigned uimm12x8_out_0;
1752 unsigned uimm12x8_in_0;
1753 uimm12x8_in_0 = *valp & 0xfff;
1754 uimm12x8_out_0 = uimm12x8_in_0 << 3;
1755 *valp = uimm12x8_out_0;
1756 return 0;
1757 }
1758
1759 static int
1760 OperandSem_opnd_sem_uimm12x8_encode (uint32 *valp)
1761 {
1762 unsigned uimm12x8_in_0;
1763 unsigned uimm12x8_out_0;
1764 uimm12x8_out_0 = *valp;
1765 uimm12x8_in_0 = ((uimm12x8_out_0 >> 3) & 0xfff);
1766 *valp = uimm12x8_in_0;
1767 return 0;
1768 }
1769
1770 static int
1771 OperandSem_opnd_sem_simm4_decode (uint32 *valp)
1772 {
1773 unsigned simm4_out_0;
1774 unsigned simm4_in_0;
1775 simm4_in_0 = *valp & 0xf;
1776 simm4_out_0 = ((int) simm4_in_0 << 28) >> 28;
1777 *valp = simm4_out_0;
1778 return 0;
1779 }
1780
1781 static int
1782 OperandSem_opnd_sem_simm4_encode (uint32 *valp)
1783 {
1784 unsigned simm4_in_0;
1785 unsigned simm4_out_0;
1786 simm4_out_0 = *valp;
1787 simm4_in_0 = (simm4_out_0 & 0xf);
1788 *valp = simm4_in_0;
1789 return 0;
1790 }
1791
1792 static int
1793 OperandSem_opnd_sem_AR_decode (uint32 *valp ATTRIBUTE_UNUSED)
1794 {
1795 return 0;
1796 }
1797
1798 static int
1799 OperandSem_opnd_sem_AR_encode (uint32 *valp)
1800 {
1801 return (*valp >= 32);
1802 }
1803
1804 static int
1805 OperandSem_opnd_sem_AR_0_decode (uint32 *valp ATTRIBUTE_UNUSED)
1806 {
1807 return 0;
1808 }
1809
1810 static int
1811 OperandSem_opnd_sem_AR_0_encode (uint32 *valp)
1812 {
1813 return (*valp >= 32);
1814 }
1815
1816 static int
1817 OperandSem_opnd_sem_AR_1_decode (uint32 *valp ATTRIBUTE_UNUSED)
1818 {
1819 return 0;
1820 }
1821
1822 static int
1823 OperandSem_opnd_sem_AR_1_encode (uint32 *valp)
1824 {
1825 return (*valp >= 32);
1826 }
1827
1828 static int
1829 OperandSem_opnd_sem_AR_2_decode (uint32 *valp ATTRIBUTE_UNUSED)
1830 {
1831 return 0;
1832 }
1833
1834 static int
1835 OperandSem_opnd_sem_AR_2_encode (uint32 *valp)
1836 {
1837 return (*valp >= 32);
1838 }
1839
1840 static int
1841 OperandSem_opnd_sem_AR_3_decode (uint32 *valp ATTRIBUTE_UNUSED)
1842 {
1843 return 0;
1844 }
1845
1846 static int
1847 OperandSem_opnd_sem_AR_3_encode (uint32 *valp)
1848 {
1849 return (*valp >= 32);
1850 }
1851
1852 static int
1853 OperandSem_opnd_sem_AR_4_decode (uint32 *valp ATTRIBUTE_UNUSED)
1854 {
1855 return 0;
1856 }
1857
1858 static int
1859 OperandSem_opnd_sem_AR_4_encode (uint32 *valp)
1860 {
1861 return (*valp >= 32);
1862 }
1863
1864 static int
1865 OperandSem_opnd_sem_immrx4_decode (uint32 *valp)
1866 {
1867 unsigned immrx4_out_0;
1868 unsigned immrx4_in_0;
1869 immrx4_in_0 = *valp & 0xf;
1870 immrx4_out_0 = (((0xfffffff) << 4) | immrx4_in_0) << 2;
1871 *valp = immrx4_out_0;
1872 return 0;
1873 }
1874
1875 static int
1876 OperandSem_opnd_sem_immrx4_encode (uint32 *valp)
1877 {
1878 unsigned immrx4_in_0;
1879 unsigned immrx4_out_0;
1880 immrx4_out_0 = *valp;
1881 immrx4_in_0 = ((immrx4_out_0 >> 2) & 0xf);
1882 *valp = immrx4_in_0;
1883 return 0;
1884 }
1885
1886 static int
1887 OperandSem_opnd_sem_lsi4x4_decode (uint32 *valp)
1888 {
1889 unsigned lsi4x4_out_0;
1890 unsigned lsi4x4_in_0;
1891 lsi4x4_in_0 = *valp & 0xf;
1892 lsi4x4_out_0 = lsi4x4_in_0 << 2;
1893 *valp = lsi4x4_out_0;
1894 return 0;
1895 }
1896
1897 static int
1898 OperandSem_opnd_sem_lsi4x4_encode (uint32 *valp)
1899 {
1900 unsigned lsi4x4_in_0;
1901 unsigned lsi4x4_out_0;
1902 lsi4x4_out_0 = *valp;
1903 lsi4x4_in_0 = ((lsi4x4_out_0 >> 2) & 0xf);
1904 *valp = lsi4x4_in_0;
1905 return 0;
1906 }
1907
1908 static int
1909 OperandSem_opnd_sem_simm7_decode (uint32 *valp)
1910 {
1911 unsigned simm7_out_0;
1912 unsigned simm7_in_0;
1913 simm7_in_0 = *valp & 0x7f;
1914 simm7_out_0 = ((((-((((simm7_in_0 >> 6) & 1)) & (((simm7_in_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | simm7_in_0;
1915 *valp = simm7_out_0;
1916 return 0;
1917 }
1918
1919 static int
1920 OperandSem_opnd_sem_simm7_encode (uint32 *valp)
1921 {
1922 unsigned simm7_in_0;
1923 unsigned simm7_out_0;
1924 simm7_out_0 = *valp;
1925 simm7_in_0 = (simm7_out_0 & 0x7f);
1926 *valp = simm7_in_0;
1927 return 0;
1928 }
1929
1930 static int
1931 OperandSem_opnd_sem_uimm6_decode (uint32 *valp)
1932 {
1933 unsigned uimm6_out_0;
1934 unsigned uimm6_in_0;
1935 uimm6_in_0 = *valp & 0x3f;
1936 uimm6_out_0 = 0x4 + (((0) << 6) | uimm6_in_0);
1937 *valp = uimm6_out_0;
1938 return 0;
1939 }
1940
1941 static int
1942 OperandSem_opnd_sem_uimm6_encode (uint32 *valp)
1943 {
1944 unsigned uimm6_in_0;
1945 unsigned uimm6_out_0;
1946 uimm6_out_0 = *valp;
1947 uimm6_in_0 = (uimm6_out_0 - 0x4) & 0x3f;
1948 *valp = uimm6_in_0;
1949 return 0;
1950 }
1951
1952 static int
1953 OperandSem_opnd_sem_ai4const_decode (uint32 *valp)
1954 {
1955 unsigned ai4const_out_0;
1956 unsigned ai4const_in_0;
1957 ai4const_in_0 = *valp & 0xf;
1958 ai4const_out_0 = CONST_TBL_ai4c_0[ai4const_in_0 & 0xf];
1959 *valp = ai4const_out_0;
1960 return 0;
1961 }
1962
1963 static int
1964 OperandSem_opnd_sem_ai4const_encode (uint32 *valp)
1965 {
1966 unsigned ai4const_in_0;
1967 unsigned ai4const_out_0;
1968 ai4const_out_0 = *valp;
1969 switch (ai4const_out_0)
1970 {
1971 case 0xffffffff: ai4const_in_0 = 0; break;
1972 case 0x1: ai4const_in_0 = 0x1; break;
1973 case 0x2: ai4const_in_0 = 0x2; break;
1974 case 0x3: ai4const_in_0 = 0x3; break;
1975 case 0x4: ai4const_in_0 = 0x4; break;
1976 case 0x5: ai4const_in_0 = 0x5; break;
1977 case 0x6: ai4const_in_0 = 0x6; break;
1978 case 0x7: ai4const_in_0 = 0x7; break;
1979 case 0x8: ai4const_in_0 = 0x8; break;
1980 case 0x9: ai4const_in_0 = 0x9; break;
1981 case 0xa: ai4const_in_0 = 0xa; break;
1982 case 0xb: ai4const_in_0 = 0xb; break;
1983 case 0xc: ai4const_in_0 = 0xc; break;
1984 case 0xd: ai4const_in_0 = 0xd; break;
1985 case 0xe: ai4const_in_0 = 0xe; break;
1986 default: ai4const_in_0 = 0xf; break;
1987 }
1988 *valp = ai4const_in_0;
1989 return 0;
1990 }
1991
1992 static int
1993 OperandSem_opnd_sem_b4const_decode (uint32 *valp)
1994 {
1995 unsigned b4const_out_0;
1996 unsigned b4const_in_0;
1997 b4const_in_0 = *valp & 0xf;
1998 b4const_out_0 = CONST_TBL_b4c_0[b4const_in_0 & 0xf];
1999 *valp = b4const_out_0;
2000 return 0;
2001 }
2002
2003 static int
2004 OperandSem_opnd_sem_b4const_encode (uint32 *valp)
2005 {
2006 unsigned b4const_in_0;
2007 unsigned b4const_out_0;
2008 b4const_out_0 = *valp;
2009 switch (b4const_out_0)
2010 {
2011 case 0xffffffff: b4const_in_0 = 0; break;
2012 case 0x1: b4const_in_0 = 0x1; break;
2013 case 0x2: b4const_in_0 = 0x2; break;
2014 case 0x3: b4const_in_0 = 0x3; break;
2015 case 0x4: b4const_in_0 = 0x4; break;
2016 case 0x5: b4const_in_0 = 0x5; break;
2017 case 0x6: b4const_in_0 = 0x6; break;
2018 case 0x7: b4const_in_0 = 0x7; break;
2019 case 0x8: b4const_in_0 = 0x8; break;
2020 case 0xa: b4const_in_0 = 0x9; break;
2021 case 0xc: b4const_in_0 = 0xa; break;
2022 case 0x10: b4const_in_0 = 0xb; break;
2023 case 0x20: b4const_in_0 = 0xc; break;
2024 case 0x40: b4const_in_0 = 0xd; break;
2025 case 0x80: b4const_in_0 = 0xe; break;
2026 default: b4const_in_0 = 0xf; break;
2027 }
2028 *valp = b4const_in_0;
2029 return 0;
2030 }
2031
2032 static int
2033 OperandSem_opnd_sem_b4constu_decode (uint32 *valp)
2034 {
2035 unsigned b4constu_out_0;
2036 unsigned b4constu_in_0;
2037 b4constu_in_0 = *valp & 0xf;
2038 b4constu_out_0 = CONST_TBL_b4cu_0[b4constu_in_0 & 0xf];
2039 *valp = b4constu_out_0;
2040 return 0;
2041 }
2042
2043 static int
2044 OperandSem_opnd_sem_b4constu_encode (uint32 *valp)
2045 {
2046 unsigned b4constu_in_0;
2047 unsigned b4constu_out_0;
2048 b4constu_out_0 = *valp;
2049 switch (b4constu_out_0)
2050 {
2051 case 0x8000: b4constu_in_0 = 0; break;
2052 case 0x10000: b4constu_in_0 = 0x1; break;
2053 case 0x2: b4constu_in_0 = 0x2; break;
2054 case 0x3: b4constu_in_0 = 0x3; break;
2055 case 0x4: b4constu_in_0 = 0x4; break;
2056 case 0x5: b4constu_in_0 = 0x5; break;
2057 case 0x6: b4constu_in_0 = 0x6; break;
2058 case 0x7: b4constu_in_0 = 0x7; break;
2059 case 0x8: b4constu_in_0 = 0x8; break;
2060 case 0xa: b4constu_in_0 = 0x9; break;
2061 case 0xc: b4constu_in_0 = 0xa; break;
2062 case 0x10: b4constu_in_0 = 0xb; break;
2063 case 0x20: b4constu_in_0 = 0xc; break;
2064 case 0x40: b4constu_in_0 = 0xd; break;
2065 case 0x80: b4constu_in_0 = 0xe; break;
2066 default: b4constu_in_0 = 0xf; break;
2067 }
2068 *valp = b4constu_in_0;
2069 return 0;
2070 }
2071
2072 static int
2073 OperandSem_opnd_sem_uimm8_decode (uint32 *valp)
2074 {
2075 unsigned uimm8_out_0;
2076 unsigned uimm8_in_0;
2077 uimm8_in_0 = *valp & 0xff;
2078 uimm8_out_0 = uimm8_in_0;
2079 *valp = uimm8_out_0;
2080 return 0;
2081 }
2082
2083 static int
2084 OperandSem_opnd_sem_uimm8_encode (uint32 *valp)
2085 {
2086 unsigned uimm8_in_0;
2087 unsigned uimm8_out_0;
2088 uimm8_out_0 = *valp;
2089 uimm8_in_0 = (uimm8_out_0 & 0xff);
2090 *valp = uimm8_in_0;
2091 return 0;
2092 }
2093
2094 static int
2095 OperandSem_opnd_sem_uimm8x2_decode (uint32 *valp)
2096 {
2097 unsigned uimm8x2_out_0;
2098 unsigned uimm8x2_in_0;
2099 uimm8x2_in_0 = *valp & 0xff;
2100 uimm8x2_out_0 = uimm8x2_in_0 << 1;
2101 *valp = uimm8x2_out_0;
2102 return 0;
2103 }
2104
2105 static int
2106 OperandSem_opnd_sem_uimm8x2_encode (uint32 *valp)
2107 {
2108 unsigned uimm8x2_in_0;
2109 unsigned uimm8x2_out_0;
2110 uimm8x2_out_0 = *valp;
2111 uimm8x2_in_0 = ((uimm8x2_out_0 >> 1) & 0xff);
2112 *valp = uimm8x2_in_0;
2113 return 0;
2114 }
2115
2116 static int
2117 OperandSem_opnd_sem_uimm8x4_decode (uint32 *valp)
2118 {
2119 unsigned uimm8x4_out_0;
2120 unsigned uimm8x4_in_0;
2121 uimm8x4_in_0 = *valp & 0xff;
2122 uimm8x4_out_0 = uimm8x4_in_0 << 2;
2123 *valp = uimm8x4_out_0;
2124 return 0;
2125 }
2126
2127 static int
2128 OperandSem_opnd_sem_uimm8x4_encode (uint32 *valp)
2129 {
2130 unsigned uimm8x4_in_0;
2131 unsigned uimm8x4_out_0;
2132 uimm8x4_out_0 = *valp;
2133 uimm8x4_in_0 = ((uimm8x4_out_0 >> 2) & 0xff);
2134 *valp = uimm8x4_in_0;
2135 return 0;
2136 }
2137
2138 static int
2139 OperandSem_opnd_sem_uimm4x16_decode (uint32 *valp)
2140 {
2141 unsigned uimm4x16_out_0;
2142 unsigned uimm4x16_in_0;
2143 uimm4x16_in_0 = *valp & 0xf;
2144 uimm4x16_out_0 = uimm4x16_in_0 << 4;
2145 *valp = uimm4x16_out_0;
2146 return 0;
2147 }
2148
2149 static int
2150 OperandSem_opnd_sem_uimm4x16_encode (uint32 *valp)
2151 {
2152 unsigned uimm4x16_in_0;
2153 unsigned uimm4x16_out_0;
2154 uimm4x16_out_0 = *valp;
2155 uimm4x16_in_0 = ((uimm4x16_out_0 >> 4) & 0xf);
2156 *valp = uimm4x16_in_0;
2157 return 0;
2158 }
2159
2160 static int
2161 OperandSem_opnd_sem_uimmrx4_decode (uint32 *valp)
2162 {
2163 unsigned uimmrx4_out_0;
2164 unsigned uimmrx4_in_0;
2165 uimmrx4_in_0 = *valp & 0xf;
2166 uimmrx4_out_0 = uimmrx4_in_0 << 2;
2167 *valp = uimmrx4_out_0;
2168 return 0;
2169 }
2170
2171 static int
2172 OperandSem_opnd_sem_uimmrx4_encode (uint32 *valp)
2173 {
2174 unsigned uimmrx4_in_0;
2175 unsigned uimmrx4_out_0;
2176 uimmrx4_out_0 = *valp;
2177 uimmrx4_in_0 = ((uimmrx4_out_0 >> 2) & 0xf);
2178 *valp = uimmrx4_in_0;
2179 return 0;
2180 }
2181
2182 static int
2183 OperandSem_opnd_sem_simm8_decode (uint32 *valp)
2184 {
2185 unsigned simm8_out_0;
2186 unsigned simm8_in_0;
2187 simm8_in_0 = *valp & 0xff;
2188 simm8_out_0 = ((int) simm8_in_0 << 24) >> 24;
2189 *valp = simm8_out_0;
2190 return 0;
2191 }
2192
2193 static int
2194 OperandSem_opnd_sem_simm8_encode (uint32 *valp)
2195 {
2196 unsigned simm8_in_0;
2197 unsigned simm8_out_0;
2198 simm8_out_0 = *valp;
2199 simm8_in_0 = (simm8_out_0 & 0xff);
2200 *valp = simm8_in_0;
2201 return 0;
2202 }
2203
2204 static int
2205 OperandSem_opnd_sem_simm8x256_decode (uint32 *valp)
2206 {
2207 unsigned simm8x256_out_0;
2208 unsigned simm8x256_in_0;
2209 simm8x256_in_0 = *valp & 0xff;
2210 simm8x256_out_0 = (((int) simm8x256_in_0 << 24) >> 24) << 8;
2211 *valp = simm8x256_out_0;
2212 return 0;
2213 }
2214
2215 static int
2216 OperandSem_opnd_sem_simm8x256_encode (uint32 *valp)
2217 {
2218 unsigned simm8x256_in_0;
2219 unsigned simm8x256_out_0;
2220 simm8x256_out_0 = *valp;
2221 simm8x256_in_0 = ((simm8x256_out_0 >> 8) & 0xff);
2222 *valp = simm8x256_in_0;
2223 return 0;
2224 }
2225
2226 static int
2227 OperandSem_opnd_sem_simm12b_decode (uint32 *valp)
2228 {
2229 unsigned simm12b_out_0;
2230 unsigned simm12b_in_0;
2231 simm12b_in_0 = *valp & 0xfff;
2232 simm12b_out_0 = ((int) simm12b_in_0 << 20) >> 20;
2233 *valp = simm12b_out_0;
2234 return 0;
2235 }
2236
2237 static int
2238 OperandSem_opnd_sem_simm12b_encode (uint32 *valp)
2239 {
2240 unsigned simm12b_in_0;
2241 unsigned simm12b_out_0;
2242 simm12b_out_0 = *valp;
2243 simm12b_in_0 = (simm12b_out_0 & 0xfff);
2244 *valp = simm12b_in_0;
2245 return 0;
2246 }
2247
2248 static int
2249 OperandSem_opnd_sem_msalp32_decode (uint32 *valp)
2250 {
2251 unsigned msalp32_out_0;
2252 unsigned msalp32_in_0;
2253 msalp32_in_0 = *valp & 0x1f;
2254 msalp32_out_0 = 0x20 - msalp32_in_0;
2255 *valp = msalp32_out_0;
2256 return 0;
2257 }
2258
2259 static int
2260 OperandSem_opnd_sem_msalp32_encode (uint32 *valp)
2261 {
2262 unsigned msalp32_in_0;
2263 unsigned msalp32_out_0;
2264 msalp32_out_0 = *valp;
2265 msalp32_in_0 = (0x20 - msalp32_out_0) & 0x1f;
2266 *valp = msalp32_in_0;
2267 return 0;
2268 }
2269
2270 static int
2271 OperandSem_opnd_sem_op2p1_decode (uint32 *valp)
2272 {
2273 unsigned op2p1_out_0;
2274 unsigned op2p1_in_0;
2275 op2p1_in_0 = *valp & 0xf;
2276 op2p1_out_0 = op2p1_in_0 + 0x1;
2277 *valp = op2p1_out_0;
2278 return 0;
2279 }
2280
2281 static int
2282 OperandSem_opnd_sem_op2p1_encode (uint32 *valp)
2283 {
2284 unsigned op2p1_in_0;
2285 unsigned op2p1_out_0;
2286 op2p1_out_0 = *valp;
2287 op2p1_in_0 = (op2p1_out_0 - 0x1) & 0xf;
2288 *valp = op2p1_in_0;
2289 return 0;
2290 }
2291
2292 static int
2293 OperandSem_opnd_sem_label8_decode (uint32 *valp)
2294 {
2295 unsigned label8_out_0;
2296 unsigned label8_in_0;
2297 label8_in_0 = *valp & 0xff;
2298 label8_out_0 = 0x4 + (((int) label8_in_0 << 24) >> 24);
2299 *valp = label8_out_0;
2300 return 0;
2301 }
2302
2303 static int
2304 OperandSem_opnd_sem_label8_encode (uint32 *valp)
2305 {
2306 unsigned label8_in_0;
2307 unsigned label8_out_0;
2308 label8_out_0 = *valp;
2309 label8_in_0 = (label8_out_0 - 0x4) & 0xff;
2310 *valp = label8_in_0;
2311 return 0;
2312 }
2313
2314 static int
2315 OperandSem_opnd_sem_ulabel8_decode (uint32 *valp)
2316 {
2317 unsigned ulabel8_out_0;
2318 unsigned ulabel8_in_0;
2319 ulabel8_in_0 = *valp & 0xff;
2320 ulabel8_out_0 = 0x4 + (((0) << 8) | ulabel8_in_0);
2321 *valp = ulabel8_out_0;
2322 return 0;
2323 }
2324
2325 static int
2326 OperandSem_opnd_sem_ulabel8_encode (uint32 *valp)
2327 {
2328 unsigned ulabel8_in_0;
2329 unsigned ulabel8_out_0;
2330 ulabel8_out_0 = *valp;
2331 ulabel8_in_0 = (ulabel8_out_0 - 0x4) & 0xff;
2332 *valp = ulabel8_in_0;
2333 return 0;
2334 }
2335
2336 static int
2337 OperandSem_opnd_sem_label12_decode (uint32 *valp)
2338 {
2339 unsigned label12_out_0;
2340 unsigned label12_in_0;
2341 label12_in_0 = *valp & 0xfff;
2342 label12_out_0 = 0x4 + (((int) label12_in_0 << 20) >> 20);
2343 *valp = label12_out_0;
2344 return 0;
2345 }
2346
2347 static int
2348 OperandSem_opnd_sem_label12_encode (uint32 *valp)
2349 {
2350 unsigned label12_in_0;
2351 unsigned label12_out_0;
2352 label12_out_0 = *valp;
2353 label12_in_0 = (label12_out_0 - 0x4) & 0xfff;
2354 *valp = label12_in_0;
2355 return 0;
2356 }
2357
2358 static int
2359 OperandSem_opnd_sem_soffset_decode (uint32 *valp)
2360 {
2361 unsigned soffset_out_0;
2362 unsigned soffset_in_0;
2363 soffset_in_0 = *valp & 0x3ffff;
2364 soffset_out_0 = 0x4 + (((int) soffset_in_0 << 14) >> 14);
2365 *valp = soffset_out_0;
2366 return 0;
2367 }
2368
2369 static int
2370 OperandSem_opnd_sem_soffset_encode (uint32 *valp)
2371 {
2372 unsigned soffset_in_0;
2373 unsigned soffset_out_0;
2374 soffset_out_0 = *valp;
2375 soffset_in_0 = (soffset_out_0 - 0x4) & 0x3ffff;
2376 *valp = soffset_in_0;
2377 return 0;
2378 }
2379
2380 static int
2381 OperandSem_opnd_sem_uimm16x4_decode (uint32 *valp)
2382 {
2383 unsigned uimm16x4_out_0;
2384 unsigned uimm16x4_in_0;
2385 uimm16x4_in_0 = *valp & 0xffff;
2386 uimm16x4_out_0 = (((0xffff) << 16) | uimm16x4_in_0) << 2;
2387 *valp = uimm16x4_out_0;
2388 return 0;
2389 }
2390
2391 static int
2392 OperandSem_opnd_sem_uimm16x4_encode (uint32 *valp)
2393 {
2394 unsigned uimm16x4_in_0;
2395 unsigned uimm16x4_out_0;
2396 uimm16x4_out_0 = *valp;
2397 uimm16x4_in_0 = (uimm16x4_out_0 >> 2) & 0xffff;
2398 *valp = uimm16x4_in_0;
2399 return 0;
2400 }
2401
2402 static int
2403 OperandSem_opnd_sem_bbi_decode (uint32 *valp)
2404 {
2405 unsigned bbi_out_0;
2406 unsigned bbi_in_0;
2407 bbi_in_0 = *valp & 0x1f;
2408 bbi_out_0 = (0 << 5) | bbi_in_0;
2409 *valp = bbi_out_0;
2410 return 0;
2411 }
2412
2413 static int
2414 OperandSem_opnd_sem_bbi_encode (uint32 *valp)
2415 {
2416 unsigned bbi_in_0;
2417 unsigned bbi_out_0;
2418 bbi_out_0 = *valp;
2419 bbi_in_0 = (bbi_out_0 & 0x1f);
2420 *valp = bbi_in_0;
2421 return 0;
2422 }
2423
2424 static int
2425 OperandSem_opnd_sem_s_decode (uint32 *valp)
2426 {
2427 unsigned s_out_0;
2428 unsigned s_in_0;
2429 s_in_0 = *valp & 0xf;
2430 s_out_0 = (0 << 4) | s_in_0;
2431 *valp = s_out_0;
2432 return 0;
2433 }
2434
2435 static int
2436 OperandSem_opnd_sem_s_encode (uint32 *valp)
2437 {
2438 unsigned s_in_0;
2439 unsigned s_out_0;
2440 s_out_0 = *valp;
2441 s_in_0 = (s_out_0 & 0xf);
2442 *valp = s_in_0;
2443 return 0;
2444 }
2445
2446 static int
2447 OperandSem_opnd_sem_MR_decode (uint32 *valp ATTRIBUTE_UNUSED)
2448 {
2449 return 0;
2450 }
2451
2452 static int
2453 OperandSem_opnd_sem_MR_encode (uint32 *valp)
2454 {
2455 return (*valp >= 4);
2456 }
2457
2458 static int
2459 OperandSem_opnd_sem_MR_1_decode (uint32 *valp ATTRIBUTE_UNUSED)
2460 {
2461 return 0;
2462 }
2463
2464 static int
2465 OperandSem_opnd_sem_MR_1_encode (uint32 *valp)
2466 {
2467 return (*valp >= 4);
2468 }
2469
2470 static int
2471 OperandSem_opnd_sem_MR_2_decode (uint32 *valp ATTRIBUTE_UNUSED)
2472 {
2473 return 0;
2474 }
2475
2476 static int
2477 OperandSem_opnd_sem_MR_2_encode (uint32 *valp)
2478 {
2479 return (*valp >= 4);
2480 }
2481
2482 static int
2483 OperandSem_opnd_sem_MR_3_decode (uint32 *valp ATTRIBUTE_UNUSED)
2484 {
2485 return 0;
2486 }
2487
2488 static int
2489 OperandSem_opnd_sem_MR_3_encode (uint32 *valp)
2490 {
2491 return (*valp >= 4);
2492 }
2493
2494 static int
2495 OperandSem_opnd_sem_MR_4_decode (uint32 *valp ATTRIBUTE_UNUSED)
2496 {
2497 return 0;
2498 }
2499
2500 static int
2501 OperandSem_opnd_sem_MR_4_encode (uint32 *valp)
2502 {
2503 return (*valp >= 4);
2504 }
2505
2506 static int
2507 OperandSem_opnd_sem_MR_5_decode (uint32 *valp ATTRIBUTE_UNUSED)
2508 {
2509 return 0;
2510 }
2511
2512 static int
2513 OperandSem_opnd_sem_MR_5_encode (uint32 *valp)
2514 {
2515 return (*valp >= 4);
2516 }
2517
2518 static int
2519 OperandSem_opnd_sem_immt_decode (uint32 *valp)
2520 {
2521 unsigned immt_out_0;
2522 unsigned immt_in_0;
2523 immt_in_0 = *valp & 0xf;
2524 immt_out_0 = immt_in_0;
2525 *valp = immt_out_0;
2526 return 0;
2527 }
2528
2529 static int
2530 OperandSem_opnd_sem_immt_encode (uint32 *valp)
2531 {
2532 unsigned immt_in_0;
2533 unsigned immt_out_0;
2534 immt_out_0 = *valp;
2535 immt_in_0 = immt_out_0 & 0xf;
2536 *valp = immt_in_0;
2537 return 0;
2538 }
2539
2540 static int
2541 OperandSem_opnd_sem_tp7_decode (uint32 *valp)
2542 {
2543 unsigned tp7_out_0;
2544 unsigned tp7_in_0;
2545 tp7_in_0 = *valp & 0xf;
2546 tp7_out_0 = tp7_in_0 + 0x7;
2547 *valp = tp7_out_0;
2548 return 0;
2549 }
2550
2551 static int
2552 OperandSem_opnd_sem_tp7_encode (uint32 *valp)
2553 {
2554 unsigned tp7_in_0;
2555 unsigned tp7_out_0;
2556 tp7_out_0 = *valp;
2557 tp7_in_0 = (tp7_out_0 - 0x7) & 0xf;
2558 *valp = tp7_in_0;
2559 return 0;
2560 }
2561
2562 static int
2563 OperandSem_opnd_sem_xt_wbr15_label_decode (uint32 *valp)
2564 {
2565 unsigned xt_wbr15_label_out_0;
2566 unsigned xt_wbr15_label_in_0;
2567 xt_wbr15_label_in_0 = *valp & 0x7fff;
2568 xt_wbr15_label_out_0 = 0x4 + (((int) xt_wbr15_label_in_0 << 17) >> 17);
2569 *valp = xt_wbr15_label_out_0;
2570 return 0;
2571 }
2572
2573 static int
2574 OperandSem_opnd_sem_xt_wbr15_label_encode (uint32 *valp)
2575 {
2576 unsigned xt_wbr15_label_in_0;
2577 unsigned xt_wbr15_label_out_0;
2578 xt_wbr15_label_out_0 = *valp;
2579 xt_wbr15_label_in_0 = (xt_wbr15_label_out_0 - 0x4) & 0x7fff;
2580 *valp = xt_wbr15_label_in_0;
2581 return 0;
2582 }
2583
2584 static int
2585 OperandSem_opnd_sem_xt_wbr18_label_decode (uint32 *valp)
2586 {
2587 unsigned xt_wbr18_label_out_0;
2588 unsigned xt_wbr18_label_in_0;
2589 xt_wbr18_label_in_0 = *valp & 0x3ffff;
2590 xt_wbr18_label_out_0 = 0x4 + (((int) xt_wbr18_label_in_0 << 14) >> 14);
2591 *valp = xt_wbr18_label_out_0;
2592 return 0;
2593 }
2594
2595 static int
2596 OperandSem_opnd_sem_xt_wbr18_label_encode (uint32 *valp)
2597 {
2598 unsigned xt_wbr18_label_in_0;
2599 unsigned xt_wbr18_label_out_0;
2600 xt_wbr18_label_out_0 = *valp;
2601 xt_wbr18_label_in_0 = (xt_wbr18_label_out_0 - 0x4) & 0x3ffff;
2602 *valp = xt_wbr18_label_in_0;
2603 return 0;
2604 }
2605
2606 static int
2607 OperandSem_opnd_sem_bitindex_decode (uint32 *valp)
2608 {
2609 unsigned bitindex_out_0;
2610 unsigned bitindex_in_0;
2611 bitindex_in_0 = *valp & 0x1f;
2612 bitindex_out_0 = (0 << 5) | bitindex_in_0;
2613 *valp = bitindex_out_0;
2614 return 0;
2615 }
2616
2617 static int
2618 OperandSem_opnd_sem_bitindex_encode (uint32 *valp)
2619 {
2620 unsigned bitindex_in_0;
2621 unsigned bitindex_out_0;
2622 bitindex_out_0 = *valp;
2623 bitindex_in_0 = (bitindex_out_0 & 0x1f);
2624 *valp = bitindex_in_0;
2625 return 0;
2626 }
2627
2628 static int
2629 Operand_soffsetx4_ator (uint32 *valp, uint32 pc)
2630 {
2631 *valp -= (pc & ~0x3);
2632 return 0;
2633 }
2634
2635 static int
2636 Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc)
2637 {
2638 *valp += (pc & ~0x3);
2639 return 0;
2640 }
2641
2642 static int
2643 Operand_uimm6_ator (uint32 *valp, uint32 pc)
2644 {
2645 *valp -= pc;
2646 return 0;
2647 }
2648
2649 static int
2650 Operand_uimm6_rtoa (uint32 *valp, uint32 pc)
2651 {
2652 *valp += pc;
2653 return 0;
2654 }
2655
2656 static int
2657 Operand_label8_ator (uint32 *valp, uint32 pc)
2658 {
2659 *valp -= pc;
2660 return 0;
2661 }
2662
2663 static int
2664 Operand_label8_rtoa (uint32 *valp, uint32 pc)
2665 {
2666 *valp += pc;
2667 return 0;
2668 }
2669
2670 static int
2671 Operand_ulabel8_ator (uint32 *valp, uint32 pc)
2672 {
2673 *valp -= pc;
2674 return 0;
2675 }
2676
2677 static int
2678 Operand_ulabel8_rtoa (uint32 *valp, uint32 pc)
2679 {
2680 *valp += pc;
2681 return 0;
2682 }
2683
2684 static int
2685 Operand_label12_ator (uint32 *valp, uint32 pc)
2686 {
2687 *valp -= pc;
2688 return 0;
2689 }
2690
2691 static int
2692 Operand_label12_rtoa (uint32 *valp, uint32 pc)
2693 {
2694 *valp += pc;
2695 return 0;
2696 }
2697
2698 static int
2699 Operand_soffset_ator (uint32 *valp, uint32 pc)
2700 {
2701 *valp -= pc;
2702 return 0;
2703 }
2704
2705 static int
2706 Operand_soffset_rtoa (uint32 *valp, uint32 pc)
2707 {
2708 *valp += pc;
2709 return 0;
2710 }
2711
2712 static int
2713 Operand_uimm16x4_ator (uint32 *valp, uint32 pc)
2714 {
2715 *valp -= ((pc + 3) & ~0x3);
2716 return 0;
2717 }
2718
2719 static int
2720 Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc)
2721 {
2722 *valp += ((pc + 3) & ~0x3);
2723 return 0;
2724 }
2725
2726 static int
2727 Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc)
2728 {
2729 *valp -= pc;
2730 return 0;
2731 }
2732
2733 static int
2734 Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc)
2735 {
2736 *valp += pc;
2737 return 0;
2738 }
2739
2740 static int
2741 Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc)
2742 {
2743 *valp -= pc;
2744 return 0;
2745 }
2746
2747 static int
2748 Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc)
2749 {
2750 *valp += pc;
2751 return 0;
2752 }
2753
2754 static xtensa_operand_internal operands[] = {
2755 { "soffsetx4", FIELD_offset, -1, 0,
2756 XTENSA_OPERAND_IS_PCRELATIVE,
2757 OperandSem_opnd_sem_soffsetx4_encode, OperandSem_opnd_sem_soffsetx4_decode,
2758 Operand_soffsetx4_ator, Operand_soffsetx4_rtoa },
2759 { "uimm12x8", FIELD_imm12, -1, 0,
2760 0,
2761 OperandSem_opnd_sem_uimm12x8_encode, OperandSem_opnd_sem_uimm12x8_decode,
2762 0, 0 },
2763 { "simm4", FIELD_mn, -1, 0,
2764 0,
2765 OperandSem_opnd_sem_simm4_encode, OperandSem_opnd_sem_simm4_decode,
2766 0, 0 },
2767 { "arr", FIELD_r, REGFILE_AR, 1,
2768 XTENSA_OPERAND_IS_REGISTER,
2769 OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
2770 0, 0 },
2771 { "ars", FIELD_s, REGFILE_AR, 1,
2772 XTENSA_OPERAND_IS_REGISTER,
2773 OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
2774 0, 0 },
2775 { "*ars_invisible", FIELD_s, REGFILE_AR, 1,
2776 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2777 OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
2778 0, 0 },
2779 { "art", FIELD_t, REGFILE_AR, 1,
2780 XTENSA_OPERAND_IS_REGISTER,
2781 OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
2782 0, 0 },
2783 { "ar0", FIELD__ar0, REGFILE_AR, 1,
2784 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2785 OperandSem_opnd_sem_AR_0_encode, OperandSem_opnd_sem_AR_0_decode,
2786 0, 0 },
2787 { "ar4", FIELD__ar4, REGFILE_AR, 1,
2788 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2789 OperandSem_opnd_sem_AR_1_encode, OperandSem_opnd_sem_AR_1_decode,
2790 0, 0 },
2791 { "ar8", FIELD__ar8, REGFILE_AR, 1,
2792 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2793 OperandSem_opnd_sem_AR_2_encode, OperandSem_opnd_sem_AR_2_decode,
2794 0, 0 },
2795 { "ar12", FIELD__ar12, REGFILE_AR, 1,
2796 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2797 OperandSem_opnd_sem_AR_3_encode, OperandSem_opnd_sem_AR_3_decode,
2798 0, 0 },
2799 { "ars_entry", FIELD_s, REGFILE_AR, 1,
2800 XTENSA_OPERAND_IS_REGISTER,
2801 OperandSem_opnd_sem_AR_4_encode, OperandSem_opnd_sem_AR_4_decode,
2802 0, 0 },
2803 { "immrx4", FIELD_r, -1, 0,
2804 0,
2805 OperandSem_opnd_sem_immrx4_encode, OperandSem_opnd_sem_immrx4_decode,
2806 0, 0 },
2807 { "lsi4x4", FIELD_r, -1, 0,
2808 0,
2809 OperandSem_opnd_sem_lsi4x4_encode, OperandSem_opnd_sem_lsi4x4_decode,
2810 0, 0 },
2811 { "simm7", FIELD_imm7, -1, 0,
2812 0,
2813 OperandSem_opnd_sem_simm7_encode, OperandSem_opnd_sem_simm7_decode,
2814 0, 0 },
2815 { "uimm6", FIELD_imm6, -1, 0,
2816 XTENSA_OPERAND_IS_PCRELATIVE,
2817 OperandSem_opnd_sem_uimm6_encode, OperandSem_opnd_sem_uimm6_decode,
2818 Operand_uimm6_ator, Operand_uimm6_rtoa },
2819 { "ai4const", FIELD_t, -1, 0,
2820 0,
2821 OperandSem_opnd_sem_ai4const_encode, OperandSem_opnd_sem_ai4const_decode,
2822 0, 0 },
2823 { "b4const", FIELD_r, -1, 0,
2824 0,
2825 OperandSem_opnd_sem_b4const_encode, OperandSem_opnd_sem_b4const_decode,
2826 0, 0 },
2827 { "b4constu", FIELD_r, -1, 0,
2828 0,
2829 OperandSem_opnd_sem_b4constu_encode, OperandSem_opnd_sem_b4constu_decode,
2830 0, 0 },
2831 { "uimm8", FIELD_imm8, -1, 0,
2832 0,
2833 OperandSem_opnd_sem_uimm8_encode, OperandSem_opnd_sem_uimm8_decode,
2834 0, 0 },
2835 { "uimm8x2", FIELD_imm8, -1, 0,
2836 0,
2837 OperandSem_opnd_sem_uimm8x2_encode, OperandSem_opnd_sem_uimm8x2_decode,
2838 0, 0 },
2839 { "uimm8x4", FIELD_imm8, -1, 0,
2840 0,
2841 OperandSem_opnd_sem_uimm8x4_encode, OperandSem_opnd_sem_uimm8x4_decode,
2842 0, 0 },
2843 { "uimm4x16", FIELD_op2, -1, 0,
2844 0,
2845 OperandSem_opnd_sem_uimm4x16_encode, OperandSem_opnd_sem_uimm4x16_decode,
2846 0, 0 },
2847 { "uimmrx4", FIELD_r, -1, 0,
2848 0,
2849 OperandSem_opnd_sem_uimmrx4_encode, OperandSem_opnd_sem_uimmrx4_decode,
2850 0, 0 },
2851 { "simm8", FIELD_imm8, -1, 0,
2852 0,
2853 OperandSem_opnd_sem_simm8_encode, OperandSem_opnd_sem_simm8_decode,
2854 0, 0 },
2855 { "simm8x256", FIELD_imm8, -1, 0,
2856 0,
2857 OperandSem_opnd_sem_simm8x256_encode, OperandSem_opnd_sem_simm8x256_decode,
2858 0, 0 },
2859 { "simm12b", FIELD_imm12b, -1, 0,
2860 0,
2861 OperandSem_opnd_sem_simm12b_encode, OperandSem_opnd_sem_simm12b_decode,
2862 0, 0 },
2863 { "msalp32", FIELD_sal, -1, 0,
2864 0,
2865 OperandSem_opnd_sem_msalp32_encode, OperandSem_opnd_sem_msalp32_decode,
2866 0, 0 },
2867 { "op2p1", FIELD_op2, -1, 0,
2868 0,
2869 OperandSem_opnd_sem_op2p1_encode, OperandSem_opnd_sem_op2p1_decode,
2870 0, 0 },
2871 { "label8", FIELD_imm8, -1, 0,
2872 XTENSA_OPERAND_IS_PCRELATIVE,
2873 OperandSem_opnd_sem_label8_encode, OperandSem_opnd_sem_label8_decode,
2874 Operand_label8_ator, Operand_label8_rtoa },
2875 { "ulabel8", FIELD_imm8, -1, 0,
2876 XTENSA_OPERAND_IS_PCRELATIVE,
2877 OperandSem_opnd_sem_ulabel8_encode, OperandSem_opnd_sem_ulabel8_decode,
2878 Operand_ulabel8_ator, Operand_ulabel8_rtoa },
2879 { "label12", FIELD_imm12, -1, 0,
2880 XTENSA_OPERAND_IS_PCRELATIVE,
2881 OperandSem_opnd_sem_label12_encode, OperandSem_opnd_sem_label12_decode,
2882 Operand_label12_ator, Operand_label12_rtoa },
2883 { "soffset", FIELD_offset, -1, 0,
2884 XTENSA_OPERAND_IS_PCRELATIVE,
2885 OperandSem_opnd_sem_soffset_encode, OperandSem_opnd_sem_soffset_decode,
2886 Operand_soffset_ator, Operand_soffset_rtoa },
2887 { "uimm16x4", FIELD_imm16, -1, 0,
2888 XTENSA_OPERAND_IS_PCRELATIVE,
2889 OperandSem_opnd_sem_uimm16x4_encode, OperandSem_opnd_sem_uimm16x4_decode,
2890 Operand_uimm16x4_ator, Operand_uimm16x4_rtoa },
2891 { "bbi", FIELD_bbi, -1, 0,
2892 0,
2893 OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
2894 0, 0 },
2895 { "sae", FIELD_sae, -1, 0,
2896 0,
2897 OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
2898 0, 0 },
2899 { "sas", FIELD_sas, -1, 0,
2900 0,
2901 OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
2902 0, 0 },
2903 { "sargt", FIELD_sargt, -1, 0,
2904 0,
2905 OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
2906 0, 0 },
2907 { "s", FIELD_s, -1, 0,
2908 0,
2909 OperandSem_opnd_sem_s_encode, OperandSem_opnd_sem_s_decode,
2910 0, 0 },
2911 { "mx", FIELD_x, REGFILE_MR, 1,
2912 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN,
2913 OperandSem_opnd_sem_MR_encode, OperandSem_opnd_sem_MR_decode,
2914 0, 0 },
2915 { "my", FIELD_y, REGFILE_MR, 1,
2916 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN,
2917 OperandSem_opnd_sem_MR_0_encode, OperandSem_opnd_sem_MR_0_decode,
2918 0, 0 },
2919 { "mw", FIELD_w, REGFILE_MR, 1,
2920 XTENSA_OPERAND_IS_REGISTER,
2921 OperandSem_opnd_sem_MR_1_encode, OperandSem_opnd_sem_MR_1_decode,
2922 0, 0 },
2923 { "mr0", FIELD__mr0, REGFILE_MR, 1,
2924 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2925 OperandSem_opnd_sem_MR_2_encode, OperandSem_opnd_sem_MR_2_decode,
2926 0, 0 },
2927 { "mr1", FIELD__mr1, REGFILE_MR, 1,
2928 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2929 OperandSem_opnd_sem_MR_3_encode, OperandSem_opnd_sem_MR_3_decode,
2930 0, 0 },
2931 { "mr2", FIELD__mr2, REGFILE_MR, 1,
2932 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2933 OperandSem_opnd_sem_MR_4_encode, OperandSem_opnd_sem_MR_4_decode,
2934 0, 0 },
2935 { "mr3", FIELD__mr3, REGFILE_MR, 1,
2936 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2937 OperandSem_opnd_sem_MR_5_encode, OperandSem_opnd_sem_MR_5_decode,
2938 0, 0 },
2939 { "immt", FIELD_t, -1, 0,
2940 0,
2941 OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode,
2942 0, 0 },
2943 { "imms", FIELD_s, -1, 0,
2944 0,
2945 OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode,
2946 0, 0 },
2947 { "tp7", FIELD_t, -1, 0,
2948 0,
2949 OperandSem_opnd_sem_tp7_encode, OperandSem_opnd_sem_tp7_decode,
2950 0, 0 },
2951 { "xt_wbr15_label", FIELD_xt_wbr15_imm, -1, 0,
2952 XTENSA_OPERAND_IS_PCRELATIVE,
2953 OperandSem_opnd_sem_xt_wbr15_label_encode, OperandSem_opnd_sem_xt_wbr15_label_decode,
2954 Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa },
2955 { "xt_wbr18_label", FIELD_xt_wbr18_imm, -1, 0,
2956 XTENSA_OPERAND_IS_PCRELATIVE,
2957 OperandSem_opnd_sem_xt_wbr18_label_encode, OperandSem_opnd_sem_xt_wbr18_label_decode,
2958 Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa },
2959 { "bitindex", FIELD_bitindex, -1, 0,
2960 0,
2961 OperandSem_opnd_sem_bitindex_encode, OperandSem_opnd_sem_bitindex_decode,
2962 0, 0 },
2963 { "t", FIELD_t, -1, 0, 0, 0, 0, 0, 0 },
2964 { "bbi4", FIELD_bbi4, -1, 0, 0, 0, 0, 0, 0 },
2965 { "imm12", FIELD_imm12, -1, 0, 0, 0, 0, 0, 0 },
2966 { "imm8", FIELD_imm8, -1, 0, 0, 0, 0, 0, 0 },
2967 { "imm12b", FIELD_imm12b, -1, 0, 0, 0, 0, 0, 0 },
2968 { "imm16", FIELD_imm16, -1, 0, 0, 0, 0, 0, 0 },
2969 { "m", FIELD_m, -1, 0, 0, 0, 0, 0, 0 },
2970 { "n", FIELD_n, -1, 0, 0, 0, 0, 0, 0 },
2971 { "offset", FIELD_offset, -1, 0, 0, 0, 0, 0, 0 },
2972 { "op0", FIELD_op0, -1, 0, 0, 0, 0, 0, 0 },
2973 { "op1", FIELD_op1, -1, 0, 0, 0, 0, 0, 0 },
2974 { "op2", FIELD_op2, -1, 0, 0, 0, 0, 0, 0 },
2975 { "r", FIELD_r, -1, 0, 0, 0, 0, 0, 0 },
2976 { "sa4", FIELD_sa4, -1, 0, 0, 0, 0, 0, 0 },
2977 { "sae4", FIELD_sae4, -1, 0, 0, 0, 0, 0, 0 },
2978 { "sal", FIELD_sal, -1, 0, 0, 0, 0, 0, 0 },
2979 { "sas4", FIELD_sas4, -1, 0, 0, 0, 0, 0, 0 },
2980 { "sr", FIELD_sr, -1, 0, 0, 0, 0, 0, 0 },
2981 { "st", FIELD_st, -1, 0, 0, 0, 0, 0, 0 },
2982 { "thi3", FIELD_thi3, -1, 0, 0, 0, 0, 0, 0 },
2983 { "imm4", FIELD_imm4, -1, 0, 0, 0, 0, 0, 0 },
2984 { "mn", FIELD_mn, -1, 0, 0, 0, 0, 0, 0 },
2985 { "i", FIELD_i, -1, 0, 0, 0, 0, 0, 0 },
2986 { "imm6lo", FIELD_imm6lo, -1, 0, 0, 0, 0, 0, 0 },
2987 { "imm6hi", FIELD_imm6hi, -1, 0, 0, 0, 0, 0, 0 },
2988 { "imm7lo", FIELD_imm7lo, -1, 0, 0, 0, 0, 0, 0 },
2989 { "imm7hi", FIELD_imm7hi, -1, 0, 0, 0, 0, 0, 0 },
2990 { "z", FIELD_z, -1, 0, 0, 0, 0, 0, 0 },
2991 { "imm6", FIELD_imm6, -1, 0, 0, 0, 0, 0, 0 },
2992 { "imm7", FIELD_imm7, -1, 0, 0, 0, 0, 0, 0 },
2993 { "r3", FIELD_r3, -1, 0, 0, 0, 0, 0, 0 },
2994 { "rbit2", FIELD_rbit2, -1, 0, 0, 0, 0, 0, 0 },
2995 { "rhi", FIELD_rhi, -1, 0, 0, 0, 0, 0, 0 },
2996 { "t3", FIELD_t3, -1, 0, 0, 0, 0, 0, 0 },
2997 { "tbit2", FIELD_tbit2, -1, 0, 0, 0, 0, 0, 0 },
2998 { "tlo", FIELD_tlo, -1, 0, 0, 0, 0, 0, 0 },
2999 { "w", FIELD_w, -1, 0, 0, 0, 0, 0, 0 },
3000 { "y", FIELD_y, -1, 0, 0, 0, 0, 0, 0 },
3001 { "x", FIELD_x, -1, 0, 0, 0, 0, 0, 0 },
3002 { "xt_wbr15_imm", FIELD_xt_wbr15_imm, -1, 0, 0, 0, 0, 0, 0 },
3003 { "xt_wbr18_imm", FIELD_xt_wbr18_imm, -1, 0, 0, 0, 0, 0, 0 },
3004 { "s3to1", FIELD_s3to1, -1, 0, 0, 0, 0, 0, 0 }
3005 };
3006
3007 enum xtensa_operand_id {
3008 OPERAND_soffsetx4,
3009 OPERAND_uimm12x8,
3010 OPERAND_simm4,
3011 OPERAND_arr,
3012 OPERAND_ars,
3013 OPERAND__ars_invisible,
3014 OPERAND_art,
3015 OPERAND_ar0,
3016 OPERAND_ar4,
3017 OPERAND_ar8,
3018 OPERAND_ar12,
3019 OPERAND_ars_entry,
3020 OPERAND_immrx4,
3021 OPERAND_lsi4x4,
3022 OPERAND_simm7,
3023 OPERAND_uimm6,
3024 OPERAND_ai4const,
3025 OPERAND_b4const,
3026 OPERAND_b4constu,
3027 OPERAND_uimm8,
3028 OPERAND_uimm8x2,
3029 OPERAND_uimm8x4,
3030 OPERAND_uimm4x16,
3031 OPERAND_uimmrx4,
3032 OPERAND_simm8,
3033 OPERAND_simm8x256,
3034 OPERAND_simm12b,
3035 OPERAND_msalp32,
3036 OPERAND_op2p1,
3037 OPERAND_label8,
3038 OPERAND_ulabel8,
3039 OPERAND_label12,
3040 OPERAND_soffset,
3041 OPERAND_uimm16x4,
3042 OPERAND_bbi,
3043 OPERAND_sae,
3044 OPERAND_sas,
3045 OPERAND_sargt,
3046 OPERAND_s,
3047 OPERAND_mx,
3048 OPERAND_my,
3049 OPERAND_mw,
3050 OPERAND_mr0,
3051 OPERAND_mr1,
3052 OPERAND_mr2,
3053 OPERAND_mr3,
3054 OPERAND_immt,
3055 OPERAND_imms,
3056 OPERAND_tp7,
3057 OPERAND_xt_wbr15_label,
3058 OPERAND_xt_wbr18_label,
3059 OPERAND_bitindex,
3060 OPERAND_t,
3061 OPERAND_bbi4,
3062 OPERAND_imm12,
3063 OPERAND_imm8,
3064 OPERAND_imm12b,
3065 OPERAND_imm16,
3066 OPERAND_m,
3067 OPERAND_n,
3068 OPERAND_offset,
3069 OPERAND_op0,
3070 OPERAND_op1,
3071 OPERAND_op2,
3072 OPERAND_r,
3073 OPERAND_sa4,
3074 OPERAND_sae4,
3075 OPERAND_sal,
3076 OPERAND_sas4,
3077 OPERAND_sr,
3078 OPERAND_st,
3079 OPERAND_thi3,
3080 OPERAND_imm4,
3081 OPERAND_mn,
3082 OPERAND_i,
3083 OPERAND_imm6lo,
3084 OPERAND_imm6hi,
3085 OPERAND_imm7lo,
3086 OPERAND_imm7hi,
3087 OPERAND_z,
3088 OPERAND_imm6,
3089 OPERAND_imm7,
3090 OPERAND_r3,
3091 OPERAND_rbit2,
3092 OPERAND_rhi,
3093 OPERAND_t3,
3094 OPERAND_tbit2,
3095 OPERAND_tlo,
3096 OPERAND_w,
3097 OPERAND_y,
3098 OPERAND_x,
3099 OPERAND_xt_wbr15_imm,
3100 OPERAND_xt_wbr18_imm,
3101 OPERAND_s3to1
3102 };
3103
3104
3105 /* Iclass table. */
3106
3107 static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = {
3108 { { STATE_PSEXCM }, 'o' },
3109 { { STATE_EPC1 }, 'i' }
3110 };
3111
3112 static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = {
3113 { { STATE_DEPC }, 'i' }
3114 };
3115
3116 static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = {
3117 { { OPERAND_soffsetx4 }, 'i' },
3118 { { OPERAND_ar12 }, 'o' }
3119 };
3120
3121 static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = {
3122 { { STATE_PSCALLINC }, 'o' }
3123 };
3124
3125 static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = {
3126 { { OPERAND_soffsetx4 }, 'i' },
3127 { { OPERAND_ar8 }, 'o' }
3128 };
3129
3130 static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = {
3131 { { STATE_PSCALLINC }, 'o' }
3132 };
3133
3134 static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = {
3135 { { OPERAND_soffsetx4 }, 'i' },
3136 { { OPERAND_ar4 }, 'o' }
3137 };
3138
3139 static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = {
3140 { { STATE_PSCALLINC }, 'o' }
3141 };
3142
3143 static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = {
3144 { { OPERAND_ars }, 'i' },
3145 { { OPERAND_ar12 }, 'o' }
3146 };
3147
3148 static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = {
3149 { { STATE_PSCALLINC }, 'o' }
3150 };
3151
3152 static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = {
3153 { { OPERAND_ars }, 'i' },
3154 { { OPERAND_ar8 }, 'o' }
3155 };
3156
3157 static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = {
3158 { { STATE_PSCALLINC }, 'o' }
3159 };
3160
3161 static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = {
3162 { { OPERAND_ars }, 'i' },
3163 { { OPERAND_ar4 }, 'o' }
3164 };
3165
3166 static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = {
3167 { { STATE_PSCALLINC }, 'o' }
3168 };
3169
3170 static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = {
3171 { { OPERAND_ars_entry }, 's' },
3172 { { OPERAND_ars }, 'i' },
3173 { { OPERAND_uimm12x8 }, 'i' }
3174 };
3175
3176 static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = {
3177 { { STATE_PSCALLINC }, 'i' },
3178 { { STATE_PSEXCM }, 'i' },
3179 { { STATE_PSWOE }, 'i' },
3180 { { STATE_WindowBase }, 'm' },
3181 { { STATE_WindowStart }, 'm' }
3182 };
3183
3184 static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = {
3185 { { OPERAND_art }, 'o' },
3186 { { OPERAND_ars }, 'i' }
3187 };
3188
3189 static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = {
3190 { { STATE_WindowBase }, 'i' },
3191 { { STATE_WindowStart }, 'i' }
3192 };
3193
3194 static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = {
3195 { { OPERAND_simm4 }, 'i' }
3196 };
3197
3198 static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = {
3199 { { STATE_WindowBase }, 'm' }
3200 };
3201
3202 static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = {
3203 { { OPERAND__ars_invisible }, 'i' }
3204 };
3205
3206 static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = {
3207 { { STATE_WindowBase }, 'm' },
3208 { { STATE_WindowStart }, 'm' },
3209 { { STATE_PSCALLINC }, 'o' },
3210 { { STATE_PSEXCM }, 'i' },
3211 { { STATE_PSWOE }, 'i' }
3212 };
3213
3214 static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = {
3215 { { STATE_EPC1 }, 'i' },
3216 { { STATE_PSEXCM }, 'o' },
3217 { { STATE_WindowBase }, 'm' },
3218 { { STATE_WindowStart }, 'm' },
3219 { { STATE_PSOWB }, 'i' }
3220 };
3221
3222 static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = {
3223 { { OPERAND_art }, 'o' },
3224 { { OPERAND_ars }, 'i' },
3225 { { OPERAND_immrx4 }, 'i' }
3226 };
3227
3228 static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = {
3229 { { OPERAND_art }, 'i' },
3230 { { OPERAND_ars }, 'i' },
3231 { { OPERAND_immrx4 }, 'i' }
3232 };
3233
3234 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = {
3235 { { OPERAND_art }, 'o' }
3236 };
3237
3238 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = {
3239 { { STATE_WindowBase }, 'i' }
3240 };
3241
3242 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = {
3243 { { OPERAND_art }, 'i' }
3244 };
3245
3246 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = {
3247 { { STATE_WindowBase }, 'o' }
3248 };
3249
3250 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = {
3251 { { OPERAND_art }, 'm' }
3252 };
3253
3254 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = {
3255 { { STATE_WindowBase }, 'm' }
3256 };
3257
3258 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = {
3259 { { OPERAND_art }, 'o' }
3260 };
3261
3262 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = {
3263 { { STATE_WindowStart }, 'i' }
3264 };
3265
3266 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = {
3267 { { OPERAND_art }, 'i' }
3268 };
3269
3270 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = {
3271 { { STATE_WindowStart }, 'o' }
3272 };
3273
3274 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = {
3275 { { OPERAND_art }, 'm' }
3276 };
3277
3278 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = {
3279 { { STATE_WindowStart }, 'm' }
3280 };
3281
3282 static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = {
3283 { { OPERAND_arr }, 'o' },
3284 { { OPERAND_ars }, 'i' },
3285 { { OPERAND_art }, 'i' }
3286 };
3287
3288 static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = {
3289 { { OPERAND_arr }, 'o' },
3290 { { OPERAND_ars }, 'i' },
3291 { { OPERAND_ai4const }, 'i' }
3292 };
3293
3294 static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = {
3295 { { OPERAND_ars }, 'i' },
3296 { { OPERAND_uimm6 }, 'i' }
3297 };
3298
3299 static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = {
3300 { { OPERAND_art }, 'o' },
3301 { { OPERAND_ars }, 'i' },
3302 { { OPERAND_lsi4x4 }, 'i' }
3303 };
3304
3305 static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = {
3306 { { OPERAND_art }, 'o' },
3307 { { OPERAND_ars }, 'i' }
3308 };
3309
3310 static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = {
3311 { { OPERAND_ars }, 'o' },
3312 { { OPERAND_simm7 }, 'i' }
3313 };
3314
3315 static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = {
3316 { { OPERAND__ars_invisible }, 'i' }
3317 };
3318
3319 static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = {
3320 { { OPERAND_art }, 'i' },
3321 { { OPERAND_ars }, 'i' },
3322 { { OPERAND_lsi4x4 }, 'i' }
3323 };
3324
3325 static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = {
3326 { { OPERAND_art }, 'o' },
3327 { { OPERAND_ars }, 'i' },
3328 { { OPERAND_simm8 }, 'i' }
3329 };
3330
3331 static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = {
3332 { { OPERAND_art }, 'o' },
3333 { { OPERAND_ars }, 'i' },
3334 { { OPERAND_simm8x256 }, 'i' }
3335 };
3336
3337 static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = {
3338 { { OPERAND_arr }, 'o' },
3339 { { OPERAND_ars }, 'i' },
3340 { { OPERAND_art }, 'i' }
3341 };
3342
3343 static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = {
3344 { { OPERAND_arr }, 'o' },
3345 { { OPERAND_ars }, 'i' },
3346 { { OPERAND_art }, 'i' }
3347 };
3348
3349 static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = {
3350 { { OPERAND_ars }, 'i' },
3351 { { OPERAND_b4const }, 'i' },
3352 { { OPERAND_label8 }, 'i' }
3353 };
3354
3355 static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = {
3356 { { OPERAND_ars }, 'i' },
3357 { { OPERAND_bbi }, 'i' },
3358 { { OPERAND_label8 }, 'i' }
3359 };
3360
3361 static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = {
3362 { { OPERAND_ars }, 'i' },
3363 { { OPERAND_b4constu }, 'i' },
3364 { { OPERAND_label8 }, 'i' }
3365 };
3366
3367 static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = {
3368 { { OPERAND_ars }, 'i' },
3369 { { OPERAND_art }, 'i' },
3370 { { OPERAND_label8 }, 'i' }
3371 };
3372
3373 static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = {
3374 { { OPERAND_ars }, 'i' },
3375 { { OPERAND_label12 }, 'i' }
3376 };
3377
3378 static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = {
3379 { { OPERAND_soffsetx4 }, 'i' },
3380 { { OPERAND_ar0 }, 'o' }
3381 };
3382
3383 static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = {
3384 { { OPERAND_ars }, 'i' },
3385 { { OPERAND_ar0 }, 'o' }
3386 };
3387
3388 static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = {
3389 { { OPERAND_arr }, 'o' },
3390 { { OPERAND_art }, 'i' },
3391 { { OPERAND_sae }, 'i' },
3392 { { OPERAND_op2p1 }, 'i' }
3393 };
3394
3395 static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = {
3396 { { OPERAND_soffset }, 'i' }
3397 };
3398
3399 static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = {
3400 { { OPERAND_ars }, 'i' }
3401 };
3402
3403 static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = {
3404 { { OPERAND_art }, 'o' },
3405 { { OPERAND_ars }, 'i' },
3406 { { OPERAND_uimm8x2 }, 'i' }
3407 };
3408
3409 static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = {
3410 { { OPERAND_art }, 'o' },
3411 { { OPERAND_ars }, 'i' },
3412 { { OPERAND_uimm8x2 }, 'i' }
3413 };
3414
3415 static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = {
3416 { { OPERAND_art }, 'o' },
3417 { { OPERAND_ars }, 'i' },
3418 { { OPERAND_uimm8x4 }, 'i' }
3419 };
3420
3421 static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = {
3422 { { OPERAND_art }, 'o' },
3423 { { OPERAND_uimm16x4 }, 'i' }
3424 };
3425
3426 static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = {
3427 { { OPERAND_art }, 'o' },
3428 { { OPERAND_ars }, 'i' },
3429 { { OPERAND_uimm8 }, 'i' }
3430 };
3431
3432 static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = {
3433 { { OPERAND_ars }, 'i' },
3434 { { OPERAND_ulabel8 }, 'i' }
3435 };
3436
3437 static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = {
3438 { { STATE_LBEG }, 'o' },
3439 { { STATE_LEND }, 'o' },
3440 { { STATE_LCOUNT }, 'o' }
3441 };
3442
3443 static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = {
3444 { { OPERAND_ars }, 'i' },
3445 { { OPERAND_ulabel8 }, 'i' }
3446 };
3447
3448 static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = {
3449 { { STATE_LBEG }, 'o' },
3450 { { STATE_LEND }, 'o' },
3451 { { STATE_LCOUNT }, 'o' }
3452 };
3453
3454 static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = {
3455 { { OPERAND_art }, 'o' },
3456 { { OPERAND_simm12b }, 'i' }
3457 };
3458
3459 static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = {
3460 { { OPERAND_arr }, 'm' },
3461 { { OPERAND_ars }, 'i' },
3462 { { OPERAND_art }, 'i' }
3463 };
3464
3465 static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = {
3466 { { OPERAND_arr }, 'o' },
3467 { { OPERAND_art }, 'i' }
3468 };
3469
3470 static xtensa_arg_internal Iclass_xt_iclass_return_args[] = {
3471 { { OPERAND__ars_invisible }, 'i' }
3472 };
3473
3474 static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = {
3475 { { OPERAND_art }, 'i' },
3476 { { OPERAND_ars }, 'i' },
3477 { { OPERAND_uimm8x2 }, 'i' }
3478 };
3479
3480 static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = {
3481 { { OPERAND_art }, 'i' },
3482 { { OPERAND_ars }, 'i' },
3483 { { OPERAND_uimm8x4 }, 'i' }
3484 };
3485
3486 static xtensa_arg_internal Iclass_xt_iclass_s32nb_args[] = {
3487 { { OPERAND_art }, 'i' },
3488 { { OPERAND_ars }, 'i' },
3489 { { OPERAND_uimmrx4 }, 'i' }
3490 };
3491
3492 static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = {
3493 { { OPERAND_art }, 'i' },
3494 { { OPERAND_ars }, 'i' },
3495 { { OPERAND_uimm8 }, 'i' }
3496 };
3497
3498 static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = {
3499 { { OPERAND_ars }, 'i' }
3500 };
3501
3502 static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = {
3503 { { STATE_SAR }, 'o' }
3504 };
3505
3506 static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = {
3507 { { OPERAND_sas }, 'i' }
3508 };
3509
3510 static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = {
3511 { { STATE_SAR }, 'o' }
3512 };
3513
3514 static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = {
3515 { { OPERAND_arr }, 'o' },
3516 { { OPERAND_ars }, 'i' }
3517 };
3518
3519 static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = {
3520 { { STATE_SAR }, 'i' }
3521 };
3522
3523 static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = {
3524 { { OPERAND_arr }, 'o' },
3525 { { OPERAND_ars }, 'i' },
3526 { { OPERAND_art }, 'i' }
3527 };
3528
3529 static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = {
3530 { { STATE_SAR }, 'i' }
3531 };
3532
3533 static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = {
3534 { { OPERAND_arr }, 'o' },
3535 { { OPERAND_art }, 'i' }
3536 };
3537
3538 static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = {
3539 { { STATE_SAR }, 'i' }
3540 };
3541
3542 static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = {
3543 { { OPERAND_arr }, 'o' },
3544 { { OPERAND_ars }, 'i' },
3545 { { OPERAND_msalp32 }, 'i' }
3546 };
3547
3548 static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = {
3549 { { OPERAND_arr }, 'o' },
3550 { { OPERAND_art }, 'i' },
3551 { { OPERAND_sargt }, 'i' }
3552 };
3553
3554 static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = {
3555 { { OPERAND_arr }, 'o' },
3556 { { OPERAND_art }, 'i' },
3557 { { OPERAND_s }, 'i' }
3558 };
3559
3560 static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = {
3561 { { STATE_XTSYNC }, 'i' }
3562 };
3563
3564 static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = {
3565 { { OPERAND_art }, 'o' },
3566 { { OPERAND_s }, 'i' }
3567 };
3568
3569 static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = {
3570 { { STATE_PSWOE }, 'i' },
3571 { { STATE_PSCALLINC }, 'i' },
3572 { { STATE_PSOWB }, 'i' },
3573 { { STATE_PSUM }, 'i' },
3574 { { STATE_PSEXCM }, 'i' },
3575 { { STATE_PSINTLEVEL }, 'm' }
3576 };
3577
3578 static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = {
3579 { { OPERAND_art }, 'o' }
3580 };
3581
3582 static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = {
3583 { { STATE_LEND }, 'i' }
3584 };
3585
3586 static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = {
3587 { { OPERAND_art }, 'i' }
3588 };
3589
3590 static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = {
3591 { { STATE_LEND }, 'o' }
3592 };
3593
3594 static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = {
3595 { { OPERAND_art }, 'm' }
3596 };
3597
3598 static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = {
3599 { { STATE_LEND }, 'm' }
3600 };
3601
3602 static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = {
3603 { { OPERAND_art }, 'o' }
3604 };
3605
3606 static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = {
3607 { { STATE_LCOUNT }, 'i' }
3608 };
3609
3610 static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = {
3611 { { OPERAND_art }, 'i' }
3612 };
3613
3614 static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = {
3615 { { STATE_XTSYNC }, 'o' },
3616 { { STATE_LCOUNT }, 'o' }
3617 };
3618
3619 static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = {
3620 { { OPERAND_art }, 'm' }
3621 };
3622
3623 static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = {
3624 { { STATE_XTSYNC }, 'o' },
3625 { { STATE_LCOUNT }, 'm' }
3626 };
3627
3628 static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = {
3629 { { OPERAND_art }, 'o' }
3630 };
3631
3632 static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = {
3633 { { STATE_LBEG }, 'i' }
3634 };
3635
3636 static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = {
3637 { { OPERAND_art }, 'i' }
3638 };
3639
3640 static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = {
3641 { { STATE_LBEG }, 'o' }
3642 };
3643
3644 static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = {
3645 { { OPERAND_art }, 'm' }
3646 };
3647
3648 static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = {
3649 { { STATE_LBEG }, 'm' }
3650 };
3651
3652 static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = {
3653 { { OPERAND_art }, 'o' }
3654 };
3655
3656 static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = {
3657 { { STATE_SAR }, 'i' }
3658 };
3659
3660 static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = {
3661 { { OPERAND_art }, 'i' }
3662 };
3663
3664 static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = {
3665 { { STATE_SAR }, 'o' },
3666 { { STATE_XTSYNC }, 'o' }
3667 };
3668
3669 static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = {
3670 { { OPERAND_art }, 'm' }
3671 };
3672
3673 static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = {
3674 { { STATE_SAR }, 'm' }
3675 };
3676
3677 static xtensa_arg_internal Iclass_xt_iclass_rsr_memctl_args[] = {
3678 { { OPERAND_art }, 'o' }
3679 };
3680
3681 static xtensa_arg_internal Iclass_xt_iclass_wsr_memctl_args[] = {
3682 { { OPERAND_art }, 'i' }
3683 };
3684
3685 static xtensa_arg_internal Iclass_xt_iclass_xsr_memctl_args[] = {
3686 { { OPERAND_art }, 'm' }
3687 };
3688
3689 static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = {
3690 { { OPERAND_art }, 'o' }
3691 };
3692
3693 static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = {
3694 { { OPERAND_art }, 'i' }
3695 };
3696
3697 static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = {
3698 { { OPERAND_art }, 'm' }
3699 };
3700
3701 static xtensa_arg_internal Iclass_xt_iclass_rsr_configid0_args[] = {
3702 { { OPERAND_art }, 'o' }
3703 };
3704
3705 static xtensa_arg_internal Iclass_xt_iclass_wsr_configid0_args[] = {
3706 { { OPERAND_art }, 'i' }
3707 };
3708
3709 static xtensa_arg_internal Iclass_xt_iclass_rsr_configid1_args[] = {
3710 { { OPERAND_art }, 'o' }
3711 };
3712
3713 static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = {
3714 { { OPERAND_art }, 'o' }
3715 };
3716
3717 static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = {
3718 { { STATE_PSWOE }, 'i' },
3719 { { STATE_PSCALLINC }, 'i' },
3720 { { STATE_PSOWB }, 'i' },
3721 { { STATE_PSUM }, 'i' },
3722 { { STATE_PSEXCM }, 'i' },
3723 { { STATE_PSINTLEVEL }, 'i' }
3724 };
3725
3726 static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = {
3727 { { OPERAND_art }, 'i' }
3728 };
3729
3730 static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = {
3731 { { STATE_PSWOE }, 'o' },
3732 { { STATE_PSCALLINC }, 'o' },
3733 { { STATE_PSOWB }, 'o' },
3734 { { STATE_PSUM }, 'o' },
3735 { { STATE_PSEXCM }, 'o' },
3736 { { STATE_PSINTLEVEL }, 'o' }
3737 };
3738
3739 static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = {
3740 { { OPERAND_art }, 'm' }
3741 };
3742
3743 static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = {
3744 { { STATE_PSWOE }, 'm' },
3745 { { STATE_PSCALLINC }, 'm' },
3746 { { STATE_PSOWB }, 'm' },
3747 { { STATE_PSUM }, 'm' },
3748 { { STATE_PSEXCM }, 'm' },
3749 { { STATE_PSINTLEVEL }, 'm' }
3750 };
3751
3752 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = {
3753 { { OPERAND_art }, 'o' }
3754 };
3755
3756 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = {
3757 { { STATE_EPC1 }, 'i' }
3758 };
3759
3760 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = {
3761 { { OPERAND_art }, 'i' }
3762 };
3763
3764 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = {
3765 { { STATE_EPC1 }, 'o' }
3766 };
3767
3768 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = {
3769 { { OPERAND_art }, 'm' }
3770 };
3771
3772 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = {
3773 { { STATE_EPC1 }, 'm' }
3774 };
3775
3776 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = {
3777 { { OPERAND_art }, 'o' }
3778 };
3779
3780 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = {
3781 { { STATE_EXCSAVE1 }, 'i' }
3782 };
3783
3784 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = {
3785 { { OPERAND_art }, 'i' }
3786 };
3787
3788 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = {
3789 { { STATE_EXCSAVE1 }, 'o' }
3790 };
3791
3792 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = {
3793 { { OPERAND_art }, 'm' }
3794 };
3795
3796 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = {
3797 { { STATE_EXCSAVE1 }, 'm' }
3798 };
3799
3800 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = {
3801 { { OPERAND_art }, 'o' }
3802 };
3803
3804 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = {
3805 { { STATE_EPC2 }, 'i' }
3806 };
3807
3808 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = {
3809 { { OPERAND_art }, 'i' }
3810 };
3811
3812 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = {
3813 { { STATE_EPC2 }, 'o' }
3814 };
3815
3816 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = {
3817 { { OPERAND_art }, 'm' }
3818 };
3819
3820 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = {
3821 { { STATE_EPC2 }, 'm' }
3822 };
3823
3824 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = {
3825 { { OPERAND_art }, 'o' }
3826 };
3827
3828 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = {
3829 { { STATE_EXCSAVE2 }, 'i' }
3830 };
3831
3832 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = {
3833 { { OPERAND_art }, 'i' }
3834 };
3835
3836 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = {
3837 { { STATE_EXCSAVE2 }, 'o' }
3838 };
3839
3840 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = {
3841 { { OPERAND_art }, 'm' }
3842 };
3843
3844 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = {
3845 { { STATE_EXCSAVE2 }, 'm' }
3846 };
3847
3848 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = {
3849 { { OPERAND_art }, 'o' }
3850 };
3851
3852 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = {
3853 { { STATE_EPC3 }, 'i' }
3854 };
3855
3856 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = {
3857 { { OPERAND_art }, 'i' }
3858 };
3859
3860 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = {
3861 { { STATE_EPC3 }, 'o' }
3862 };
3863
3864 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = {
3865 { { OPERAND_art }, 'm' }
3866 };
3867
3868 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = {
3869 { { STATE_EPC3 }, 'm' }
3870 };
3871
3872 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = {
3873 { { OPERAND_art }, 'o' }
3874 };
3875
3876 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = {
3877 { { STATE_EXCSAVE3 }, 'i' }
3878 };
3879
3880 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = {
3881 { { OPERAND_art }, 'i' }
3882 };
3883
3884 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = {
3885 { { STATE_EXCSAVE3 }, 'o' }
3886 };
3887
3888 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = {
3889 { { OPERAND_art }, 'm' }
3890 };
3891
3892 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = {
3893 { { STATE_EXCSAVE3 }, 'm' }
3894 };
3895
3896 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = {
3897 { { OPERAND_art }, 'o' }
3898 };
3899
3900 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = {
3901 { { STATE_EPC4 }, 'i' }
3902 };
3903
3904 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = {
3905 { { OPERAND_art }, 'i' }
3906 };
3907
3908 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = {
3909 { { STATE_EPC4 }, 'o' }
3910 };
3911
3912 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = {
3913 { { OPERAND_art }, 'm' }
3914 };
3915
3916 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = {
3917 { { STATE_EPC4 }, 'm' }
3918 };
3919
3920 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = {
3921 { { OPERAND_art }, 'o' }
3922 };
3923
3924 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = {
3925 { { STATE_EXCSAVE4 }, 'i' }
3926 };
3927
3928 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = {
3929 { { OPERAND_art }, 'i' }
3930 };
3931
3932 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = {
3933 { { STATE_EXCSAVE4 }, 'o' }
3934 };
3935
3936 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = {
3937 { { OPERAND_art }, 'm' }
3938 };
3939
3940 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = {
3941 { { STATE_EXCSAVE4 }, 'm' }
3942 };
3943
3944 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_args[] = {
3945 { { OPERAND_art }, 'o' }
3946 };
3947
3948 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_stateArgs[] = {
3949 { { STATE_EPC5 }, 'i' }
3950 };
3951
3952 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_args[] = {
3953 { { OPERAND_art }, 'i' }
3954 };
3955
3956 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_stateArgs[] = {
3957 { { STATE_EPC5 }, 'o' }
3958 };
3959
3960 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_args[] = {
3961 { { OPERAND_art }, 'm' }
3962 };
3963
3964 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_stateArgs[] = {
3965 { { STATE_EPC5 }, 'm' }
3966 };
3967
3968 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_args[] = {
3969 { { OPERAND_art }, 'o' }
3970 };
3971
3972 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_stateArgs[] = {
3973 { { STATE_EXCSAVE5 }, 'i' }
3974 };
3975
3976 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_args[] = {
3977 { { OPERAND_art }, 'i' }
3978 };
3979
3980 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_stateArgs[] = {
3981 { { STATE_EXCSAVE5 }, 'o' }
3982 };
3983
3984 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_args[] = {
3985 { { OPERAND_art }, 'm' }
3986 };
3987
3988 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_stateArgs[] = {
3989 { { STATE_EXCSAVE5 }, 'm' }
3990 };
3991
3992 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_args[] = {
3993 { { OPERAND_art }, 'o' }
3994 };
3995
3996 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_stateArgs[] = {
3997 { { STATE_EPC6 }, 'i' }
3998 };
3999
4000 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_args[] = {
4001 { { OPERAND_art }, 'i' }
4002 };
4003
4004 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_stateArgs[] = {
4005 { { STATE_EPC6 }, 'o' }
4006 };
4007
4008 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_args[] = {
4009 { { OPERAND_art }, 'm' }
4010 };
4011
4012 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_stateArgs[] = {
4013 { { STATE_EPC6 }, 'm' }
4014 };
4015
4016 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_args[] = {
4017 { { OPERAND_art }, 'o' }
4018 };
4019
4020 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_stateArgs[] = {
4021 { { STATE_EXCSAVE6 }, 'i' }
4022 };
4023
4024 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_args[] = {
4025 { { OPERAND_art }, 'i' }
4026 };
4027
4028 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_stateArgs[] = {
4029 { { STATE_EXCSAVE6 }, 'o' }
4030 };
4031
4032 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_args[] = {
4033 { { OPERAND_art }, 'm' }
4034 };
4035
4036 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_stateArgs[] = {
4037 { { STATE_EXCSAVE6 }, 'm' }
4038 };
4039
4040 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_args[] = {
4041 { { OPERAND_art }, 'o' }
4042 };
4043
4044 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_stateArgs[] = {
4045 { { STATE_EPC7 }, 'i' }
4046 };
4047
4048 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_args[] = {
4049 { { OPERAND_art }, 'i' }
4050 };
4051
4052 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_stateArgs[] = {
4053 { { STATE_EPC7 }, 'o' }
4054 };
4055
4056 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_args[] = {
4057 { { OPERAND_art }, 'm' }
4058 };
4059
4060 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_stateArgs[] = {
4061 { { STATE_EPC7 }, 'm' }
4062 };
4063
4064 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_args[] = {
4065 { { OPERAND_art }, 'o' }
4066 };
4067
4068 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_stateArgs[] = {
4069 { { STATE_EXCSAVE7 }, 'i' }
4070 };
4071
4072 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_args[] = {
4073 { { OPERAND_art }, 'i' }
4074 };
4075
4076 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_stateArgs[] = {
4077 { { STATE_EXCSAVE7 }, 'o' }
4078 };
4079
4080 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_args[] = {
4081 { { OPERAND_art }, 'm' }
4082 };
4083
4084 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_stateArgs[] = {
4085 { { STATE_EXCSAVE7 }, 'm' }
4086 };
4087
4088 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = {
4089 { { OPERAND_art }, 'o' }
4090 };
4091
4092 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = {
4093 { { STATE_EPS2 }, 'i' }
4094 };
4095
4096 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = {
4097 { { OPERAND_art }, 'i' }
4098 };
4099
4100 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = {
4101 { { STATE_EPS2 }, 'o' }
4102 };
4103
4104 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = {
4105 { { OPERAND_art }, 'm' }
4106 };
4107
4108 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = {
4109 { { STATE_EPS2 }, 'm' }
4110 };
4111
4112 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = {
4113 { { OPERAND_art }, 'o' }
4114 };
4115
4116 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = {
4117 { { STATE_EPS3 }, 'i' }
4118 };
4119
4120 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = {
4121 { { OPERAND_art }, 'i' }
4122 };
4123
4124 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = {
4125 { { STATE_EPS3 }, 'o' }
4126 };
4127
4128 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = {
4129 { { OPERAND_art }, 'm' }
4130 };
4131
4132 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = {
4133 { { STATE_EPS3 }, 'm' }
4134 };
4135
4136 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = {
4137 { { OPERAND_art }, 'o' }
4138 };
4139
4140 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = {
4141 { { STATE_EPS4 }, 'i' }
4142 };
4143
4144 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = {
4145 { { OPERAND_art }, 'i' }
4146 };
4147
4148 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = {
4149 { { STATE_EPS4 }, 'o' }
4150 };
4151
4152 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = {
4153 { { OPERAND_art }, 'm' }
4154 };
4155
4156 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = {
4157 { { STATE_EPS4 }, 'm' }
4158 };
4159
4160 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_args[] = {
4161 { { OPERAND_art }, 'o' }
4162 };
4163
4164 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_stateArgs[] = {
4165 { { STATE_EPS5 }, 'i' }
4166 };
4167
4168 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_args[] = {
4169 { { OPERAND_art }, 'i' }
4170 };
4171
4172 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_stateArgs[] = {
4173 { { STATE_EPS5 }, 'o' }
4174 };
4175
4176 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_args[] = {
4177 { { OPERAND_art }, 'm' }
4178 };
4179
4180 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_stateArgs[] = {
4181 { { STATE_EPS5 }, 'm' }
4182 };
4183
4184 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_args[] = {
4185 { { OPERAND_art }, 'o' }
4186 };
4187
4188 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_stateArgs[] = {
4189 { { STATE_EPS6 }, 'i' }
4190 };
4191
4192 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_args[] = {
4193 { { OPERAND_art }, 'i' }
4194 };
4195
4196 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_stateArgs[] = {
4197 { { STATE_EPS6 }, 'o' }
4198 };
4199
4200 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_args[] = {
4201 { { OPERAND_art }, 'm' }
4202 };
4203
4204 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_stateArgs[] = {
4205 { { STATE_EPS6 }, 'm' }
4206 };
4207
4208 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_args[] = {
4209 { { OPERAND_art }, 'o' }
4210 };
4211
4212 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_stateArgs[] = {
4213 { { STATE_EPS7 }, 'i' }
4214 };
4215
4216 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_args[] = {
4217 { { OPERAND_art }, 'i' }
4218 };
4219
4220 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_stateArgs[] = {
4221 { { STATE_EPS7 }, 'o' }
4222 };
4223
4224 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_args[] = {
4225 { { OPERAND_art }, 'm' }
4226 };
4227
4228 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_stateArgs[] = {
4229 { { STATE_EPS7 }, 'm' }
4230 };
4231
4232 static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = {
4233 { { OPERAND_art }, 'o' }
4234 };
4235
4236 static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = {
4237 { { STATE_EXCVADDR }, 'i' }
4238 };
4239
4240 static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = {
4241 { { OPERAND_art }, 'i' }
4242 };
4243
4244 static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = {
4245 { { STATE_EXCVADDR }, 'o' }
4246 };
4247
4248 static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = {
4249 { { OPERAND_art }, 'm' }
4250 };
4251
4252 static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = {
4253 { { STATE_EXCVADDR }, 'm' }
4254 };
4255
4256 static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = {
4257 { { OPERAND_art }, 'o' }
4258 };
4259
4260 static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = {
4261 { { STATE_DEPC }, 'i' }
4262 };
4263
4264 static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = {
4265 { { OPERAND_art }, 'i' }
4266 };
4267
4268 static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = {
4269 { { STATE_DEPC }, 'o' }
4270 };
4271
4272 static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = {
4273 { { OPERAND_art }, 'm' }
4274 };
4275
4276 static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = {
4277 { { STATE_DEPC }, 'm' }
4278 };
4279
4280 static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = {
4281 { { OPERAND_art }, 'o' }
4282 };
4283
4284 static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = {
4285 { { STATE_EXCCAUSE }, 'i' },
4286 { { STATE_XTSYNC }, 'i' }
4287 };
4288
4289 static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = {
4290 { { OPERAND_art }, 'i' }
4291 };
4292
4293 static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = {
4294 { { STATE_EXCCAUSE }, 'o' }
4295 };
4296
4297 static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = {
4298 { { OPERAND_art }, 'm' }
4299 };
4300
4301 static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = {
4302 { { STATE_EXCCAUSE }, 'm' }
4303 };
4304
4305 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = {
4306 { { OPERAND_art }, 'o' }
4307 };
4308
4309 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = {
4310 { { STATE_MISC0 }, 'i' }
4311 };
4312
4313 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = {
4314 { { OPERAND_art }, 'i' }
4315 };
4316
4317 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = {
4318 { { STATE_MISC0 }, 'o' }
4319 };
4320
4321 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = {
4322 { { OPERAND_art }, 'm' }
4323 };
4324
4325 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = {
4326 { { STATE_MISC0 }, 'm' }
4327 };
4328
4329 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = {
4330 { { OPERAND_art }, 'o' }
4331 };
4332
4333 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = {
4334 { { STATE_MISC1 }, 'i' }
4335 };
4336
4337 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = {
4338 { { OPERAND_art }, 'i' }
4339 };
4340
4341 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = {
4342 { { STATE_MISC1 }, 'o' }
4343 };
4344
4345 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = {
4346 { { OPERAND_art }, 'm' }
4347 };
4348
4349 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = {
4350 { { STATE_MISC1 }, 'm' }
4351 };
4352
4353 static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = {
4354 { { OPERAND_art }, 'o' }
4355 };
4356
4357 static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = {
4358 { { OPERAND_art }, 'o' }
4359 };
4360
4361 static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = {
4362 { { STATE_VECBASE }, 'i' }
4363 };
4364
4365 static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = {
4366 { { OPERAND_art }, 'i' }
4367 };
4368
4369 static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = {
4370 { { STATE_VECBASE }, 'o' }
4371 };
4372
4373 static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = {
4374 { { OPERAND_art }, 'm' }
4375 };
4376
4377 static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = {
4378 { { STATE_VECBASE }, 'm' }
4379 };
4380
4381 static xtensa_arg_internal Iclass_xt_mul16_args[] = {
4382 { { OPERAND_arr }, 'o' },
4383 { { OPERAND_ars }, 'i' },
4384 { { OPERAND_art }, 'i' }
4385 };
4386
4387 static xtensa_arg_internal Iclass_xt_mul32_args[] = {
4388 { { OPERAND_arr }, 'o' },
4389 { { OPERAND_ars }, 'i' },
4390 { { OPERAND_art }, 'i' }
4391 };
4392
4393 static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_args[] = {
4394 { { OPERAND_ars }, 'i' },
4395 { { OPERAND_art }, 'i' }
4396 };
4397
4398 static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_stateArgs[] = {
4399 { { STATE_ACC }, 'o' }
4400 };
4401
4402 static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_args[] = {
4403 { { OPERAND_ars }, 'i' },
4404 { { OPERAND_my }, 'i' }
4405 };
4406
4407 static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_stateArgs[] = {
4408 { { STATE_ACC }, 'o' }
4409 };
4410
4411 static xtensa_arg_internal Iclass_xt_iclass_mac16_da_args[] = {
4412 { { OPERAND_mx }, 'i' },
4413 { { OPERAND_art }, 'i' }
4414 };
4415
4416 static xtensa_arg_internal Iclass_xt_iclass_mac16_da_stateArgs[] = {
4417 { { STATE_ACC }, 'o' }
4418 };
4419
4420 static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_args[] = {
4421 { { OPERAND_mx }, 'i' },
4422 { { OPERAND_my }, 'i' }
4423 };
4424
4425 static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_stateArgs[] = {
4426 { { STATE_ACC }, 'o' }
4427 };
4428
4429 static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_args[] = {
4430 { { OPERAND_ars }, 'i' },
4431 { { OPERAND_art }, 'i' }
4432 };
4433
4434 static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_stateArgs[] = {
4435 { { STATE_ACC }, 'm' }
4436 };
4437
4438 static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_args[] = {
4439 { { OPERAND_ars }, 'i' },
4440 { { OPERAND_my }, 'i' }
4441 };
4442
4443 static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_stateArgs[] = {
4444 { { STATE_ACC }, 'm' }
4445 };
4446
4447 static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_args[] = {
4448 { { OPERAND_mx }, 'i' },
4449 { { OPERAND_art }, 'i' }
4450 };
4451
4452 static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_stateArgs[] = {
4453 { { STATE_ACC }, 'm' }
4454 };
4455
4456 static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_args[] = {
4457 { { OPERAND_mx }, 'i' },
4458 { { OPERAND_my }, 'i' }
4459 };
4460
4461 static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_stateArgs[] = {
4462 { { STATE_ACC }, 'm' }
4463 };
4464
4465 static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_args[] = {
4466 { { OPERAND_mw }, 'o' },
4467 { { OPERAND_ars }, 'm' },
4468 { { OPERAND_mx }, 'i' },
4469 { { OPERAND_art }, 'i' }
4470 };
4471
4472 static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_stateArgs[] = {
4473 { { STATE_ACC }, 'm' }
4474 };
4475
4476 static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_args[] = {
4477 { { OPERAND_mw }, 'o' },
4478 { { OPERAND_ars }, 'm' },
4479 { { OPERAND_mx }, 'i' },
4480 { { OPERAND_my }, 'i' }
4481 };
4482
4483 static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_stateArgs[] = {
4484 { { STATE_ACC }, 'm' }
4485 };
4486
4487 static xtensa_arg_internal Iclass_xt_iclass_mac16_l_args[] = {
4488 { { OPERAND_mw }, 'o' },
4489 { { OPERAND_ars }, 'm' }
4490 };
4491
4492 static xtensa_arg_internal Iclass_xt_iclass_rsr_m0_args[] = {
4493 { { OPERAND_art }, 'o' },
4494 { { OPERAND_mr0 }, 'i' }
4495 };
4496
4497 static xtensa_arg_internal Iclass_xt_iclass_wsr_m0_args[] = {
4498 { { OPERAND_art }, 'i' },
4499 { { OPERAND_mr0 }, 'o' }
4500 };
4501
4502 static xtensa_arg_internal Iclass_xt_iclass_xsr_m0_args[] = {
4503 { { OPERAND_art }, 'm' },
4504 { { OPERAND_mr0 }, 'm' }
4505 };
4506
4507 static xtensa_arg_internal Iclass_xt_iclass_rsr_m1_args[] = {
4508 { { OPERAND_art }, 'o' },
4509 { { OPERAND_mr1 }, 'i' }
4510 };
4511
4512 static xtensa_arg_internal Iclass_xt_iclass_wsr_m1_args[] = {
4513 { { OPERAND_art }, 'i' },
4514 { { OPERAND_mr1 }, 'o' }
4515 };
4516
4517 static xtensa_arg_internal Iclass_xt_iclass_xsr_m1_args[] = {
4518 { { OPERAND_art }, 'm' },
4519 { { OPERAND_mr1 }, 'm' }
4520 };
4521
4522 static xtensa_arg_internal Iclass_xt_iclass_rsr_m2_args[] = {
4523 { { OPERAND_art }, 'o' },
4524 { { OPERAND_mr2 }, 'i' }
4525 };
4526
4527 static xtensa_arg_internal Iclass_xt_iclass_wsr_m2_args[] = {
4528 { { OPERAND_art }, 'i' },
4529 { { OPERAND_mr2 }, 'o' }
4530 };
4531
4532 static xtensa_arg_internal Iclass_xt_iclass_xsr_m2_args[] = {
4533 { { OPERAND_art }, 'm' },
4534 { { OPERAND_mr2 }, 'm' }
4535 };
4536
4537 static xtensa_arg_internal Iclass_xt_iclass_rsr_m3_args[] = {
4538 { { OPERAND_art }, 'o' },
4539 { { OPERAND_mr3 }, 'i' }
4540 };
4541
4542 static xtensa_arg_internal Iclass_xt_iclass_wsr_m3_args[] = {
4543 { { OPERAND_art }, 'i' },
4544 { { OPERAND_mr3 }, 'o' }
4545 };
4546
4547 static xtensa_arg_internal Iclass_xt_iclass_xsr_m3_args[] = {
4548 { { OPERAND_art }, 'm' },
4549 { { OPERAND_mr3 }, 'm' }
4550 };
4551
4552 static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_args[] = {
4553 { { OPERAND_art }, 'o' }
4554 };
4555
4556 static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_stateArgs[] = {
4557 { { STATE_ACC }, 'i' }
4558 };
4559
4560 static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_args[] = {
4561 { { OPERAND_art }, 'i' }
4562 };
4563
4564 static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_stateArgs[] = {
4565 { { STATE_ACC }, 'm' }
4566 };
4567
4568 static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_args[] = {
4569 { { OPERAND_art }, 'm' }
4570 };
4571
4572 static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_stateArgs[] = {
4573 { { STATE_ACC }, 'm' }
4574 };
4575
4576 static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_args[] = {
4577 { { OPERAND_art }, 'o' }
4578 };
4579
4580 static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_stateArgs[] = {
4581 { { STATE_ACC }, 'i' }
4582 };
4583
4584 static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_args[] = {
4585 { { OPERAND_art }, 'i' }
4586 };
4587
4588 static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_stateArgs[] = {
4589 { { STATE_ACC }, 'm' }
4590 };
4591
4592 static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_args[] = {
4593 { { OPERAND_art }, 'm' }
4594 };
4595
4596 static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_stateArgs[] = {
4597 { { STATE_ACC }, 'm' }
4598 };
4599
4600 static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = {
4601 { { OPERAND_s }, 'i' }
4602 };
4603
4604 static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = {
4605 { { STATE_PSWOE }, 'o' },
4606 { { STATE_PSCALLINC }, 'o' },
4607 { { STATE_PSOWB }, 'o' },
4608 { { STATE_PSUM }, 'o' },
4609 { { STATE_PSEXCM }, 'o' },
4610 { { STATE_PSINTLEVEL }, 'o' },
4611 { { STATE_EPC1 }, 'i' },
4612 { { STATE_EPC2 }, 'i' },
4613 { { STATE_EPC3 }, 'i' },
4614 { { STATE_EPC4 }, 'i' },
4615 { { STATE_EPC5 }, 'i' },
4616 { { STATE_EPC6 }, 'i' },
4617 { { STATE_EPC7 }, 'i' },
4618 { { STATE_EPS2 }, 'i' },
4619 { { STATE_EPS3 }, 'i' },
4620 { { STATE_EPS4 }, 'i' },
4621 { { STATE_EPS5 }, 'i' },
4622 { { STATE_EPS6 }, 'i' },
4623 { { STATE_EPS7 }, 'i' },
4624 { { STATE_InOCDMode }, 'm' }
4625 };
4626
4627 static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = {
4628 { { OPERAND_s }, 'i' }
4629 };
4630
4631 static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = {
4632 { { STATE_PSINTLEVEL }, 'o' }
4633 };
4634
4635 static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = {
4636 { { OPERAND_art }, 'o' }
4637 };
4638
4639 static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = {
4640 { { STATE_INTERRUPT }, 'i' }
4641 };
4642
4643 static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = {
4644 { { OPERAND_art }, 'i' }
4645 };
4646
4647 static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = {
4648 { { STATE_XTSYNC }, 'o' },
4649 { { STATE_INTERRUPT }, 'm' }
4650 };
4651
4652 static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = {
4653 { { OPERAND_art }, 'i' }
4654 };
4655
4656 static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = {
4657 { { STATE_XTSYNC }, 'o' },
4658 { { STATE_INTERRUPT }, 'm' }
4659 };
4660
4661 static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = {
4662 { { OPERAND_art }, 'o' }
4663 };
4664
4665 static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = {
4666 { { STATE_INTENABLE }, 'i' }
4667 };
4668
4669 static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = {
4670 { { OPERAND_art }, 'i' }
4671 };
4672
4673 static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = {
4674 { { STATE_INTENABLE }, 'o' }
4675 };
4676
4677 static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = {
4678 { { OPERAND_art }, 'm' }
4679 };
4680
4681 static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = {
4682 { { STATE_INTENABLE }, 'm' }
4683 };
4684
4685 static xtensa_arg_internal Iclass_xt_iclass_break_args[] = {
4686 { { OPERAND_imms }, 'i' },
4687 { { OPERAND_immt }, 'i' }
4688 };
4689
4690 static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = {
4691 { { STATE_PSEXCM }, 'i' },
4692 { { STATE_PSINTLEVEL }, 'i' }
4693 };
4694
4695 static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = {
4696 { { OPERAND_imms }, 'i' }
4697 };
4698
4699 static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = {
4700 { { STATE_PSEXCM }, 'i' },
4701 { { STATE_PSINTLEVEL }, 'i' }
4702 };
4703
4704 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = {
4705 { { OPERAND_art }, 'o' }
4706 };
4707
4708 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = {
4709 { { STATE_DBREAKA0 }, 'i' }
4710 };
4711
4712 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = {
4713 { { OPERAND_art }, 'i' }
4714 };
4715
4716 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = {
4717 { { STATE_DBREAKA0 }, 'o' },
4718 { { STATE_XTSYNC }, 'o' }
4719 };
4720
4721 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = {
4722 { { OPERAND_art }, 'm' }
4723 };
4724
4725 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = {
4726 { { STATE_DBREAKA0 }, 'm' },
4727 { { STATE_XTSYNC }, 'o' }
4728 };
4729
4730 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = {
4731 { { OPERAND_art }, 'o' }
4732 };
4733
4734 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = {
4735 { { STATE_DBREAKC0 }, 'i' }
4736 };
4737
4738 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = {
4739 { { OPERAND_art }, 'i' }
4740 };
4741
4742 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = {
4743 { { STATE_DBREAKC0 }, 'o' },
4744 { { STATE_XTSYNC }, 'o' }
4745 };
4746
4747 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = {
4748 { { OPERAND_art }, 'm' }
4749 };
4750
4751 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = {
4752 { { STATE_DBREAKC0 }, 'm' },
4753 { { STATE_XTSYNC }, 'o' }
4754 };
4755
4756 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = {
4757 { { OPERAND_art }, 'o' }
4758 };
4759
4760 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = {
4761 { { STATE_DBREAKA1 }, 'i' }
4762 };
4763
4764 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = {
4765 { { OPERAND_art }, 'i' }
4766 };
4767
4768 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = {
4769 { { STATE_DBREAKA1 }, 'o' },
4770 { { STATE_XTSYNC }, 'o' }
4771 };
4772
4773 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = {
4774 { { OPERAND_art }, 'm' }
4775 };
4776
4777 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = {
4778 { { STATE_DBREAKA1 }, 'm' },
4779 { { STATE_XTSYNC }, 'o' }
4780 };
4781
4782 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = {
4783 { { OPERAND_art }, 'o' }
4784 };
4785
4786 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = {
4787 { { STATE_DBREAKC1 }, 'i' }
4788 };
4789
4790 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = {
4791 { { OPERAND_art }, 'i' }
4792 };
4793
4794 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = {
4795 { { STATE_DBREAKC1 }, 'o' },
4796 { { STATE_XTSYNC }, 'o' }
4797 };
4798
4799 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = {
4800 { { OPERAND_art }, 'm' }
4801 };
4802
4803 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = {
4804 { { STATE_DBREAKC1 }, 'm' },
4805 { { STATE_XTSYNC }, 'o' }
4806 };
4807
4808 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = {
4809 { { OPERAND_art }, 'o' }
4810 };
4811
4812 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = {
4813 { { STATE_IBREAKA0 }, 'i' }
4814 };
4815
4816 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = {
4817 { { OPERAND_art }, 'i' }
4818 };
4819
4820 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = {
4821 { { STATE_IBREAKA0 }, 'o' }
4822 };
4823
4824 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = {
4825 { { OPERAND_art }, 'm' }
4826 };
4827
4828 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = {
4829 { { STATE_IBREAKA0 }, 'm' }
4830 };
4831
4832 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = {
4833 { { OPERAND_art }, 'o' }
4834 };
4835
4836 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = {
4837 { { STATE_IBREAKA1 }, 'i' }
4838 };
4839
4840 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = {
4841 { { OPERAND_art }, 'i' }
4842 };
4843
4844 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = {
4845 { { STATE_IBREAKA1 }, 'o' }
4846 };
4847
4848 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = {
4849 { { OPERAND_art }, 'm' }
4850 };
4851
4852 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = {
4853 { { STATE_IBREAKA1 }, 'm' }
4854 };
4855
4856 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = {
4857 { { OPERAND_art }, 'o' }
4858 };
4859
4860 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = {
4861 { { STATE_IBREAKENABLE }, 'i' }
4862 };
4863
4864 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = {
4865 { { OPERAND_art }, 'i' }
4866 };
4867
4868 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = {
4869 { { STATE_IBREAKENABLE }, 'o' }
4870 };
4871
4872 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = {
4873 { { OPERAND_art }, 'm' }
4874 };
4875
4876 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = {
4877 { { STATE_IBREAKENABLE }, 'm' }
4878 };
4879
4880 static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = {
4881 { { OPERAND_art }, 'o' }
4882 };
4883
4884 static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = {
4885 { { STATE_DEBUGCAUSE }, 'i' },
4886 { { STATE_DBNUM }, 'i' }
4887 };
4888
4889 static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = {
4890 { { OPERAND_art }, 'i' }
4891 };
4892
4893 static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = {
4894 { { STATE_DEBUGCAUSE }, 'o' },
4895 { { STATE_DBNUM }, 'o' }
4896 };
4897
4898 static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = {
4899 { { OPERAND_art }, 'm' }
4900 };
4901
4902 static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = {
4903 { { STATE_DEBUGCAUSE }, 'm' },
4904 { { STATE_DBNUM }, 'm' }
4905 };
4906
4907 static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = {
4908 { { OPERAND_art }, 'o' }
4909 };
4910
4911 static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = {
4912 { { STATE_ICOUNT }, 'i' }
4913 };
4914
4915 static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = {
4916 { { OPERAND_art }, 'i' }
4917 };
4918
4919 static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = {
4920 { { STATE_XTSYNC }, 'o' },
4921 { { STATE_ICOUNT }, 'o' }
4922 };
4923
4924 static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = {
4925 { { OPERAND_art }, 'm' }
4926 };
4927
4928 static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = {
4929 { { STATE_XTSYNC }, 'o' },
4930 { { STATE_ICOUNT }, 'm' }
4931 };
4932
4933 static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = {
4934 { { OPERAND_art }, 'o' }
4935 };
4936
4937 static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = {
4938 { { STATE_ICOUNTLEVEL }, 'i' }
4939 };
4940
4941 static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = {
4942 { { OPERAND_art }, 'i' }
4943 };
4944
4945 static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = {
4946 { { STATE_ICOUNTLEVEL }, 'o' }
4947 };
4948
4949 static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = {
4950 { { OPERAND_art }, 'm' }
4951 };
4952
4953 static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = {
4954 { { STATE_ICOUNTLEVEL }, 'm' }
4955 };
4956
4957 static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = {
4958 { { OPERAND_art }, 'o' }
4959 };
4960
4961 static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = {
4962 { { STATE_DDR }, 'i' }
4963 };
4964
4965 static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = {
4966 { { OPERAND_art }, 'i' }
4967 };
4968
4969 static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = {
4970 { { STATE_XTSYNC }, 'o' },
4971 { { STATE_DDR }, 'o' }
4972 };
4973
4974 static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = {
4975 { { OPERAND_art }, 'm' }
4976 };
4977
4978 static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = {
4979 { { STATE_XTSYNC }, 'o' },
4980 { { STATE_DDR }, 'm' }
4981 };
4982
4983 static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_args[] = {
4984 { { OPERAND_ars }, 'm' }
4985 };
4986
4987 static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_stateArgs[] = {
4988 { { STATE_XTSYNC }, 'o' },
4989 { { STATE_InOCDMode }, 'i' },
4990 { { STATE_DDR }, 'o' }
4991 };
4992
4993 static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_args[] = {
4994 { { OPERAND_ars }, 'm' }
4995 };
4996
4997 static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_stateArgs[] = {
4998 { { STATE_InOCDMode }, 'i' },
4999 { { STATE_DDR }, 'i' }
5000 };
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