| 1 | /* |
| 2 | * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa |
| 3 | * processor CORE configuration |
| 4 | * |
| 5 | * See <xtensa/config/core.h>, which includes this file, for more details. |
| 6 | */ |
| 7 | |
| 8 | /* Xtensa processor core configuration information. |
| 9 | |
| 10 | Copyright (c) 1999-2020 Tensilica Inc. |
| 11 | |
| 12 | Permission is hereby granted, free of charge, to any person obtaining |
| 13 | a copy of this software and associated documentation files (the |
| 14 | "Software"), to deal in the Software without restriction, including |
| 15 | without limitation the rights to use, copy, modify, merge, publish, |
| 16 | distribute, sublicense, and/or sell copies of the Software, and to |
| 17 | permit persons to whom the Software is furnished to do so, subject to |
| 18 | the following conditions: |
| 19 | |
| 20 | The above copyright notice and this permission notice shall be included |
| 21 | in all copies or substantial portions of the Software. |
| 22 | |
| 23 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
| 24 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 25 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
| 26 | IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY |
| 27 | CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| 28 | TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
| 29 | SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ |
| 30 | |
| 31 | #ifndef XTENSA_CORE_DE233_FPU_CORE_ISA_H |
| 32 | #define XTENSA_CORE_DE233_FPU_CORE_ISA_H |
| 33 | |
| 34 | //depot/dev/Homewood/Xtensa/SWConfig/hal/core-common.h.tph#24 - edit change 444323 (text+ko) |
| 35 | |
| 36 | /**************************************************************************** |
| 37 | Parameters Useful for Any Code, USER or PRIVILEGED |
| 38 | ****************************************************************************/ |
| 39 | |
| 40 | /* |
| 41 | * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is |
| 42 | * configured, and a value of 0 otherwise. These macros are always defined. |
| 43 | */ |
| 44 | |
| 45 | |
| 46 | /*---------------------------------------------------------------------- |
| 47 | ISA |
| 48 | ----------------------------------------------------------------------*/ |
| 49 | |
| 50 | #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ |
| 51 | #define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */ |
| 52 | #define XCHAL_NUM_AREGS 32 /* num of physical addr regs */ |
| 53 | #define XCHAL_NUM_AREGS_LOG2 5 /* log2(XCHAL_NUM_AREGS) */ |
| 54 | #define XCHAL_MAX_INSTRUCTION_SIZE 3 /* max instr bytes (3..8) */ |
| 55 | #define XCHAL_HAVE_DEBUG 1 /* debug option */ |
| 56 | #define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */ |
| 57 | #define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */ |
| 58 | #define XCHAL_LOOP_BUFFER_SIZE 0 /* zero-ov. loop instr buffer size */ |
| 59 | #define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */ |
| 60 | #define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */ |
| 61 | #define XCHAL_HAVE_SEXT 1 /* SEXT instruction */ |
| 62 | #define XCHAL_HAVE_DEPBITS 0 /* DEPBITS instruction */ |
| 63 | #define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */ |
| 64 | #define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */ |
| 65 | #define XCHAL_HAVE_MUL32 1 /* MULL instruction */ |
| 66 | #define XCHAL_HAVE_MUL32_HIGH 0 /* MULUH/MULSH instructions */ |
| 67 | #define XCHAL_HAVE_DIV32 1 /* QUOS/QUOU/REMS/REMU instructions */ |
| 68 | #define XCHAL_HAVE_L32R 1 /* L32R instruction */ |
| 69 | #define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */ |
| 70 | #define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */ |
| 71 | #define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */ |
| 72 | #define XCHAL_HAVE_EXCLUSIVE 0 /* L32EX/S32EX instructions */ |
| 73 | #define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */ |
| 74 | #define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */ |
| 75 | #define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */ |
| 76 | #define XCHAL_HAVE_ABS 1 /* ABS instruction */ |
| 77 | #define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */ |
| 78 | #define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */ |
| 79 | #define XCHAL_HAVE_SPECULATION 0 /* speculation */ |
| 80 | #define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */ |
| 81 | #define XCHAL_NUM_CONTEXTS 1 /* */ |
| 82 | #define XCHAL_NUM_MISC_REGS 2 /* num of scratch regs (0..4) */ |
| 83 | #define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */ |
| 84 | #define XCHAL_HAVE_PRID 1 /* processor ID register */ |
| 85 | #define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */ |
| 86 | #define XCHAL_HAVE_MX 0 /* MX core (Tensilica internal) */ |
| 87 | #define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */ |
| 88 | #define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */ |
| 89 | #define XCHAL_HAVE_PSO 0 /* Power Shut-Off */ |
| 90 | #define XCHAL_HAVE_PSO_CDM 0 /* core/debug/mem pwr domains */ |
| 91 | #define XCHAL_HAVE_PSO_FULL_RETENTION 0 /* all regs preserved on PSO */ |
| 92 | #define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */ |
| 93 | #define XCHAL_HAVE_BOOLEANS 1 /* boolean registers */ |
| 94 | #define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */ |
| 95 | #define XCHAL_CP_MAXCFG 8 /* max allowed cp id plus one */ |
| 96 | #define XCHAL_HAVE_MAC16 1 /* MAC16 package */ |
| 97 | #define XCHAL_HAVE_LX 1 /* LX core */ |
| 98 | #define XCHAL_HAVE_NX 0 /* NX core (starting RH) */ |
| 99 | |
| 100 | #define XCHAL_HAVE_SUPERGATHER 0 /* SuperGather */ |
| 101 | |
| 102 | #define XCHAL_HAVE_FUSION 0 /* Fusion*/ |
| 103 | #define XCHAL_HAVE_FUSION_FP 0 /* Fusion FP option */ |
| 104 | #define XCHAL_HAVE_FUSION_LOW_POWER 0 /* Fusion Low Power option */ |
| 105 | #define XCHAL_HAVE_FUSION_AES 0 /* Fusion BLE/Wifi AES-128 CCM option */ |
| 106 | #define XCHAL_HAVE_FUSION_CONVENC 0 /* Fusion Conv Encode option */ |
| 107 | #define XCHAL_HAVE_FUSION_LFSR_CRC 0 /* Fusion LFSR-CRC option */ |
| 108 | #define XCHAL_HAVE_FUSION_BITOPS 0 /* Fusion Bit Operations Support option */ |
| 109 | #define XCHAL_HAVE_FUSION_AVS 0 /* Fusion AVS option */ |
| 110 | #define XCHAL_HAVE_FUSION_16BIT_BASEBAND 0 /* Fusion 16-bit Baseband option */ |
| 111 | #define XCHAL_HAVE_FUSION_VITERBI 0 /* Fusion Viterbi option */ |
| 112 | #define XCHAL_HAVE_FUSION_SOFTDEMAP 0 /* Fusion Soft Bit Demap option */ |
| 113 | #define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */ |
| 114 | #define XCHAL_HAVE_HIFI5 0 /* HiFi5 Audio Engine pkg */ |
| 115 | #define XCHAL_HAVE_HIFI5_NN_MAC 0 /* HiFi5 Audio Engine NN-MAC option */ |
| 116 | #define XCHAL_HAVE_HIFI5_VFPU 0 /* HiFi5 Audio Engine Single-Precision VFPU option */ |
| 117 | #define XCHAL_HAVE_HIFI5_HP_VFPU 0 /* HiFi5 Audio Engine Half-Precision VFPU option */ |
| 118 | #define XCHAL_HAVE_HIFI4 0 /* HiFi4 Audio Engine pkg */ |
| 119 | #define XCHAL_HAVE_HIFI4_VFPU 0 /* HiFi4 Audio Engine VFPU option */ |
| 120 | #define XCHAL_HAVE_HIFI3 0 /* HiFi3 Audio Engine pkg */ |
| 121 | #define XCHAL_HAVE_HIFI3_VFPU 0 /* HiFi3 Audio Engine VFPU option */ |
| 122 | #define XCHAL_HAVE_HIFI3Z 0 /* HiFi3Z Audio Engine pkg */ |
| 123 | #define XCHAL_HAVE_HIFI3Z_VFPU 0 /* HiFi3Z Audio Engine VFPU option */ |
| 124 | #define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */ |
| 125 | #define XCHAL_HAVE_HIFI2EP 0 /* HiFi2EP */ |
| 126 | #define XCHAL_HAVE_HIFI_MINI 0 |
| 127 | |
| 128 | |
| 129 | |
| 130 | #define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */ |
| 131 | #define XCHAL_HAVE_USER_DPFPU 0 /* user DP floating-point pkg */ |
| 132 | #define XCHAL_HAVE_USER_SPFPU 0 /* user SP floating-point pkg */ |
| 133 | #define XCHAL_HAVE_FP 1 /* single prec floating point */ |
| 134 | #define XCHAL_HAVE_FP_DIV 1 /* FP with DIV instructions */ |
| 135 | #define XCHAL_HAVE_FP_RECIP 1 /* FP with RECIP instructions */ |
| 136 | #define XCHAL_HAVE_FP_SQRT 1 /* FP with SQRT instructions */ |
| 137 | #define XCHAL_HAVE_FP_RSQRT 1 /* FP with RSQRT instructions */ |
| 138 | #define XCHAL_HAVE_DFP 1 /* double precision FP pkg */ |
| 139 | #define XCHAL_HAVE_DFP_DIV 1 /* DFP with DIV instructions */ |
| 140 | #define XCHAL_HAVE_DFP_RECIP 1 /* DFP with RECIP instructions*/ |
| 141 | #define XCHAL_HAVE_DFP_SQRT 1 /* DFP with SQRT instructions */ |
| 142 | #define XCHAL_HAVE_DFP_RSQRT 1 /* DFP with RSQRT instructions*/ |
| 143 | #define XCHAL_HAVE_DFP_ACCEL 0 /* double precision FP acceleration pkg */ |
| 144 | #define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL /* for backward compatibility */ |
| 145 | |
| 146 | #define XCHAL_HAVE_DFPU_SINGLE_ONLY 0 /* DFPU Coprocessor, single precision only */ |
| 147 | #define XCHAL_HAVE_DFPU_SINGLE_DOUBLE 1 /* DFPU Coprocessor, single and double precision */ |
| 148 | #define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */ |
| 149 | #define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */ |
| 150 | |
| 151 | #define XCHAL_HAVE_FUSIONG 0 /* FusionG */ |
| 152 | #define XCHAL_HAVE_FUSIONG3 0 /* FusionG3 */ |
| 153 | #define XCHAL_HAVE_FUSIONG6 0 /* FusionG6 */ |
| 154 | #define XCHAL_HAVE_FUSIONG_SP_VFPU 0 /* sp_vfpu option on FusionG */ |
| 155 | #define XCHAL_HAVE_FUSIONG_DP_VFPU 0 /* dp_vfpu option on FusionG */ |
| 156 | #define XCHAL_FUSIONG_SIMD32 0 /* simd32 for FusionG */ |
| 157 | |
| 158 | #define XCHAL_HAVE_FUSIONJ 0 /* FusionJ */ |
| 159 | #define XCHAL_HAVE_FUSIONJ6 0 /* FusionJ6 */ |
| 160 | #define XCHAL_HAVE_FUSIONJ_SP_VFPU 0 /* sp_vfpu option on FusionJ */ |
| 161 | #define XCHAL_HAVE_FUSIONJ_DP_VFPU 0 /* dp_vfpu option on FusionJ */ |
| 162 | #define XCHAL_FUSIONJ_SIMD32 0 /* simd32 for FusionJ */ |
| 163 | |
| 164 | #define XCHAL_HAVE_PDX 0 /* PDX-LX */ |
| 165 | #define XCHAL_PDX_SIMD32 0 /* simd32 for PDX */ |
| 166 | #define XCHAL_HAVE_PDX4 0 /* PDX4-LX */ |
| 167 | #define XCHAL_HAVE_PDX8 0 /* PDX8-LX */ |
| 168 | #define XCHAL_HAVE_PDX16 0 /* PDX16-LX */ |
| 169 | #define XCHAL_HAVE_PDXNX 0 /* PDX-NX */ |
| 170 | |
| 171 | #define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */ |
| 172 | #define XCHAL_HAVE_CONNXD2_DUALLSFLIX 0 /* ConnX D2 & Dual LoadStore Flix */ |
| 173 | #define XCHAL_HAVE_BALL 0 |
| 174 | #define XCHAL_HAVE_BALLAP 0 |
| 175 | #define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */ |
| 176 | #define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */ |
| 177 | #define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */ |
| 178 | #define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */ |
| 179 | #define XCHAL_HAVE_CONNX_B10 0 /* ConnX B10 pkg*/ |
| 180 | #define XCHAL_HAVE_CONNX_B20 0 /* ConnX B20 pkg*/ |
| 181 | #define XCHAL_HAVE_CONNX_B_SP_VFPU 0 /* Single-precision Vector Floating-point option on ConnX B10 & B20 */ |
| 182 | #define XCHAL_HAVE_CONNX_B_SPX_VFPU 0 /* Single-precision Extended Vector Floating-point option on ConnX B10 & B20 */ |
| 183 | #define XCHAL_HAVE_CONNX_B_HPX_VFPU 0 /* Half-precision Extended Vector Floating-point option on ConnX B10 & B20 */ |
| 184 | #define XCHAL_HAVE_CONNX_B_32B_MAC 0 /* 32-bit vector MAC (real and complex), FIR & FFT option on ConnX B10 & B20 */ |
| 185 | #define XCHAL_HAVE_CONNX_B_VITERBI 0 /* Viterbi option on ConnX B10 & B20 */ |
| 186 | #define XCHAL_HAVE_CONNX_B_TURBO 0 /* Turbo option on ConnX B10 & B20 */ |
| 187 | #define XCHAL_HAVE_CONNX_B_LDPC 0 /* LDPC option on ConnX B10 & B20 */ |
| 188 | #define XCHAL_HAVE_BBENEP 0 /* ConnX BBENEP pkgs */ |
| 189 | #define XCHAL_HAVE_BBENEP_SP_VFPU 0 /* sp_vfpu option on BBE-EP */ |
| 190 | #define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */ |
| 191 | #define XCHAL_HAVE_BSP3_TRANSPOSE 0 /* BSP3 & transpose32x32 */ |
| 192 | #define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */ |
| 193 | #define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */ |
| 194 | #define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */ |
| 195 | #define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */ |
| 196 | #define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */ |
| 197 | #define XCHAL_HAVE_GRIVPEP 0 /* General Release of IVPEP */ |
| 198 | #define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */ |
| 199 | |
| 200 | #define XCHAL_HAVE_VISION 0 /* Vision P5/P6 */ |
| 201 | #define XCHAL_VISION_SIMD16 0 /* simd16 for Vision P5/P6 */ |
| 202 | #define XCHAL_VISION_TYPE 0 /* Vision P5, P6, Q6 or Q7 */ |
| 203 | #define XCHAL_VISION_QUAD_MAC_TYPE 0 /* quad_mac option on Vision P6 */ |
| 204 | #define XCHAL_HAVE_VISION_HISTOGRAM 0 /* histogram option on Vision P5/P6 */ |
| 205 | #define XCHAL_HAVE_VISION_SP_VFPU 0 /* sp_vfpu option on Vision P5/P6/Q6/Q7 */ |
| 206 | #define XCHAL_HAVE_VISION_SP_VFPU_2XFMAC 0 /* sp_vfpu_2xfma option on Vision Q7 */ |
| 207 | #define XCHAL_HAVE_VISION_HP_VFPU 0 /* hp_vfpu option on Vision P6/Q6 */ |
| 208 | #define XCHAL_HAVE_VISION_HP_VFPU_2XFMAC 0 /* hp_vfpu_2xfma option on Vision Q7 */ |
| 209 | |
| 210 | #define XCHAL_HAVE_VISIONC 0 /* Vision C */ |
| 211 | |
| 212 | #define XCHAL_HAVE_XNNE 0 /* XNNE */ |
| 213 | |
| 214 | /*---------------------------------------------------------------------- |
| 215 | MISC |
| 216 | ----------------------------------------------------------------------*/ |
| 217 | |
| 218 | #define XCHAL_NUM_LOADSTORE_UNITS 1 /* load/store units */ |
| 219 | #define XCHAL_NUM_WRITEBUFFER_ENTRIES 8 /* size of write buffer */ |
| 220 | #define XCHAL_INST_FETCH_WIDTH 4 /* instr-fetch width in bytes */ |
| 221 | #define XCHAL_DATA_WIDTH 8 /* data width in bytes */ |
| 222 | #define XCHAL_DATA_PIPE_DELAY 1 /* d-side pipeline delay |
| 223 | (1 = 5-stage, 2 = 7-stage) */ |
| 224 | #define XCHAL_CLOCK_GATING_GLOBAL 1 /* global clock gating */ |
| 225 | #define XCHAL_CLOCK_GATING_FUNCUNIT 1 /* funct. unit clock gating */ |
| 226 | /* In T1050, applies to selected core load and store instructions (see ISA): */ |
| 227 | #define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */ |
| 228 | #define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/ |
| 229 | #define XCHAL_UNALIGNED_LOAD_HW 0 /* unaligned loads work in hw */ |
| 230 | #define XCHAL_UNALIGNED_STORE_HW 0 /* unaligned stores work in hw*/ |
| 231 | |
| 232 | #define XCHAL_UNIFIED_LOADSTORE 0 |
| 233 | |
| 234 | #define XCHAL_SW_VERSION 1403000 /* sw version of this header */ |
| 235 | #define XCHAL_SW_VERSION_MAJOR 14000 /* major ver# of sw */ |
| 236 | #define XCHAL_SW_VERSION_MINOR 3 /* minor ver# of sw */ |
| 237 | #define XCHAL_SW_VERSION_MICRO 0 /* micro ver# of sw */ |
| 238 | #define XCHAL_SW_MINOR_VERSION 1403000 /* with zeroed micro */ |
| 239 | #define XCHAL_SW_MICRO_VERSION 1403000 |
| 240 | |
| 241 | #define XCHAL_CORE_ID "DE_233L_FPU" /* alphanum core name |
| 242 | (CoreID) set in the Xtensa |
| 243 | Processor Generator */ |
| 244 | |
| 245 | #define XCHAL_BUILD_UNIQUE_ID 0x000872E0 /* 22-bit sw build ID */ |
| 246 | |
| 247 | /* |
| 248 | * These definitions describe the hardware targeted by this software. |
| 249 | */ |
| 250 | #define XCHAL_HW_CONFIGID0 0xC1039286 /* ConfigID hi 32 bits*/ |
| 251 | #define XCHAL_HW_CONFIGID1 0x28C872E0 /* ConfigID lo 32 bits*/ |
| 252 | #define XCHAL_HW_VERSION_NAME "LX7.1.3" /* full version name */ |
| 253 | #define XCHAL_HW_VERSION_MAJOR 2810 /* major ver# of targeted hw */ |
| 254 | #define XCHAL_HW_VERSION_MINOR 3 /* minor ver# of targeted hw */ |
| 255 | #define XCHAL_HW_VERSION_MICRO 0 /* subdot ver# of targeted hw */ |
| 256 | #define XCHAL_HW_VERSION 281030 /* major*100+(major<2810 ? minor : minor*10+micro) */ |
| 257 | #define XCHAL_HW_REL_LX7 1 |
| 258 | #define XCHAL_HW_REL_LX7_1 1 |
| 259 | #define XCHAL_HW_REL_LX7_1_3 1 |
| 260 | #define XCHAL_HW_CONFIGID_RELIABLE 1 |
| 261 | /* If software targets a *range* of hardware versions, these are the bounds: */ |
| 262 | #define XCHAL_HW_MIN_VERSION_MAJOR 2810 /* major v of earliest tgt hw */ |
| 263 | #define XCHAL_HW_MIN_VERSION_MINOR 3 /* minor v of earliest tgt hw */ |
| 264 | #define XCHAL_HW_MIN_VERSION_MICRO 0 /* micro v of earliest tgt hw */ |
| 265 | #define XCHAL_HW_MIN_VERSION 281030 /* earliest targeted hw */ |
| 266 | #define XCHAL_HW_MAX_VERSION_MAJOR 2810 /* major v of latest tgt hw */ |
| 267 | #define XCHAL_HW_MAX_VERSION_MINOR 3 /* minor v of latest tgt hw */ |
| 268 | #define XCHAL_HW_MAX_VERSION_MICRO 0 /* micro v of latest tgt hw */ |
| 269 | #define XCHAL_HW_MAX_VERSION 281030 /* latest targeted hw */ |
| 270 | |
| 271 | /* Config is enabled for functional safety: */ |
| 272 | #define XCHAL_HAVE_FUNC_SAFETY 0 |
| 273 | |
| 274 | #define XCHAL_HAVE_APB 0 |
| 275 | |
| 276 | /*---------------------------------------------------------------------- |
| 277 | CACHE |
| 278 | ----------------------------------------------------------------------*/ |
| 279 | |
| 280 | #define XCHAL_ICACHE_LINESIZE 32 /* I-cache line size in bytes */ |
| 281 | #define XCHAL_DCACHE_LINESIZE 32 /* D-cache line size in bytes */ |
| 282 | #define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */ |
| 283 | #define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */ |
| 284 | |
| 285 | #define XCHAL_ICACHE_SIZE 16384 /* I-cache size in bytes or 0 */ |
| 286 | #define XCHAL_ICACHE_SIZE_LOG2 14 |
| 287 | #define XCHAL_DCACHE_SIZE 16384 /* D-cache size in bytes or 0 */ |
| 288 | #define XCHAL_DCACHE_SIZE_LOG2 14 |
| 289 | |
| 290 | #define XCHAL_DCACHE_IS_WRITEBACK 1 /* writeback feature */ |
| 291 | #define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */ |
| 292 | |
| 293 | #define XCHAL_HAVE_PREFETCH 0 /* PREFCTL register */ |
| 294 | #define XCHAL_HAVE_PREFETCH_L1 0 /* prefetch to L1 cache */ |
| 295 | #define XCHAL_PREFETCH_CASTOUT_LINES 0 /* dcache pref. castout bufsz */ |
| 296 | #define XCHAL_PREFETCH_ENTRIES 0 /* cache prefetch entries */ |
| 297 | #define XCHAL_PREFETCH_BLOCK_ENTRIES 0 /* prefetch block streams */ |
| 298 | #define XCHAL_HAVE_CACHE_BLOCKOPS 0 /* block prefetch for caches */ |
| 299 | #define XCHAL_HAVE_CME_DOWNGRADES 0 |
| 300 | #define XCHAL_HAVE_ICACHE_TEST 1 /* Icache test instructions */ |
| 301 | #define XCHAL_HAVE_DCACHE_TEST 1 /* Dcache test instructions */ |
| 302 | #define XCHAL_HAVE_ICACHE_DYN_WAYS 0 /* Icache dynamic way support */ |
| 303 | #define XCHAL_HAVE_DCACHE_DYN_WAYS 0 /* Dcache dynamic way support */ |
| 304 | #define XCHAL_HAVE_ICACHE_DYN_ENABLE 0 /* Icache enabled via MEMCTL */ |
| 305 | #define XCHAL_HAVE_DCACHE_DYN_ENABLE 0 /* Dcache enabled via MEMCTL */ |
| 306 | |
| 307 | #define XCHAL_L1SCACHE_SIZE 0 |
| 308 | #define XCHAL_L1SCACHE_SIZE_LOG2 0 |
| 309 | #define XCHAL_L1SCACHE_WAYS 1 |
| 310 | #define XCHAL_L1SCACHE_WAYS_LOG2 0 |
| 311 | #define XCHAL_L1SCACHE_ACCESS_SIZE 0 |
| 312 | #define XCHAL_L1SCACHE_BANKS 1 |
| 313 | |
| 314 | #define XCHAL_HAVE_L2 0 /* NX L2 cache controller */ |
| 315 | |
| 316 | /* Number of cores in cluster */ |
| 317 | #if XCHAL_HAVE_L2 |
| 318 | #define XCHAL_NUM_CORES_IN_CLUSTER XCHAL_L2CC_NUM_CORES_LOG2 |
| 319 | #else |
| 320 | #define XCHAL_NUM_CORES_IN_CLUSTER 0 |
| 321 | #endif |
| 322 | |
| 323 | /* PRID_ID macros are for internal use only ... subject to removal */ |
| 324 | #define PRID_ID_SHIFT 0 |
| 325 | #define PRID_ID_BITS 4 |
| 326 | #define PRID_ID_MASK 0x0000000F |
| 327 | |
| 328 | /* This one is a form of caching, though not architecturally visible: */ |
| 329 | #define XCHAL_HAVE_BRANCH_PREDICTION 0 /* branch [target] prediction */ |
| 330 | |
| 331 | |
| 332 | |
| 333 | |
| 334 | /**************************************************************************** |
| 335 | Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code |
| 336 | ****************************************************************************/ |
| 337 | |
| 338 | |
| 339 | #ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY |
| 340 | |
| 341 | /*---------------------------------------------------------------------- |
| 342 | CACHE |
| 343 | ----------------------------------------------------------------------*/ |
| 344 | |
| 345 | #define XCHAL_HAVE_PIF 1 /* any outbound bus present */ |
| 346 | |
| 347 | #define XCHAL_HAVE_AXI 0 /* AXI bus */ |
| 348 | #define XCHAL_HAVE_AXI_ECC 0 /* ECC on AXI bus */ |
| 349 | #define XCHAL_HAVE_ACELITE 0 /* ACELite bus */ |
| 350 | |
| 351 | #define XCHAL_HAVE_PIF_WR_RESP 0 /* pif write response */ |
| 352 | #define XCHAL_HAVE_PIF_REQ_ATTR 0 /* pif attribute */ |
| 353 | |
| 354 | /* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */ |
| 355 | |
| 356 | /* Number of cache sets in log2(lines per way): */ |
| 357 | #define XCHAL_ICACHE_SETWIDTH 7 |
| 358 | #define XCHAL_DCACHE_SETWIDTH 7 |
| 359 | |
| 360 | /* Cache set associativity (number of ways): */ |
| 361 | #define XCHAL_ICACHE_WAYS 4 |
| 362 | #define XCHAL_ICACHE_WAYS_LOG2 2 |
| 363 | #define XCHAL_DCACHE_WAYS 4 |
| 364 | #define XCHAL_DCACHE_WAYS_LOG2 2 |
| 365 | |
| 366 | /* Cache features: */ |
| 367 | #define XCHAL_ICACHE_LINE_LOCKABLE 1 |
| 368 | #define XCHAL_DCACHE_LINE_LOCKABLE 1 |
| 369 | #define XCHAL_ICACHE_ECC_PARITY 0 |
| 370 | #define XCHAL_DCACHE_ECC_PARITY 0 |
| 371 | #define XCHAL_ICACHE_ECC_WIDTH 4 |
| 372 | #define XCHAL_DCACHE_ECC_WIDTH 1 |
| 373 | |
| 374 | /* Cache access size in bytes (affects operation of SICW instruction): */ |
| 375 | #define XCHAL_ICACHE_ACCESS_SIZE 4 |
| 376 | #define XCHAL_DCACHE_ACCESS_SIZE 8 |
| 377 | |
| 378 | #define XCHAL_DCACHE_BANKS 1 /* number of banks */ |
| 379 | |
| 380 | /* The number of Cache lines associated with a single cache tag */ |
| 381 | #define XCHAL_DCACHE_LINES_PER_TAG_LOG2 0 |
| 382 | |
| 383 | /* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */ |
| 384 | #define XCHAL_CA_BITS 4 |
| 385 | |
| 386 | |
| 387 | /*---------------------------------------------------------------------- |
| 388 | INTERNAL I/D RAM/ROMs and XLMI |
| 389 | ----------------------------------------------------------------------*/ |
| 390 | #define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */ |
| 391 | #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */ |
| 392 | #define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */ |
| 393 | #define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */ |
| 394 | #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/ |
| 395 | #define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */ |
| 396 | #define XCHAL_HAVE_IRAMCFG 0 /* IRAMxCFG register present */ |
| 397 | #define XCHAL_HAVE_DRAMCFG 0 /* DRAMxCFG register present */ |
| 398 | |
| 399 | |
| 400 | #define XCHAL_HAVE_IDMA 0 |
| 401 | |
| 402 | |
| 403 | #define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/ |
| 404 | |
| 405 | /*---------------------------------------------------------------------- |
| 406 | INTERRUPTS and TIMERS |
| 407 | ----------------------------------------------------------------------*/ |
| 408 | |
| 409 | #define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */ |
| 410 | #define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */ |
| 411 | #define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */ |
| 412 | #define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */ |
| 413 | #define XCHAL_NUM_INTERRUPTS 22 /* number of interrupts */ |
| 414 | #define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */ |
| 415 | #define XCHAL_NUM_EXTINTERRUPTS 17 /* num of external interrupts */ |
| 416 | #define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels |
| 417 | (not including level zero) */ |
| 418 | |
| 419 | |
| 420 | #define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */ |
| 421 | #define XCHAL_EXCM_LEVEL 3 /* level masked by PS.EXCM */ |
| 422 | /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */ |
| 423 | |
| 424 | /* Masks of interrupts at each interrupt level: */ |
| 425 | #define XCHAL_INTLEVEL1_MASK 0x001F80FF |
| 426 | #define XCHAL_INTLEVEL2_MASK 0x00000100 |
| 427 | #define XCHAL_INTLEVEL3_MASK 0x00200E00 |
| 428 | #define XCHAL_INTLEVEL4_MASK 0x00001000 |
| 429 | #define XCHAL_INTLEVEL5_MASK 0x00002000 |
| 430 | #define XCHAL_INTLEVEL6_MASK 0x00000000 |
| 431 | #define XCHAL_INTLEVEL7_MASK 0x00004000 |
| 432 | |
| 433 | /* Masks of interrupts at each range 1..n of interrupt levels: */ |
| 434 | #define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x001F80FF |
| 435 | #define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x001F81FF |
| 436 | #define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x003F8FFF |
| 437 | #define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x003F9FFF |
| 438 | #define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x003FBFFF |
| 439 | #define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x003FBFFF |
| 440 | #define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x003FFFFF |
| 441 | |
| 442 | /* Level of each interrupt: */ |
| 443 | #define XCHAL_INT0_LEVEL 1 |
| 444 | #define XCHAL_INT1_LEVEL 1 |
| 445 | #define XCHAL_INT2_LEVEL 1 |
| 446 | #define XCHAL_INT3_LEVEL 1 |
| 447 | #define XCHAL_INT4_LEVEL 1 |
| 448 | #define XCHAL_INT5_LEVEL 1 |
| 449 | #define XCHAL_INT6_LEVEL 1 |
| 450 | #define XCHAL_INT7_LEVEL 1 |
| 451 | #define XCHAL_INT8_LEVEL 2 |
| 452 | #define XCHAL_INT9_LEVEL 3 |
| 453 | #define XCHAL_INT10_LEVEL 3 |
| 454 | #define XCHAL_INT11_LEVEL 3 |
| 455 | #define XCHAL_INT12_LEVEL 4 |
| 456 | #define XCHAL_INT13_LEVEL 5 |
| 457 | #define XCHAL_INT14_LEVEL 7 |
| 458 | #define XCHAL_INT15_LEVEL 1 |
| 459 | #define XCHAL_INT16_LEVEL 1 |
| 460 | #define XCHAL_INT17_LEVEL 1 |
| 461 | #define XCHAL_INT18_LEVEL 1 |
| 462 | #define XCHAL_INT19_LEVEL 1 |
| 463 | #define XCHAL_INT20_LEVEL 1 |
| 464 | #define XCHAL_INT21_LEVEL 3 |
| 465 | #define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */ |
| 466 | #define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */ |
| 467 | #define XCHAL_NMILEVEL 7 /* NMI "level" (for use with |
| 468 | EXCSAVE/EPS/EPC_n, RFI n) */ |
| 469 | |
| 470 | /* Type of each interrupt: */ |
| 471 | #define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL |
| 472 | #define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL |
| 473 | #define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL |
| 474 | #define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL |
| 475 | #define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL |
| 476 | #define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL |
| 477 | #define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER |
| 478 | #define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE |
| 479 | #define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL |
| 480 | #define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL |
| 481 | #define XCHAL_INT10_TYPE XTHAL_INTTYPE_TIMER |
| 482 | #define XCHAL_INT11_TYPE XTHAL_INTTYPE_SOFTWARE |
| 483 | #define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL |
| 484 | #define XCHAL_INT13_TYPE XTHAL_INTTYPE_TIMER |
| 485 | #define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI |
| 486 | #define XCHAL_INT15_TYPE XTHAL_INTTYPE_EXTERN_EDGE |
| 487 | #define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_EDGE |
| 488 | #define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_EDGE |
| 489 | #define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_EDGE |
| 490 | #define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_EDGE |
| 491 | #define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_EDGE |
| 492 | #define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_EDGE |
| 493 | |
| 494 | /* Masks of interrupts for each type of interrupt: */ |
| 495 | #define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFC00000 |
| 496 | #define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x0000133F |
| 497 | #define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x003F8000 |
| 498 | #define XCHAL_INTTYPE_MASK_NMI 0x00004000 |
| 499 | #define XCHAL_INTTYPE_MASK_SOFTWARE 0x00000880 |
| 500 | #define XCHAL_INTTYPE_MASK_TIMER 0x00002440 |
| 501 | #define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000 |
| 502 | #define XCHAL_INTTYPE_MASK_DBG_REQUEST 0x00000000 |
| 503 | #define XCHAL_INTTYPE_MASK_BREAKIN 0x00000000 |
| 504 | #define XCHAL_INTTYPE_MASK_TRAX 0x00000000 |
| 505 | #define XCHAL_INTTYPE_MASK_PROFILING 0x00000000 |
| 506 | #define XCHAL_INTTYPE_MASK_IDMA_DONE 0x00000000 |
| 507 | #define XCHAL_INTTYPE_MASK_IDMA_ERR 0x00000000 |
| 508 | #define XCHAL_INTTYPE_MASK_GS_ERR 0x00000000 |
| 509 | #define XCHAL_INTTYPE_MASK_L2_ERR 0x00000000 |
| 510 | #define XCHAL_INTTYPE_MASK_L2_STATUS 0x00000000 |
| 511 | #define XCHAL_INTTYPE_MASK_COR_ECC_ERR 0x00000000 |
| 512 | |
| 513 | /* Interrupt numbers assigned to specific interrupt sources: */ |
| 514 | #define XCHAL_TIMER0_INTERRUPT 6 /* CCOMPARE0 */ |
| 515 | #define XCHAL_TIMER1_INTERRUPT 10 /* CCOMPARE1 */ |
| 516 | #define XCHAL_TIMER2_INTERRUPT 13 /* CCOMPARE2 */ |
| 517 | #define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED |
| 518 | #define XCHAL_NMI_INTERRUPT 14 /* non-maskable interrupt */ |
| 519 | |
| 520 | /* Interrupt numbers for levels at which only one interrupt is configured: */ |
| 521 | #define XCHAL_INTLEVEL2_NUM 8 |
| 522 | #define XCHAL_INTLEVEL4_NUM 12 |
| 523 | #define XCHAL_INTLEVEL5_NUM 13 |
| 524 | #define XCHAL_INTLEVEL7_NUM 14 |
| 525 | /* (There are many interrupts each at level(s) 1, 3.) */ |
| 526 | |
| 527 | |
| 528 | /* |
| 529 | * External interrupt mapping. |
| 530 | * These macros describe how Xtensa processor interrupt numbers |
| 531 | * (as numbered internally, eg. in INTERRUPT and INTENABLE registers) |
| 532 | * map to external BInterrupt<n> pins, for those interrupts |
| 533 | * configured as external (level-triggered, edge-triggered, or NMI). |
| 534 | * See the Xtensa processor databook for more details. |
| 535 | */ |
| 536 | |
| 537 | /* Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number: */ |
| 538 | #define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */ |
| 539 | #define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */ |
| 540 | #define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */ |
| 541 | #define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */ |
| 542 | #define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */ |
| 543 | #define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */ |
| 544 | #define XCHAL_EXTINT6_NUM 8 /* (intlevel 2) */ |
| 545 | #define XCHAL_EXTINT7_NUM 9 /* (intlevel 3) */ |
| 546 | #define XCHAL_EXTINT8_NUM 12 /* (intlevel 4) */ |
| 547 | #define XCHAL_EXTINT9_NUM 14 /* (intlevel 7) */ |
| 548 | #define XCHAL_EXTINT10_NUM 15 /* (intlevel 1) */ |
| 549 | #define XCHAL_EXTINT11_NUM 16 /* (intlevel 1) */ |
| 550 | #define XCHAL_EXTINT12_NUM 17 /* (intlevel 1) */ |
| 551 | #define XCHAL_EXTINT13_NUM 18 /* (intlevel 1) */ |
| 552 | #define XCHAL_EXTINT14_NUM 19 /* (intlevel 1) */ |
| 553 | #define XCHAL_EXTINT15_NUM 20 /* (intlevel 1) */ |
| 554 | #define XCHAL_EXTINT16_NUM 21 /* (intlevel 3) */ |
| 555 | /* EXTERNAL BInterrupt pin numbers mapped to each core interrupt number: */ |
| 556 | #define XCHAL_INT0_EXTNUM 0 /* (intlevel 1) */ |
| 557 | #define XCHAL_INT1_EXTNUM 1 /* (intlevel 1) */ |
| 558 | #define XCHAL_INT2_EXTNUM 2 /* (intlevel 1) */ |
| 559 | #define XCHAL_INT3_EXTNUM 3 /* (intlevel 1) */ |
| 560 | #define XCHAL_INT4_EXTNUM 4 /* (intlevel 1) */ |
| 561 | #define XCHAL_INT5_EXTNUM 5 /* (intlevel 1) */ |
| 562 | #define XCHAL_INT8_EXTNUM 6 /* (intlevel 2) */ |
| 563 | #define XCHAL_INT9_EXTNUM 7 /* (intlevel 3) */ |
| 564 | #define XCHAL_INT12_EXTNUM 8 /* (intlevel 4) */ |
| 565 | #define XCHAL_INT14_EXTNUM 9 /* (intlevel 7) */ |
| 566 | #define XCHAL_INT15_EXTNUM 10 /* (intlevel 1) */ |
| 567 | #define XCHAL_INT16_EXTNUM 11 /* (intlevel 1) */ |
| 568 | #define XCHAL_INT17_EXTNUM 12 /* (intlevel 1) */ |
| 569 | #define XCHAL_INT18_EXTNUM 13 /* (intlevel 1) */ |
| 570 | #define XCHAL_INT19_EXTNUM 14 /* (intlevel 1) */ |
| 571 | #define XCHAL_INT20_EXTNUM 15 /* (intlevel 1) */ |
| 572 | #define XCHAL_INT21_EXTNUM 16 /* (intlevel 3) */ |
| 573 | |
| 574 | #define XCHAL_HAVE_ISB 0 /* No ISB */ |
| 575 | #define XCHAL_ISB_VADDR 0 /* N/A */ |
| 576 | #define XCHAL_HAVE_ITB 0 /* No ITB */ |
| 577 | #define XCHAL_ITB_VADDR 0 /* N/A */ |
| 578 | |
| 579 | #define XCHAL_HAVE_KSL 0 /* Kernel Stack Limit */ |
| 580 | #define XCHAL_HAVE_ISL 0 /* Interrupt Stack Limit */ |
| 581 | #define XCHAL_HAVE_PSL 0 /* Pageable Stack Limit */ |
| 582 | |
| 583 | |
| 584 | /*---------------------------------------------------------------------- |
| 585 | EXCEPTIONS and VECTORS |
| 586 | ----------------------------------------------------------------------*/ |
| 587 | |
| 588 | #define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture |
| 589 | number: 1 == XEA1 (until T1050) |
| 590 | 2 == XEA2 (T1040 onwards) |
| 591 | 3 == XEA3 (LX8/NX/SX onwards) |
| 592 | 0 == XEAX (extern) or TX */ |
| 593 | #define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */ |
| 594 | #define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */ |
| 595 | #define XCHAL_HAVE_XEA3 0 /* Exception Architecture 3 */ |
| 596 | #define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */ |
| 597 | #define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */ |
| 598 | #define XCHAL_HAVE_IMPRECISE_EXCEPTIONS 0 /* imprecise exception option */ |
| 599 | #define XCHAL_EXCCAUSE_NUM 64 /* Number of exceptions */ |
| 600 | #define XCHAL_HAVE_HALT 0 /* halt architecture option */ |
| 601 | #define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */ |
| 602 | #define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */ |
| 603 | #define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */ |
| 604 | #define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */ |
| 605 | #define XCHAL_VECBASE_RESET_VADDR 0x00002000 /* VECBASE reset value */ |
| 606 | #define XCHAL_VECBASE_RESET_PADDR 0x00002000 |
| 607 | #define XCHAL_RESET_VECBASE_OVERLAP 0 /* UNUSED */ |
| 608 | |
| 609 | #define XCHAL_RESET_VECTOR0_VADDR 0xFE000000 |
| 610 | #define XCHAL_RESET_VECTOR0_PADDR 0xFE000000 |
| 611 | #define XCHAL_RESET_VECTOR1_VADDR 0x00001000 |
| 612 | #define XCHAL_RESET_VECTOR1_PADDR 0x00001000 |
| 613 | #define XCHAL_RESET_VECTOR_VADDR XCHAL_RESET_VECTOR0_VADDR |
| 614 | #define XCHAL_RESET_VECTOR_PADDR XCHAL_RESET_VECTOR0_PADDR |
| 615 | #define XCHAL_USER_VECOFS 0x00000340 |
| 616 | #define XCHAL_USER_VECTOR_VADDR 0x00002340 |
| 617 | #define XCHAL_USER_VECTOR_PADDR 0x00002340 |
| 618 | #define XCHAL_KERNEL_VECOFS 0x00000300 |
| 619 | #define XCHAL_KERNEL_VECTOR_VADDR 0x00002300 |
| 620 | #define XCHAL_KERNEL_VECTOR_PADDR 0x00002300 |
| 621 | #define XCHAL_DOUBLEEXC_VECOFS 0x000003C0 |
| 622 | #define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x000023C0 |
| 623 | #define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x000023C0 |
| 624 | #define XCHAL_WINDOW_OF4_VECOFS 0x00000000 |
| 625 | #define XCHAL_WINDOW_UF4_VECOFS 0x00000040 |
| 626 | #define XCHAL_WINDOW_OF8_VECOFS 0x00000080 |
| 627 | #define XCHAL_WINDOW_UF8_VECOFS 0x000000C0 |
| 628 | #define XCHAL_WINDOW_OF12_VECOFS 0x00000100 |
| 629 | #define XCHAL_WINDOW_UF12_VECOFS 0x00000140 |
| 630 | #define XCHAL_WINDOW_VECTORS_VADDR 0x00002000 |
| 631 | #define XCHAL_WINDOW_VECTORS_PADDR 0x00002000 |
| 632 | #define XCHAL_INTLEVEL2_VECOFS 0x00000180 |
| 633 | #define XCHAL_INTLEVEL2_VECTOR_VADDR 0x00002180 |
| 634 | #define XCHAL_INTLEVEL2_VECTOR_PADDR 0x00002180 |
| 635 | #define XCHAL_INTLEVEL3_VECOFS 0x000001C0 |
| 636 | #define XCHAL_INTLEVEL3_VECTOR_VADDR 0x000021C0 |
| 637 | #define XCHAL_INTLEVEL3_VECTOR_PADDR 0x000021C0 |
| 638 | #define XCHAL_INTLEVEL4_VECOFS 0x00000200 |
| 639 | #define XCHAL_INTLEVEL4_VECTOR_VADDR 0x00002200 |
| 640 | #define XCHAL_INTLEVEL4_VECTOR_PADDR 0x00002200 |
| 641 | #define XCHAL_INTLEVEL5_VECOFS 0x00000240 |
| 642 | #define XCHAL_INTLEVEL5_VECTOR_VADDR 0x00002240 |
| 643 | #define XCHAL_INTLEVEL5_VECTOR_PADDR 0x00002240 |
| 644 | #define XCHAL_INTLEVEL6_VECOFS 0x00000280 |
| 645 | #define XCHAL_INTLEVEL6_VECTOR_VADDR 0x00002280 |
| 646 | #define XCHAL_INTLEVEL6_VECTOR_PADDR 0x00002280 |
| 647 | #define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS |
| 648 | #define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR |
| 649 | #define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR |
| 650 | #define XCHAL_NMI_VECOFS 0x000002C0 |
| 651 | #define XCHAL_NMI_VECTOR_VADDR 0x000022C0 |
| 652 | #define XCHAL_NMI_VECTOR_PADDR 0x000022C0 |
| 653 | #define XCHAL_INTLEVEL7_VECOFS XCHAL_NMI_VECOFS |
| 654 | #define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR |
| 655 | #define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR |
| 656 | |
| 657 | |
| 658 | /*---------------------------------------------------------------------- |
| 659 | DEBUG MODULE |
| 660 | ----------------------------------------------------------------------*/ |
| 661 | |
| 662 | /* Misc */ |
| 663 | #define XCHAL_HAVE_DEBUG_ERI 0 /* ERI to debug module */ |
| 664 | #define XCHAL_HAVE_DEBUG_APB 0 /* APB to debug module */ |
| 665 | #define XCHAL_HAVE_DEBUG_JTAG 1 /* JTAG to debug module */ |
| 666 | |
| 667 | /* On-Chip Debug (OCD) */ |
| 668 | #define XCHAL_HAVE_OCD 1 /* OnChipDebug option */ |
| 669 | #define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */ |
| 670 | #define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ |
| 671 | #define XCHAL_HAVE_OCD_DIR_ARRAY 0 /* faster OCD option (to LX4) */ |
| 672 | #define XCHAL_HAVE_OCD_LS32DDR 1 /* L32DDR/S32DDR (faster OCD) */ |
| 673 | |
| 674 | /* TRAX (in core) */ |
| 675 | #define XCHAL_HAVE_TRAX 0 /* TRAX in debug module */ |
| 676 | #define XCHAL_TRAX_MEM_SIZE 0 /* TRAX memory size in bytes */ |
| 677 | #define XCHAL_TRAX_MEM_SHAREABLE 0 /* start/end regs; ready sig. */ |
| 678 | #define XCHAL_TRAX_ATB_WIDTH 0 /* ATB width (bits), 0=no ATB */ |
| 679 | #define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */ |
| 680 | |
| 681 | /* Perf counters */ |
| 682 | #define XCHAL_NUM_PERF_COUNTERS 0 /* performance counters */ |
| 683 | |
| 684 | |
| 685 | /*---------------------------------------------------------------------- |
| 686 | MMU |
| 687 | ----------------------------------------------------------------------*/ |
| 688 | |
| 689 | /* See core-matmap.h header file for more details. */ |
| 690 | |
| 691 | #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ |
| 692 | #define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */ |
| 693 | #define XCHAL_SPANNING_WAY 6 /* TLB spanning way number */ |
| 694 | #define XCHAL_HAVE_IDENTITY_MAP 0 /* vaddr == paddr always */ |
| 695 | #define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ |
| 696 | #define XCHAL_HAVE_MIMIC_CACHEATTR 0 /* region protection */ |
| 697 | #define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ |
| 698 | #define XCHAL_HAVE_PTP_MMU 1 /* full MMU (with page table |
| 699 | [autorefill] and protection) |
| 700 | usable for an MMU-based OS */ |
| 701 | |
| 702 | /* If none of the above last 5 are set, it's a custom TLB configuration. */ |
| 703 | #define XCHAL_ITLB_ARF_ENTRIES_LOG2 2 /* log2(autorefill way size) */ |
| 704 | #define XCHAL_DTLB_ARF_ENTRIES_LOG2 2 /* log2(autorefill way size) */ |
| 705 | |
| 706 | #define XCHAL_MMU_ASID_BITS 8 /* number of bits in ASIDs */ |
| 707 | #define XCHAL_MMU_RINGS 4 /* number of rings (1..4) */ |
| 708 | #define XCHAL_MMU_RING_BITS 2 /* num of bits in RING field */ |
| 709 | |
| 710 | /*---------------------------------------------------------------------- |
| 711 | MPU |
| 712 | ----------------------------------------------------------------------*/ |
| 713 | #define XCHAL_HAVE_MPU 0 |
| 714 | #define XCHAL_MPU_ENTRIES 0 |
| 715 | |
| 716 | #define XCHAL_MPU_ALIGN_REQ 1 /* MPU requires alignment of entries to background map */ |
| 717 | #define XCHAL_MPU_BACKGROUND_ENTRIES 0 /* number of entries in bg map*/ |
| 718 | #define XCHAL_MPU_BG_CACHEADRDIS 0 /* default CACHEADRDIS for bg */ |
| 719 | |
| 720 | #define XCHAL_MPU_ALIGN_BITS 0 |
| 721 | #define XCHAL_MPU_ALIGN 0 |
| 722 | |
| 723 | #endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */ |
| 724 | |
| 725 | |
| 726 | #endif /* XTENSA_CORE_DE233_FPU_CORE_ISA_H */ |