| 1 | /* |
| 2 | * xtensa/config/core-matmap.h -- Memory access and translation mapping |
| 3 | * parameters (CHAL) of the Xtensa processor core configuration. |
| 4 | * |
| 5 | * If you are using Xtensa Tools, see <xtensa/config/core.h> (which includes |
| 6 | * this file) for more details. |
| 7 | * |
| 8 | * In the Xtensa processor products released to date, all parameters |
| 9 | * defined in this file are derivable (at least in theory) from |
| 10 | * information contained in the core-isa.h header file. |
| 11 | * In particular, the following core configuration parameters are relevant: |
| 12 | * XCHAL_HAVE_CACHEATTR |
| 13 | * XCHAL_HAVE_MIMIC_CACHEATTR |
| 14 | * XCHAL_HAVE_XLT_CACHEATTR |
| 15 | * XCHAL_HAVE_PTP_MMU |
| 16 | * XCHAL_ITLB_ARF_ENTRIES_LOG2 |
| 17 | * XCHAL_DTLB_ARF_ENTRIES_LOG2 |
| 18 | * XCHAL_DCACHE_IS_WRITEBACK |
| 19 | * XCHAL_ICACHE_SIZE (presence of I-cache) |
| 20 | * XCHAL_DCACHE_SIZE (presence of D-cache) |
| 21 | * XCHAL_HW_VERSION_MAJOR |
| 22 | * XCHAL_HW_VERSION_MINOR |
| 23 | */ |
| 24 | |
| 25 | /* Copyright (c) 1999-2020 Tensilica Inc. |
| 26 | |
| 27 | Permission is hereby granted, free of charge, to any person obtaining |
| 28 | a copy of this software and associated documentation files (the |
| 29 | "Software"), to deal in the Software without restriction, including |
| 30 | without limitation the rights to use, copy, modify, merge, publish, |
| 31 | distribute, sublicense, and/or sell copies of the Software, and to |
| 32 | permit persons to whom the Software is furnished to do so, subject to |
| 33 | the following conditions: |
| 34 | |
| 35 | The above copyright notice and this permission notice shall be included |
| 36 | in all copies or substantial portions of the Software. |
| 37 | |
| 38 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
| 39 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 40 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
| 41 | IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY |
| 42 | CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| 43 | TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
| 44 | SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ |
| 45 | |
| 46 | #ifndef XTENSA_CONFIG_CORE_MATMAP_H |
| 47 | #define XTENSA_CONFIG_CORE_MATMAP_H |
| 48 | |
| 49 | /*---------------------------------------------------------------------- |
| 50 | CACHE (MEMORY ACCESS) ATTRIBUTES |
| 51 | ----------------------------------------------------------------------*/ |
| 52 | |
| 53 | |
| 54 | |
| 55 | /* Cache Attribute encodings -- lists of access modes for each cache attribute: */ |
| 56 | #define XCHAL_FCA_LIST XTHAL_FAM_EXCEPTION XCHAL_SEP \ |
| 57 | XTHAL_FAM_BYPASS XCHAL_SEP \ |
| 58 | XTHAL_FAM_EXCEPTION XCHAL_SEP \ |
| 59 | XTHAL_FAM_BYPASS XCHAL_SEP \ |
| 60 | XTHAL_FAM_EXCEPTION XCHAL_SEP \ |
| 61 | XTHAL_FAM_CACHED XCHAL_SEP \ |
| 62 | XTHAL_FAM_EXCEPTION XCHAL_SEP \ |
| 63 | XTHAL_FAM_CACHED XCHAL_SEP \ |
| 64 | XTHAL_FAM_EXCEPTION XCHAL_SEP \ |
| 65 | XTHAL_FAM_CACHED XCHAL_SEP \ |
| 66 | XTHAL_FAM_EXCEPTION XCHAL_SEP \ |
| 67 | XTHAL_FAM_CACHED XCHAL_SEP \ |
| 68 | XTHAL_FAM_EXCEPTION XCHAL_SEP \ |
| 69 | XTHAL_FAM_EXCEPTION XCHAL_SEP \ |
| 70 | XTHAL_FAM_EXCEPTION XCHAL_SEP \ |
| 71 | XTHAL_FAM_EXCEPTION |
| 72 | #define XCHAL_LCA_LIST XTHAL_LAM_BYPASSG XCHAL_SEP \ |
| 73 | XTHAL_LAM_BYPASSG XCHAL_SEP \ |
| 74 | XTHAL_LAM_BYPASSG XCHAL_SEP \ |
| 75 | XTHAL_LAM_BYPASSG XCHAL_SEP \ |
| 76 | XTHAL_LAM_CACHED XCHAL_SEP \ |
| 77 | XTHAL_LAM_CACHED XCHAL_SEP \ |
| 78 | XTHAL_LAM_CACHED XCHAL_SEP \ |
| 79 | XTHAL_LAM_CACHED XCHAL_SEP \ |
| 80 | XTHAL_LAM_CACHED XCHAL_SEP \ |
| 81 | XTHAL_LAM_CACHED XCHAL_SEP \ |
| 82 | XTHAL_LAM_CACHED XCHAL_SEP \ |
| 83 | XTHAL_LAM_CACHED XCHAL_SEP \ |
| 84 | XTHAL_LAM_EXCEPTION XCHAL_SEP \ |
| 85 | XTHAL_LAM_EXCEPTION XCHAL_SEP \ |
| 86 | XTHAL_LAM_EXCEPTION XCHAL_SEP \ |
| 87 | XTHAL_LAM_EXCEPTION |
| 88 | #define XCHAL_SCA_LIST XTHAL_SAM_EXCEPTION XCHAL_SEP \ |
| 89 | XTHAL_SAM_EXCEPTION XCHAL_SEP \ |
| 90 | XTHAL_SAM_BYPASS XCHAL_SEP \ |
| 91 | XTHAL_SAM_BYPASS XCHAL_SEP \ |
| 92 | XTHAL_SAM_EXCEPTION XCHAL_SEP \ |
| 93 | XTHAL_SAM_EXCEPTION XCHAL_SEP \ |
| 94 | XTHAL_SAM_WRITEBACK XCHAL_SEP \ |
| 95 | XTHAL_SAM_WRITEBACK XCHAL_SEP \ |
| 96 | XTHAL_SAM_EXCEPTION XCHAL_SEP \ |
| 97 | XTHAL_SAM_EXCEPTION XCHAL_SEP \ |
| 98 | XTHAL_SAM_WRITETHRU XCHAL_SEP \ |
| 99 | XTHAL_SAM_WRITETHRU XCHAL_SEP \ |
| 100 | XTHAL_SAM_EXCEPTION XCHAL_SEP \ |
| 101 | XTHAL_SAM_EXCEPTION XCHAL_SEP \ |
| 102 | XTHAL_SAM_EXCEPTION XCHAL_SEP \ |
| 103 | XTHAL_SAM_EXCEPTION |
| 104 | |
| 105 | #define XCHAL_CA_R (0xC0 | 0x40000000) |
| 106 | #define XCHAL_CA_RX (0xD0 | 0x40000000) |
| 107 | #define XCHAL_CA_RW (0xE0 | 0x40000000) |
| 108 | #define XCHAL_CA_RWX (0xF0 | 0x40000000) |
| 109 | |
| 110 | /* |
| 111 | * Specific encoded cache attribute values of general interest. |
| 112 | * If a specific cache mode is not available, the closest available |
| 113 | * one is returned instead (eg. writethru instead of writeback, |
| 114 | * bypass instead of writethru). |
| 115 | */ |
| 116 | #define XCHAL_CA_BYPASS 3 /* cache disabled (bypassed) mode */ |
| 117 | #define XCHAL_CA_WRITETHRU 11 /* cache enabled (write-through) mode */ |
| 118 | #define XCHAL_CA_WRITEBACK 7 /* cache enabled (write-back) mode */ |
| 119 | #define XCHAL_HAVE_CA_WRITEBACK_NOALLOC 0 /* write-back no-allocate availability */ |
| 120 | #define XCHAL_CA_WRITEBACK_NOALLOC 7 /* cache enabled (write-back no-allocate) mode */ |
| 121 | #define XCHAL_CA_BYPASS_RX 1 /* cache disabled (bypassed) mode (no write) */ |
| 122 | #define XCHAL_CA_WRITETHRU_RX 9 /* cache enabled (write-through) mode (no write) */ |
| 123 | #define XCHAL_CA_WRITEBACK_RX 5 /* cache enabled (write-back) mode (no write) */ |
| 124 | #define XCHAL_CA_WRITEBACK_NOALLOC_RX 5 /* cache enabled (write-back no-allocate) mode (no write) */ |
| 125 | #define XCHAL_CA_BYPASS_RW 2 /* cache disabled (bypassed) mode (no exec) */ |
| 126 | #define XCHAL_CA_WRITETHRU_RW 10 /* cache enabled (write-through) mode (no exec) */ |
| 127 | #define XCHAL_CA_WRITEBACK_RW 6 /* cache enabled (write-back) mode (no exec) */ |
| 128 | #define XCHAL_CA_WRITEBACK_NOALLOC_RW 6 /* cache enabled (write-back no-allocate) mode (no exec) */ |
| 129 | #define XCHAL_CA_BYPASS_R 0 /* cache disabled (bypassed) mode (no exec, no write) */ |
| 130 | #define XCHAL_CA_WRITETHRU_R 8 /* cache enabled (write-through) mode (no exec, no write) */ |
| 131 | #define XCHAL_CA_WRITEBACK_R 4 /* cache enabled (write-back) mode (no exec, no write) */ |
| 132 | #define XCHAL_CA_WRITEBACK_NOALLOC_R 4 /* cache enabled (write-back no-allocate) mode (no exec, no write) */ |
| 133 | #define XCHAL_CA_ILLEGAL 12 /* no access allowed (all cause exceptions) mode */ |
| 134 | |
| 135 | /*---------------------------------------------------------------------- |
| 136 | MMU |
| 137 | ----------------------------------------------------------------------*/ |
| 138 | |
| 139 | /* |
| 140 | * General notes on MMU parameters. |
| 141 | * |
| 142 | * Terminology: |
| 143 | * ASID = address-space ID (acts as an "extension" of virtual addresses) |
| 144 | * VPN = virtual page number |
| 145 | * PPN = physical page number |
| 146 | * CA = encoded cache attribute (access modes) |
| 147 | * TLB = translation look-aside buffer (term is stretched somewhat here) |
| 148 | * I = instruction (fetch accesses) |
| 149 | * D = data (load and store accesses) |
| 150 | * way = each TLB (ITLB and DTLB) consists of a number of "ways" |
| 151 | * that simultaneously match the virtual address of an access; |
| 152 | * a TLB successfully translates a virtual address if exactly |
| 153 | * one way matches the vaddr; if none match, it is a miss; |
| 154 | * if multiple match, one gets a "multihit" exception; |
| 155 | * each way can be independently configured in terms of number of |
| 156 | * entries, page sizes, which fields are writable or constant, etc. |
| 157 | * set = group of contiguous ways with exactly identical parameters |
| 158 | * ARF = auto-refill; hardware services a 1st-level miss by loading a PTE |
| 159 | * from the page table and storing it in one of the auto-refill ways; |
| 160 | * if this PTE load also misses, a miss exception is posted for s/w. |
| 161 | * min-wired = a "min-wired" way can be used to map a single (minimum-sized) |
| 162 | * page arbitrarily under program control; it has a single entry, |
| 163 | * is non-auto-refill (some other way(s) must be auto-refill), |
| 164 | * all its fields (VPN, PPN, ASID, CA) are all writable, and it |
| 165 | * supports the XCHAL_MMU_MIN_PTE_PAGE_SIZE page size (a current |
| 166 | * restriction is that this be the only page size it supports). |
| 167 | * |
| 168 | * TLB way entries are virtually indexed. |
| 169 | * TLB ways that support multiple page sizes: |
| 170 | * - must have all writable VPN and PPN fields; |
| 171 | * - can only use one page size at any given time (eg. setup at startup), |
| 172 | * selected by the respective ITLBCFG or DTLBCFG special register, |
| 173 | * whose bits n*4+3 .. n*4 index the list of page sizes for way n |
| 174 | * (XCHAL_xTLB_SETm_PAGESZ_LOG2_LIST for set m corresponding to way n); |
| 175 | * this list may be sparse for auto-refill ways because auto-refill |
| 176 | * ways have independent lists of supported page sizes sharing a |
| 177 | * common encoding with PTE entries; the encoding is the index into |
| 178 | * this list; unsupported sizes for a given way are zero in the list; |
| 179 | * selecting unsupported sizes results in undefine hardware behaviour; |
| 180 | * - is only possible for ways 0 thru 7 (due to ITLBCFG/DTLBCFG definition). |
| 181 | */ |
| 182 | |
| 183 | #define XCHAL_MMU_ASID_INVALID 0 /* ASID value indicating invalid address space */ |
| 184 | #define XCHAL_MMU_ASID_KERNEL 1 /* ASID value indicating kernel (ring 0) address space */ |
| 185 | #define XCHAL_MMU_SR_BITS 0 /* number of size-restriction bits supported */ |
| 186 | #define XCHAL_MMU_CA_BITS 4 /* number of bits needed to hold cache attribute encoding */ |
| 187 | #define XCHAL_MMU_MAX_PTE_PAGE_SIZE 12 /* max page size in a PTE structure (log2) */ |
| 188 | #define XCHAL_MMU_MIN_PTE_PAGE_SIZE 12 /* min page size in a PTE structure (log2) */ |
| 189 | |
| 190 | |
| 191 | /*** Instruction TLB: ***/ |
| 192 | |
| 193 | #define XCHAL_ITLB_WAY_BITS 3 /* number of bits holding the ways */ |
| 194 | #define XCHAL_ITLB_WAYS 7 /* number of ways (n-way set-associative TLB) */ |
| 195 | #define XCHAL_ITLB_ARF_WAYS 4 /* number of auto-refill ways */ |
| 196 | #define XCHAL_ITLB_SETS 7 /* number of sets (groups of ways with identical settings) */ |
| 197 | |
| 198 | /* Way set to which each way belongs: */ |
| 199 | #define XCHAL_ITLB_WAY0_SET 0 |
| 200 | #define XCHAL_ITLB_WAY1_SET 1 |
| 201 | #define XCHAL_ITLB_WAY2_SET 2 |
| 202 | #define XCHAL_ITLB_WAY3_SET 3 |
| 203 | #define XCHAL_ITLB_WAY4_SET 4 |
| 204 | #define XCHAL_ITLB_WAY5_SET 5 |
| 205 | #define XCHAL_ITLB_WAY6_SET 6 |
| 206 | |
| 207 | /* Ways sets that are used by hardware auto-refill (ARF): */ |
| 208 | #define XCHAL_ITLB_ARF_SETS 4 /* number of auto-refill sets */ |
| 209 | #define XCHAL_ITLB_ARF_SET0 0 /* index of n'th auto-refill set */ |
| 210 | #define XCHAL_ITLB_ARF_SET1 1 /* index of n'th auto-refill set */ |
| 211 | #define XCHAL_ITLB_ARF_SET2 2 /* index of n'th auto-refill set */ |
| 212 | #define XCHAL_ITLB_ARF_SET3 3 /* index of n'th auto-refill set */ |
| 213 | |
| 214 | /* Way sets that are "min-wired" (see terminology comment above): */ |
| 215 | #define XCHAL_ITLB_MINWIRED_SETS 0 /* number of "min-wired" sets */ |
| 216 | |
| 217 | |
| 218 | /* ITLB way set 0 (group of ways 0 thru 0): */ |
| 219 | #define XCHAL_ITLB_SET0_WAY 0 /* index of first way in this way set */ |
| 220 | #define XCHAL_ITLB_SET0_WAYS 1 /* number of (contiguous) ways in this way set */ |
| 221 | #define XCHAL_ITLB_SET0_ENTRIES_LOG2 2 /* log2(number of entries in this way) */ |
| 222 | #define XCHAL_ITLB_SET0_ENTRIES 4 /* number of entries in this way (always a power of 2) */ |
| 223 | #define XCHAL_ITLB_SET0_ARF 1 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */ |
| 224 | #define XCHAL_ITLB_SET0_PAGESIZES 1 /* number of supported page sizes in this way */ |
| 225 | #define XCHAL_ITLB_SET0_PAGESZ_BITS 0 /* number of bits to encode the page size */ |
| 226 | #define XCHAL_ITLB_SET0_PAGESZ_LOG2_MIN 12 /* log2(minimum supported page size) */ |
| 227 | #define XCHAL_ITLB_SET0_PAGESZ_LOG2_MAX 12 /* log2(maximum supported page size) */ |
| 228 | #define XCHAL_ITLB_SET0_PAGESZ_LOG2_LIST 12 /* list of log2(page size)s, separated by XCHAL_SEP; |
| 229 | 2^PAGESZ_BITS entries in list, unsupported entries are zero */ |
| 230 | #define XCHAL_ITLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */ |
| 231 | #define XCHAL_ITLB_SET0_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */ |
| 232 | #define XCHAL_ITLB_SET0_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */ |
| 233 | #define XCHAL_ITLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */ |
| 234 | #define XCHAL_ITLB_SET0_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */ |
| 235 | #define XCHAL_ITLB_SET0_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */ |
| 236 | #define XCHAL_ITLB_SET0_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */ |
| 237 | #define XCHAL_ITLB_SET0_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */ |
| 238 | |
| 239 | /* ITLB way set 1 (group of ways 1 thru 1): */ |
| 240 | #define XCHAL_ITLB_SET1_WAY 1 /* index of first way in this way set */ |
| 241 | #define XCHAL_ITLB_SET1_WAYS 1 /* number of (contiguous) ways in this way set */ |
| 242 | #define XCHAL_ITLB_SET1_ENTRIES_LOG2 2 /* log2(number of entries in this way) */ |
| 243 | #define XCHAL_ITLB_SET1_ENTRIES 4 /* number of entries in this way (always a power of 2) */ |
| 244 | #define XCHAL_ITLB_SET1_ARF 1 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */ |
| 245 | #define XCHAL_ITLB_SET1_PAGESIZES 1 /* number of supported page sizes in this way */ |
| 246 | #define XCHAL_ITLB_SET1_PAGESZ_BITS 0 /* number of bits to encode the page size */ |
| 247 | #define XCHAL_ITLB_SET1_PAGESZ_LOG2_MIN 12 /* log2(minimum supported page size) */ |
| 248 | #define XCHAL_ITLB_SET1_PAGESZ_LOG2_MAX 12 /* log2(maximum supported page size) */ |
| 249 | #define XCHAL_ITLB_SET1_PAGESZ_LOG2_LIST 12 /* list of log2(page size)s, separated by XCHAL_SEP; |
| 250 | 2^PAGESZ_BITS entries in list, unsupported entries are zero */ |
| 251 | #define XCHAL_ITLB_SET1_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */ |
| 252 | #define XCHAL_ITLB_SET1_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */ |
| 253 | #define XCHAL_ITLB_SET1_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */ |
| 254 | #define XCHAL_ITLB_SET1_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */ |
| 255 | #define XCHAL_ITLB_SET1_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */ |
| 256 | #define XCHAL_ITLB_SET1_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */ |
| 257 | #define XCHAL_ITLB_SET1_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */ |
| 258 | #define XCHAL_ITLB_SET1_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */ |
| 259 | |
| 260 | /* ITLB way set 2 (group of ways 2 thru 2): */ |
| 261 | #define XCHAL_ITLB_SET2_WAY 2 /* index of first way in this way set */ |
| 262 | #define XCHAL_ITLB_SET2_WAYS 1 /* number of (contiguous) ways in this way set */ |
| 263 | #define XCHAL_ITLB_SET2_ENTRIES_LOG2 2 /* log2(number of entries in this way) */ |
| 264 | #define XCHAL_ITLB_SET2_ENTRIES 4 /* number of entries in this way (always a power of 2) */ |
| 265 | #define XCHAL_ITLB_SET2_ARF 1 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */ |
| 266 | #define XCHAL_ITLB_SET2_PAGESIZES 1 /* number of supported page sizes in this way */ |
| 267 | #define XCHAL_ITLB_SET2_PAGESZ_BITS 0 /* number of bits to encode the page size */ |
| 268 | #define XCHAL_ITLB_SET2_PAGESZ_LOG2_MIN 12 /* log2(minimum supported page size) */ |
| 269 | #define XCHAL_ITLB_SET2_PAGESZ_LOG2_MAX 12 /* log2(maximum supported page size) */ |
| 270 | #define XCHAL_ITLB_SET2_PAGESZ_LOG2_LIST 12 /* list of log2(page size)s, separated by XCHAL_SEP; |
| 271 | 2^PAGESZ_BITS entries in list, unsupported entries are zero */ |
| 272 | #define XCHAL_ITLB_SET2_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */ |
| 273 | #define XCHAL_ITLB_SET2_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */ |
| 274 | #define XCHAL_ITLB_SET2_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */ |
| 275 | #define XCHAL_ITLB_SET2_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */ |
| 276 | #define XCHAL_ITLB_SET2_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */ |
| 277 | #define XCHAL_ITLB_SET2_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */ |
| 278 | #define XCHAL_ITLB_SET2_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */ |
| 279 | #define XCHAL_ITLB_SET2_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */ |
| 280 | |
| 281 | /* ITLB way set 3 (group of ways 3 thru 3): */ |
| 282 | #define XCHAL_ITLB_SET3_WAY 3 /* index of first way in this way set */ |
| 283 | #define XCHAL_ITLB_SET3_WAYS 1 /* number of (contiguous) ways in this way set */ |
| 284 | #define XCHAL_ITLB_SET3_ENTRIES_LOG2 2 /* log2(number of entries in this way) */ |
| 285 | #define XCHAL_ITLB_SET3_ENTRIES 4 /* number of entries in this way (always a power of 2) */ |
| 286 | #define XCHAL_ITLB_SET3_ARF 1 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */ |
| 287 | #define XCHAL_ITLB_SET3_PAGESIZES 1 /* number of supported page sizes in this way */ |
| 288 | #define XCHAL_ITLB_SET3_PAGESZ_BITS 0 /* number of bits to encode the page size */ |
| 289 | #define XCHAL_ITLB_SET3_PAGESZ_LOG2_MIN 12 /* log2(minimum supported page size) */ |
| 290 | #define XCHAL_ITLB_SET3_PAGESZ_LOG2_MAX 12 /* log2(maximum supported page size) */ |
| 291 | #define XCHAL_ITLB_SET3_PAGESZ_LOG2_LIST 12 /* list of log2(page size)s, separated by XCHAL_SEP; |
| 292 | 2^PAGESZ_BITS entries in list, unsupported entries are zero */ |
| 293 | #define XCHAL_ITLB_SET3_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */ |
| 294 | #define XCHAL_ITLB_SET3_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */ |
| 295 | #define XCHAL_ITLB_SET3_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */ |
| 296 | #define XCHAL_ITLB_SET3_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */ |
| 297 | #define XCHAL_ITLB_SET3_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */ |
| 298 | #define XCHAL_ITLB_SET3_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */ |
| 299 | #define XCHAL_ITLB_SET3_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */ |
| 300 | #define XCHAL_ITLB_SET3_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */ |
| 301 | |
| 302 | /* ITLB way set 4 (group of ways 4 thru 4): */ |
| 303 | #define XCHAL_ITLB_SET4_WAY 4 /* index of first way in this way set */ |
| 304 | #define XCHAL_ITLB_SET4_WAYS 1 /* number of (contiguous) ways in this way set */ |
| 305 | #define XCHAL_ITLB_SET4_ENTRIES_LOG2 2 /* log2(number of entries in this way) */ |
| 306 | #define XCHAL_ITLB_SET4_ENTRIES 4 /* number of entries in this way (always a power of 2) */ |
| 307 | #define XCHAL_ITLB_SET4_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */ |
| 308 | #define XCHAL_ITLB_SET4_PAGESIZES 4 /* number of supported page sizes in this way */ |
| 309 | #define XCHAL_ITLB_SET4_PAGESZ_BITS 2 /* number of bits to encode the page size */ |
| 310 | #define XCHAL_ITLB_SET4_PAGESZ_LOG2_MIN 20 /* log2(minimum supported page size) */ |
| 311 | #define XCHAL_ITLB_SET4_PAGESZ_LOG2_MAX 26 /* log2(maximum supported page size) */ |
| 312 | #define XCHAL_ITLB_SET4_PAGESZ_LOG2_LIST 20 XCHAL_SEP 22 XCHAL_SEP 24 XCHAL_SEP 26 /* list of log2(page size)s, separated by XCHAL_SEP; |
| 313 | 2^PAGESZ_BITS entries in list, unsupported entries are zero */ |
| 314 | #define XCHAL_ITLB_SET4_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */ |
| 315 | #define XCHAL_ITLB_SET4_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */ |
| 316 | #define XCHAL_ITLB_SET4_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */ |
| 317 | #define XCHAL_ITLB_SET4_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */ |
| 318 | #define XCHAL_ITLB_SET4_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */ |
| 319 | #define XCHAL_ITLB_SET4_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */ |
| 320 | #define XCHAL_ITLB_SET4_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */ |
| 321 | #define XCHAL_ITLB_SET4_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */ |
| 322 | |
| 323 | /* ITLB way set 5 (group of ways 5 thru 5): */ |
| 324 | #define XCHAL_ITLB_SET5_WAY 5 /* index of first way in this way set */ |
| 325 | #define XCHAL_ITLB_SET5_WAYS 1 /* number of (contiguous) ways in this way set */ |
| 326 | #define XCHAL_ITLB_SET5_ENTRIES_LOG2 2 /* log2(number of entries in this way) */ |
| 327 | #define XCHAL_ITLB_SET5_ENTRIES 4 /* number of entries in this way (always a power of 2) */ |
| 328 | #define XCHAL_ITLB_SET5_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */ |
| 329 | #define XCHAL_ITLB_SET5_PAGESIZES 2 /* number of supported page sizes in this way */ |
| 330 | #define XCHAL_ITLB_SET5_PAGESZ_BITS 1 /* number of bits to encode the page size */ |
| 331 | #define XCHAL_ITLB_SET5_PAGESZ_LOG2_MIN 27 /* log2(minimum supported page size) */ |
| 332 | #define XCHAL_ITLB_SET5_PAGESZ_LOG2_MAX 28 /* log2(maximum supported page size) */ |
| 333 | #define XCHAL_ITLB_SET5_PAGESZ_LOG2_LIST 27 XCHAL_SEP 28 /* list of log2(page size)s, separated by XCHAL_SEP; |
| 334 | 2^PAGESZ_BITS entries in list, unsupported entries are zero */ |
| 335 | #define XCHAL_ITLB_SET5_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */ |
| 336 | #define XCHAL_ITLB_SET5_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */ |
| 337 | #define XCHAL_ITLB_SET5_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */ |
| 338 | #define XCHAL_ITLB_SET5_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */ |
| 339 | #define XCHAL_ITLB_SET5_ASID_RESET 1 /* 1 if ASID reset values defined (and all writable); 0 otherwise */ |
| 340 | #define XCHAL_ITLB_SET5_VPN_RESET 1 /* 1 if VPN reset values defined (and all writable); 0 otherwise */ |
| 341 | #define XCHAL_ITLB_SET5_PPN_RESET 1 /* 1 if PPN reset values defined (and all writable); 0 otherwise */ |
| 342 | #define XCHAL_ITLB_SET5_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */ |
| 343 | /* Reset ASID values for each entry of ITLB way set 5 (because SET5_ASID_RESET is non-zero): */ |
| 344 | #define XCHAL_ITLB_SET5_E0_ASID_RESET 0x00 |
| 345 | #define XCHAL_ITLB_SET5_E1_ASID_RESET 0x00 |
| 346 | #define XCHAL_ITLB_SET5_E2_ASID_RESET 0x00 |
| 347 | #define XCHAL_ITLB_SET5_E3_ASID_RESET 0x00 |
| 348 | /* Reset VPN values for each entry of ITLB way set 5 (because SET5_VPN_RESET is non-zero): */ |
| 349 | #define XCHAL_ITLB_SET5_E0_VPN_RESET 0x00000000 |
| 350 | #define XCHAL_ITLB_SET5_E1_VPN_RESET 0x00000000 |
| 351 | #define XCHAL_ITLB_SET5_E2_VPN_RESET 0x00000000 |
| 352 | #define XCHAL_ITLB_SET5_E3_VPN_RESET 0x00000000 |
| 353 | /* Reset PPN values for each entry of ITLB way set 5 (because SET5_PPN_RESET is non-zero): */ |
| 354 | #define XCHAL_ITLB_SET5_E0_PPN_RESET 0x00000000 |
| 355 | #define XCHAL_ITLB_SET5_E1_PPN_RESET 0x00000000 |
| 356 | #define XCHAL_ITLB_SET5_E2_PPN_RESET 0x00000000 |
| 357 | #define XCHAL_ITLB_SET5_E3_PPN_RESET 0x00000000 |
| 358 | |
| 359 | /* ITLB way set 6 (group of ways 6 thru 6): */ |
| 360 | #define XCHAL_ITLB_SET6_WAY 6 /* index of first way in this way set */ |
| 361 | #define XCHAL_ITLB_SET6_WAYS 1 /* number of (contiguous) ways in this way set */ |
| 362 | #define XCHAL_ITLB_SET6_ENTRIES_LOG2 3 /* log2(number of entries in this way) */ |
| 363 | #define XCHAL_ITLB_SET6_ENTRIES 8 /* number of entries in this way (always a power of 2) */ |
| 364 | #define XCHAL_ITLB_SET6_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */ |
| 365 | #define XCHAL_ITLB_SET6_PAGESIZES 2 /* number of supported page sizes in this way */ |
| 366 | #define XCHAL_ITLB_SET6_PAGESZ_BITS 1 /* number of bits to encode the page size */ |
| 367 | #define XCHAL_ITLB_SET6_PAGESZ_LOG2_MIN 28 /* log2(minimum supported page size) */ |
| 368 | #define XCHAL_ITLB_SET6_PAGESZ_LOG2_MAX 29 /* log2(maximum supported page size) */ |
| 369 | #define XCHAL_ITLB_SET6_PAGESZ_LOG2_LIST 29 XCHAL_SEP 28 /* list of log2(page size)s, separated by XCHAL_SEP; |
| 370 | 2^PAGESZ_BITS entries in list, unsupported entries are zero */ |
| 371 | #define XCHAL_ITLB_SET6_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */ |
| 372 | #define XCHAL_ITLB_SET6_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */ |
| 373 | #define XCHAL_ITLB_SET6_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */ |
| 374 | #define XCHAL_ITLB_SET6_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */ |
| 375 | #define XCHAL_ITLB_SET6_ASID_RESET 1 /* 1 if ASID reset values defined (and all writable); 0 otherwise */ |
| 376 | #define XCHAL_ITLB_SET6_VPN_RESET 1 /* 1 if VPN reset values defined (and all writable); 0 otherwise */ |
| 377 | #define XCHAL_ITLB_SET6_PPN_RESET 1 /* 1 if PPN reset values defined (and all writable); 0 otherwise */ |
| 378 | #define XCHAL_ITLB_SET6_CA_RESET 1 /* 1 if CA reset values defined (and all writable); 0 otherwise */ |
| 379 | /* Reset ASID values for each entry of ITLB way set 6 (because SET6_ASID_RESET is non-zero): */ |
| 380 | #define XCHAL_ITLB_SET6_E0_ASID_RESET 0x01 |
| 381 | #define XCHAL_ITLB_SET6_E1_ASID_RESET 0x01 |
| 382 | #define XCHAL_ITLB_SET6_E2_ASID_RESET 0x01 |
| 383 | #define XCHAL_ITLB_SET6_E3_ASID_RESET 0x01 |
| 384 | #define XCHAL_ITLB_SET6_E4_ASID_RESET 0x01 |
| 385 | #define XCHAL_ITLB_SET6_E5_ASID_RESET 0x01 |
| 386 | #define XCHAL_ITLB_SET6_E6_ASID_RESET 0x01 |
| 387 | #define XCHAL_ITLB_SET6_E7_ASID_RESET 0x01 |
| 388 | /* Reset VPN values for each entry of ITLB way set 6 (because SET6_VPN_RESET is non-zero): */ |
| 389 | #define XCHAL_ITLB_SET6_E0_VPN_RESET 0x00000000 |
| 390 | #define XCHAL_ITLB_SET6_E1_VPN_RESET 0x20000000 |
| 391 | #define XCHAL_ITLB_SET6_E2_VPN_RESET 0x40000000 |
| 392 | #define XCHAL_ITLB_SET6_E3_VPN_RESET 0x60000000 |
| 393 | #define XCHAL_ITLB_SET6_E4_VPN_RESET 0x80000000 |
| 394 | #define XCHAL_ITLB_SET6_E5_VPN_RESET 0xA0000000 |
| 395 | #define XCHAL_ITLB_SET6_E6_VPN_RESET 0xC0000000 |
| 396 | #define XCHAL_ITLB_SET6_E7_VPN_RESET 0xE0000000 |
| 397 | /* Reset PPN values for each entry of ITLB way set 6 (because SET6_PPN_RESET is non-zero): */ |
| 398 | #define XCHAL_ITLB_SET6_E0_PPN_RESET 0x00000000 |
| 399 | #define XCHAL_ITLB_SET6_E1_PPN_RESET 0x20000000 |
| 400 | #define XCHAL_ITLB_SET6_E2_PPN_RESET 0x40000000 |
| 401 | #define XCHAL_ITLB_SET6_E3_PPN_RESET 0x60000000 |
| 402 | #define XCHAL_ITLB_SET6_E4_PPN_RESET 0x80000000 |
| 403 | #define XCHAL_ITLB_SET6_E5_PPN_RESET 0xA0000000 |
| 404 | #define XCHAL_ITLB_SET6_E6_PPN_RESET 0xC0000000 |
| 405 | #define XCHAL_ITLB_SET6_E7_PPN_RESET 0xE0000000 |
| 406 | /* Reset CA values for each entry of ITLB way set 6 (because SET6_CA_RESET is non-zero): */ |
| 407 | #define XCHAL_ITLB_SET6_E0_CA_RESET 0x03 |
| 408 | #define XCHAL_ITLB_SET6_E1_CA_RESET 0x03 |
| 409 | #define XCHAL_ITLB_SET6_E2_CA_RESET 0x03 |
| 410 | #define XCHAL_ITLB_SET6_E3_CA_RESET 0x03 |
| 411 | #define XCHAL_ITLB_SET6_E4_CA_RESET 0x03 |
| 412 | #define XCHAL_ITLB_SET6_E5_CA_RESET 0x03 |
| 413 | #define XCHAL_ITLB_SET6_E6_CA_RESET 0x03 |
| 414 | #define XCHAL_ITLB_SET6_E7_CA_RESET 0x03 |
| 415 | |
| 416 | |
| 417 | /*** Data TLB: ***/ |
| 418 | |
| 419 | #define XCHAL_DTLB_WAY_BITS 4 /* number of bits holding the ways */ |
| 420 | #define XCHAL_DTLB_WAYS 10 /* number of ways (n-way set-associative TLB) */ |
| 421 | #define XCHAL_DTLB_ARF_WAYS 4 /* number of auto-refill ways */ |
| 422 | #define XCHAL_DTLB_SETS 10 /* number of sets (groups of ways with identical settings) */ |
| 423 | |
| 424 | /* Way set to which each way belongs: */ |
| 425 | #define XCHAL_DTLB_WAY0_SET 0 |
| 426 | #define XCHAL_DTLB_WAY1_SET 1 |
| 427 | #define XCHAL_DTLB_WAY2_SET 2 |
| 428 | #define XCHAL_DTLB_WAY3_SET 3 |
| 429 | #define XCHAL_DTLB_WAY4_SET 4 |
| 430 | #define XCHAL_DTLB_WAY5_SET 5 |
| 431 | #define XCHAL_DTLB_WAY6_SET 6 |
| 432 | #define XCHAL_DTLB_WAY7_SET 7 |
| 433 | #define XCHAL_DTLB_WAY8_SET 8 |
| 434 | #define XCHAL_DTLB_WAY9_SET 9 |
| 435 | |
| 436 | /* Ways sets that are used by hardware auto-refill (ARF): */ |
| 437 | #define XCHAL_DTLB_ARF_SETS 4 /* number of auto-refill sets */ |
| 438 | #define XCHAL_DTLB_ARF_SET0 0 /* index of n'th auto-refill set */ |
| 439 | #define XCHAL_DTLB_ARF_SET1 1 /* index of n'th auto-refill set */ |
| 440 | #define XCHAL_DTLB_ARF_SET2 2 /* index of n'th auto-refill set */ |
| 441 | #define XCHAL_DTLB_ARF_SET3 3 /* index of n'th auto-refill set */ |
| 442 | |
| 443 | /* Way sets that are "min-wired" (see terminology comment above): */ |
| 444 | #define XCHAL_DTLB_MINWIRED_SETS 3 /* number of "min-wired" sets */ |
| 445 | #define XCHAL_DTLB_MINWIRED_SET0 7 /* index of n'th "min-wired" set */ |
| 446 | #define XCHAL_DTLB_MINWIRED_SET1 8 /* index of n'th "min-wired" set */ |
| 447 | #define XCHAL_DTLB_MINWIRED_SET2 9 /* index of n'th "min-wired" set */ |
| 448 | |
| 449 | |
| 450 | /* DTLB way set 0 (group of ways 0 thru 0): */ |
| 451 | #define XCHAL_DTLB_SET0_WAY 0 /* index of first way in this way set */ |
| 452 | #define XCHAL_DTLB_SET0_WAYS 1 /* number of (contiguous) ways in this way set */ |
| 453 | #define XCHAL_DTLB_SET0_ENTRIES_LOG2 2 /* log2(number of entries in this way) */ |
| 454 | #define XCHAL_DTLB_SET0_ENTRIES 4 /* number of entries in this way (always a power of 2) */ |
| 455 | #define XCHAL_DTLB_SET0_ARF 1 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */ |
| 456 | #define XCHAL_DTLB_SET0_PAGESIZES 1 /* number of supported page sizes in this way */ |
| 457 | #define XCHAL_DTLB_SET0_PAGESZ_BITS 0 /* number of bits to encode the page size */ |
| 458 | #define XCHAL_DTLB_SET0_PAGESZ_LOG2_MIN 12 /* log2(minimum supported page size) */ |
| 459 | #define XCHAL_DTLB_SET0_PAGESZ_LOG2_MAX 12 /* log2(maximum supported page size) */ |
| 460 | #define XCHAL_DTLB_SET0_PAGESZ_LOG2_LIST 12 /* list of log2(page size)s, separated by XCHAL_SEP; |
| 461 | 2^PAGESZ_BITS entries in list, unsupported entries are zero */ |
| 462 | #define XCHAL_DTLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */ |
| 463 | #define XCHAL_DTLB_SET0_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */ |
| 464 | #define XCHAL_DTLB_SET0_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */ |
| 465 | #define XCHAL_DTLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */ |
| 466 | #define XCHAL_DTLB_SET0_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */ |
| 467 | #define XCHAL_DTLB_SET0_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */ |
| 468 | #define XCHAL_DTLB_SET0_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */ |
| 469 | #define XCHAL_DTLB_SET0_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */ |
| 470 | |
| 471 | /* DTLB way set 1 (group of ways 1 thru 1): */ |
| 472 | #define XCHAL_DTLB_SET1_WAY 1 /* index of first way in this way set */ |
| 473 | #define XCHAL_DTLB_SET1_WAYS 1 /* number of (contiguous) ways in this way set */ |
| 474 | #define XCHAL_DTLB_SET1_ENTRIES_LOG2 2 /* log2(number of entries in this way) */ |
| 475 | #define XCHAL_DTLB_SET1_ENTRIES 4 /* number of entries in this way (always a power of 2) */ |
| 476 | #define XCHAL_DTLB_SET1_ARF 1 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */ |
| 477 | #define XCHAL_DTLB_SET1_PAGESIZES 1 /* number of supported page sizes in this way */ |
| 478 | #define XCHAL_DTLB_SET1_PAGESZ_BITS 0 /* number of bits to encode the page size */ |
| 479 | #define XCHAL_DTLB_SET1_PAGESZ_LOG2_MIN 12 /* log2(minimum supported page size) */ |
| 480 | #define XCHAL_DTLB_SET1_PAGESZ_LOG2_MAX 12 /* log2(maximum supported page size) */ |
| 481 | #define XCHAL_DTLB_SET1_PAGESZ_LOG2_LIST 12 /* list of log2(page size)s, separated by XCHAL_SEP; |
| 482 | 2^PAGESZ_BITS entries in list, unsupported entries are zero */ |
| 483 | #define XCHAL_DTLB_SET1_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */ |
| 484 | #define XCHAL_DTLB_SET1_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */ |
| 485 | #define XCHAL_DTLB_SET1_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */ |
| 486 | #define XCHAL_DTLB_SET1_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */ |
| 487 | #define XCHAL_DTLB_SET1_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */ |
| 488 | #define XCHAL_DTLB_SET1_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */ |
| 489 | #define XCHAL_DTLB_SET1_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */ |
| 490 | #define XCHAL_DTLB_SET1_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */ |
| 491 | |
| 492 | /* DTLB way set 2 (group of ways 2 thru 2): */ |
| 493 | #define XCHAL_DTLB_SET2_WAY 2 /* index of first way in this way set */ |
| 494 | #define XCHAL_DTLB_SET2_WAYS 1 /* number of (contiguous) ways in this way set */ |
| 495 | #define XCHAL_DTLB_SET2_ENTRIES_LOG2 2 /* log2(number of entries in this way) */ |
| 496 | #define XCHAL_DTLB_SET2_ENTRIES 4 /* number of entries in this way (always a power of 2) */ |
| 497 | #define XCHAL_DTLB_SET2_ARF 1 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */ |
| 498 | #define XCHAL_DTLB_SET2_PAGESIZES 1 /* number of supported page sizes in this way */ |
| 499 | #define XCHAL_DTLB_SET2_PAGESZ_BITS 0 /* number of bits to encode the page size */ |
| 500 | #define XCHAL_DTLB_SET2_PAGESZ_LOG2_MIN 12 /* log2(minimum supported page size) */ |
| 501 | #define XCHAL_DTLB_SET2_PAGESZ_LOG2_MAX 12 /* log2(maximum supported page size) */ |
| 502 | #define XCHAL_DTLB_SET2_PAGESZ_LOG2_LIST 12 /* list of log2(page size)s, separated by XCHAL_SEP; |
| 503 | 2^PAGESZ_BITS entries in list, unsupported entries are zero */ |
| 504 | #define XCHAL_DTLB_SET2_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */ |
| 505 | #define XCHAL_DTLB_SET2_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */ |
| 506 | #define XCHAL_DTLB_SET2_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */ |
| 507 | #define XCHAL_DTLB_SET2_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */ |
| 508 | #define XCHAL_DTLB_SET2_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */ |
| 509 | #define XCHAL_DTLB_SET2_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */ |
| 510 | #define XCHAL_DTLB_SET2_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */ |
| 511 | #define XCHAL_DTLB_SET2_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */ |
| 512 | |
| 513 | /* DTLB way set 3 (group of ways 3 thru 3): */ |
| 514 | #define XCHAL_DTLB_SET3_WAY 3 /* index of first way in this way set */ |
| 515 | #define XCHAL_DTLB_SET3_WAYS 1 /* number of (contiguous) ways in this way set */ |
| 516 | #define XCHAL_DTLB_SET3_ENTRIES_LOG2 2 /* log2(number of entries in this way) */ |
| 517 | #define XCHAL_DTLB_SET3_ENTRIES 4 /* number of entries in this way (always a power of 2) */ |
| 518 | #define XCHAL_DTLB_SET3_ARF 1 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */ |
| 519 | #define XCHAL_DTLB_SET3_PAGESIZES 1 /* number of supported page sizes in this way */ |
| 520 | #define XCHAL_DTLB_SET3_PAGESZ_BITS 0 /* number of bits to encode the page size */ |
| 521 | #define XCHAL_DTLB_SET3_PAGESZ_LOG2_MIN 12 /* log2(minimum supported page size) */ |
| 522 | #define XCHAL_DTLB_SET3_PAGESZ_LOG2_MAX 12 /* log2(maximum supported page size) */ |
| 523 | #define XCHAL_DTLB_SET3_PAGESZ_LOG2_LIST 12 /* list of log2(page size)s, separated by XCHAL_SEP; |
| 524 | 2^PAGESZ_BITS entries in list, unsupported entries are zero */ |
| 525 | #define XCHAL_DTLB_SET3_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */ |
| 526 | #define XCHAL_DTLB_SET3_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */ |
| 527 | #define XCHAL_DTLB_SET3_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */ |
| 528 | #define XCHAL_DTLB_SET3_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */ |
| 529 | #define XCHAL_DTLB_SET3_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */ |
| 530 | #define XCHAL_DTLB_SET3_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */ |
| 531 | #define XCHAL_DTLB_SET3_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */ |
| 532 | #define XCHAL_DTLB_SET3_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */ |
| 533 | |
| 534 | /* DTLB way set 4 (group of ways 4 thru 4): */ |
| 535 | #define XCHAL_DTLB_SET4_WAY 4 /* index of first way in this way set */ |
| 536 | #define XCHAL_DTLB_SET4_WAYS 1 /* number of (contiguous) ways in this way set */ |
| 537 | #define XCHAL_DTLB_SET4_ENTRIES_LOG2 2 /* log2(number of entries in this way) */ |
| 538 | #define XCHAL_DTLB_SET4_ENTRIES 4 /* number of entries in this way (always a power of 2) */ |
| 539 | #define XCHAL_DTLB_SET4_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */ |
| 540 | #define XCHAL_DTLB_SET4_PAGESIZES 4 /* number of supported page sizes in this way */ |
| 541 | #define XCHAL_DTLB_SET4_PAGESZ_BITS 2 /* number of bits to encode the page size */ |
| 542 | #define XCHAL_DTLB_SET4_PAGESZ_LOG2_MIN 20 /* log2(minimum supported page size) */ |
| 543 | #define XCHAL_DTLB_SET4_PAGESZ_LOG2_MAX 26 /* log2(maximum supported page size) */ |
| 544 | #define XCHAL_DTLB_SET4_PAGESZ_LOG2_LIST 20 XCHAL_SEP 22 XCHAL_SEP 24 XCHAL_SEP 26 /* list of log2(page size)s, separated by XCHAL_SEP; |
| 545 | 2^PAGESZ_BITS entries in list, unsupported entries are zero */ |
| 546 | #define XCHAL_DTLB_SET4_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */ |
| 547 | #define XCHAL_DTLB_SET4_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */ |
| 548 | #define XCHAL_DTLB_SET4_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */ |
| 549 | #define XCHAL_DTLB_SET4_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */ |
| 550 | #define XCHAL_DTLB_SET4_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */ |
| 551 | #define XCHAL_DTLB_SET4_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */ |
| 552 | #define XCHAL_DTLB_SET4_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */ |
| 553 | #define XCHAL_DTLB_SET4_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */ |
| 554 | |
| 555 | /* DTLB way set 5 (group of ways 5 thru 5): */ |
| 556 | #define XCHAL_DTLB_SET5_WAY 5 /* index of first way in this way set */ |
| 557 | #define XCHAL_DTLB_SET5_WAYS 1 /* number of (contiguous) ways in this way set */ |
| 558 | #define XCHAL_DTLB_SET5_ENTRIES_LOG2 2 /* log2(number of entries in this way) */ |
| 559 | #define XCHAL_DTLB_SET5_ENTRIES 4 /* number of entries in this way (always a power of 2) */ |
| 560 | #define XCHAL_DTLB_SET5_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */ |
| 561 | #define XCHAL_DTLB_SET5_PAGESIZES 2 /* number of supported page sizes in this way */ |
| 562 | #define XCHAL_DTLB_SET5_PAGESZ_BITS 1 /* number of bits to encode the page size */ |
| 563 | #define XCHAL_DTLB_SET5_PAGESZ_LOG2_MIN 27 /* log2(minimum supported page size) */ |
| 564 | #define XCHAL_DTLB_SET5_PAGESZ_LOG2_MAX 28 /* log2(maximum supported page size) */ |
| 565 | #define XCHAL_DTLB_SET5_PAGESZ_LOG2_LIST 27 XCHAL_SEP 28 /* list of log2(page size)s, separated by XCHAL_SEP; |
| 566 | 2^PAGESZ_BITS entries in list, unsupported entries are zero */ |
| 567 | #define XCHAL_DTLB_SET5_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */ |
| 568 | #define XCHAL_DTLB_SET5_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */ |
| 569 | #define XCHAL_DTLB_SET5_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */ |
| 570 | #define XCHAL_DTLB_SET5_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */ |
| 571 | #define XCHAL_DTLB_SET5_ASID_RESET 1 /* 1 if ASID reset values defined (and all writable); 0 otherwise */ |
| 572 | #define XCHAL_DTLB_SET5_VPN_RESET 1 /* 1 if VPN reset values defined (and all writable); 0 otherwise */ |
| 573 | #define XCHAL_DTLB_SET5_PPN_RESET 1 /* 1 if PPN reset values defined (and all writable); 0 otherwise */ |
| 574 | #define XCHAL_DTLB_SET5_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */ |
| 575 | /* Reset ASID values for each entry of DTLB way set 5 (because SET5_ASID_RESET is non-zero): */ |
| 576 | #define XCHAL_DTLB_SET5_E0_ASID_RESET 0x00 |
| 577 | #define XCHAL_DTLB_SET5_E1_ASID_RESET 0x00 |
| 578 | #define XCHAL_DTLB_SET5_E2_ASID_RESET 0x00 |
| 579 | #define XCHAL_DTLB_SET5_E3_ASID_RESET 0x00 |
| 580 | /* Reset VPN values for each entry of DTLB way set 5 (because SET5_VPN_RESET is non-zero): */ |
| 581 | #define XCHAL_DTLB_SET5_E0_VPN_RESET 0x00000000 |
| 582 | #define XCHAL_DTLB_SET5_E1_VPN_RESET 0x00000000 |
| 583 | #define XCHAL_DTLB_SET5_E2_VPN_RESET 0x00000000 |
| 584 | #define XCHAL_DTLB_SET5_E3_VPN_RESET 0x00000000 |
| 585 | /* Reset PPN values for each entry of DTLB way set 5 (because SET5_PPN_RESET is non-zero): */ |
| 586 | #define XCHAL_DTLB_SET5_E0_PPN_RESET 0x00000000 |
| 587 | #define XCHAL_DTLB_SET5_E1_PPN_RESET 0x00000000 |
| 588 | #define XCHAL_DTLB_SET5_E2_PPN_RESET 0x00000000 |
| 589 | #define XCHAL_DTLB_SET5_E3_PPN_RESET 0x00000000 |
| 590 | |
| 591 | /* DTLB way set 6 (group of ways 6 thru 6): */ |
| 592 | #define XCHAL_DTLB_SET6_WAY 6 /* index of first way in this way set */ |
| 593 | #define XCHAL_DTLB_SET6_WAYS 1 /* number of (contiguous) ways in this way set */ |
| 594 | #define XCHAL_DTLB_SET6_ENTRIES_LOG2 3 /* log2(number of entries in this way) */ |
| 595 | #define XCHAL_DTLB_SET6_ENTRIES 8 /* number of entries in this way (always a power of 2) */ |
| 596 | #define XCHAL_DTLB_SET6_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */ |
| 597 | #define XCHAL_DTLB_SET6_PAGESIZES 2 /* number of supported page sizes in this way */ |
| 598 | #define XCHAL_DTLB_SET6_PAGESZ_BITS 1 /* number of bits to encode the page size */ |
| 599 | #define XCHAL_DTLB_SET6_PAGESZ_LOG2_MIN 28 /* log2(minimum supported page size) */ |
| 600 | #define XCHAL_DTLB_SET6_PAGESZ_LOG2_MAX 29 /* log2(maximum supported page size) */ |
| 601 | #define XCHAL_DTLB_SET6_PAGESZ_LOG2_LIST 29 XCHAL_SEP 28 /* list of log2(page size)s, separated by XCHAL_SEP; |
| 602 | 2^PAGESZ_BITS entries in list, unsupported entries are zero */ |
| 603 | #define XCHAL_DTLB_SET6_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */ |
| 604 | #define XCHAL_DTLB_SET6_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */ |
| 605 | #define XCHAL_DTLB_SET6_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */ |
| 606 | #define XCHAL_DTLB_SET6_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */ |
| 607 | #define XCHAL_DTLB_SET6_ASID_RESET 1 /* 1 if ASID reset values defined (and all writable); 0 otherwise */ |
| 608 | #define XCHAL_DTLB_SET6_VPN_RESET 1 /* 1 if VPN reset values defined (and all writable); 0 otherwise */ |
| 609 | #define XCHAL_DTLB_SET6_PPN_RESET 1 /* 1 if PPN reset values defined (and all writable); 0 otherwise */ |
| 610 | #define XCHAL_DTLB_SET6_CA_RESET 1 /* 1 if CA reset values defined (and all writable); 0 otherwise */ |
| 611 | /* Reset ASID values for each entry of DTLB way set 6 (because SET6_ASID_RESET is non-zero): */ |
| 612 | #define XCHAL_DTLB_SET6_E0_ASID_RESET 0x01 |
| 613 | #define XCHAL_DTLB_SET6_E1_ASID_RESET 0x01 |
| 614 | #define XCHAL_DTLB_SET6_E2_ASID_RESET 0x01 |
| 615 | #define XCHAL_DTLB_SET6_E3_ASID_RESET 0x01 |
| 616 | #define XCHAL_DTLB_SET6_E4_ASID_RESET 0x01 |
| 617 | #define XCHAL_DTLB_SET6_E5_ASID_RESET 0x01 |
| 618 | #define XCHAL_DTLB_SET6_E6_ASID_RESET 0x01 |
| 619 | #define XCHAL_DTLB_SET6_E7_ASID_RESET 0x01 |
| 620 | /* Reset VPN values for each entry of DTLB way set 6 (because SET6_VPN_RESET is non-zero): */ |
| 621 | #define XCHAL_DTLB_SET6_E0_VPN_RESET 0x00000000 |
| 622 | #define XCHAL_DTLB_SET6_E1_VPN_RESET 0x20000000 |
| 623 | #define XCHAL_DTLB_SET6_E2_VPN_RESET 0x40000000 |
| 624 | #define XCHAL_DTLB_SET6_E3_VPN_RESET 0x60000000 |
| 625 | #define XCHAL_DTLB_SET6_E4_VPN_RESET 0x80000000 |
| 626 | #define XCHAL_DTLB_SET6_E5_VPN_RESET 0xA0000000 |
| 627 | #define XCHAL_DTLB_SET6_E6_VPN_RESET 0xC0000000 |
| 628 | #define XCHAL_DTLB_SET6_E7_VPN_RESET 0xE0000000 |
| 629 | /* Reset PPN values for each entry of DTLB way set 6 (because SET6_PPN_RESET is non-zero): */ |
| 630 | #define XCHAL_DTLB_SET6_E0_PPN_RESET 0x00000000 |
| 631 | #define XCHAL_DTLB_SET6_E1_PPN_RESET 0x20000000 |
| 632 | #define XCHAL_DTLB_SET6_E2_PPN_RESET 0x40000000 |
| 633 | #define XCHAL_DTLB_SET6_E3_PPN_RESET 0x60000000 |
| 634 | #define XCHAL_DTLB_SET6_E4_PPN_RESET 0x80000000 |
| 635 | #define XCHAL_DTLB_SET6_E5_PPN_RESET 0xA0000000 |
| 636 | #define XCHAL_DTLB_SET6_E6_PPN_RESET 0xC0000000 |
| 637 | #define XCHAL_DTLB_SET6_E7_PPN_RESET 0xE0000000 |
| 638 | /* Reset CA values for each entry of DTLB way set 6 (because SET6_CA_RESET is non-zero): */ |
| 639 | #define XCHAL_DTLB_SET6_E0_CA_RESET 0x03 |
| 640 | #define XCHAL_DTLB_SET6_E1_CA_RESET 0x03 |
| 641 | #define XCHAL_DTLB_SET6_E2_CA_RESET 0x03 |
| 642 | #define XCHAL_DTLB_SET6_E3_CA_RESET 0x03 |
| 643 | #define XCHAL_DTLB_SET6_E4_CA_RESET 0x03 |
| 644 | #define XCHAL_DTLB_SET6_E5_CA_RESET 0x03 |
| 645 | #define XCHAL_DTLB_SET6_E6_CA_RESET 0x03 |
| 646 | #define XCHAL_DTLB_SET6_E7_CA_RESET 0x03 |
| 647 | |
| 648 | /* DTLB way set 7 (group of ways 7 thru 7): */ |
| 649 | #define XCHAL_DTLB_SET7_WAY 7 /* index of first way in this way set */ |
| 650 | #define XCHAL_DTLB_SET7_WAYS 1 /* number of (contiguous) ways in this way set */ |
| 651 | #define XCHAL_DTLB_SET7_ENTRIES_LOG2 0 /* log2(number of entries in this way) */ |
| 652 | #define XCHAL_DTLB_SET7_ENTRIES 1 /* number of entries in this way (always a power of 2) */ |
| 653 | #define XCHAL_DTLB_SET7_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */ |
| 654 | #define XCHAL_DTLB_SET7_PAGESIZES 1 /* number of supported page sizes in this way */ |
| 655 | #define XCHAL_DTLB_SET7_PAGESZ_BITS 0 /* number of bits to encode the page size */ |
| 656 | #define XCHAL_DTLB_SET7_PAGESZ_LOG2_MIN 12 /* log2(minimum supported page size) */ |
| 657 | #define XCHAL_DTLB_SET7_PAGESZ_LOG2_MAX 12 /* log2(maximum supported page size) */ |
| 658 | #define XCHAL_DTLB_SET7_PAGESZ_LOG2_LIST 12 /* list of log2(page size)s, separated by XCHAL_SEP; |
| 659 | 2^PAGESZ_BITS entries in list, unsupported entries are zero */ |
| 660 | #define XCHAL_DTLB_SET7_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */ |
| 661 | #define XCHAL_DTLB_SET7_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */ |
| 662 | #define XCHAL_DTLB_SET7_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */ |
| 663 | #define XCHAL_DTLB_SET7_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */ |
| 664 | #define XCHAL_DTLB_SET7_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */ |
| 665 | #define XCHAL_DTLB_SET7_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */ |
| 666 | #define XCHAL_DTLB_SET7_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */ |
| 667 | #define XCHAL_DTLB_SET7_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */ |
| 668 | |
| 669 | /* DTLB way set 8 (group of ways 8 thru 8): */ |
| 670 | #define XCHAL_DTLB_SET8_WAY 8 /* index of first way in this way set */ |
| 671 | #define XCHAL_DTLB_SET8_WAYS 1 /* number of (contiguous) ways in this way set */ |
| 672 | #define XCHAL_DTLB_SET8_ENTRIES_LOG2 0 /* log2(number of entries in this way) */ |
| 673 | #define XCHAL_DTLB_SET8_ENTRIES 1 /* number of entries in this way (always a power of 2) */ |
| 674 | #define XCHAL_DTLB_SET8_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */ |
| 675 | #define XCHAL_DTLB_SET8_PAGESIZES 1 /* number of supported page sizes in this way */ |
| 676 | #define XCHAL_DTLB_SET8_PAGESZ_BITS 0 /* number of bits to encode the page size */ |
| 677 | #define XCHAL_DTLB_SET8_PAGESZ_LOG2_MIN 12 /* log2(minimum supported page size) */ |
| 678 | #define XCHAL_DTLB_SET8_PAGESZ_LOG2_MAX 12 /* log2(maximum supported page size) */ |
| 679 | #define XCHAL_DTLB_SET8_PAGESZ_LOG2_LIST 12 /* list of log2(page size)s, separated by XCHAL_SEP; |
| 680 | 2^PAGESZ_BITS entries in list, unsupported entries are zero */ |
| 681 | #define XCHAL_DTLB_SET8_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */ |
| 682 | #define XCHAL_DTLB_SET8_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */ |
| 683 | #define XCHAL_DTLB_SET8_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */ |
| 684 | #define XCHAL_DTLB_SET8_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */ |
| 685 | #define XCHAL_DTLB_SET8_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */ |
| 686 | #define XCHAL_DTLB_SET8_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */ |
| 687 | #define XCHAL_DTLB_SET8_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */ |
| 688 | #define XCHAL_DTLB_SET8_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */ |
| 689 | |
| 690 | /* DTLB way set 9 (group of ways 9 thru 9): */ |
| 691 | #define XCHAL_DTLB_SET9_WAY 9 /* index of first way in this way set */ |
| 692 | #define XCHAL_DTLB_SET9_WAYS 1 /* number of (contiguous) ways in this way set */ |
| 693 | #define XCHAL_DTLB_SET9_ENTRIES_LOG2 0 /* log2(number of entries in this way) */ |
| 694 | #define XCHAL_DTLB_SET9_ENTRIES 1 /* number of entries in this way (always a power of 2) */ |
| 695 | #define XCHAL_DTLB_SET9_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */ |
| 696 | #define XCHAL_DTLB_SET9_PAGESIZES 1 /* number of supported page sizes in this way */ |
| 697 | #define XCHAL_DTLB_SET9_PAGESZ_BITS 0 /* number of bits to encode the page size */ |
| 698 | #define XCHAL_DTLB_SET9_PAGESZ_LOG2_MIN 12 /* log2(minimum supported page size) */ |
| 699 | #define XCHAL_DTLB_SET9_PAGESZ_LOG2_MAX 12 /* log2(maximum supported page size) */ |
| 700 | #define XCHAL_DTLB_SET9_PAGESZ_LOG2_LIST 12 /* list of log2(page size)s, separated by XCHAL_SEP; |
| 701 | 2^PAGESZ_BITS entries in list, unsupported entries are zero */ |
| 702 | #define XCHAL_DTLB_SET9_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */ |
| 703 | #define XCHAL_DTLB_SET9_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */ |
| 704 | #define XCHAL_DTLB_SET9_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */ |
| 705 | #define XCHAL_DTLB_SET9_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */ |
| 706 | #define XCHAL_DTLB_SET9_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */ |
| 707 | #define XCHAL_DTLB_SET9_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */ |
| 708 | #define XCHAL_DTLB_SET9_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */ |
| 709 | #define XCHAL_DTLB_SET9_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */ |
| 710 | |
| 711 | |
| 712 | |
| 713 | |
| 714 | #endif /* XTENSA_CONFIG_CORE_MATMAP_H */ |
| 715 |