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1 /* Xtensa configuration-specific ISA information.
2
3 Copyright (c) 2003-2020 Tensilica Inc.
4
5 Permission is hereby granted, free of charge, to any person obtaining
6 a copy of this software and associated documentation files (the
7 "Software"), to deal in the Software without restriction, including
8 without limitation the rights to use, copy, modify, merge, publish,
9 distribute, sublicense, and/or sell copies of the Software, and to
10 permit persons to whom the Software is furnished to do so, subject to
11 the following conditions:
12
13 The above copyright notice and this permission notice shall be included
14 in all copies or substantial portions of the Software.
15
16 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
17 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
19 IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
20 CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
23
24 #include "xtensa-isa.h"
25 #include "xtensa-isa-internal.h"
26
27
28 /* Sysregs. */
29
30 static xtensa_sysreg_internal sysregs[] = {
31 { "LBEG", 0, 0 },
32 { "LEND", 1, 0 },
33 { "LCOUNT", 2, 0 },
34 { "BR", 4, 0 },
35 { "ACCLO", 16, 0 },
36 { "ACCHI", 17, 0 },
37 { "M0", 32, 0 },
38 { "M1", 33, 0 },
39 { "M2", 34, 0 },
40 { "M3", 35, 0 },
41 { "PTEVADDR", 83, 0 },
42 { "MMID", 89, 0 },
43 { "DDR", 104, 0 },
44 { "CONFIGID0", 176, 0 },
45 { "CONFIGID1", 208, 0 },
46 { "INTERRUPT", 226, 0 },
47 { "INTCLEAR", 227, 0 },
48 { "CCOUNT", 234, 0 },
49 { "PRID", 235, 0 },
50 { "ICOUNT", 236, 0 },
51 { "CCOMPARE0", 240, 0 },
52 { "CCOMPARE1", 241, 0 },
53 { "CCOMPARE2", 242, 0 },
54 { "VECBASE", 231, 0 },
55 { "EPC1", 177, 0 },
56 { "EPC2", 178, 0 },
57 { "EPC3", 179, 0 },
58 { "EPC4", 180, 0 },
59 { "EPC5", 181, 0 },
60 { "EPC6", 182, 0 },
61 { "EPC7", 183, 0 },
62 { "EXCSAVE1", 209, 0 },
63 { "EXCSAVE2", 210, 0 },
64 { "EXCSAVE3", 211, 0 },
65 { "EXCSAVE4", 212, 0 },
66 { "EXCSAVE5", 213, 0 },
67 { "EXCSAVE6", 214, 0 },
68 { "EXCSAVE7", 215, 0 },
69 { "EPS2", 194, 0 },
70 { "EPS3", 195, 0 },
71 { "EPS4", 196, 0 },
72 { "EPS5", 197, 0 },
73 { "EPS6", 198, 0 },
74 { "EPS7", 199, 0 },
75 { "EXCCAUSE", 232, 0 },
76 { "DEPC", 192, 0 },
77 { "EXCVADDR", 238, 0 },
78 { "WINDOWBASE", 72, 0 },
79 { "WINDOWSTART", 73, 0 },
80 { "SAR", 3, 0 },
81 { "PS", 230, 0 },
82 { "MISC0", 244, 0 },
83 { "MISC1", 245, 0 },
84 { "INTENABLE", 228, 0 },
85 { "DBREAKA0", 144, 0 },
86 { "DBREAKC0", 160, 0 },
87 { "DBREAKA1", 145, 0 },
88 { "DBREAKC1", 161, 0 },
89 { "IBREAKA0", 128, 0 },
90 { "IBREAKA1", 129, 0 },
91 { "IBREAKENABLE", 96, 0 },
92 { "ICOUNTLEVEL", 237, 0 },
93 { "DEBUGCAUSE", 233, 0 },
94 { "RASID", 90, 0 },
95 { "ITLBCFG", 91, 0 },
96 { "DTLBCFG", 92, 0 },
97 { "CPENABLE", 224, 0 },
98 { "SCOMPARE1", 12, 0 },
99 { "ATOMCTL", 99, 0 },
100 { "ERACCESS", 95, 0 },
101 { "THREADPTR", 231, 1 },
102 { "FCR", 232, 1 },
103 { "FSR", 233, 1 },
104 { "EXPSTATE", 230, 1 }
105 };
106
107 #define NUM_SYSREGS 74
108 #define MAX_SPECIAL_REG 245
109 #define MAX_USER_REG 233
110
111
112 /* Processor states. */
113
114 static xtensa_state_internal states[] = {
115 { "LCOUNT", 32, 0 },
116 { "PC", 32, 0 },
117 { "ICOUNT", 32, 0 },
118 { "DDR", 32, 0 },
119 { "INTERRUPT", 22, 0 },
120 { "CCOUNT", 32, 0 },
121 { "XTSYNC", 1, 0 },
122 { "VECBASE", 22, 0 },
123 { "EPC1", 32, 0 },
124 { "EPC2", 32, 0 },
125 { "EPC3", 32, 0 },
126 { "EPC4", 32, 0 },
127 { "EPC5", 32, 0 },
128 { "EPC6", 32, 0 },
129 { "EPC7", 32, 0 },
130 { "EXCSAVE1", 32, 0 },
131 { "EXCSAVE2", 32, 0 },
132 { "EXCSAVE3", 32, 0 },
133 { "EXCSAVE4", 32, 0 },
134 { "EXCSAVE5", 32, 0 },
135 { "EXCSAVE6", 32, 0 },
136 { "EXCSAVE7", 32, 0 },
137 { "EPS2", 15, 0 },
138 { "EPS3", 15, 0 },
139 { "EPS4", 15, 0 },
140 { "EPS5", 15, 0 },
141 { "EPS6", 15, 0 },
142 { "EPS7", 15, 0 },
143 { "EXCCAUSE", 6, 0 },
144 { "PSINTLEVEL", 4, 0 },
145 { "PSUM", 1, 0 },
146 { "PSWOE", 1, 0 },
147 { "PSRING", 2, 0 },
148 { "PSEXCM", 1, 0 },
149 { "DEPC", 32, 0 },
150 { "EXCVADDR", 32, 0 },
151 { "WindowBase", 3, 0 },
152 { "WindowStart", 8, 0 },
153 { "PSCALLINC", 2, 0 },
154 { "PSOWB", 4, 0 },
155 { "LBEG", 32, 0 },
156 { "LEND", 32, 0 },
157 { "SAR", 6, 0 },
158 { "THREADPTR", 32, 0 },
159 { "MISC0", 32, 0 },
160 { "MISC1", 32, 0 },
161 { "ACC", 40, 0 },
162 { "InOCDMode", 1, 0 },
163 { "INTENABLE", 22, 0 },
164 { "DBREAKA0", 32, 0 },
165 { "DBREAKC0", 8, 0 },
166 { "DBREAKA1", 32, 0 },
167 { "DBREAKC1", 8, 0 },
168 { "IBREAKA0", 32, 0 },
169 { "IBREAKA1", 32, 0 },
170 { "IBREAKENABLE", 2, 0 },
171 { "ICOUNTLEVEL", 4, 0 },
172 { "DEBUGCAUSE", 6, 0 },
173 { "DBNUM", 4, 0 },
174 { "CCOMPARE0", 32, 0 },
175 { "CCOMPARE1", 32, 0 },
176 { "CCOMPARE2", 32, 0 },
177 { "ASID3", 8, 0 },
178 { "ASID2", 8, 0 },
179 { "ASID1", 8, 0 },
180 { "INSTPGSZID6", 1, 0 },
181 { "INSTPGSZID5", 1, 0 },
182 { "INSTPGSZID4", 2, 0 },
183 { "DATAPGSZID6", 1, 0 },
184 { "DATAPGSZID5", 1, 0 },
185 { "DATAPGSZID4", 2, 0 },
186 { "PTBASE", 10, 0 },
187 { "CPENABLE", 8, 0 },
188 { "SCOMPARE1", 32, 0 },
189 { "ATOMCTL", 6, 0 },
190 { "ERACCESS", 16, 0 },
191 { "RoundMode", 2, 0 },
192 { "InvalidEnable", 1, 0 },
193 { "DivZeroEnable", 1, 0 },
194 { "OverflowEnable", 1, 0 },
195 { "UnderflowEnable", 1, 0 },
196 { "InexactEnable", 1, 0 },
197 { "InvalidFlag", 1, XTENSA_STATE_IS_SHARED_OR },
198 { "DivZeroFlag", 1, XTENSA_STATE_IS_SHARED_OR },
199 { "OverflowFlag", 1, XTENSA_STATE_IS_SHARED_OR },
200 { "UnderflowFlag", 1, XTENSA_STATE_IS_SHARED_OR },
201 { "InexactFlag", 1, XTENSA_STATE_IS_SHARED_OR },
202 { "FPreserved20", 20, 0 },
203 { "FPreserved20a", 20, 0 },
204 { "FPreserved5", 5, 0 },
205 { "FPreserved7", 7, 0 },
206 { "EXPSTATE", 32, XTENSA_STATE_IS_EXPORTED }
207 };
208
209 #define NUM_STATES 92
210
211 enum xtensa_state_id {
212 STATE_LCOUNT,
213 STATE_PC,
214 STATE_ICOUNT,
215 STATE_DDR,
216 STATE_INTERRUPT,
217 STATE_CCOUNT,
218 STATE_XTSYNC,
219 STATE_VECBASE,
220 STATE_EPC1,
221 STATE_EPC2,
222 STATE_EPC3,
223 STATE_EPC4,
224 STATE_EPC5,
225 STATE_EPC6,
226 STATE_EPC7,
227 STATE_EXCSAVE1,
228 STATE_EXCSAVE2,
229 STATE_EXCSAVE3,
230 STATE_EXCSAVE4,
231 STATE_EXCSAVE5,
232 STATE_EXCSAVE6,
233 STATE_EXCSAVE7,
234 STATE_EPS2,
235 STATE_EPS3,
236 STATE_EPS4,
237 STATE_EPS5,
238 STATE_EPS6,
239 STATE_EPS7,
240 STATE_EXCCAUSE,
241 STATE_PSINTLEVEL,
242 STATE_PSUM,
243 STATE_PSWOE,
244 STATE_PSRING,
245 STATE_PSEXCM,
246 STATE_DEPC,
247 STATE_EXCVADDR,
248 STATE_WindowBase,
249 STATE_WindowStart,
250 STATE_PSCALLINC,
251 STATE_PSOWB,
252 STATE_LBEG,
253 STATE_LEND,
254 STATE_SAR,
255 STATE_THREADPTR,
256 STATE_MISC0,
257 STATE_MISC1,
258 STATE_ACC,
259 STATE_InOCDMode,
260 STATE_INTENABLE,
261 STATE_DBREAKA0,
262 STATE_DBREAKC0,
263 STATE_DBREAKA1,
264 STATE_DBREAKC1,
265 STATE_IBREAKA0,
266 STATE_IBREAKA1,
267 STATE_IBREAKENABLE,
268 STATE_ICOUNTLEVEL,
269 STATE_DEBUGCAUSE,
270 STATE_DBNUM,
271 STATE_CCOMPARE0,
272 STATE_CCOMPARE1,
273 STATE_CCOMPARE2,
274 STATE_ASID3,
275 STATE_ASID2,
276 STATE_ASID1,
277 STATE_INSTPGSZID6,
278 STATE_INSTPGSZID5,
279 STATE_INSTPGSZID4,
280 STATE_DATAPGSZID6,
281 STATE_DATAPGSZID5,
282 STATE_DATAPGSZID4,
283 STATE_PTBASE,
284 STATE_CPENABLE,
285 STATE_SCOMPARE1,
286 STATE_ATOMCTL,
287 STATE_ERACCESS,
288 STATE_RoundMode,
289 STATE_InvalidEnable,
290 STATE_DivZeroEnable,
291 STATE_OverflowEnable,
292 STATE_UnderflowEnable,
293 STATE_InexactEnable,
294 STATE_InvalidFlag,
295 STATE_DivZeroFlag,
296 STATE_OverflowFlag,
297 STATE_UnderflowFlag,
298 STATE_InexactFlag,
299 STATE_FPreserved20,
300 STATE_FPreserved20a,
301 STATE_FPreserved5,
302 STATE_FPreserved7,
303 STATE_EXPSTATE
304 };
305
306
307 /* Field definitions. */
308
309 static unsigned
310 Field_t_Slot_inst_get (const xtensa_insnbuf insn)
311 {
312 unsigned tie_t = 0;
313 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
314 return tie_t;
315 }
316
317 static void
318 Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
319 {
320 uint32 tie_t;
321 tie_t = (val << 28) >> 28;
322 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
323 }
324
325 static unsigned
326 Field_s_Slot_inst_get (const xtensa_insnbuf insn)
327 {
328 unsigned tie_t = 0;
329 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
330 return tie_t;
331 }
332
333 static void
334 Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
335 {
336 uint32 tie_t;
337 tie_t = (val << 28) >> 28;
338 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
339 }
340
341 static unsigned
342 Field_r_Slot_inst_get (const xtensa_insnbuf insn)
343 {
344 unsigned tie_t = 0;
345 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
346 return tie_t;
347 }
348
349 static void
350 Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
351 {
352 uint32 tie_t;
353 tie_t = (val << 28) >> 28;
354 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
355 }
356
357 static unsigned
358 Field_op2_Slot_inst_get (const xtensa_insnbuf insn)
359 {
360 unsigned tie_t = 0;
361 tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28);
362 return tie_t;
363 }
364
365 static void
366 Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
367 {
368 uint32 tie_t;
369 tie_t = (val << 28) >> 28;
370 insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20);
371 }
372
373 static unsigned
374 Field_op1_Slot_inst_get (const xtensa_insnbuf insn)
375 {
376 unsigned tie_t = 0;
377 tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
378 return tie_t;
379 }
380
381 static void
382 Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
383 {
384 uint32 tie_t;
385 tie_t = (val << 28) >> 28;
386 insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
387 }
388
389 static unsigned
390 Field_op0_Slot_inst_get (const xtensa_insnbuf insn)
391 {
392 unsigned tie_t = 0;
393 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
394 return tie_t;
395 }
396
397 static void
398 Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
399 {
400 uint32 tie_t;
401 tie_t = (val << 28) >> 28;
402 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
403 }
404
405 static unsigned
406 Field_n_Slot_inst_get (const xtensa_insnbuf insn)
407 {
408 unsigned tie_t = 0;
409 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
410 return tie_t;
411 }
412
413 static void
414 Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
415 {
416 uint32 tie_t;
417 tie_t = (val << 30) >> 30;
418 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
419 }
420
421 static unsigned
422 Field_m_Slot_inst_get (const xtensa_insnbuf insn)
423 {
424 unsigned tie_t = 0;
425 tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
426 return tie_t;
427 }
428
429 static void
430 Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
431 {
432 uint32 tie_t;
433 tie_t = (val << 30) >> 30;
434 insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
435 }
436
437 static unsigned
438 Field_sr_Slot_inst_get (const xtensa_insnbuf insn)
439 {
440 unsigned tie_t = 0;
441 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
442 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
443 return tie_t;
444 }
445
446 static void
447 Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
448 {
449 uint32 tie_t;
450 tie_t = (val << 28) >> 28;
451 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
452 tie_t = (val << 24) >> 28;
453 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
454 }
455
456 static unsigned
457 Field_st_Slot_inst_get (const xtensa_insnbuf insn)
458 {
459 unsigned tie_t = 0;
460 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
461 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
462 return tie_t;
463 }
464
465 static void
466 Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
467 {
468 uint32 tie_t;
469 tie_t = (val << 28) >> 28;
470 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
471 tie_t = (val << 24) >> 28;
472 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
473 }
474
475 static unsigned
476 Field_thi3_Slot_inst_get (const xtensa_insnbuf insn)
477 {
478 unsigned tie_t = 0;
479 tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
480 return tie_t;
481 }
482
483 static void
484 Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
485 {
486 uint32 tie_t;
487 tie_t = (val << 29) >> 29;
488 insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
489 }
490
491 static unsigned
492 Field_t3_Slot_inst_get (const xtensa_insnbuf insn)
493 {
494 unsigned tie_t = 0;
495 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
496 return tie_t;
497 }
498
499 static void
500 Field_t3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
501 {
502 uint32 tie_t;
503 tie_t = (val << 31) >> 31;
504 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
505 }
506
507 static unsigned
508 Field_tlo_Slot_inst_get (const xtensa_insnbuf insn)
509 {
510 unsigned tie_t = 0;
511 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
512 return tie_t;
513 }
514
515 static void
516 Field_tlo_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
517 {
518 uint32 tie_t;
519 tie_t = (val << 30) >> 30;
520 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
521 }
522
523 static unsigned
524 Field_w_Slot_inst_get (const xtensa_insnbuf insn)
525 {
526 unsigned tie_t = 0;
527 tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30);
528 return tie_t;
529 }
530
531 static void
532 Field_w_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
533 {
534 uint32 tie_t;
535 tie_t = (val << 30) >> 30;
536 insn[0] = (insn[0] & ~0x3000) | (tie_t << 12);
537 }
538
539 static unsigned
540 Field_r3_Slot_inst_get (const xtensa_insnbuf insn)
541 {
542 unsigned tie_t = 0;
543 tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
544 return tie_t;
545 }
546
547 static void
548 Field_r3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
549 {
550 uint32 tie_t;
551 tie_t = (val << 31) >> 31;
552 insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
553 }
554
555 static unsigned
556 Field_rhi_Slot_inst_get (const xtensa_insnbuf insn)
557 {
558 unsigned tie_t = 0;
559 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
560 return tie_t;
561 }
562
563 static void
564 Field_rhi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
565 {
566 uint32 tie_t;
567 tie_t = (val << 30) >> 30;
568 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
569 }
570
571 static unsigned
572 Field_s3to1_Slot_inst_get (const xtensa_insnbuf insn)
573 {
574 unsigned tie_t = 0;
575 tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
576 return tie_t;
577 }
578
579 static void
580 Field_s3to1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
581 {
582 uint32 tie_t;
583 tie_t = (val << 29) >> 29;
584 insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
585 }
586
587 static unsigned
588 Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn)
589 {
590 unsigned tie_t = 0;
591 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
592 return tie_t;
593 }
594
595 static void
596 Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
597 {
598 uint32 tie_t;
599 tie_t = (val << 28) >> 28;
600 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
601 }
602
603 static unsigned
604 Field_t_Slot_inst16b_get (const xtensa_insnbuf insn)
605 {
606 unsigned tie_t = 0;
607 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
608 return tie_t;
609 }
610
611 static void
612 Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
613 {
614 uint32 tie_t;
615 tie_t = (val << 28) >> 28;
616 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
617 }
618
619 static unsigned
620 Field_r_Slot_inst16b_get (const xtensa_insnbuf insn)
621 {
622 unsigned tie_t = 0;
623 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
624 return tie_t;
625 }
626
627 static void
628 Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
629 {
630 uint32 tie_t;
631 tie_t = (val << 28) >> 28;
632 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
633 }
634
635 static unsigned
636 Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn)
637 {
638 unsigned tie_t = 0;
639 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
640 return tie_t;
641 }
642
643 static void
644 Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
645 {
646 uint32 tie_t;
647 tie_t = (val << 28) >> 28;
648 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
649 }
650
651 static unsigned
652 Field_z_Slot_inst16b_get (const xtensa_insnbuf insn)
653 {
654 unsigned tie_t = 0;
655 tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
656 return tie_t;
657 }
658
659 static void
660 Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
661 {
662 uint32 tie_t;
663 tie_t = (val << 31) >> 31;
664 insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
665 }
666
667 static unsigned
668 Field_i_Slot_inst16b_get (const xtensa_insnbuf insn)
669 {
670 unsigned tie_t = 0;
671 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
672 return tie_t;
673 }
674
675 static void
676 Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
677 {
678 uint32 tie_t;
679 tie_t = (val << 31) >> 31;
680 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
681 }
682
683 static unsigned
684 Field_s_Slot_inst16b_get (const xtensa_insnbuf insn)
685 {
686 unsigned tie_t = 0;
687 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
688 return tie_t;
689 }
690
691 static void
692 Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
693 {
694 uint32 tie_t;
695 tie_t = (val << 28) >> 28;
696 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
697 }
698
699 static unsigned
700 Field_t_Slot_inst16a_get (const xtensa_insnbuf insn)
701 {
702 unsigned tie_t = 0;
703 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
704 return tie_t;
705 }
706
707 static void
708 Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
709 {
710 uint32 tie_t;
711 tie_t = (val << 28) >> 28;
712 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
713 }
714
715 static unsigned
716 Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn)
717 {
718 unsigned tie_t = 0;
719 tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
720 return tie_t;
721 }
722
723 static void
724 Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
725 {
726 uint32 tie_t;
727 tie_t = (val << 31) >> 31;
728 insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
729 }
730
731 static unsigned
732 Field_bbi_Slot_inst_get (const xtensa_insnbuf insn)
733 {
734 unsigned tie_t = 0;
735 tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
736 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
737 return tie_t;
738 }
739
740 static void
741 Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
742 {
743 uint32 tie_t;
744 tie_t = (val << 28) >> 28;
745 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
746 tie_t = (val << 27) >> 31;
747 insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
748 }
749
750 static unsigned
751 Field_imm12_Slot_inst_get (const xtensa_insnbuf insn)
752 {
753 unsigned tie_t = 0;
754 tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20);
755 return tie_t;
756 }
757
758 static void
759 Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
760 {
761 uint32 tie_t;
762 tie_t = (val << 20) >> 20;
763 insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12);
764 }
765
766 static unsigned
767 Field_imm8_Slot_inst_get (const xtensa_insnbuf insn)
768 {
769 unsigned tie_t = 0;
770 tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
771 return tie_t;
772 }
773
774 static void
775 Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
776 {
777 uint32 tie_t;
778 tie_t = (val << 24) >> 24;
779 insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
780 }
781
782 static unsigned
783 Field_s_Slot_inst16a_get (const xtensa_insnbuf insn)
784 {
785 unsigned tie_t = 0;
786 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
787 return tie_t;
788 }
789
790 static void
791 Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
792 {
793 uint32 tie_t;
794 tie_t = (val << 28) >> 28;
795 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
796 }
797
798 static unsigned
799 Field_s8_Slot_inst_get (const xtensa_insnbuf insn)
800 {
801 unsigned tie_t = 0;
802 tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
803 return tie_t;
804 }
805
806 static void
807 Field_s8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
808 {
809 uint32 tie_t;
810 tie_t = (val << 31) >> 31;
811 insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
812 }
813
814 static unsigned
815 Field_imms8_Slot_inst_get (const xtensa_insnbuf insn)
816 {
817 unsigned tie_t = 0;
818 tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
819 return tie_t;
820 }
821
822 static void
823 Field_imms8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
824 {
825 uint32 tie_t;
826 tie_t = (val << 29) >> 29;
827 insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
828 }
829
830 static unsigned
831 Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn)
832 {
833 unsigned tie_t = 0;
834 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
835 tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
836 return tie_t;
837 }
838
839 static void
840 Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
841 {
842 uint32 tie_t;
843 tie_t = (val << 24) >> 24;
844 insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
845 tie_t = (val << 20) >> 28;
846 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
847 }
848
849 static unsigned
850 Field_imm16_Slot_inst_get (const xtensa_insnbuf insn)
851 {
852 unsigned tie_t = 0;
853 tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16);
854 return tie_t;
855 }
856
857 static void
858 Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
859 {
860 uint32 tie_t;
861 tie_t = (val << 16) >> 16;
862 insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8);
863 }
864
865 static unsigned
866 Field_offset_Slot_inst_get (const xtensa_insnbuf insn)
867 {
868 unsigned tie_t = 0;
869 tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
870 return tie_t;
871 }
872
873 static void
874 Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
875 {
876 uint32 tie_t;
877 tie_t = (val << 14) >> 14;
878 insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
879 }
880
881 static unsigned
882 Field_r_Slot_inst16a_get (const xtensa_insnbuf insn)
883 {
884 unsigned tie_t = 0;
885 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
886 return tie_t;
887 }
888
889 static void
890 Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
891 {
892 uint32 tie_t;
893 tie_t = (val << 28) >> 28;
894 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
895 }
896
897 static unsigned
898 Field_r_disp_Slot_inst_get (const xtensa_insnbuf insn)
899 {
900 unsigned tie_t = 0;
901 tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29);
902 return tie_t;
903 }
904
905 static void
906 Field_r_disp_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
907 {
908 uint32 tie_t;
909 tie_t = (val << 29) >> 29;
910 insn[0] = (insn[0] & ~0x7000) | (tie_t << 12);
911 }
912
913 static unsigned
914 Field_r_3_Slot_inst_get (const xtensa_insnbuf insn)
915 {
916 unsigned tie_t = 0;
917 tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
918 return tie_t;
919 }
920
921 static void
922 Field_r_3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
923 {
924 uint32 tie_t;
925 tie_t = (val << 31) >> 31;
926 insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
927 }
928
929 static unsigned
930 Field_sa4_Slot_inst_get (const xtensa_insnbuf insn)
931 {
932 unsigned tie_t = 0;
933 tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
934 return tie_t;
935 }
936
937 static void
938 Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
939 {
940 uint32 tie_t;
941 tie_t = (val << 31) >> 31;
942 insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
943 }
944
945 static unsigned
946 Field_sae4_Slot_inst_get (const xtensa_insnbuf insn)
947 {
948 unsigned tie_t = 0;
949 tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
950 return tie_t;
951 }
952
953 static void
954 Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
955 {
956 uint32 tie_t;
957 tie_t = (val << 31) >> 31;
958 insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
959 }
960
961 static unsigned
962 Field_sae_Slot_inst_get (const xtensa_insnbuf insn)
963 {
964 unsigned tie_t = 0;
965 tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
966 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
967 return tie_t;
968 }
969
970 static void
971 Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
972 {
973 uint32 tie_t;
974 tie_t = (val << 28) >> 28;
975 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
976 tie_t = (val << 27) >> 31;
977 insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
978 }
979
980 static unsigned
981 Field_sal_Slot_inst_get (const xtensa_insnbuf insn)
982 {
983 unsigned tie_t = 0;
984 tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
985 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
986 return tie_t;
987 }
988
989 static void
990 Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
991 {
992 uint32 tie_t;
993 tie_t = (val << 28) >> 28;
994 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
995 tie_t = (val << 27) >> 31;
996 insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
997 }
998
999 static unsigned
1000 Field_sargt_Slot_inst_get (const xtensa_insnbuf insn)
1001 {
1002 unsigned tie_t = 0;
1003 tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
1004 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
1005 return tie_t;
1006 }
1007
1008 static void
1009 Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1010 {
1011 uint32 tie_t;
1012 tie_t = (val << 28) >> 28;
1013 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1014 tie_t = (val << 27) >> 31;
1015 insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
1016 }
1017
1018 static unsigned
1019 Field_sas4_Slot_inst_get (const xtensa_insnbuf insn)
1020 {
1021 unsigned tie_t = 0;
1022 tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
1023 return tie_t;
1024 }
1025
1026 static void
1027 Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1028 {
1029 uint32 tie_t;
1030 tie_t = (val << 31) >> 31;
1031 insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
1032 }
1033
1034 static unsigned
1035 Field_sas_Slot_inst_get (const xtensa_insnbuf insn)
1036 {
1037 unsigned tie_t = 0;
1038 tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
1039 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
1040 return tie_t;
1041 }
1042
1043 static void
1044 Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1045 {
1046 uint32 tie_t;
1047 tie_t = (val << 28) >> 28;
1048 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1049 tie_t = (val << 27) >> 31;
1050 insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
1051 }
1052
1053 static unsigned
1054 Field_imm4_Slot_inst_get (const xtensa_insnbuf insn)
1055 {
1056 unsigned tie_t = 0;
1057 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1058 return tie_t;
1059 }
1060
1061 static void
1062 Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1063 {
1064 uint32 tie_t;
1065 tie_t = (val << 28) >> 28;
1066 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1067 }
1068
1069 static unsigned
1070 Field_mn_Slot_inst_get (const xtensa_insnbuf insn)
1071 {
1072 unsigned tie_t = 0;
1073 tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
1074 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1075 return tie_t;
1076 }
1077
1078 static void
1079 Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1080 {
1081 uint32 tie_t;
1082 tie_t = (val << 30) >> 30;
1083 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1084 tie_t = (val << 28) >> 30;
1085 insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
1086 }
1087
1088 static unsigned
1089 Field_i_Slot_inst16a_get (const xtensa_insnbuf insn)
1090 {
1091 unsigned tie_t = 0;
1092 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
1093 return tie_t;
1094 }
1095
1096 static void
1097 Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1098 {
1099 uint32 tie_t;
1100 tie_t = (val << 31) >> 31;
1101 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
1102 }
1103
1104 static unsigned
1105 Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn)
1106 {
1107 unsigned tie_t = 0;
1108 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1109 return tie_t;
1110 }
1111
1112 static void
1113 Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1114 {
1115 uint32 tie_t;
1116 tie_t = (val << 28) >> 28;
1117 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1118 }
1119
1120 static unsigned
1121 Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn)
1122 {
1123 unsigned tie_t = 0;
1124 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1125 return tie_t;
1126 }
1127
1128 static void
1129 Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1130 {
1131 uint32 tie_t;
1132 tie_t = (val << 28) >> 28;
1133 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1134 }
1135
1136 static unsigned
1137 Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn)
1138 {
1139 unsigned tie_t = 0;
1140 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1141 return tie_t;
1142 }
1143
1144 static void
1145 Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1146 {
1147 uint32 tie_t;
1148 tie_t = (val << 30) >> 30;
1149 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1150 }
1151
1152 static unsigned
1153 Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn)
1154 {
1155 unsigned tie_t = 0;
1156 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1157 return tie_t;
1158 }
1159
1160 static void
1161 Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1162 {
1163 uint32 tie_t;
1164 tie_t = (val << 30) >> 30;
1165 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1166 }
1167
1168 static unsigned
1169 Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn)
1170 {
1171 unsigned tie_t = 0;
1172 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1173 return tie_t;
1174 }
1175
1176 static void
1177 Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1178 {
1179 uint32 tie_t;
1180 tie_t = (val << 28) >> 28;
1181 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1182 }
1183
1184 static unsigned
1185 Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn)
1186 {
1187 unsigned tie_t = 0;
1188 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1189 return tie_t;
1190 }
1191
1192 static void
1193 Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1194 {
1195 uint32 tie_t;
1196 tie_t = (val << 28) >> 28;
1197 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1198 }
1199
1200 static unsigned
1201 Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn)
1202 {
1203 unsigned tie_t = 0;
1204 tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
1205 return tie_t;
1206 }
1207
1208 static void
1209 Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1210 {
1211 uint32 tie_t;
1212 tie_t = (val << 29) >> 29;
1213 insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
1214 }
1215
1216 static unsigned
1217 Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn)
1218 {
1219 unsigned tie_t = 0;
1220 tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
1221 return tie_t;
1222 }
1223
1224 static void
1225 Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1226 {
1227 uint32 tie_t;
1228 tie_t = (val << 29) >> 29;
1229 insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
1230 }
1231
1232 static unsigned
1233 Field_z_Slot_inst16a_get (const xtensa_insnbuf insn)
1234 {
1235 unsigned tie_t = 0;
1236 tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
1237 return tie_t;
1238 }
1239
1240 static void
1241 Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1242 {
1243 uint32 tie_t;
1244 tie_t = (val << 31) >> 31;
1245 insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
1246 }
1247
1248 static unsigned
1249 Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn)
1250 {
1251 unsigned tie_t = 0;
1252 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1253 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1254 return tie_t;
1255 }
1256
1257 static void
1258 Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1259 {
1260 uint32 tie_t;
1261 tie_t = (val << 28) >> 28;
1262 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1263 tie_t = (val << 26) >> 30;
1264 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1265 }
1266
1267 static unsigned
1268 Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn)
1269 {
1270 unsigned tie_t = 0;
1271 tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
1272 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1273 return tie_t;
1274 }
1275
1276 static void
1277 Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1278 {
1279 uint32 tie_t;
1280 tie_t = (val << 28) >> 28;
1281 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1282 tie_t = (val << 25) >> 29;
1283 insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
1284 }
1285
1286 static unsigned
1287 Field_rbit2_Slot_inst_get (const xtensa_insnbuf insn)
1288 {
1289 unsigned tie_t = 0;
1290 tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
1291 return tie_t;
1292 }
1293
1294 static void
1295 Field_rbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1296 {
1297 uint32 tie_t;
1298 tie_t = (val << 31) >> 31;
1299 insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
1300 }
1301
1302 static unsigned
1303 Field_tbit2_Slot_inst_get (const xtensa_insnbuf insn)
1304 {
1305 unsigned tie_t = 0;
1306 tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
1307 return tie_t;
1308 }
1309
1310 static void
1311 Field_tbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1312 {
1313 uint32 tie_t;
1314 tie_t = (val << 31) >> 31;
1315 insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
1316 }
1317
1318 static unsigned
1319 Field_y_Slot_inst_get (const xtensa_insnbuf insn)
1320 {
1321 unsigned tie_t = 0;
1322 tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
1323 return tie_t;
1324 }
1325
1326 static void
1327 Field_y_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1328 {
1329 uint32 tie_t;
1330 tie_t = (val << 31) >> 31;
1331 insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
1332 }
1333
1334 static unsigned
1335 Field_x_Slot_inst_get (const xtensa_insnbuf insn)
1336 {
1337 unsigned tie_t = 0;
1338 tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
1339 return tie_t;
1340 }
1341
1342 static void
1343 Field_x_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1344 {
1345 uint32 tie_t;
1346 tie_t = (val << 31) >> 31;
1347 insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
1348 }
1349
1350 static unsigned
1351 Field_t2_Slot_inst_get (const xtensa_insnbuf insn)
1352 {
1353 unsigned tie_t = 0;
1354 tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
1355 return tie_t;
1356 }
1357
1358 static void
1359 Field_t2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1360 {
1361 uint32 tie_t;
1362 tie_t = (val << 29) >> 29;
1363 insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
1364 }
1365
1366 static unsigned
1367 Field_s2_Slot_inst_get (const xtensa_insnbuf insn)
1368 {
1369 unsigned tie_t = 0;
1370 tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
1371 return tie_t;
1372 }
1373
1374 static void
1375 Field_s2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1376 {
1377 uint32 tie_t;
1378 tie_t = (val << 29) >> 29;
1379 insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
1380 }
1381
1382 static unsigned
1383 Field_r2_Slot_inst_get (const xtensa_insnbuf insn)
1384 {
1385 unsigned tie_t = 0;
1386 tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29);
1387 return tie_t;
1388 }
1389
1390 static void
1391 Field_r2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1392 {
1393 uint32 tie_t;
1394 tie_t = (val << 29) >> 29;
1395 insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
1396 }
1397
1398 static unsigned
1399 Field_t4_Slot_inst_get (const xtensa_insnbuf insn)
1400 {
1401 unsigned tie_t = 0;
1402 tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
1403 return tie_t;
1404 }
1405
1406 static void
1407 Field_t4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1408 {
1409 uint32 tie_t;
1410 tie_t = (val << 30) >> 30;
1411 insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
1412 }
1413
1414 static unsigned
1415 Field_s4_Slot_inst_get (const xtensa_insnbuf insn)
1416 {
1417 unsigned tie_t = 0;
1418 tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30);
1419 return tie_t;
1420 }
1421
1422 static void
1423 Field_s4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1424 {
1425 uint32 tie_t;
1426 tie_t = (val << 30) >> 30;
1427 insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
1428 }
1429
1430 static unsigned
1431 Field_r4_Slot_inst_get (const xtensa_insnbuf insn)
1432 {
1433 unsigned tie_t = 0;
1434 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
1435 return tie_t;
1436 }
1437
1438 static void
1439 Field_r4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1440 {
1441 uint32 tie_t;
1442 tie_t = (val << 30) >> 30;
1443 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
1444 }
1445
1446 static unsigned
1447 Field_t8_Slot_inst_get (const xtensa_insnbuf insn)
1448 {
1449 unsigned tie_t = 0;
1450 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
1451 return tie_t;
1452 }
1453
1454 static void
1455 Field_t8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1456 {
1457 uint32 tie_t;
1458 tie_t = (val << 31) >> 31;
1459 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
1460 }
1461
1462 static unsigned
1463 Field_r8_Slot_inst_get (const xtensa_insnbuf insn)
1464 {
1465 unsigned tie_t = 0;
1466 tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
1467 return tie_t;
1468 }
1469
1470 static void
1471 Field_r8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1472 {
1473 uint32 tie_t;
1474 tie_t = (val << 31) >> 31;
1475 insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
1476 }
1477
1478 static unsigned
1479 Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn)
1480 {
1481 unsigned tie_t = 0;
1482 tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17);
1483 return tie_t;
1484 }
1485
1486 static void
1487 Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1488 {
1489 uint32 tie_t;
1490 tie_t = (val << 17) >> 17;
1491 insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9);
1492 }
1493
1494 static unsigned
1495 Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn)
1496 {
1497 unsigned tie_t = 0;
1498 tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
1499 return tie_t;
1500 }
1501
1502 static void
1503 Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1504 {
1505 uint32 tie_t;
1506 tie_t = (val << 14) >> 14;
1507 insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
1508 }
1509
1510 static unsigned
1511 Field_bitindex_Slot_inst_get (const xtensa_insnbuf insn)
1512 {
1513 unsigned tie_t = 0;
1514 tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27);
1515 return tie_t;
1516 }
1517
1518 static void
1519 Field_bitindex_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1520 {
1521 uint32 tie_t;
1522 tie_t = (val << 27) >> 27;
1523 insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4);
1524 }
1525
1526 static void
1527 Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED,
1528 uint32 val ATTRIBUTE_UNUSED)
1529 {
1530 /* Do nothing. */
1531 }
1532
1533 static unsigned
1534 Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1535 {
1536 return 0;
1537 }
1538
1539 static unsigned
1540 Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1541 {
1542 return 4;
1543 }
1544
1545 static unsigned
1546 Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1547 {
1548 return 8;
1549 }
1550
1551 static unsigned
1552 Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1553 {
1554 return 12;
1555 }
1556
1557 static unsigned
1558 Implicit_Field_mr0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1559 {
1560 return 0;
1561 }
1562
1563 static unsigned
1564 Implicit_Field_mr1_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1565 {
1566 return 1;
1567 }
1568
1569 static unsigned
1570 Implicit_Field_mr2_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1571 {
1572 return 2;
1573 }
1574
1575 static unsigned
1576 Implicit_Field_mr3_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1577 {
1578 return 3;
1579 }
1580
1581 static unsigned
1582 Implicit_Field_bt16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1583 {
1584 return 0;
1585 }
1586
1587 static unsigned
1588 Implicit_Field_bs16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1589 {
1590 return 0;
1591 }
1592
1593 static unsigned
1594 Implicit_Field_br16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1595 {
1596 return 0;
1597 }
1598
1599 static unsigned
1600 Implicit_Field_brall_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1601 {
1602 return 0;
1603 }
1604
1605 enum xtensa_field_id {
1606 FIELD_t,
1607 FIELD_bbi4,
1608 FIELD_bbi,
1609 FIELD_imm12,
1610 FIELD_imm8,
1611 FIELD_s,
1612 FIELD_s8,
1613 FIELD_imms8,
1614 FIELD_imm12b,
1615 FIELD_imm16,
1616 FIELD_m,
1617 FIELD_n,
1618 FIELD_offset,
1619 FIELD_op0,
1620 FIELD_op1,
1621 FIELD_op2,
1622 FIELD_r,
1623 FIELD_r_disp,
1624 FIELD_r_3,
1625 FIELD_sa4,
1626 FIELD_sae4,
1627 FIELD_sae,
1628 FIELD_sal,
1629 FIELD_sargt,
1630 FIELD_sas4,
1631 FIELD_sas,
1632 FIELD_sr,
1633 FIELD_st,
1634 FIELD_thi3,
1635 FIELD_imm4,
1636 FIELD_mn,
1637 FIELD_i,
1638 FIELD_imm6lo,
1639 FIELD_imm6hi,
1640 FIELD_imm7lo,
1641 FIELD_imm7hi,
1642 FIELD_z,
1643 FIELD_imm6,
1644 FIELD_imm7,
1645 FIELD_r3,
1646 FIELD_rbit2,
1647 FIELD_rhi,
1648 FIELD_t3,
1649 FIELD_tbit2,
1650 FIELD_tlo,
1651 FIELD_w,
1652 FIELD_y,
1653 FIELD_x,
1654 FIELD_t2,
1655 FIELD_s2,
1656 FIELD_r2,
1657 FIELD_t4,
1658 FIELD_s4,
1659 FIELD_r4,
1660 FIELD_t8,
1661 FIELD_r8,
1662 FIELD_xt_wbr15_imm,
1663 FIELD_xt_wbr18_imm,
1664 FIELD_bitindex,
1665 FIELD_s3to1,
1666 FIELD__ar0,
1667 FIELD__ar4,
1668 FIELD__ar8,
1669 FIELD__ar12,
1670 FIELD__mr0,
1671 FIELD__mr1,
1672 FIELD__mr2,
1673 FIELD__mr3,
1674 FIELD__bt16,
1675 FIELD__bs16,
1676 FIELD__br16,
1677 FIELD__brall
1678 };
1679
1680
1681 /* Functional units. */
1682
1683 static xtensa_funcUnit_internal funcUnits[] = {
1684 {"XT_LOADSTORE_UNIT", 1}
1685 };
1686
1687 enum xtensa_funcUnit_id {
1688 FUNCUNIT_XT_LOADSTORE_UNIT
1689 };
1690
1691
1692 /* Register files. */
1693
1694 enum xtensa_regfile_id {
1695 REGFILE_AR,
1696 REGFILE_MR,
1697 REGFILE_BR,
1698 REGFILE_FR,
1699 REGFILE_BR2,
1700 REGFILE_BR4,
1701 REGFILE_BR8,
1702 REGFILE_BR16
1703 };
1704
1705 static xtensa_regfile_internal regfiles[] = {
1706 { "AR", "a", REGFILE_AR, 32, 32 },
1707 { "MR", "m", REGFILE_MR, 32, 4 },
1708 { "BR", "b", REGFILE_BR, 1, 16 },
1709 { "FR", "f", REGFILE_FR, 64, 16 },
1710 { "BR2", "b", REGFILE_BR, 2, 8 },
1711 { "BR4", "b", REGFILE_BR, 4, 4 },
1712 { "BR8", "b", REGFILE_BR, 8, 2 },
1713 { "BR16", "b", REGFILE_BR, 16, 1 }
1714 };
1715
1716
1717 /* Interfaces. */
1718
1719 static xtensa_interface_internal interfaces[] = {
1720 { "IMPWIRE", 32, 0, 0, 'i' }
1721 };
1722
1723 enum xtensa_interface_id {
1724 INTERFACE_IMPWIRE
1725 };
1726
1727
1728 /* Constant tables. */
1729
1730 /* constant table ai4c */
1731 static const unsigned CONST_TBL_ai4c_0[] = {
1732 0xffffffff,
1733 0x1,
1734 0x2,
1735 0x3,
1736 0x4,
1737 0x5,
1738 0x6,
1739 0x7,
1740 0x8,
1741 0x9,
1742 0xa,
1743 0xb,
1744 0xc,
1745 0xd,
1746 0xe,
1747 0xf,
1748 0
1749 };
1750
1751 /* constant table b4c */
1752 static const unsigned CONST_TBL_b4c_0[] = {
1753 0xffffffff,
1754 0x1,
1755 0x2,
1756 0x3,
1757 0x4,
1758 0x5,
1759 0x6,
1760 0x7,
1761 0x8,
1762 0xa,
1763 0xc,
1764 0x10,
1765 0x20,
1766 0x40,
1767 0x80,
1768 0x100,
1769 0
1770 };
1771
1772 /* constant table b4cu */
1773 static const unsigned CONST_TBL_b4cu_0[] = {
1774 0x8000,
1775 0x10000,
1776 0x2,
1777 0x3,
1778 0x4,
1779 0x5,
1780 0x6,
1781 0x7,
1782 0x8,
1783 0xa,
1784 0xc,
1785 0x10,
1786 0x20,
1787 0x40,
1788 0x80,
1789 0x100,
1790 0
1791 };
1792
1793 /* constant table RECIP_Data8 */
1794 static const unsigned CONST_TBL_RECIP_Data8_0[] = {
1795 0xff & 0xff,
1796 0xfd & 0xff,
1797 0xfb & 0xff,
1798 0xf9 & 0xff,
1799 0xf7 & 0xff,
1800 0xf5 & 0xff,
1801 0xf4 & 0xff,
1802 0xf2 & 0xff,
1803 0xf0 & 0xff,
1804 0xee & 0xff,
1805 0xed & 0xff,
1806 0xeb & 0xff,
1807 0xe9 & 0xff,
1808 0xe8 & 0xff,
1809 0xe6 & 0xff,
1810 0xe4 & 0xff,
1811 0xe3 & 0xff,
1812 0xe1 & 0xff,
1813 0xe0 & 0xff,
1814 0xde & 0xff,
1815 0xdd & 0xff,
1816 0xdb & 0xff,
1817 0xda & 0xff,
1818 0xd8 & 0xff,
1819 0xd7 & 0xff,
1820 0xd5 & 0xff,
1821 0xd4 & 0xff,
1822 0xd3 & 0xff,
1823 0xd1 & 0xff,
1824 0xd0 & 0xff,
1825 0xcf & 0xff,
1826 0xcd & 0xff,
1827 0xcc & 0xff,
1828 0xcb & 0xff,
1829 0xca & 0xff,
1830 0xc8 & 0xff,
1831 0xc7 & 0xff,
1832 0xc6 & 0xff,
1833 0xc5 & 0xff,
1834 0xc4 & 0xff,
1835 0xc2 & 0xff,
1836 0xc1 & 0xff,
1837 0xc0 & 0xff,
1838 0xbf & 0xff,
1839 0xbe & 0xff,
1840 0xbd & 0xff,
1841 0xbc & 0xff,
1842 0xbb & 0xff,
1843 0xba & 0xff,
1844 0xb9 & 0xff,
1845 0xb8 & 0xff,
1846 0xb7 & 0xff,
1847 0xb6 & 0xff,
1848 0xb5 & 0xff,
1849 0xb4 & 0xff,
1850 0xb3 & 0xff,
1851 0xb2 & 0xff,
1852 0xb1 & 0xff,
1853 0xb0 & 0xff,
1854 0xaf & 0xff,
1855 0xae & 0xff,
1856 0xad & 0xff,
1857 0xac & 0xff,
1858 0xab & 0xff,
1859 0xaa & 0xff,
1860 0xa9 & 0xff,
1861 0xa8 & 0xff,
1862 0xa8 & 0xff,
1863 0xa7 & 0xff,
1864 0xa6 & 0xff,
1865 0xa5 & 0xff,
1866 0xa4 & 0xff,
1867 0xa3 & 0xff,
1868 0xa3 & 0xff,
1869 0xa2 & 0xff,
1870 0xa1 & 0xff,
1871 0xa0 & 0xff,
1872 0x9f & 0xff,
1873 0x9f & 0xff,
1874 0x9e & 0xff,
1875 0x9d & 0xff,
1876 0x9c & 0xff,
1877 0x9c & 0xff,
1878 0x9b & 0xff,
1879 0x9a & 0xff,
1880 0x99 & 0xff,
1881 0x99 & 0xff,
1882 0x98 & 0xff,
1883 0x97 & 0xff,
1884 0x97 & 0xff,
1885 0x96 & 0xff,
1886 0x95 & 0xff,
1887 0x95 & 0xff,
1888 0x94 & 0xff,
1889 0x93 & 0xff,
1890 0x93 & 0xff,
1891 0x92 & 0xff,
1892 0x91 & 0xff,
1893 0x91 & 0xff,
1894 0x90 & 0xff,
1895 0x8f & 0xff,
1896 0x8f & 0xff,
1897 0x8e & 0xff,
1898 0x8e & 0xff,
1899 0x8d & 0xff,
1900 0x8c & 0xff,
1901 0x8c & 0xff,
1902 0x8b & 0xff,
1903 0x8b & 0xff,
1904 0x8a & 0xff,
1905 0x89 & 0xff,
1906 0x89 & 0xff,
1907 0x88 & 0xff,
1908 0x88 & 0xff,
1909 0x87 & 0xff,
1910 0x87 & 0xff,
1911 0x86 & 0xff,
1912 0x85 & 0xff,
1913 0x85 & 0xff,
1914 0x84 & 0xff,
1915 0x84 & 0xff,
1916 0x83 & 0xff,
1917 0x83 & 0xff,
1918 0x82 & 0xff,
1919 0x82 & 0xff,
1920 0x81 & 0xff,
1921 0x81 & 0xff,
1922 0x81 & 0xff,
1923 0
1924 };
1925
1926 /* constant table RSQRT_Data8 */
1927 static const unsigned CONST_TBL_RSQRT_Data8_0[] = {
1928 0xb4 & 0xff,
1929 0xb3 & 0xff,
1930 0xb2 & 0xff,
1931 0xb0 & 0xff,
1932 0xaf & 0xff,
1933 0xae & 0xff,
1934 0xac & 0xff,
1935 0xab & 0xff,
1936 0xaa & 0xff,
1937 0xa9 & 0xff,
1938 0xa8 & 0xff,
1939 0xa7 & 0xff,
1940 0xa6 & 0xff,
1941 0xa5 & 0xff,
1942 0xa3 & 0xff,
1943 0xa2 & 0xff,
1944 0xa1 & 0xff,
1945 0xa0 & 0xff,
1946 0x9f & 0xff,
1947 0x9e & 0xff,
1948 0x9e & 0xff,
1949 0x9d & 0xff,
1950 0x9c & 0xff,
1951 0x9b & 0xff,
1952 0x9a & 0xff,
1953 0x99 & 0xff,
1954 0x98 & 0xff,
1955 0x97 & 0xff,
1956 0x97 & 0xff,
1957 0x96 & 0xff,
1958 0x95 & 0xff,
1959 0x94 & 0xff,
1960 0x93 & 0xff,
1961 0x93 & 0xff,
1962 0x92 & 0xff,
1963 0x91 & 0xff,
1964 0x90 & 0xff,
1965 0x90 & 0xff,
1966 0x8f & 0xff,
1967 0x8e & 0xff,
1968 0x8e & 0xff,
1969 0x8d & 0xff,
1970 0x8c & 0xff,
1971 0x8c & 0xff,
1972 0x8b & 0xff,
1973 0x8a & 0xff,
1974 0x8a & 0xff,
1975 0x89 & 0xff,
1976 0x89 & 0xff,
1977 0x88 & 0xff,
1978 0x87 & 0xff,
1979 0x87 & 0xff,
1980 0x86 & 0xff,
1981 0x86 & 0xff,
1982 0x85 & 0xff,
1983 0x84 & 0xff,
1984 0x84 & 0xff,
1985 0x83 & 0xff,
1986 0x83 & 0xff,
1987 0x82 & 0xff,
1988 0x82 & 0xff,
1989 0x81 & 0xff,
1990 0x81 & 0xff,
1991 0x80 & 0xff,
1992 0xff & 0xff,
1993 0xfd & 0xff,
1994 0xfb & 0xff,
1995 0xf9 & 0xff,
1996 0xf7 & 0xff,
1997 0xf6 & 0xff,
1998 0xf4 & 0xff,
1999 0xf2 & 0xff,
2000 0xf1 & 0xff,
2001 0xef & 0xff,
2002 0xed & 0xff,
2003 0xec & 0xff,
2004 0xea & 0xff,
2005 0xe9 & 0xff,
2006 0xe7 & 0xff,
2007 0xe6 & 0xff,
2008 0xe4 & 0xff,
2009 0xe3 & 0xff,
2010 0xe1 & 0xff,
2011 0xe0 & 0xff,
2012 0xdf & 0xff,
2013 0xdd & 0xff,
2014 0xdc & 0xff,
2015 0xdb & 0xff,
2016 0xda & 0xff,
2017 0xd8 & 0xff,
2018 0xd7 & 0xff,
2019 0xd6 & 0xff,
2020 0xd5 & 0xff,
2021 0xd4 & 0xff,
2022 0xd3 & 0xff,
2023 0xd2 & 0xff,
2024 0xd0 & 0xff,
2025 0xcf & 0xff,
2026 0xce & 0xff,
2027 0xcd & 0xff,
2028 0xcc & 0xff,
2029 0xcb & 0xff,
2030 0xca & 0xff,
2031 0xc9 & 0xff,
2032 0xc8 & 0xff,
2033 0xc7 & 0xff,
2034 0xc6 & 0xff,
2035 0xc6 & 0xff,
2036 0xc5 & 0xff,
2037 0xc4 & 0xff,
2038 0xc3 & 0xff,
2039 0xc2 & 0xff,
2040 0xc1 & 0xff,
2041 0xc0 & 0xff,
2042 0xbf & 0xff,
2043 0xbf & 0xff,
2044 0xbe & 0xff,
2045 0xbd & 0xff,
2046 0xbc & 0xff,
2047 0xbb & 0xff,
2048 0xbb & 0xff,
2049 0xba & 0xff,
2050 0xb9 & 0xff,
2051 0xb8 & 0xff,
2052 0xb8 & 0xff,
2053 0xb7 & 0xff,
2054 0xb6 & 0xff,
2055 0xb5 & 0xff,
2056 0
2057 };
2058
2059 /* constant table RECIP_Data10_2 */
2060 static const unsigned CONST_TBL_RECIP_Data10_2_0[] = {
2061 0x3fc & 0x3ff,
2062 0x3f4 & 0x3ff,
2063 0x3ec & 0x3ff,
2064 0x3e5 & 0x3ff,
2065 0x3dd & 0x3ff,
2066 0x3d6 & 0x3ff,
2067 0x3cf & 0x3ff,
2068 0x3c7 & 0x3ff,
2069 0x3c0 & 0x3ff,
2070 0x3b9 & 0x3ff,
2071 0x3b2 & 0x3ff,
2072 0x3ac & 0x3ff,
2073 0x3a5 & 0x3ff,
2074 0x39e & 0x3ff,
2075 0x398 & 0x3ff,
2076 0x391 & 0x3ff,
2077 0x38b & 0x3ff,
2078 0x385 & 0x3ff,
2079 0x37f & 0x3ff,
2080 0x378 & 0x3ff,
2081 0x373 & 0x3ff,
2082 0x36c & 0x3ff,
2083 0x367 & 0x3ff,
2084 0x361 & 0x3ff,
2085 0x35c & 0x3ff,
2086 0x356 & 0x3ff,
2087 0x350 & 0x3ff,
2088 0x34b & 0x3ff,
2089 0x345 & 0x3ff,
2090 0x340 & 0x3ff,
2091 0x33b & 0x3ff,
2092 0x335 & 0x3ff,
2093 0x330 & 0x3ff,
2094 0x32c & 0x3ff,
2095 0x327 & 0x3ff,
2096 0x322 & 0x3ff,
2097 0x31c & 0x3ff,
2098 0x318 & 0x3ff,
2099 0x314 & 0x3ff,
2100 0x30e & 0x3ff,
2101 0x30a & 0x3ff,
2102 0x306 & 0x3ff,
2103 0x300 & 0x3ff,
2104 0x2fc & 0x3ff,
2105 0x2f8 & 0x3ff,
2106 0x2f4 & 0x3ff,
2107 0x2f0 & 0x3ff,
2108 0x2ea & 0x3ff,
2109 0x2e6 & 0x3ff,
2110 0x2e2 & 0x3ff,
2111 0x2de & 0x3ff,
2112 0x2da & 0x3ff,
2113 0x2d6 & 0x3ff,
2114 0x2d2 & 0x3ff,
2115 0x2ce & 0x3ff,
2116 0x2ca & 0x3ff,
2117 0x2c6 & 0x3ff,
2118 0x2c2 & 0x3ff,
2119 0x2be & 0x3ff,
2120 0x2ba & 0x3ff,
2121 0x2b8 & 0x3ff,
2122 0x2b4 & 0x3ff,
2123 0x2b0 & 0x3ff,
2124 0x2ac & 0x3ff,
2125 0x2a8 & 0x3ff,
2126 0x2a6 & 0x3ff,
2127 0x2a2 & 0x3ff,
2128 0x29e & 0x3ff,
2129 0x29c & 0x3ff,
2130 0x298 & 0x3ff,
2131 0x294 & 0x3ff,
2132 0x290 & 0x3ff,
2133 0x28e & 0x3ff,
2134 0x28a & 0x3ff,
2135 0x288 & 0x3ff,
2136 0x284 & 0x3ff,
2137 0x280 & 0x3ff,
2138 0x27e & 0x3ff,
2139 0x27a & 0x3ff,
2140 0x278 & 0x3ff,
2141 0x274 & 0x3ff,
2142 0x272 & 0x3ff,
2143 0x26e & 0x3ff,
2144 0x26c & 0x3ff,
2145 0x268 & 0x3ff,
2146 0x266 & 0x3ff,
2147 0x264 & 0x3ff,
2148 0x260 & 0x3ff,
2149 0x25e & 0x3ff,
2150 0x25a & 0x3ff,
2151 0x258 & 0x3ff,
2152 0x254 & 0x3ff,
2153 0x252 & 0x3ff,
2154 0x250 & 0x3ff,
2155 0x24c & 0x3ff,
2156 0x24a & 0x3ff,
2157 0x248 & 0x3ff,
2158 0x246 & 0x3ff,
2159 0x242 & 0x3ff,
2160 0x240 & 0x3ff,
2161 0x23e & 0x3ff,
2162 0x23c & 0x3ff,
2163 0x238 & 0x3ff,
2164 0x236 & 0x3ff,
2165 0x234 & 0x3ff,
2166 0x232 & 0x3ff,
2167 0x230 & 0x3ff,
2168 0x22c & 0x3ff,
2169 0x22a & 0x3ff,
2170 0x228 & 0x3ff,
2171 0x226 & 0x3ff,
2172 0x224 & 0x3ff,
2173 0x220 & 0x3ff,
2174 0x21e & 0x3ff,
2175 0x21c & 0x3ff,
2176 0x21a & 0x3ff,
2177 0x218 & 0x3ff,
2178 0x216 & 0x3ff,
2179 0x214 & 0x3ff,
2180 0x212 & 0x3ff,
2181 0x210 & 0x3ff,
2182 0x20e & 0x3ff,
2183 0x20c & 0x3ff,
2184 0x208 & 0x3ff,
2185 0x208 & 0x3ff,
2186 0x204 & 0x3ff,
2187 0x204 & 0x3ff,
2188 0x201 & 0x3ff,
2189 0
2190 };
2191
2192 /* constant table RSQRT_10b_256 */
2193 static const unsigned CONST_TBL_RSQRT_10b_256_0[] = {
2194 0x1a5 & 0x3ff,
2195 0x1a0 & 0x3ff,
2196 0x19a & 0x3ff,
2197 0x195 & 0x3ff,
2198 0x18f & 0x3ff,
2199 0x18a & 0x3ff,
2200 0x185 & 0x3ff,
2201 0x180 & 0x3ff,
2202 0x17a & 0x3ff,
2203 0x175 & 0x3ff,
2204 0x170 & 0x3ff,
2205 0x16b & 0x3ff,
2206 0x166 & 0x3ff,
2207 0x161 & 0x3ff,
2208 0x15d & 0x3ff,
2209 0x158 & 0x3ff,
2210 0x153 & 0x3ff,
2211 0x14e & 0x3ff,
2212 0x14a & 0x3ff,
2213 0x145 & 0x3ff,
2214 0x140 & 0x3ff,
2215 0x13c & 0x3ff,
2216 0x138 & 0x3ff,
2217 0x133 & 0x3ff,
2218 0x12f & 0x3ff,
2219 0x12a & 0x3ff,
2220 0x126 & 0x3ff,
2221 0x122 & 0x3ff,
2222 0x11e & 0x3ff,
2223 0x11a & 0x3ff,
2224 0x115 & 0x3ff,
2225 0x111 & 0x3ff,
2226 0x10d & 0x3ff,
2227 0x109 & 0x3ff,
2228 0x105 & 0x3ff,
2229 0x101 & 0x3ff,
2230 0xfd & 0x3ff,
2231 0xfa & 0x3ff,
2232 0xf6 & 0x3ff,
2233 0xf2 & 0x3ff,
2234 0xee & 0x3ff,
2235 0xea & 0x3ff,
2236 0xe7 & 0x3ff,
2237 0xe3 & 0x3ff,
2238 0xdf & 0x3ff,
2239 0xdc & 0x3ff,
2240 0xd8 & 0x3ff,
2241 0xd5 & 0x3ff,
2242 0xd1 & 0x3ff,
2243 0xce & 0x3ff,
2244 0xca & 0x3ff,
2245 0xc7 & 0x3ff,
2246 0xc3 & 0x3ff,
2247 0xc0 & 0x3ff,
2248 0xbd & 0x3ff,
2249 0xb9 & 0x3ff,
2250 0xb6 & 0x3ff,
2251 0xb3 & 0x3ff,
2252 0xb0 & 0x3ff,
2253 0xad & 0x3ff,
2254 0xa9 & 0x3ff,
2255 0xa6 & 0x3ff,
2256 0xa3 & 0x3ff,
2257 0xa0 & 0x3ff,
2258 0x9d & 0x3ff,
2259 0x9a & 0x3ff,
2260 0x97 & 0x3ff,
2261 0x94 & 0x3ff,
2262 0x91 & 0x3ff,
2263 0x8e & 0x3ff,
2264 0x8b & 0x3ff,
2265 0x88 & 0x3ff,
2266 0x85 & 0x3ff,
2267 0x82 & 0x3ff,
2268 0x7f & 0x3ff,
2269 0x7d & 0x3ff,
2270 0x7a & 0x3ff,
2271 0x77 & 0x3ff,
2272 0x74 & 0x3ff,
2273 0x71 & 0x3ff,
2274 0x6f & 0x3ff,
2275 0x6c & 0x3ff,
2276 0x69 & 0x3ff,
2277 0x67 & 0x3ff,
2278 0x64 & 0x3ff,
2279 0x61 & 0x3ff,
2280 0x5f & 0x3ff,
2281 0x5c & 0x3ff,
2282 0x5a & 0x3ff,
2283 0x57 & 0x3ff,
2284 0x54 & 0x3ff,
2285 0x52 & 0x3ff,
2286 0x4f & 0x3ff,
2287 0x4d & 0x3ff,
2288 0x4a & 0x3ff,
2289 0x48 & 0x3ff,
2290 0x45 & 0x3ff,
2291 0x43 & 0x3ff,
2292 0x41 & 0x3ff,
2293 0x3e & 0x3ff,
2294 0x3c & 0x3ff,
2295 0x3a & 0x3ff,
2296 0x37 & 0x3ff,
2297 0x35 & 0x3ff,
2298 0x33 & 0x3ff,
2299 0x30 & 0x3ff,
2300 0x2e & 0x3ff,
2301 0x2c & 0x3ff,
2302 0x29 & 0x3ff,
2303 0x27 & 0x3ff,
2304 0x25 & 0x3ff,
2305 0x23 & 0x3ff,
2306 0x20 & 0x3ff,
2307 0x1e & 0x3ff,
2308 0x1c & 0x3ff,
2309 0x1a & 0x3ff,
2310 0x18 & 0x3ff,
2311 0x16 & 0x3ff,
2312 0x14 & 0x3ff,
2313 0x11 & 0x3ff,
2314 0xf & 0x3ff,
2315 0xd & 0x3ff,
2316 0xb & 0x3ff,
2317 0x9 & 0x3ff,
2318 0x7 & 0x3ff,
2319 0x5 & 0x3ff,
2320 0x3 & 0x3ff,
2321 0x1 & 0x3ff,
2322 0x3fc & 0x3ff,
2323 0x3f4 & 0x3ff,
2324 0x3ec & 0x3ff,
2325 0x3e5 & 0x3ff,
2326 0x3dd & 0x3ff,
2327 0x3d5 & 0x3ff,
2328 0x3ce & 0x3ff,
2329 0x3c7 & 0x3ff,
2330 0x3bf & 0x3ff,
2331 0x3b8 & 0x3ff,
2332 0x3b1 & 0x3ff,
2333 0x3aa & 0x3ff,
2334 0x3a3 & 0x3ff,
2335 0x39c & 0x3ff,
2336 0x395 & 0x3ff,
2337 0x38e & 0x3ff,
2338 0x388 & 0x3ff,
2339 0x381 & 0x3ff,
2340 0x37a & 0x3ff,
2341 0x374 & 0x3ff,
2342 0x36d & 0x3ff,
2343 0x367 & 0x3ff,
2344 0x361 & 0x3ff,
2345 0x35a & 0x3ff,
2346 0x354 & 0x3ff,
2347 0x34e & 0x3ff,
2348 0x348 & 0x3ff,
2349 0x342 & 0x3ff,
2350 0x33c & 0x3ff,
2351 0x336 & 0x3ff,
2352 0x330 & 0x3ff,
2353 0x32b & 0x3ff,
2354 0x325 & 0x3ff,
2355 0x31f & 0x3ff,
2356 0x31a & 0x3ff,
2357 0x314 & 0x3ff,
2358 0x30f & 0x3ff,
2359 0x309 & 0x3ff,
2360 0x304 & 0x3ff,
2361 0x2fe & 0x3ff,
2362 0x2f9 & 0x3ff,
2363 0x2f4 & 0x3ff,
2364 0x2ee & 0x3ff,
2365 0x2e9 & 0x3ff,
2366 0x2e4 & 0x3ff,
2367 0x2df & 0x3ff,
2368 0x2da & 0x3ff,
2369 0x2d5 & 0x3ff,
2370 0x2d0 & 0x3ff,
2371 0x2cb & 0x3ff,
2372 0x2c6 & 0x3ff,
2373 0x2c1 & 0x3ff,
2374 0x2bd & 0x3ff,
2375 0x2b8 & 0x3ff,
2376 0x2b3 & 0x3ff,
2377 0x2ae & 0x3ff,
2378 0x2aa & 0x3ff,
2379 0x2a5 & 0x3ff,
2380 0x2a1 & 0x3ff,
2381 0x29c & 0x3ff,
2382 0x298 & 0x3ff,
2383 0x293 & 0x3ff,
2384 0x28f & 0x3ff,
2385 0x28a & 0x3ff,
2386 0x286 & 0x3ff,
2387 0x282 & 0x3ff,
2388 0x27d & 0x3ff,
2389 0x279 & 0x3ff,
2390 0x275 & 0x3ff,
2391 0x271 & 0x3ff,
2392 0x26d & 0x3ff,
2393 0x268 & 0x3ff,
2394 0x264 & 0x3ff,
2395 0x260 & 0x3ff,
2396 0x25c & 0x3ff,
2397 0x258 & 0x3ff,
2398 0x254 & 0x3ff,
2399 0x250 & 0x3ff,
2400 0x24c & 0x3ff,
2401 0x249 & 0x3ff,
2402 0x245 & 0x3ff,
2403 0x241 & 0x3ff,
2404 0x23d & 0x3ff,
2405 0x239 & 0x3ff,
2406 0x235 & 0x3ff,
2407 0x232 & 0x3ff,
2408 0x22e & 0x3ff,
2409 0x22a & 0x3ff,
2410 0x227 & 0x3ff,
2411 0x223 & 0x3ff,
2412 0x220 & 0x3ff,
2413 0x21c & 0x3ff,
2414 0x218 & 0x3ff,
2415 0x215 & 0x3ff,
2416 0x211 & 0x3ff,
2417 0x20e & 0x3ff,
2418 0x20a & 0x3ff,
2419 0x207 & 0x3ff,
2420 0x204 & 0x3ff,
2421 0x200 & 0x3ff,
2422 0x1fd & 0x3ff,
2423 0x1f9 & 0x3ff,
2424 0x1f6 & 0x3ff,
2425 0x1f3 & 0x3ff,
2426 0x1f0 & 0x3ff,
2427 0x1ec & 0x3ff,
2428 0x1e9 & 0x3ff,
2429 0x1e6 & 0x3ff,
2430 0x1e3 & 0x3ff,
2431 0x1df & 0x3ff,
2432 0x1dc & 0x3ff,
2433 0x1d9 & 0x3ff,
2434 0x1d6 & 0x3ff,
2435 0x1d3 & 0x3ff,
2436 0x1d0 & 0x3ff,
2437 0x1cd & 0x3ff,
2438 0x1ca & 0x3ff,
2439 0x1c7 & 0x3ff,
2440 0x1c4 & 0x3ff,
2441 0x1c1 & 0x3ff,
2442 0x1be & 0x3ff,
2443 0x1bb & 0x3ff,
2444 0x1b8 & 0x3ff,
2445 0x1b5 & 0x3ff,
2446 0x1b2 & 0x3ff,
2447 0x1af & 0x3ff,
2448 0x1ac & 0x3ff,
2449 0x1aa & 0x3ff,
2450 0
2451 };
2452
2453 /* constant table RECIP_10b_256 */
2454 static const unsigned CONST_TBL_RECIP_10b_256_0[] = {
2455 0x3fc & 0x3ff,
2456 0x3f4 & 0x3ff,
2457 0x3ec & 0x3ff,
2458 0x3e4 & 0x3ff,
2459 0x3dd & 0x3ff,
2460 0x3d5 & 0x3ff,
2461 0x3cd & 0x3ff,
2462 0x3c6 & 0x3ff,
2463 0x3be & 0x3ff,
2464 0x3b7 & 0x3ff,
2465 0x3af & 0x3ff,
2466 0x3a8 & 0x3ff,
2467 0x3a1 & 0x3ff,
2468 0x399 & 0x3ff,
2469 0x392 & 0x3ff,
2470 0x38b & 0x3ff,
2471 0x384 & 0x3ff,
2472 0x37d & 0x3ff,
2473 0x376 & 0x3ff,
2474 0x36f & 0x3ff,
2475 0x368 & 0x3ff,
2476 0x361 & 0x3ff,
2477 0x35b & 0x3ff,
2478 0x354 & 0x3ff,
2479 0x34d & 0x3ff,
2480 0x346 & 0x3ff,
2481 0x340 & 0x3ff,
2482 0x339 & 0x3ff,
2483 0x333 & 0x3ff,
2484 0x32c & 0x3ff,
2485 0x326 & 0x3ff,
2486 0x320 & 0x3ff,
2487 0x319 & 0x3ff,
2488 0x313 & 0x3ff,
2489 0x30d & 0x3ff,
2490 0x307 & 0x3ff,
2491 0x300 & 0x3ff,
2492 0x2fa & 0x3ff,
2493 0x2f4 & 0x3ff,
2494 0x2ee & 0x3ff,
2495 0x2e8 & 0x3ff,
2496 0x2e2 & 0x3ff,
2497 0x2dc & 0x3ff,
2498 0x2d7 & 0x3ff,
2499 0x2d1 & 0x3ff,
2500 0x2cb & 0x3ff,
2501 0x2c5 & 0x3ff,
2502 0x2bf & 0x3ff,
2503 0x2ba & 0x3ff,
2504 0x2b4 & 0x3ff,
2505 0x2af & 0x3ff,
2506 0x2a9 & 0x3ff,
2507 0x2a3 & 0x3ff,
2508 0x29e & 0x3ff,
2509 0x299 & 0x3ff,
2510 0x293 & 0x3ff,
2511 0x28e & 0x3ff,
2512 0x288 & 0x3ff,
2513 0x283 & 0x3ff,
2514 0x27e & 0x3ff,
2515 0x279 & 0x3ff,
2516 0x273 & 0x3ff,
2517 0x26e & 0x3ff,
2518 0x269 & 0x3ff,
2519 0x264 & 0x3ff,
2520 0x25f & 0x3ff,
2521 0x25a & 0x3ff,
2522 0x255 & 0x3ff,
2523 0x250 & 0x3ff,
2524 0x24b & 0x3ff,
2525 0x246 & 0x3ff,
2526 0x241 & 0x3ff,
2527 0x23c & 0x3ff,
2528 0x237 & 0x3ff,
2529 0x232 & 0x3ff,
2530 0x22e & 0x3ff,
2531 0x229 & 0x3ff,
2532 0x224 & 0x3ff,
2533 0x21f & 0x3ff,
2534 0x21b & 0x3ff,
2535 0x216 & 0x3ff,
2536 0x211 & 0x3ff,
2537 0x20d & 0x3ff,
2538 0x208 & 0x3ff,
2539 0x204 & 0x3ff,
2540 0x1ff & 0x3ff,
2541 0x1fb & 0x3ff,
2542 0x1f6 & 0x3ff,
2543 0x1f2 & 0x3ff,
2544 0x1ed & 0x3ff,
2545 0x1e9 & 0x3ff,
2546 0x1e5 & 0x3ff,
2547 0x1e0 & 0x3ff,
2548 0x1dc & 0x3ff,
2549 0x1d8 & 0x3ff,
2550 0x1d4 & 0x3ff,
2551 0x1cf & 0x3ff,
2552 0x1cb & 0x3ff,
2553 0x1c7 & 0x3ff,
2554 0x1c3 & 0x3ff,
2555 0x1bf & 0x3ff,
2556 0x1bb & 0x3ff,
2557 0x1b6 & 0x3ff,
2558 0x1b2 & 0x3ff,
2559 0x1ae & 0x3ff,
2560 0x1aa & 0x3ff,
2561 0x1a6 & 0x3ff,
2562 0x1a2 & 0x3ff,
2563 0x19e & 0x3ff,
2564 0x19a & 0x3ff,
2565 0x197 & 0x3ff,
2566 0x193 & 0x3ff,
2567 0x18f & 0x3ff,
2568 0x18b & 0x3ff,
2569 0x187 & 0x3ff,
2570 0x183 & 0x3ff,
2571 0x17f & 0x3ff,
2572 0x17c & 0x3ff,
2573 0x178 & 0x3ff,
2574 0x174 & 0x3ff,
2575 0x171 & 0x3ff,
2576 0x16d & 0x3ff,
2577 0x169 & 0x3ff,
2578 0x166 & 0x3ff,
2579 0x162 & 0x3ff,
2580 0x15e & 0x3ff,
2581 0x15b & 0x3ff,
2582 0x157 & 0x3ff,
2583 0x154 & 0x3ff,
2584 0x150 & 0x3ff,
2585 0x14d & 0x3ff,
2586 0x149 & 0x3ff,
2587 0x146 & 0x3ff,
2588 0x142 & 0x3ff,
2589 0x13f & 0x3ff,
2590 0x13b & 0x3ff,
2591 0x138 & 0x3ff,
2592 0x134 & 0x3ff,
2593 0x131 & 0x3ff,
2594 0x12e & 0x3ff,
2595 0x12a & 0x3ff,
2596 0x127 & 0x3ff,
2597 0x124 & 0x3ff,
2598 0x120 & 0x3ff,
2599 0x11d & 0x3ff,
2600 0x11a & 0x3ff,
2601 0x117 & 0x3ff,
2602 0x113 & 0x3ff,
2603 0x110 & 0x3ff,
2604 0x10d & 0x3ff,
2605 0x10a & 0x3ff,
2606 0x107 & 0x3ff,
2607 0x103 & 0x3ff,
2608 0x100 & 0x3ff,
2609 0xfd & 0x3ff,
2610 0xfa & 0x3ff,
2611 0xf7 & 0x3ff,
2612 0xf4 & 0x3ff,
2613 0xf1 & 0x3ff,
2614 0xee & 0x3ff,
2615 0xeb & 0x3ff,
2616 0xe8 & 0x3ff,
2617 0xe5 & 0x3ff,
2618 0xe2 & 0x3ff,
2619 0xdf & 0x3ff,
2620 0xdc & 0x3ff,
2621 0xd9 & 0x3ff,
2622 0xd6 & 0x3ff,
2623 0xd3 & 0x3ff,
2624 0xd0 & 0x3ff,
2625 0xcd & 0x3ff,
2626 0xca & 0x3ff,
2627 0xc8 & 0x3ff,
2628 0xc5 & 0x3ff,
2629 0xc2 & 0x3ff,
2630 0xbf & 0x3ff,
2631 0xbc & 0x3ff,
2632 0xb9 & 0x3ff,
2633 0xb7 & 0x3ff,
2634 0xb4 & 0x3ff,
2635 0xb1 & 0x3ff,
2636 0xae & 0x3ff,
2637 0xac & 0x3ff,
2638 0xa9 & 0x3ff,
2639 0xa6 & 0x3ff,
2640 0xa4 & 0x3ff,
2641 0xa1 & 0x3ff,
2642 0x9e & 0x3ff,
2643 0x9c & 0x3ff,
2644 0x99 & 0x3ff,
2645 0x96 & 0x3ff,
2646 0x94 & 0x3ff,
2647 0x91 & 0x3ff,
2648 0x8e & 0x3ff,
2649 0x8c & 0x3ff,
2650 0x89 & 0x3ff,
2651 0x87 & 0x3ff,
2652 0x84 & 0x3ff,
2653 0x82 & 0x3ff,
2654 0x7f & 0x3ff,
2655 0x7c & 0x3ff,
2656 0x7a & 0x3ff,
2657 0x77 & 0x3ff,
2658 0x75 & 0x3ff,
2659 0x73 & 0x3ff,
2660 0x70 & 0x3ff,
2661 0x6e & 0x3ff,
2662 0x6b & 0x3ff,
2663 0x69 & 0x3ff,
2664 0x66 & 0x3ff,
2665 0x64 & 0x3ff,
2666 0x61 & 0x3ff,
2667 0x5f & 0x3ff,
2668 0x5d & 0x3ff,
2669 0x5a & 0x3ff,
2670 0x58 & 0x3ff,
2671 0x56 & 0x3ff,
2672 0x53 & 0x3ff,
2673 0x51 & 0x3ff,
2674 0x4f & 0x3ff,
2675 0x4c & 0x3ff,
2676 0x4a & 0x3ff,
2677 0x48 & 0x3ff,
2678 0x45 & 0x3ff,
2679 0x43 & 0x3ff,
2680 0x41 & 0x3ff,
2681 0x3f & 0x3ff,
2682 0x3c & 0x3ff,
2683 0x3a & 0x3ff,
2684 0x38 & 0x3ff,
2685 0x36 & 0x3ff,
2686 0x33 & 0x3ff,
2687 0x31 & 0x3ff,
2688 0x2f & 0x3ff,
2689 0x2d & 0x3ff,
2690 0x2b & 0x3ff,
2691 0x29 & 0x3ff,
2692 0x26 & 0x3ff,
2693 0x24 & 0x3ff,
2694 0x22 & 0x3ff,
2695 0x20 & 0x3ff,
2696 0x1e & 0x3ff,
2697 0x1c & 0x3ff,
2698 0x1a & 0x3ff,
2699 0x18 & 0x3ff,
2700 0x15 & 0x3ff,
2701 0x13 & 0x3ff,
2702 0x11 & 0x3ff,
2703 0xf & 0x3ff,
2704 0xd & 0x3ff,
2705 0xb & 0x3ff,
2706 0x9 & 0x3ff,
2707 0x7 & 0x3ff,
2708 0x5 & 0x3ff,
2709 0x3 & 0x3ff,
2710 0x1 & 0x3ff,
2711 0
2712 };
2713
2714
2715 /* Instruction operands. */
2716
2717 static int
2718 OperandSem_opnd_sem_MR_0_decode (uint32 *valp)
2719 {
2720 *valp += 2;
2721 return 0;
2722 }
2723
2724 static int
2725 OperandSem_opnd_sem_MR_0_encode (uint32 *valp)
2726 {
2727 int error;
2728 error = ((*valp & ~0x3) != 0) || ((*valp & 0x2) == 0);
2729 *valp = *valp & 1;
2730 return error;
2731 }
2732
2733 static int
2734 OperandSem_opnd_sem_soffsetx4_decode (uint32 *valp)
2735 {
2736 unsigned soffsetx4_out_0;
2737 unsigned soffsetx4_in_0;
2738 soffsetx4_in_0 = *valp & 0x3ffff;
2739 soffsetx4_out_0 = 0x4 + ((((int) soffsetx4_in_0 << 14) >> 14) << 2);
2740 *valp = soffsetx4_out_0;
2741 return 0;
2742 }
2743
2744 static int
2745 OperandSem_opnd_sem_soffsetx4_encode (uint32 *valp)
2746 {
2747 unsigned soffsetx4_in_0;
2748 unsigned soffsetx4_out_0;
2749 soffsetx4_out_0 = *valp;
2750 soffsetx4_in_0 = ((soffsetx4_out_0 - 0x4) >> 2) & 0x3ffff;
2751 *valp = soffsetx4_in_0;
2752 return 0;
2753 }
2754
2755 static int
2756 OperandSem_opnd_sem_immr_decode (uint32 *valp)
2757 {
2758 unsigned immr_out_0;
2759 unsigned immr_in_0;
2760 immr_in_0 = *valp & 0xf;
2761 immr_out_0 = immr_in_0;
2762 *valp = immr_out_0;
2763 return 0;
2764 }
2765
2766 static int
2767 OperandSem_opnd_sem_immr_encode (uint32 *valp)
2768 {
2769 unsigned immr_in_0;
2770 unsigned immr_out_0;
2771 immr_out_0 = *valp;
2772 immr_in_0 = (immr_out_0 & 0xf);
2773 *valp = immr_in_0;
2774 return 0;
2775 }
2776
2777 static int
2778 OperandSem_opnd_sem_uimm12x8_decode (uint32 *valp)
2779 {
2780 unsigned uimm12x8_out_0;
2781 unsigned uimm12x8_in_0;
2782 uimm12x8_in_0 = *valp & 0xfff;
2783 uimm12x8_out_0 = uimm12x8_in_0 << 3;
2784 *valp = uimm12x8_out_0;
2785 return 0;
2786 }
2787
2788 static int
2789 OperandSem_opnd_sem_uimm12x8_encode (uint32 *valp)
2790 {
2791 unsigned uimm12x8_in_0;
2792 unsigned uimm12x8_out_0;
2793 uimm12x8_out_0 = *valp;
2794 uimm12x8_in_0 = ((uimm12x8_out_0 >> 3) & 0xfff);
2795 *valp = uimm12x8_in_0;
2796 return 0;
2797 }
2798
2799 static int
2800 OperandSem_opnd_sem_simm4_decode (uint32 *valp)
2801 {
2802 unsigned simm4_out_0;
2803 unsigned simm4_in_0;
2804 simm4_in_0 = *valp & 0xf;
2805 simm4_out_0 = ((int) simm4_in_0 << 28) >> 28;
2806 *valp = simm4_out_0;
2807 return 0;
2808 }
2809
2810 static int
2811 OperandSem_opnd_sem_simm4_encode (uint32 *valp)
2812 {
2813 unsigned simm4_in_0;
2814 unsigned simm4_out_0;
2815 simm4_out_0 = *valp;
2816 simm4_in_0 = (simm4_out_0 & 0xf);
2817 *valp = simm4_in_0;
2818 return 0;
2819 }
2820
2821 static int
2822 OperandSem_opnd_sem_AR_decode (uint32 *valp ATTRIBUTE_UNUSED)
2823 {
2824 return 0;
2825 }
2826
2827 static int
2828 OperandSem_opnd_sem_AR_encode (uint32 *valp)
2829 {
2830 int error;
2831 error = (*valp >= 32);
2832 return error;
2833 }
2834
2835 static int
2836 OperandSem_opnd_sem_AR_0_decode (uint32 *valp ATTRIBUTE_UNUSED)
2837 {
2838 return 0;
2839 }
2840
2841 static int
2842 OperandSem_opnd_sem_AR_0_encode (uint32 *valp)
2843 {
2844 int error;
2845 error = (*valp >= 32);
2846 return error;
2847 }
2848
2849 static int
2850 OperandSem_opnd_sem_AR_4_decode (uint32 *valp ATTRIBUTE_UNUSED)
2851 {
2852 return 0;
2853 }
2854
2855 static int
2856 OperandSem_opnd_sem_AR_4_encode (uint32 *valp)
2857 {
2858 int error;
2859 error = (*valp >= 32);
2860 return error;
2861 }
2862
2863 static int
2864 OperandSem_opnd_sem_AR_8_decode (uint32 *valp ATTRIBUTE_UNUSED)
2865 {
2866 return 0;
2867 }
2868
2869 static int
2870 OperandSem_opnd_sem_AR_8_encode (uint32 *valp)
2871 {
2872 int error;
2873 error = (*valp >= 32);
2874 return error;
2875 }
2876
2877 static int
2878 OperandSem_opnd_sem_AR_12_decode (uint32 *valp ATTRIBUTE_UNUSED)
2879 {
2880 return 0;
2881 }
2882
2883 static int
2884 OperandSem_opnd_sem_AR_12_encode (uint32 *valp)
2885 {
2886 int error;
2887 error = (*valp >= 32);
2888 return error;
2889 }
2890
2891 static int
2892 OperandSem_opnd_sem_AR_entry_decode (uint32 *valp ATTRIBUTE_UNUSED)
2893 {
2894 return 0;
2895 }
2896
2897 static int
2898 OperandSem_opnd_sem_AR_entry_encode (uint32 *valp)
2899 {
2900 int error;
2901 error = (*valp >= 32);
2902 return error;
2903 }
2904
2905 static int
2906 OperandSem_opnd_sem_immrx4_decode (uint32 *valp)
2907 {
2908 unsigned immrx4_out_0;
2909 unsigned immrx4_in_0;
2910 immrx4_in_0 = *valp & 0xf;
2911 immrx4_out_0 = (((0xfffffff) << 4) | immrx4_in_0) << 2;
2912 *valp = immrx4_out_0;
2913 return 0;
2914 }
2915
2916 static int
2917 OperandSem_opnd_sem_immrx4_encode (uint32 *valp)
2918 {
2919 unsigned immrx4_in_0;
2920 unsigned immrx4_out_0;
2921 immrx4_out_0 = *valp;
2922 immrx4_in_0 = ((immrx4_out_0 >> 2) & 0xf);
2923 *valp = immrx4_in_0;
2924 return 0;
2925 }
2926
2927 static int
2928 OperandSem_opnd_sem_lsi4x4_decode (uint32 *valp)
2929 {
2930 unsigned lsi4x4_out_0;
2931 unsigned lsi4x4_in_0;
2932 lsi4x4_in_0 = *valp & 0xf;
2933 lsi4x4_out_0 = lsi4x4_in_0 << 2;
2934 *valp = lsi4x4_out_0;
2935 return 0;
2936 }
2937
2938 static int
2939 OperandSem_opnd_sem_lsi4x4_encode (uint32 *valp)
2940 {
2941 unsigned lsi4x4_in_0;
2942 unsigned lsi4x4_out_0;
2943 lsi4x4_out_0 = *valp;
2944 lsi4x4_in_0 = ((lsi4x4_out_0 >> 2) & 0xf);
2945 *valp = lsi4x4_in_0;
2946 return 0;
2947 }
2948
2949 static int
2950 OperandSem_opnd_sem_simm7_decode (uint32 *valp)
2951 {
2952 unsigned simm7_out_0;
2953 unsigned simm7_in_0;
2954 simm7_in_0 = *valp & 0x7f;
2955 simm7_out_0 = ((((-((((simm7_in_0 >> 6) & 1)) & (((simm7_in_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | simm7_in_0;
2956 *valp = simm7_out_0;
2957 return 0;
2958 }
2959
2960 static int
2961 OperandSem_opnd_sem_simm7_encode (uint32 *valp)
2962 {
2963 unsigned simm7_in_0;
2964 unsigned simm7_out_0;
2965 simm7_out_0 = *valp;
2966 simm7_in_0 = (simm7_out_0 & 0x7f);
2967 *valp = simm7_in_0;
2968 return 0;
2969 }
2970
2971 static int
2972 OperandSem_opnd_sem_uimm6_decode (uint32 *valp)
2973 {
2974 unsigned uimm6_out_0;
2975 unsigned uimm6_in_0;
2976 uimm6_in_0 = *valp & 0x3f;
2977 uimm6_out_0 = 0x4 + (((0) << 6) | uimm6_in_0);
2978 *valp = uimm6_out_0;
2979 return 0;
2980 }
2981
2982 static int
2983 OperandSem_opnd_sem_uimm6_encode (uint32 *valp)
2984 {
2985 unsigned uimm6_in_0;
2986 unsigned uimm6_out_0;
2987 uimm6_out_0 = *valp;
2988 uimm6_in_0 = (uimm6_out_0 - 0x4) & 0x3f;
2989 *valp = uimm6_in_0;
2990 return 0;
2991 }
2992
2993 static int
2994 OperandSem_opnd_sem_ai4const_decode (uint32 *valp)
2995 {
2996 unsigned ai4const_out_0;
2997 unsigned ai4const_in_0;
2998 ai4const_in_0 = *valp & 0xf;
2999 ai4const_out_0 = CONST_TBL_ai4c_0[ai4const_in_0 & 0xf];
3000 *valp = ai4const_out_0;
3001 return 0;
3002 }
3003
3004 static int
3005 OperandSem_opnd_sem_ai4const_encode (uint32 *valp)
3006 {
3007 unsigned ai4const_in_0;
3008 unsigned ai4const_out_0;
3009 ai4const_out_0 = *valp;
3010 switch (ai4const_out_0)
3011 {
3012 case 0xffffffff: ai4const_in_0 = 0; break;
3013 case 0x1: ai4const_in_0 = 0x1; break;
3014 case 0x2: ai4const_in_0 = 0x2; break;
3015 case 0x3: ai4const_in_0 = 0x3; break;
3016 case 0x4: ai4const_in_0 = 0x4; break;
3017 case 0x5: ai4const_in_0 = 0x5; break;
3018 case 0x6: ai4const_in_0 = 0x6; break;
3019 case 0x7: ai4const_in_0 = 0x7; break;
3020 case 0x8: ai4const_in_0 = 0x8; break;
3021 case 0x9: ai4const_in_0 = 0x9; break;
3022 case 0xa: ai4const_in_0 = 0xa; break;
3023 case 0xb: ai4const_in_0 = 0xb; break;
3024 case 0xc: ai4const_in_0 = 0xc; break;
3025 case 0xd: ai4const_in_0 = 0xd; break;
3026 case 0xe: ai4const_in_0 = 0xe; break;
3027 default: ai4const_in_0 = 0xf; break;
3028 }
3029 *valp = ai4const_in_0;
3030 return 0;
3031 }
3032
3033 static int
3034 OperandSem_opnd_sem_b4const_decode (uint32 *valp)
3035 {
3036 unsigned b4const_out_0;
3037 unsigned b4const_in_0;
3038 b4const_in_0 = *valp & 0xf;
3039 b4const_out_0 = CONST_TBL_b4c_0[b4const_in_0 & 0xf];
3040 *valp = b4const_out_0;
3041 return 0;
3042 }
3043
3044 static int
3045 OperandSem_opnd_sem_b4const_encode (uint32 *valp)
3046 {
3047 unsigned b4const_in_0;
3048 unsigned b4const_out_0;
3049 b4const_out_0 = *valp;
3050 switch (b4const_out_0)
3051 {
3052 case 0xffffffff: b4const_in_0 = 0; break;
3053 case 0x1: b4const_in_0 = 0x1; break;
3054 case 0x2: b4const_in_0 = 0x2; break;
3055 case 0x3: b4const_in_0 = 0x3; break;
3056 case 0x4: b4const_in_0 = 0x4; break;
3057 case 0x5: b4const_in_0 = 0x5; break;
3058 case 0x6: b4const_in_0 = 0x6; break;
3059 case 0x7: b4const_in_0 = 0x7; break;
3060 case 0x8: b4const_in_0 = 0x8; break;
3061 case 0xa: b4const_in_0 = 0x9; break;
3062 case 0xc: b4const_in_0 = 0xa; break;
3063 case 0x10: b4const_in_0 = 0xb; break;
3064 case 0x20: b4const_in_0 = 0xc; break;
3065 case 0x40: b4const_in_0 = 0xd; break;
3066 case 0x80: b4const_in_0 = 0xe; break;
3067 default: b4const_in_0 = 0xf; break;
3068 }
3069 *valp = b4const_in_0;
3070 return 0;
3071 }
3072
3073 static int
3074 OperandSem_opnd_sem_b4constu_decode (uint32 *valp)
3075 {
3076 unsigned b4constu_out_0;
3077 unsigned b4constu_in_0;
3078 b4constu_in_0 = *valp & 0xf;
3079 b4constu_out_0 = CONST_TBL_b4cu_0[b4constu_in_0 & 0xf];
3080 *valp = b4constu_out_0;
3081 return 0;
3082 }
3083
3084 static int
3085 OperandSem_opnd_sem_b4constu_encode (uint32 *valp)
3086 {
3087 unsigned b4constu_in_0;
3088 unsigned b4constu_out_0;
3089 b4constu_out_0 = *valp;
3090 switch (b4constu_out_0)
3091 {
3092 case 0x8000: b4constu_in_0 = 0; break;
3093 case 0x10000: b4constu_in_0 = 0x1; break;
3094 case 0x2: b4constu_in_0 = 0x2; break;
3095 case 0x3: b4constu_in_0 = 0x3; break;
3096 case 0x4: b4constu_in_0 = 0x4; break;
3097 case 0x5: b4constu_in_0 = 0x5; break;
3098 case 0x6: b4constu_in_0 = 0x6; break;
3099 case 0x7: b4constu_in_0 = 0x7; break;
3100 case 0x8: b4constu_in_0 = 0x8; break;
3101 case 0xa: b4constu_in_0 = 0x9; break;
3102 case 0xc: b4constu_in_0 = 0xa; break;
3103 case 0x10: b4constu_in_0 = 0xb; break;
3104 case 0x20: b4constu_in_0 = 0xc; break;
3105 case 0x40: b4constu_in_0 = 0xd; break;
3106 case 0x80: b4constu_in_0 = 0xe; break;
3107 default: b4constu_in_0 = 0xf; break;
3108 }
3109 *valp = b4constu_in_0;
3110 return 0;
3111 }
3112
3113 static int
3114 OperandSem_opnd_sem_immt_decode (uint32 *valp)
3115 {
3116 unsigned immt_out_0;
3117 unsigned immt_in_0;
3118 immt_in_0 = *valp & 0xf;
3119 immt_out_0 = immt_in_0;
3120 *valp = immt_out_0;
3121 return 0;
3122 }
3123
3124 static int
3125 OperandSem_opnd_sem_immt_encode (uint32 *valp)
3126 {
3127 unsigned immt_in_0;
3128 unsigned immt_out_0;
3129 immt_out_0 = *valp;
3130 immt_in_0 = immt_out_0 & 0xf;
3131 *valp = immt_in_0;
3132 return 0;
3133 }
3134
3135 static int
3136 OperandSem_opnd_sem_uimms8_decode (uint32 *valp)
3137 {
3138 unsigned uimms8_out_0;
3139 unsigned uimms8_in_0;
3140 uimms8_in_0 = *valp & 0x7;
3141 uimms8_out_0 = uimms8_in_0;
3142 *valp = uimms8_out_0;
3143 return 0;
3144 }
3145
3146 static int
3147 OperandSem_opnd_sem_uimms8_encode (uint32 *valp)
3148 {
3149 unsigned uimms8_in_0;
3150 unsigned uimms8_out_0;
3151 uimms8_out_0 = *valp;
3152 uimms8_in_0 = uimms8_out_0 & 0x7;
3153 *valp = uimms8_in_0;
3154 return 0;
3155 }
3156
3157 static int
3158 OperandSem_opnd_sem_uimm8_decode (uint32 *valp)
3159 {
3160 unsigned uimm8_out_0;
3161 unsigned uimm8_in_0;
3162 uimm8_in_0 = *valp & 0xff;
3163 uimm8_out_0 = uimm8_in_0;
3164 *valp = uimm8_out_0;
3165 return 0;
3166 }
3167
3168 static int
3169 OperandSem_opnd_sem_uimm8_encode (uint32 *valp)
3170 {
3171 unsigned uimm8_in_0;
3172 unsigned uimm8_out_0;
3173 uimm8_out_0 = *valp;
3174 uimm8_in_0 = (uimm8_out_0 & 0xff);
3175 *valp = uimm8_in_0;
3176 return 0;
3177 }
3178
3179 static int
3180 OperandSem_opnd_sem_uimm8x2_decode (uint32 *valp)
3181 {
3182 unsigned uimm8x2_out_0;
3183 unsigned uimm8x2_in_0;
3184 uimm8x2_in_0 = *valp & 0xff;
3185 uimm8x2_out_0 = uimm8x2_in_0 << 1;
3186 *valp = uimm8x2_out_0;
3187 return 0;
3188 }
3189
3190 static int
3191 OperandSem_opnd_sem_uimm8x2_encode (uint32 *valp)
3192 {
3193 unsigned uimm8x2_in_0;
3194 unsigned uimm8x2_out_0;
3195 uimm8x2_out_0 = *valp;
3196 uimm8x2_in_0 = ((uimm8x2_out_0 >> 1) & 0xff);
3197 *valp = uimm8x2_in_0;
3198 return 0;
3199 }
3200
3201 static int
3202 OperandSem_opnd_sem_uimm8x4_decode (uint32 *valp)
3203 {
3204 unsigned uimm8x4_out_0;
3205 unsigned uimm8x4_in_0;
3206 uimm8x4_in_0 = *valp & 0xff;
3207 uimm8x4_out_0 = uimm8x4_in_0 << 2;
3208 *valp = uimm8x4_out_0;
3209 return 0;
3210 }
3211
3212 static int
3213 OperandSem_opnd_sem_uimm8x4_encode (uint32 *valp)
3214 {
3215 unsigned uimm8x4_in_0;
3216 unsigned uimm8x4_out_0;
3217 uimm8x4_out_0 = *valp;
3218 uimm8x4_in_0 = ((uimm8x4_out_0 >> 2) & 0xff);
3219 *valp = uimm8x4_in_0;
3220 return 0;
3221 }
3222
3223 static int
3224 OperandSem_opnd_sem_uimm4x16_decode (uint32 *valp)
3225 {
3226 unsigned uimm4x16_out_0;
3227 unsigned uimm4x16_in_0;
3228 uimm4x16_in_0 = *valp & 0xf;
3229 uimm4x16_out_0 = uimm4x16_in_0 << 4;
3230 *valp = uimm4x16_out_0;
3231 return 0;
3232 }
3233
3234 static int
3235 OperandSem_opnd_sem_uimm4x16_encode (uint32 *valp)
3236 {
3237 unsigned uimm4x16_in_0;
3238 unsigned uimm4x16_out_0;
3239 uimm4x16_out_0 = *valp;
3240 uimm4x16_in_0 = ((uimm4x16_out_0 >> 4) & 0xf);
3241 *valp = uimm4x16_in_0;
3242 return 0;
3243 }
3244
3245 static int
3246 OperandSem_opnd_sem_uimmrx4_decode (uint32 *valp)
3247 {
3248 unsigned uimmrx4_out_0;
3249 unsigned uimmrx4_in_0;
3250 uimmrx4_in_0 = *valp & 0xf;
3251 uimmrx4_out_0 = uimmrx4_in_0 << 2;
3252 *valp = uimmrx4_out_0;
3253 return 0;
3254 }
3255
3256 static int
3257 OperandSem_opnd_sem_uimmrx4_encode (uint32 *valp)
3258 {
3259 unsigned uimmrx4_in_0;
3260 unsigned uimmrx4_out_0;
3261 uimmrx4_out_0 = *valp;
3262 uimmrx4_in_0 = ((uimmrx4_out_0 >> 2) & 0xf);
3263 *valp = uimmrx4_in_0;
3264 return 0;
3265 }
3266
3267 static int
3268 OperandSem_opnd_sem_simm8_decode (uint32 *valp)
3269 {
3270 unsigned simm8_out_0;
3271 unsigned simm8_in_0;
3272 simm8_in_0 = *valp & 0xff;
3273 simm8_out_0 = ((int) simm8_in_0 << 24) >> 24;
3274 *valp = simm8_out_0;
3275 return 0;
3276 }
3277
3278 static int
3279 OperandSem_opnd_sem_simm8_encode (uint32 *valp)
3280 {
3281 unsigned simm8_in_0;
3282 unsigned simm8_out_0;
3283 simm8_out_0 = *valp;
3284 simm8_in_0 = (simm8_out_0 & 0xff);
3285 *valp = simm8_in_0;
3286 return 0;
3287 }
3288
3289 static int
3290 OperandSem_opnd_sem_simm8x256_decode (uint32 *valp)
3291 {
3292 unsigned simm8x256_out_0;
3293 unsigned simm8x256_in_0;
3294 simm8x256_in_0 = *valp & 0xff;
3295 simm8x256_out_0 = (((int) simm8x256_in_0 << 24) >> 24) << 8;
3296 *valp = simm8x256_out_0;
3297 return 0;
3298 }
3299
3300 static int
3301 OperandSem_opnd_sem_simm8x256_encode (uint32 *valp)
3302 {
3303 unsigned simm8x256_in_0;
3304 unsigned simm8x256_out_0;
3305 simm8x256_out_0 = *valp;
3306 simm8x256_in_0 = ((simm8x256_out_0 >> 8) & 0xff);
3307 *valp = simm8x256_in_0;
3308 return 0;
3309 }
3310
3311 static int
3312 OperandSem_opnd_sem_simm12b_decode (uint32 *valp)
3313 {
3314 unsigned simm12b_out_0;
3315 unsigned simm12b_in_0;
3316 simm12b_in_0 = *valp & 0xfff;
3317 simm12b_out_0 = ((int) simm12b_in_0 << 20) >> 20;
3318 *valp = simm12b_out_0;
3319 return 0;
3320 }
3321
3322 static int
3323 OperandSem_opnd_sem_simm12b_encode (uint32 *valp)
3324 {
3325 unsigned simm12b_in_0;
3326 unsigned simm12b_out_0;
3327 simm12b_out_0 = *valp;
3328 simm12b_in_0 = (simm12b_out_0 & 0xfff);
3329 *valp = simm12b_in_0;
3330 return 0;
3331 }
3332
3333 static int
3334 OperandSem_opnd_sem_msalp32_decode (uint32 *valp)
3335 {
3336 unsigned msalp32_out_0;
3337 unsigned msalp32_in_0;
3338 msalp32_in_0 = *valp & 0x1f;
3339 msalp32_out_0 = 0x20 - msalp32_in_0;
3340 *valp = msalp32_out_0;
3341 return 0;
3342 }
3343
3344 static int
3345 OperandSem_opnd_sem_msalp32_encode (uint32 *valp)
3346 {
3347 unsigned msalp32_in_0;
3348 unsigned msalp32_out_0;
3349 msalp32_out_0 = *valp;
3350 msalp32_in_0 = (0x20 - msalp32_out_0) & 0x1f;
3351 *valp = msalp32_in_0;
3352 return 0;
3353 }
3354
3355 static int
3356 OperandSem_opnd_sem_op2p1_decode (uint32 *valp)
3357 {
3358 unsigned op2p1_out_0;
3359 unsigned op2p1_in_0;
3360 op2p1_in_0 = *valp & 0xf;
3361 op2p1_out_0 = op2p1_in_0 + 0x1;
3362 *valp = op2p1_out_0;
3363 return 0;
3364 }
3365
3366 static int
3367 OperandSem_opnd_sem_op2p1_encode (uint32 *valp)
3368 {
3369 unsigned op2p1_in_0;
3370 unsigned op2p1_out_0;
3371 op2p1_out_0 = *valp;
3372 op2p1_in_0 = (op2p1_out_0 - 0x1) & 0xf;
3373 *valp = op2p1_in_0;
3374 return 0;
3375 }
3376
3377 static int
3378 OperandSem_opnd_sem_label8_decode (uint32 *valp)
3379 {
3380 unsigned label8_out_0;
3381 unsigned label8_in_0;
3382 label8_in_0 = *valp & 0xff;
3383 label8_out_0 = 0x4 + (((int) label8_in_0 << 24) >> 24);
3384 *valp = label8_out_0;
3385 return 0;
3386 }
3387
3388 static int
3389 OperandSem_opnd_sem_label8_encode (uint32 *valp)
3390 {
3391 unsigned label8_in_0;
3392 unsigned label8_out_0;
3393 label8_out_0 = *valp;
3394 label8_in_0 = (label8_out_0 - 0x4) & 0xff;
3395 *valp = label8_in_0;
3396 return 0;
3397 }
3398
3399 static int
3400 OperandSem_opnd_sem_ulabel8_decode (uint32 *valp)
3401 {
3402 unsigned ulabel8_out_0;
3403 unsigned ulabel8_in_0;
3404 ulabel8_in_0 = *valp & 0xff;
3405 ulabel8_out_0 = 0x4 + (((0) << 8) | ulabel8_in_0);
3406 *valp = ulabel8_out_0;
3407 return 0;
3408 }
3409
3410 static int
3411 OperandSem_opnd_sem_ulabel8_encode (uint32 *valp)
3412 {
3413 unsigned ulabel8_in_0;
3414 unsigned ulabel8_out_0;
3415 ulabel8_out_0 = *valp;
3416 ulabel8_in_0 = (ulabel8_out_0 - 0x4) & 0xff;
3417 *valp = ulabel8_in_0;
3418 return 0;
3419 }
3420
3421 static int
3422 OperandSem_opnd_sem_label12_decode (uint32 *valp)
3423 {
3424 unsigned label12_out_0;
3425 unsigned label12_in_0;
3426 label12_in_0 = *valp & 0xfff;
3427 label12_out_0 = 0x4 + (((int) label12_in_0 << 20) >> 20);
3428 *valp = label12_out_0;
3429 return 0;
3430 }
3431
3432 static int
3433 OperandSem_opnd_sem_label12_encode (uint32 *valp)
3434 {
3435 unsigned label12_in_0;
3436 unsigned label12_out_0;
3437 label12_out_0 = *valp;
3438 label12_in_0 = (label12_out_0 - 0x4) & 0xfff;
3439 *valp = label12_in_0;
3440 return 0;
3441 }
3442
3443 static int
3444 OperandSem_opnd_sem_soffset_decode (uint32 *valp)
3445 {
3446 unsigned soffset_out_0;
3447 unsigned soffset_in_0;
3448 soffset_in_0 = *valp & 0x3ffff;
3449 soffset_out_0 = 0x4 + (((int) soffset_in_0 << 14) >> 14);
3450 *valp = soffset_out_0;
3451 return 0;
3452 }
3453
3454 static int
3455 OperandSem_opnd_sem_soffset_encode (uint32 *valp)
3456 {
3457 unsigned soffset_in_0;
3458 unsigned soffset_out_0;
3459 soffset_out_0 = *valp;
3460 soffset_in_0 = (soffset_out_0 - 0x4) & 0x3ffff;
3461 *valp = soffset_in_0;
3462 return 0;
3463 }
3464
3465 static int
3466 OperandSem_opnd_sem_uimm16x4_decode (uint32 *valp)
3467 {
3468 unsigned uimm16x4_out_0;
3469 unsigned uimm16x4_in_0;
3470 uimm16x4_in_0 = *valp & 0xffff;
3471 uimm16x4_out_0 = (((0xffff) << 16) | uimm16x4_in_0) << 2;
3472 *valp = uimm16x4_out_0;
3473 return 0;
3474 }
3475
3476 static int
3477 OperandSem_opnd_sem_uimm16x4_encode (uint32 *valp)
3478 {
3479 unsigned uimm16x4_in_0;
3480 unsigned uimm16x4_out_0;
3481 uimm16x4_out_0 = *valp;
3482 uimm16x4_in_0 = (uimm16x4_out_0 >> 2) & 0xffff;
3483 *valp = uimm16x4_in_0;
3484 return 0;
3485 }
3486
3487 static int
3488 OperandSem_opnd_sem_MR_decode (uint32 *valp ATTRIBUTE_UNUSED)
3489 {
3490 return 0;
3491 }
3492
3493 static int
3494 OperandSem_opnd_sem_MR_encode (uint32 *valp)
3495 {
3496 int error;
3497 error = (*valp >= 4);
3498 return error;
3499 }
3500
3501 static int
3502 OperandSem_opnd_sem_MR_1_decode (uint32 *valp ATTRIBUTE_UNUSED)
3503 {
3504 return 0;
3505 }
3506
3507 static int
3508 OperandSem_opnd_sem_MR_1_encode (uint32 *valp)
3509 {
3510 int error;
3511 error = (*valp >= 4);
3512 return error;
3513 }
3514
3515 static int
3516 OperandSem_opnd_sem_MR_2_decode (uint32 *valp ATTRIBUTE_UNUSED)
3517 {
3518 return 0;
3519 }
3520
3521 static int
3522 OperandSem_opnd_sem_MR_2_encode (uint32 *valp)
3523 {
3524 int error;
3525 error = (*valp >= 4);
3526 return error;
3527 }
3528
3529 static int
3530 OperandSem_opnd_sem_MR_3_decode (uint32 *valp ATTRIBUTE_UNUSED)
3531 {
3532 return 0;
3533 }
3534
3535 static int
3536 OperandSem_opnd_sem_MR_3_encode (uint32 *valp)
3537 {
3538 int error;
3539 error = (*valp >= 4);
3540 return error;
3541 }
3542
3543 static int
3544 OperandSem_opnd_sem_MR_4_decode (uint32 *valp ATTRIBUTE_UNUSED)
3545 {
3546 return 0;
3547 }
3548
3549 static int
3550 OperandSem_opnd_sem_MR_4_encode (uint32 *valp)
3551 {
3552 int error;
3553 error = (*valp >= 4);
3554 return error;
3555 }
3556
3557 static int
3558 OperandSem_opnd_sem_MR_5_decode (uint32 *valp ATTRIBUTE_UNUSED)
3559 {
3560 return 0;
3561 }
3562
3563 static int
3564 OperandSem_opnd_sem_MR_5_encode (uint32 *valp)
3565 {
3566 int error;
3567 error = (*valp >= 4);
3568 return error;
3569 }
3570
3571 static int
3572 OperandSem_opnd_sem_imms_decode (uint32 *valp)
3573 {
3574 unsigned imms_out_0;
3575 unsigned imms_in_0;
3576 imms_in_0 = *valp & 0xf;
3577 imms_out_0 = imms_in_0;
3578 *valp = imms_out_0;
3579 return 0;
3580 }
3581
3582 static int
3583 OperandSem_opnd_sem_imms_encode (uint32 *valp)
3584 {
3585 unsigned imms_in_0;
3586 unsigned imms_out_0;
3587 imms_out_0 = *valp;
3588 imms_in_0 = imms_out_0 & 0xf;
3589 *valp = imms_in_0;
3590 return 0;
3591 }
3592
3593 static int
3594 OperandSem_opnd_sem_BR_decode (uint32 *valp ATTRIBUTE_UNUSED)
3595 {
3596 return 0;
3597 }
3598
3599 static int
3600 OperandSem_opnd_sem_BR_encode (uint32 *valp)
3601 {
3602 int error;
3603 error = (*valp >= 16);
3604 return error;
3605 }
3606
3607 static int
3608 OperandSem_opnd_sem_BR2_decode (uint32 *valp)
3609 {
3610 *valp = *valp << 1;
3611 return 0;
3612 }
3613
3614 static int
3615 OperandSem_opnd_sem_BR2_encode (uint32 *valp)
3616 {
3617 int error;
3618 error = (*valp >= 16) || ((*valp & 1) != 0);
3619 *valp = *valp >> 1;
3620 return error;
3621 }
3622
3623 static int
3624 OperandSem_opnd_sem_BR4_decode (uint32 *valp)
3625 {
3626 *valp = *valp << 2;
3627 return 0;
3628 }
3629
3630 static int
3631 OperandSem_opnd_sem_BR4_encode (uint32 *valp)
3632 {
3633 int error;
3634 error = (*valp >= 16) || ((*valp & 3) != 0);
3635 *valp = *valp >> 2;
3636 return error;
3637 }
3638
3639 static int
3640 OperandSem_opnd_sem_BR8_decode (uint32 *valp)
3641 {
3642 *valp = *valp << 3;
3643 return 0;
3644 }
3645
3646 static int
3647 OperandSem_opnd_sem_BR8_encode (uint32 *valp)
3648 {
3649 int error;
3650 error = (*valp >= 16) || ((*valp & 7) != 0);
3651 *valp = *valp >> 3;
3652 return error;
3653 }
3654
3655 static int
3656 OperandSem_opnd_sem_BR16_decode (uint32 *valp)
3657 {
3658 *valp = *valp << 4;
3659 return 0;
3660 }
3661
3662 static int
3663 OperandSem_opnd_sem_BR16_encode (uint32 *valp)
3664 {
3665 int error;
3666 error = (*valp >= 16) || ((*valp & 15) != 0);
3667 *valp = *valp >> 4;
3668 return error;
3669 }
3670
3671 static int
3672 OperandSem_opnd_sem_tp7_decode (uint32 *valp)
3673 {
3674 unsigned tp7_out_0;
3675 unsigned tp7_in_0;
3676 tp7_in_0 = *valp & 0xf;
3677 tp7_out_0 = tp7_in_0 + 0x7;
3678 *valp = tp7_out_0;
3679 return 0;
3680 }
3681
3682 static int
3683 OperandSem_opnd_sem_tp7_encode (uint32 *valp)
3684 {
3685 unsigned tp7_in_0;
3686 unsigned tp7_out_0;
3687 tp7_out_0 = *valp;
3688 tp7_in_0 = (tp7_out_0 - 0x7) & 0xf;
3689 *valp = tp7_in_0;
3690 return 0;
3691 }
3692
3693 static int
3694 OperandSem_opnd_sem_xt_wbr15_label_decode (uint32 *valp)
3695 {
3696 unsigned xt_wbr15_label_out_0;
3697 unsigned xt_wbr15_label_in_0;
3698 xt_wbr15_label_in_0 = *valp & 0x7fff;
3699 xt_wbr15_label_out_0 = 0x4 + (((int) xt_wbr15_label_in_0 << 17) >> 17);
3700 *valp = xt_wbr15_label_out_0;
3701 return 0;
3702 }
3703
3704 static int
3705 OperandSem_opnd_sem_xt_wbr15_label_encode (uint32 *valp)
3706 {
3707 unsigned xt_wbr15_label_in_0;
3708 unsigned xt_wbr15_label_out_0;
3709 xt_wbr15_label_out_0 = *valp;
3710 xt_wbr15_label_in_0 = (xt_wbr15_label_out_0 - 0x4) & 0x7fff;
3711 *valp = xt_wbr15_label_in_0;
3712 return 0;
3713 }
3714
3715 static int
3716 OperandSem_opnd_sem_xt_wbr18_label_decode (uint32 *valp)
3717 {
3718 unsigned xt_wbr18_label_out_0;
3719 unsigned xt_wbr18_label_in_0;
3720 xt_wbr18_label_in_0 = *valp & 0x3ffff;
3721 xt_wbr18_label_out_0 = 0x4 + (((int) xt_wbr18_label_in_0 << 14) >> 14);
3722 *valp = xt_wbr18_label_out_0;
3723 return 0;
3724 }
3725
3726 static int
3727 OperandSem_opnd_sem_xt_wbr18_label_encode (uint32 *valp)
3728 {
3729 unsigned xt_wbr18_label_in_0;
3730 unsigned xt_wbr18_label_out_0;
3731 xt_wbr18_label_out_0 = *valp;
3732 xt_wbr18_label_in_0 = (xt_wbr18_label_out_0 - 0x4) & 0x3ffff;
3733 *valp = xt_wbr18_label_in_0;
3734 return 0;
3735 }
3736
3737 static int
3738 OperandSem_opnd_sem_FR_decode (uint32 *valp ATTRIBUTE_UNUSED)
3739 {
3740 return 0;
3741 }
3742
3743 static int
3744 OperandSem_opnd_sem_FR_encode (uint32 *valp)
3745 {
3746 int error;
3747 error = (*valp >= 16);
3748 return error;
3749 }
3750
3751 static int
3752 OperandSem_opnd_sem_imm_t_decode (uint32 *valp)
3753 {
3754 unsigned imm_t_out_0;
3755 unsigned imm_t_in_0;
3756 imm_t_in_0 = *valp & 0xf;
3757 imm_t_out_0 = (0 << 4) | imm_t_in_0;
3758 *valp = imm_t_out_0;
3759 return 0;
3760 }
3761
3762 static int
3763 OperandSem_opnd_sem_imm_t_encode (uint32 *valp)
3764 {
3765 unsigned imm_t_in_0;
3766 unsigned imm_t_out_0;
3767 imm_t_out_0 = *valp;
3768 imm_t_in_0 = (imm_t_out_0 & 0xf);
3769 *valp = imm_t_in_0;
3770 return 0;
3771 }
3772
3773 static int
3774 OperandSem_opnd_sem_imm8x4_decode (uint32 *valp)
3775 {
3776 unsigned imm8x4_out_0;
3777 unsigned imm8x4_in_0;
3778 imm8x4_in_0 = *valp & 0xff;
3779 imm8x4_out_0 = (0 << 10) | (imm8x4_in_0 << 2) | 0;
3780 *valp = imm8x4_out_0;
3781 return 0;
3782 }
3783
3784 static int
3785 OperandSem_opnd_sem_imm8x4_encode (uint32 *valp)
3786 {
3787 unsigned imm8x4_in_0;
3788 unsigned imm8x4_out_0;
3789 imm8x4_out_0 = *valp;
3790 imm8x4_in_0 = ((imm8x4_out_0 >> 2) & 0xff);
3791 *valp = imm8x4_in_0;
3792 return 0;
3793 }
3794
3795 static int
3796 OperandSem_opnd_sem_imm8x8_decode (uint32 *valp)
3797 {
3798 unsigned imm8x8_out_0;
3799 unsigned imm8x8_in_0;
3800 imm8x8_in_0 = *valp & 0xff;
3801 imm8x8_out_0 = (0 << 11) | (imm8x8_in_0 << 3) | 0;
3802 *valp = imm8x8_out_0;
3803 return 0;
3804 }
3805
3806 static int
3807 OperandSem_opnd_sem_imm8x8_encode (uint32 *valp)
3808 {
3809 unsigned imm8x8_in_0;
3810 unsigned imm8x8_out_0;
3811 imm8x8_out_0 = *valp;
3812 imm8x8_in_0 = ((imm8x8_out_0 >> 3) & 0xff);
3813 *valp = imm8x8_in_0;
3814 return 0;
3815 }
3816
3817 static int
3818 OperandSem_opnd_sem_bbi_decode (uint32 *valp)
3819 {
3820 unsigned bbi_out_0;
3821 unsigned bbi_in_0;
3822 bbi_in_0 = *valp & 0x1f;
3823 bbi_out_0 = (0 << 5) | bbi_in_0;
3824 *valp = bbi_out_0;
3825 return 0;
3826 }
3827
3828 static int
3829 OperandSem_opnd_sem_bbi_encode (uint32 *valp)
3830 {
3831 unsigned bbi_in_0;
3832 unsigned bbi_out_0;
3833 bbi_out_0 = *valp;
3834 bbi_in_0 = (bbi_out_0 & 0x1f);
3835 *valp = bbi_in_0;
3836 return 0;
3837 }
3838
3839 static int
3840 OperandSem_opnd_sem_s_decode (uint32 *valp)
3841 {
3842 unsigned s_out_0;
3843 unsigned s_in_0;
3844 s_in_0 = *valp & 0xf;
3845 s_out_0 = (0 << 4) | s_in_0;
3846 *valp = s_out_0;
3847 return 0;
3848 }
3849
3850 static int
3851 OperandSem_opnd_sem_s_encode (uint32 *valp)
3852 {
3853 unsigned s_in_0;
3854 unsigned s_out_0;
3855 s_out_0 = *valp;
3856 s_in_0 = (s_out_0 & 0xf);
3857 *valp = s_in_0;
3858 return 0;
3859 }
3860
3861 static int
3862 OperandSem_opnd_sem_bitindex_decode (uint32 *valp)
3863 {
3864 unsigned bitindex_out_0;
3865 unsigned bitindex_in_0;
3866 bitindex_in_0 = *valp & 0x1f;
3867 bitindex_out_0 = (0 << 5) | bitindex_in_0;
3868 *valp = bitindex_out_0;
3869 return 0;
3870 }
3871
3872 static int
3873 OperandSem_opnd_sem_bitindex_encode (uint32 *valp)
3874 {
3875 unsigned bitindex_in_0;
3876 unsigned bitindex_out_0;
3877 bitindex_out_0 = *valp;
3878 bitindex_in_0 = (bitindex_out_0 & 0x1f);
3879 *valp = bitindex_in_0;
3880 return 0;
3881 }
3882
3883 static int
3884 Operand_soffsetx4_ator (uint32 *valp, uint32 pc)
3885 {
3886 *valp -= (pc & ~0x3);
3887 return 0;
3888 }
3889
3890 static int
3891 Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc)
3892 {
3893 *valp += (pc & ~0x3);
3894 return 0;
3895 }
3896
3897 static int
3898 Operand_uimm6_ator (uint32 *valp, uint32 pc)
3899 {
3900 *valp -= pc;
3901 return 0;
3902 }
3903
3904 static int
3905 Operand_uimm6_rtoa (uint32 *valp, uint32 pc)
3906 {
3907 *valp += pc;
3908 return 0;
3909 }
3910
3911 static int
3912 Operand_label8_ator (uint32 *valp, uint32 pc)
3913 {
3914 *valp -= pc;
3915 return 0;
3916 }
3917
3918 static int
3919 Operand_label8_rtoa (uint32 *valp, uint32 pc)
3920 {
3921 *valp += pc;
3922 return 0;
3923 }
3924
3925 static int
3926 Operand_ulabel8_ator (uint32 *valp, uint32 pc)
3927 {
3928 *valp -= pc;
3929 return 0;
3930 }
3931
3932 static int
3933 Operand_ulabel8_rtoa (uint32 *valp, uint32 pc)
3934 {
3935 *valp += pc;
3936 return 0;
3937 }
3938
3939 static int
3940 Operand_label12_ator (uint32 *valp, uint32 pc)
3941 {
3942 *valp -= pc;
3943 return 0;
3944 }
3945
3946 static int
3947 Operand_label12_rtoa (uint32 *valp, uint32 pc)
3948 {
3949 *valp += pc;
3950 return 0;
3951 }
3952
3953 static int
3954 Operand_soffset_ator (uint32 *valp, uint32 pc)
3955 {
3956 *valp -= pc;
3957 return 0;
3958 }
3959
3960 static int
3961 Operand_soffset_rtoa (uint32 *valp, uint32 pc)
3962 {
3963 *valp += pc;
3964 return 0;
3965 }
3966
3967 static int
3968 Operand_uimm16x4_ator (uint32 *valp, uint32 pc)
3969 {
3970 *valp -= ((pc + 3) & ~0x3);
3971 return 0;
3972 }
3973
3974 static int
3975 Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc)
3976 {
3977 *valp += ((pc + 3) & ~0x3);
3978 return 0;
3979 }
3980
3981 static int
3982 Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc)
3983 {
3984 *valp -= pc;
3985 return 0;
3986 }
3987
3988 static int
3989 Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc)
3990 {
3991 *valp += pc;
3992 return 0;
3993 }
3994
3995 static int
3996 Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc)
3997 {
3998 *valp -= pc;
3999 return 0;
4000 }
4001
4002 static int
4003 Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc)
4004 {
4005 *valp += pc;
4006 return 0;
4007 }
4008
4009 static xtensa_operand_internal operands[] = {
4010 { "soffsetx4", FIELD_offset, -1, 0,
4011 XTENSA_OPERAND_IS_PCRELATIVE,
4012 OperandSem_opnd_sem_soffsetx4_encode, OperandSem_opnd_sem_soffsetx4_decode,
4013 Operand_soffsetx4_ator, Operand_soffsetx4_rtoa },
4014 { "immr", FIELD_r, -1, 0,
4015 0,
4016 OperandSem_opnd_sem_immr_encode, OperandSem_opnd_sem_immr_decode,
4017 0, 0 },
4018 { "uimm12x8", FIELD_imm12, -1, 0,
4019 0,
4020 OperandSem_opnd_sem_uimm12x8_encode, OperandSem_opnd_sem_uimm12x8_decode,
4021 0, 0 },
4022 { "simm4", FIELD_mn, -1, 0,
4023 0,
4024 OperandSem_opnd_sem_simm4_encode, OperandSem_opnd_sem_simm4_decode,
4025 0, 0 },
4026 { "arr", FIELD_r, REGFILE_AR, 1,
4027 XTENSA_OPERAND_IS_REGISTER,
4028 OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
4029 0, 0 },
4030 { "ars", FIELD_s, REGFILE_AR, 1,
4031 XTENSA_OPERAND_IS_REGISTER,
4032 OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
4033 0, 0 },
4034 { "*ars_invisible", FIELD_s, REGFILE_AR, 1,
4035 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
4036 OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
4037 0, 0 },
4038 { "art", FIELD_t, REGFILE_AR, 1,
4039 XTENSA_OPERAND_IS_REGISTER,
4040 OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
4041 0, 0 },
4042 { "ar0", FIELD__ar0, REGFILE_AR, 1,
4043 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
4044 OperandSem_opnd_sem_AR_0_encode, OperandSem_opnd_sem_AR_0_decode,
4045 0, 0 },
4046 { "ar4", FIELD__ar4, REGFILE_AR, 1,
4047 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
4048 OperandSem_opnd_sem_AR_4_encode, OperandSem_opnd_sem_AR_4_decode,
4049 0, 0 },
4050 { "ar8", FIELD__ar8, REGFILE_AR, 1,
4051 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
4052 OperandSem_opnd_sem_AR_8_encode, OperandSem_opnd_sem_AR_8_decode,
4053 0, 0 },
4054 { "ar12", FIELD__ar12, REGFILE_AR, 1,
4055 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
4056 OperandSem_opnd_sem_AR_12_encode, OperandSem_opnd_sem_AR_12_decode,
4057 0, 0 },
4058 { "ars_entry", FIELD_s, REGFILE_AR, 1,
4059 XTENSA_OPERAND_IS_REGISTER,
4060 OperandSem_opnd_sem_AR_entry_encode, OperandSem_opnd_sem_AR_entry_decode,
4061 0, 0 },
4062 { "immrx4", FIELD_r, -1, 0,
4063 0,
4064 OperandSem_opnd_sem_immrx4_encode, OperandSem_opnd_sem_immrx4_decode,
4065 0, 0 },
4066 { "lsi4x4", FIELD_r, -1, 0,
4067 0,
4068 OperandSem_opnd_sem_lsi4x4_encode, OperandSem_opnd_sem_lsi4x4_decode,
4069 0, 0 },
4070 { "simm7", FIELD_imm7, -1, 0,
4071 0,
4072 OperandSem_opnd_sem_simm7_encode, OperandSem_opnd_sem_simm7_decode,
4073 0, 0 },
4074 { "uimm6", FIELD_imm6, -1, 0,
4075 XTENSA_OPERAND_IS_PCRELATIVE,
4076 OperandSem_opnd_sem_uimm6_encode, OperandSem_opnd_sem_uimm6_decode,
4077 Operand_uimm6_ator, Operand_uimm6_rtoa },
4078 { "ai4const", FIELD_t, -1, 0,
4079 0,
4080 OperandSem_opnd_sem_ai4const_encode, OperandSem_opnd_sem_ai4const_decode,
4081 0, 0 },
4082 { "b4const", FIELD_r, -1, 0,
4083 0,
4084 OperandSem_opnd_sem_b4const_encode, OperandSem_opnd_sem_b4const_decode,
4085 0, 0 },
4086 { "b4constu", FIELD_r, -1, 0,
4087 0,
4088 OperandSem_opnd_sem_b4constu_encode, OperandSem_opnd_sem_b4constu_decode,
4089 0, 0 },
4090 { "immt", FIELD_t, -1, 0,
4091 0,
4092 OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode,
4093 0, 0 },
4094 { "uimms8", FIELD_imms8, -1, 0,
4095 0,
4096 OperandSem_opnd_sem_uimms8_encode, OperandSem_opnd_sem_uimms8_decode,
4097 0, 0 },
4098 { "uimm8", FIELD_imm8, -1, 0,
4099 0,
4100 OperandSem_opnd_sem_uimm8_encode, OperandSem_opnd_sem_uimm8_decode,
4101 0, 0 },
4102 { "uimm8x2", FIELD_imm8, -1, 0,
4103 0,
4104 OperandSem_opnd_sem_uimm8x2_encode, OperandSem_opnd_sem_uimm8x2_decode,
4105 0, 0 },
4106 { "uimm8x4", FIELD_imm8, -1, 0,
4107 0,
4108 OperandSem_opnd_sem_uimm8x4_encode, OperandSem_opnd_sem_uimm8x4_decode,
4109 0, 0 },
4110 { "uimm4x16", FIELD_op2, -1, 0,
4111 0,
4112 OperandSem_opnd_sem_uimm4x16_encode, OperandSem_opnd_sem_uimm4x16_decode,
4113 0, 0 },
4114 { "uimmrx4", FIELD_r, -1, 0,
4115 0,
4116 OperandSem_opnd_sem_uimmrx4_encode, OperandSem_opnd_sem_uimmrx4_decode,
4117 0, 0 },
4118 { "simm8", FIELD_imm8, -1, 0,
4119 0,
4120 OperandSem_opnd_sem_simm8_encode, OperandSem_opnd_sem_simm8_decode,
4121 0, 0 },
4122 { "simm8x256", FIELD_imm8, -1, 0,
4123 0,
4124 OperandSem_opnd_sem_simm8x256_encode, OperandSem_opnd_sem_simm8x256_decode,
4125 0, 0 },
4126 { "simm12b", FIELD_imm12b, -1, 0,
4127 0,
4128 OperandSem_opnd_sem_simm12b_encode, OperandSem_opnd_sem_simm12b_decode,
4129 0, 0 },
4130 { "msalp32", FIELD_sal, -1, 0,
4131 0,
4132 OperandSem_opnd_sem_msalp32_encode, OperandSem_opnd_sem_msalp32_decode,
4133 0, 0 },
4134 { "op2p1", FIELD_op2, -1, 0,
4135 0,
4136 OperandSem_opnd_sem_op2p1_encode, OperandSem_opnd_sem_op2p1_decode,
4137 0, 0 },
4138 { "label8", FIELD_imm8, -1, 0,
4139 XTENSA_OPERAND_IS_PCRELATIVE,
4140 OperandSem_opnd_sem_label8_encode, OperandSem_opnd_sem_label8_decode,
4141 Operand_label8_ator, Operand_label8_rtoa },
4142 { "ulabel8", FIELD_imm8, -1, 0,
4143 XTENSA_OPERAND_IS_PCRELATIVE,
4144 OperandSem_opnd_sem_ulabel8_encode, OperandSem_opnd_sem_ulabel8_decode,
4145 Operand_ulabel8_ator, Operand_ulabel8_rtoa },
4146 { "label12", FIELD_imm12, -1, 0,
4147 XTENSA_OPERAND_IS_PCRELATIVE,
4148 OperandSem_opnd_sem_label12_encode, OperandSem_opnd_sem_label12_decode,
4149 Operand_label12_ator, Operand_label12_rtoa },
4150 { "soffset", FIELD_offset, -1, 0,
4151 XTENSA_OPERAND_IS_PCRELATIVE,
4152 OperandSem_opnd_sem_soffset_encode, OperandSem_opnd_sem_soffset_decode,
4153 Operand_soffset_ator, Operand_soffset_rtoa },
4154 { "uimm16x4", FIELD_imm16, -1, 0,
4155 XTENSA_OPERAND_IS_PCRELATIVE,
4156 OperandSem_opnd_sem_uimm16x4_encode, OperandSem_opnd_sem_uimm16x4_decode,
4157 Operand_uimm16x4_ator, Operand_uimm16x4_rtoa },
4158 { "mx", FIELD_x, REGFILE_MR, 1,
4159 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN,
4160 OperandSem_opnd_sem_MR_encode, OperandSem_opnd_sem_MR_decode,
4161 0, 0 },
4162 { "my", FIELD_y, REGFILE_MR, 1,
4163 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN,
4164 OperandSem_opnd_sem_MR_0_encode, OperandSem_opnd_sem_MR_0_decode,
4165 0, 0 },
4166 { "mw", FIELD_w, REGFILE_MR, 1,
4167 XTENSA_OPERAND_IS_REGISTER,
4168 OperandSem_opnd_sem_MR_1_encode, OperandSem_opnd_sem_MR_1_decode,
4169 0, 0 },
4170 { "mr0", FIELD__mr0, REGFILE_MR, 1,
4171 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
4172 OperandSem_opnd_sem_MR_2_encode, OperandSem_opnd_sem_MR_2_decode,
4173 0, 0 },
4174 { "mr1", FIELD__mr1, REGFILE_MR, 1,
4175 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
4176 OperandSem_opnd_sem_MR_3_encode, OperandSem_opnd_sem_MR_3_decode,
4177 0, 0 },
4178 { "mr2", FIELD__mr2, REGFILE_MR, 1,
4179 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
4180 OperandSem_opnd_sem_MR_4_encode, OperandSem_opnd_sem_MR_4_decode,
4181 0, 0 },
4182 { "mr3", FIELD__mr3, REGFILE_MR, 1,
4183 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
4184 OperandSem_opnd_sem_MR_5_encode, OperandSem_opnd_sem_MR_5_decode,
4185 0, 0 },
4186 { "imms", FIELD_s, -1, 0,
4187 0,
4188 OperandSem_opnd_sem_imms_encode, OperandSem_opnd_sem_imms_decode,
4189 0, 0 },
4190 { "imms1", FIELD_s, -1, 0,
4191 0,
4192 OperandSem_opnd_sem_imms_encode, OperandSem_opnd_sem_imms_decode,
4193 0, 0 },
4194 { "bt", FIELD_t, REGFILE_BR, 1,
4195 XTENSA_OPERAND_IS_REGISTER,
4196 OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode,
4197 0, 0 },
4198 { "bs", FIELD_s, REGFILE_BR, 1,
4199 XTENSA_OPERAND_IS_REGISTER,
4200 OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode,
4201 0, 0 },
4202 { "br", FIELD_r, REGFILE_BR, 1,
4203 XTENSA_OPERAND_IS_REGISTER,
4204 OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode,
4205 0, 0 },
4206 { "bt2", FIELD_t2, REGFILE_BR, 2,
4207 XTENSA_OPERAND_IS_REGISTER,
4208 OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode,
4209 0, 0 },
4210 { "bs2", FIELD_s2, REGFILE_BR, 2,
4211 XTENSA_OPERAND_IS_REGISTER,
4212 OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode,
4213 0, 0 },
4214 { "br2", FIELD_r2, REGFILE_BR, 2,
4215 XTENSA_OPERAND_IS_REGISTER,
4216 OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode,
4217 0, 0 },
4218 { "bt4", FIELD_t4, REGFILE_BR, 4,
4219 XTENSA_OPERAND_IS_REGISTER,
4220 OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode,
4221 0, 0 },
4222 { "bs4", FIELD_s4, REGFILE_BR, 4,
4223 XTENSA_OPERAND_IS_REGISTER,
4224 OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode,
4225 0, 0 },
4226 { "br4", FIELD_r4, REGFILE_BR, 4,
4227 XTENSA_OPERAND_IS_REGISTER,
4228 OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode,
4229 0, 0 },
4230 { "bt8", FIELD_t8, REGFILE_BR, 8,
4231 XTENSA_OPERAND_IS_REGISTER,
4232 OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode,
4233 0, 0 },
4234 { "bs8", FIELD_s8, REGFILE_BR, 8,
4235 XTENSA_OPERAND_IS_REGISTER,
4236 OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode,
4237 0, 0 },
4238 { "br8", FIELD_r8, REGFILE_BR, 8,
4239 XTENSA_OPERAND_IS_REGISTER,
4240 OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode,
4241 0, 0 },
4242 { "bt16", FIELD__bt16, REGFILE_BR, 16,
4243 XTENSA_OPERAND_IS_REGISTER,
4244 OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode,
4245 0, 0 },
4246 { "bs16", FIELD__bs16, REGFILE_BR, 16,
4247 XTENSA_OPERAND_IS_REGISTER,
4248 OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode,
4249 0, 0 },
4250 { "br16", FIELD__br16, REGFILE_BR, 16,
4251 XTENSA_OPERAND_IS_REGISTER,
4252 OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode,
4253 0, 0 },
4254 { "brall", FIELD__brall, REGFILE_BR, 16,
4255 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
4256 OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode,
4257 0, 0 },
4258 { "tp7", FIELD_t, -1, 0,
4259 0,
4260 OperandSem_opnd_sem_tp7_encode, OperandSem_opnd_sem_tp7_decode,
4261 0, 0 },
4262 { "xt_wbr15_label", FIELD_xt_wbr15_imm, -1, 0,
4263 XTENSA_OPERAND_IS_PCRELATIVE,
4264 OperandSem_opnd_sem_xt_wbr15_label_encode, OperandSem_opnd_sem_xt_wbr15_label_decode,
4265 Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa },
4266 { "xt_wbr18_label", FIELD_xt_wbr18_imm, -1, 0,
4267 XTENSA_OPERAND_IS_PCRELATIVE,
4268 OperandSem_opnd_sem_xt_wbr18_label_encode, OperandSem_opnd_sem_xt_wbr18_label_decode,
4269 Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa },
4270 { "frr", FIELD_r, REGFILE_FR, 1,
4271 XTENSA_OPERAND_IS_REGISTER,
4272 OperandSem_opnd_sem_FR_encode, OperandSem_opnd_sem_FR_decode,
4273 0, 0 },
4274 { "frs", FIELD_s, REGFILE_FR, 1,
4275 XTENSA_OPERAND_IS_REGISTER,
4276 OperandSem_opnd_sem_FR_encode, OperandSem_opnd_sem_FR_decode,
4277 0, 0 },
4278 { "frt", FIELD_t, REGFILE_FR, 1,
4279 XTENSA_OPERAND_IS_REGISTER,
4280 OperandSem_opnd_sem_FR_encode, OperandSem_opnd_sem_FR_decode,
4281 0, 0 },
4282 { "imm_t", FIELD_t, -1, 0,
4283 0,
4284 OperandSem_opnd_sem_imm_t_encode, OperandSem_opnd_sem_imm_t_decode,
4285 0, 0 },
4286 { "imm_s", FIELD_s, -1, 0,
4287 0,
4288 OperandSem_opnd_sem_imm_t_encode, OperandSem_opnd_sem_imm_t_decode,
4289 0, 0 },
4290 { "imm8x4", FIELD_imm8, -1, 0,
4291 0,
4292 OperandSem_opnd_sem_imm8x4_encode, OperandSem_opnd_sem_imm8x4_decode,
4293 0, 0 },
4294 { "imm8x8", FIELD_imm8, -1, 0,
4295 0,
4296 OperandSem_opnd_sem_imm8x8_encode, OperandSem_opnd_sem_imm8x8_decode,
4297 0, 0 },
4298 { "bbi", FIELD_bbi, -1, 0,
4299 0,
4300 OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
4301 0, 0 },
4302 { "sae", FIELD_sae, -1, 0,
4303 0,
4304 OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
4305 0, 0 },
4306 { "sas", FIELD_sas, -1, 0,
4307 0,
4308 OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
4309 0, 0 },
4310 { "sargt", FIELD_sargt, -1, 0,
4311 0,
4312 OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
4313 0, 0 },
4314 { "s", FIELD_s, -1, 0,
4315 0,
4316 OperandSem_opnd_sem_s_encode, OperandSem_opnd_sem_s_decode,
4317 0, 0 },
4318 { "bitindex", FIELD_bitindex, -1, 0,
4319 0,
4320 OperandSem_opnd_sem_bitindex_encode, OperandSem_opnd_sem_bitindex_decode,
4321 0, 0 },
4322 { "t", FIELD_t, -1, 0, 0, 0, 0, 0, 0 },
4323 { "bbi4", FIELD_bbi4, -1, 0, 0, 0, 0, 0, 0 },
4324 { "imm12", FIELD_imm12, -1, 0, 0, 0, 0, 0, 0 },
4325 { "imm8", FIELD_imm8, -1, 0, 0, 0, 0, 0, 0 },
4326 { "s8", FIELD_s8, -1, 0, 0, 0, 0, 0, 0 },
4327 { "imms8", FIELD_imms8, -1, 0, 0, 0, 0, 0, 0 },
4328 { "imm12b", FIELD_imm12b, -1, 0, 0, 0, 0, 0, 0 },
4329 { "imm16", FIELD_imm16, -1, 0, 0, 0, 0, 0, 0 },
4330 { "m", FIELD_m, -1, 0, 0, 0, 0, 0, 0 },
4331 { "n", FIELD_n, -1, 0, 0, 0, 0, 0, 0 },
4332 { "offset", FIELD_offset, -1, 0, 0, 0, 0, 0, 0 },
4333 { "op0", FIELD_op0, -1, 0, 0, 0, 0, 0, 0 },
4334 { "op1", FIELD_op1, -1, 0, 0, 0, 0, 0, 0 },
4335 { "op2", FIELD_op2, -1, 0, 0, 0, 0, 0, 0 },
4336 { "r", FIELD_r, -1, 0, 0, 0, 0, 0, 0 },
4337 { "r_disp", FIELD_r_disp, -1, 0, 0, 0, 0, 0, 0 },
4338 { "r_3", FIELD_r_3, -1, 0, 0, 0, 0, 0, 0 },
4339 { "sa4", FIELD_sa4, -1, 0, 0, 0, 0, 0, 0 },
4340 { "sae4", FIELD_sae4, -1, 0, 0, 0, 0, 0, 0 },
4341 { "sal", FIELD_sal, -1, 0, 0, 0, 0, 0, 0 },
4342 { "sas4", FIELD_sas4, -1, 0, 0, 0, 0, 0, 0 },
4343 { "sr", FIELD_sr, -1, 0, 0, 0, 0, 0, 0 },
4344 { "st", FIELD_st, -1, 0, 0, 0, 0, 0, 0 },
4345 { "thi3", FIELD_thi3, -1, 0, 0, 0, 0, 0, 0 },
4346 { "imm4", FIELD_imm4, -1, 0, 0, 0, 0, 0, 0 },
4347 { "mn", FIELD_mn, -1, 0, 0, 0, 0, 0, 0 },
4348 { "i", FIELD_i, -1, 0, 0, 0, 0, 0, 0 },
4349 { "imm6lo", FIELD_imm6lo, -1, 0, 0, 0, 0, 0, 0 },
4350 { "imm6hi", FIELD_imm6hi, -1, 0, 0, 0, 0, 0, 0 },
4351 { "imm7lo", FIELD_imm7lo, -1, 0, 0, 0, 0, 0, 0 },
4352 { "imm7hi", FIELD_imm7hi, -1, 0, 0, 0, 0, 0, 0 },
4353 { "z", FIELD_z, -1, 0, 0, 0, 0, 0, 0 },
4354 { "imm6", FIELD_imm6, -1, 0, 0, 0, 0, 0, 0 },
4355 { "imm7", FIELD_imm7, -1, 0, 0, 0, 0, 0, 0 },
4356 { "r3", FIELD_r3, -1, 0, 0, 0, 0, 0, 0 },
4357 { "rbit2", FIELD_rbit2, -1, 0, 0, 0, 0, 0, 0 },
4358 { "rhi", FIELD_rhi, -1, 0, 0, 0, 0, 0, 0 },
4359 { "t3", FIELD_t3, -1, 0, 0, 0, 0, 0, 0 },
4360 { "tbit2", FIELD_tbit2, -1, 0, 0, 0, 0, 0, 0 },
4361 { "tlo", FIELD_tlo, -1, 0, 0, 0, 0, 0, 0 },
4362 { "w", FIELD_w, -1, 0, 0, 0, 0, 0, 0 },
4363 { "y", FIELD_y, -1, 0, 0, 0, 0, 0, 0 },
4364 { "x", FIELD_x, -1, 0, 0, 0, 0, 0, 0 },
4365 { "t2", FIELD_t2, -1, 0, 0, 0, 0, 0, 0 },
4366 { "s2", FIELD_s2, -1, 0, 0, 0, 0, 0, 0 },
4367 { "r2", FIELD_r2, -1, 0, 0, 0, 0, 0, 0 },
4368 { "t4", FIELD_t4, -1, 0, 0, 0, 0, 0, 0 },
4369 { "s4", FIELD_s4, -1, 0, 0, 0, 0, 0, 0 },
4370 { "r4", FIELD_r4, -1, 0, 0, 0, 0, 0, 0 },
4371 { "t8", FIELD_t8, -1, 0, 0, 0, 0, 0, 0 },
4372 { "r8", FIELD_r8, -1, 0, 0, 0, 0, 0, 0 },
4373 { "xt_wbr15_imm", FIELD_xt_wbr15_imm, -1, 0, 0, 0, 0, 0, 0 },
4374 { "xt_wbr18_imm", FIELD_xt_wbr18_imm, -1, 0, 0, 0, 0, 0, 0 },
4375 { "s3to1", FIELD_s3to1, -1, 0, 0, 0, 0, 0, 0 }
4376 };
4377
4378 enum xtensa_operand_id {
4379 OPERAND_soffsetx4,
4380 OPERAND_immr,
4381 OPERAND_uimm12x8,
4382 OPERAND_simm4,
4383 OPERAND_arr,
4384 OPERAND_ars,
4385 OPERAND__ars_invisible,
4386 OPERAND_art,
4387 OPERAND_ar0,
4388 OPERAND_ar4,
4389 OPERAND_ar8,
4390 OPERAND_ar12,
4391 OPERAND_ars_entry,
4392 OPERAND_immrx4,
4393 OPERAND_lsi4x4,
4394 OPERAND_simm7,
4395 OPERAND_uimm6,
4396 OPERAND_ai4const,
4397 OPERAND_b4const,
4398 OPERAND_b4constu,
4399 OPERAND_immt,
4400 OPERAND_uimms8,
4401 OPERAND_uimm8,
4402 OPERAND_uimm8x2,
4403 OPERAND_uimm8x4,
4404 OPERAND_uimm4x16,
4405 OPERAND_uimmrx4,
4406 OPERAND_simm8,
4407 OPERAND_simm8x256,
4408 OPERAND_simm12b,
4409 OPERAND_msalp32,
4410 OPERAND_op2p1,
4411 OPERAND_label8,
4412 OPERAND_ulabel8,
4413 OPERAND_label12,
4414 OPERAND_soffset,
4415 OPERAND_uimm16x4,
4416 OPERAND_mx,
4417 OPERAND_my,
4418 OPERAND_mw,
4419 OPERAND_mr0,
4420 OPERAND_mr1,
4421 OPERAND_mr2,
4422 OPERAND_mr3,
4423 OPERAND_imms,
4424 OPERAND_imms1,
4425 OPERAND_bt,
4426 OPERAND_bs,
4427 OPERAND_br,
4428 OPERAND_bt2,
4429 OPERAND_bs2,
4430 OPERAND_br2,
4431 OPERAND_bt4,
4432 OPERAND_bs4,
4433 OPERAND_br4,
4434 OPERAND_bt8,
4435 OPERAND_bs8,
4436 OPERAND_br8,
4437 OPERAND_bt16,
4438 OPERAND_bs16,
4439 OPERAND_br16,
4440 OPERAND_brall,
4441 OPERAND_tp7,
4442 OPERAND_xt_wbr15_label,
4443 OPERAND_xt_wbr18_label,
4444 OPERAND_frr,
4445 OPERAND_frs,
4446 OPERAND_frt,
4447 OPERAND_imm_t,
4448 OPERAND_imm_s,
4449 OPERAND_imm8x4,
4450 OPERAND_imm8x8,
4451 OPERAND_bbi,
4452 OPERAND_sae,
4453 OPERAND_sas,
4454 OPERAND_sargt,
4455 OPERAND_s,
4456 OPERAND_bitindex,
4457 OPERAND_t,
4458 OPERAND_bbi4,
4459 OPERAND_imm12,
4460 OPERAND_imm8,
4461 OPERAND_s8,
4462 OPERAND_imms8,
4463 OPERAND_imm12b,
4464 OPERAND_imm16,
4465 OPERAND_m,
4466 OPERAND_n,
4467 OPERAND_offset,
4468 OPERAND_op0,
4469 OPERAND_op1,
4470 OPERAND_op2,
4471 OPERAND_r,
4472 OPERAND_r_disp,
4473 OPERAND_r_3,
4474 OPERAND_sa4,
4475 OPERAND_sae4,
4476 OPERAND_sal,
4477 OPERAND_sas4,
4478 OPERAND_sr,
4479 OPERAND_st,
4480 OPERAND_thi3,
4481 OPERAND_imm4,
4482 OPERAND_mn,
4483 OPERAND_i,
4484 OPERAND_imm6lo,
4485 OPERAND_imm6hi,
4486 OPERAND_imm7lo,
4487 OPERAND_imm7hi,
4488 OPERAND_z,
4489 OPERAND_imm6,
4490 OPERAND_imm7,
4491 OPERAND_r3,
4492 OPERAND_rbit2,
4493 OPERAND_rhi,
4494 OPERAND_t3,
4495 OPERAND_tbit2,
4496 OPERAND_tlo,
4497 OPERAND_w,
4498 OPERAND_y,
4499 OPERAND_x,
4500 OPERAND_t2,
4501 OPERAND_s2,
4502 OPERAND_r2,
4503 OPERAND_t4,
4504 OPERAND_s4,
4505 OPERAND_r4,
4506 OPERAND_t8,
4507 OPERAND_r8,
4508 OPERAND_xt_wbr15_imm,
4509 OPERAND_xt_wbr18_imm,
4510 OPERAND_s3to1
4511 };
4512
4513
4514 /* Iclass table. */
4515
4516 static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = {
4517 { { STATE_PSRING }, 'i' },
4518 { { STATE_PSEXCM }, 'm' },
4519 { { STATE_EPC1 }, 'i' }
4520 };
4521
4522 static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = {
4523 { { STATE_PSEXCM }, 'i' },
4524 { { STATE_PSRING }, 'i' },
4525 { { STATE_DEPC }, 'i' }
4526 };
4527
4528 static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = {
4529 { { OPERAND_soffsetx4 }, 'i' },
4530 { { OPERAND_ar12 }, 'o' }
4531 };
4532
4533 static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = {
4534 { { STATE_PSCALLINC }, 'o' }
4535 };
4536
4537 static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = {
4538 { { OPERAND_soffsetx4 }, 'i' },
4539 { { OPERAND_ar8 }, 'o' }
4540 };
4541
4542 static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = {
4543 { { STATE_PSCALLINC }, 'o' }
4544 };
4545
4546 static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = {
4547 { { OPERAND_soffsetx4 }, 'i' },
4548 { { OPERAND_ar4 }, 'o' }
4549 };
4550
4551 static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = {
4552 { { STATE_PSCALLINC }, 'o' }
4553 };
4554
4555 static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = {
4556 { { OPERAND_ars }, 'i' },
4557 { { OPERAND_ar12 }, 'o' }
4558 };
4559
4560 static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = {
4561 { { STATE_PSCALLINC }, 'o' }
4562 };
4563
4564 static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = {
4565 { { OPERAND_ars }, 'i' },
4566 { { OPERAND_ar8 }, 'o' }
4567 };
4568
4569 static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = {
4570 { { STATE_PSCALLINC }, 'o' }
4571 };
4572
4573 static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = {
4574 { { OPERAND_ars }, 'i' },
4575 { { OPERAND_ar4 }, 'o' }
4576 };
4577
4578 static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = {
4579 { { STATE_PSCALLINC }, 'o' }
4580 };
4581
4582 static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = {
4583 { { OPERAND_ars_entry }, 's' },
4584 { { OPERAND_ars }, 'i' },
4585 { { OPERAND_uimm12x8 }, 'i' }
4586 };
4587
4588 static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = {
4589 { { STATE_PSCALLINC }, 'i' },
4590 { { STATE_PSEXCM }, 'i' },
4591 { { STATE_PSWOE }, 'i' },
4592 { { STATE_WindowBase }, 'm' },
4593 { { STATE_WindowStart }, 'm' }
4594 };
4595
4596 static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = {
4597 { { OPERAND_art }, 'o' },
4598 { { OPERAND_ars }, 'i' }
4599 };
4600
4601 static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = {
4602 { { STATE_WindowBase }, 'i' },
4603 { { STATE_WindowStart }, 'i' }
4604 };
4605
4606 static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = {
4607 { { OPERAND_simm4 }, 'i' }
4608 };
4609
4610 static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = {
4611 { { STATE_PSEXCM }, 'i' },
4612 { { STATE_PSRING }, 'i' },
4613 { { STATE_WindowBase }, 'm' }
4614 };
4615
4616 static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = {
4617 { { OPERAND__ars_invisible }, 'i' }
4618 };
4619
4620 static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = {
4621 { { STATE_WindowBase }, 'm' },
4622 { { STATE_WindowStart }, 'm' },
4623 { { STATE_PSCALLINC }, 'o' },
4624 { { STATE_PSEXCM }, 'i' },
4625 { { STATE_PSWOE }, 'i' }
4626 };
4627
4628 static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = {
4629 { { STATE_EPC1 }, 'i' },
4630 { { STATE_PSEXCM }, 'm' },
4631 { { STATE_PSRING }, 'i' },
4632 { { STATE_WindowBase }, 'm' },
4633 { { STATE_WindowStart }, 'm' },
4634 { { STATE_PSOWB }, 'i' }
4635 };
4636
4637 static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = {
4638 { { OPERAND_art }, 'o' },
4639 { { OPERAND_ars }, 'i' },
4640 { { OPERAND_immrx4 }, 'i' }
4641 };
4642
4643 static xtensa_arg_internal Iclass_xt_iclass_l32e_stateArgs[] = {
4644 { { STATE_PSEXCM }, 'i' },
4645 { { STATE_PSRING }, 'i' }
4646 };
4647
4648 static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = {
4649 { { OPERAND_art }, 'i' },
4650 { { OPERAND_ars }, 'i' },
4651 { { OPERAND_immrx4 }, 'i' }
4652 };
4653
4654 static xtensa_arg_internal Iclass_xt_iclass_s32e_stateArgs[] = {
4655 { { STATE_PSEXCM }, 'i' },
4656 { { STATE_PSRING }, 'i' }
4657 };
4658
4659 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = {
4660 { { OPERAND_art }, 'o' }
4661 };
4662
4663 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = {
4664 { { STATE_PSEXCM }, 'i' },
4665 { { STATE_PSRING }, 'i' },
4666 { { STATE_WindowBase }, 'i' }
4667 };
4668
4669 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = {
4670 { { OPERAND_art }, 'i' }
4671 };
4672
4673 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = {
4674 { { STATE_PSEXCM }, 'i' },
4675 { { STATE_PSRING }, 'i' },
4676 { { STATE_WindowBase }, 'o' }
4677 };
4678
4679 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = {
4680 { { OPERAND_art }, 'm' }
4681 };
4682
4683 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = {
4684 { { STATE_PSEXCM }, 'i' },
4685 { { STATE_PSRING }, 'i' },
4686 { { STATE_WindowBase }, 'm' }
4687 };
4688
4689 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = {
4690 { { OPERAND_art }, 'o' }
4691 };
4692
4693 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = {
4694 { { STATE_PSEXCM }, 'i' },
4695 { { STATE_PSRING }, 'i' },
4696 { { STATE_WindowStart }, 'i' }
4697 };
4698
4699 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = {
4700 { { OPERAND_art }, 'i' }
4701 };
4702
4703 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = {
4704 { { STATE_PSEXCM }, 'i' },
4705 { { STATE_PSRING }, 'i' },
4706 { { STATE_WindowStart }, 'o' }
4707 };
4708
4709 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = {
4710 { { OPERAND_art }, 'm' }
4711 };
4712
4713 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = {
4714 { { STATE_PSEXCM }, 'i' },
4715 { { STATE_PSRING }, 'i' },
4716 { { STATE_WindowStart }, 'm' }
4717 };
4718
4719 static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = {
4720 { { OPERAND_arr }, 'o' },
4721 { { OPERAND_ars }, 'i' },
4722 { { OPERAND_art }, 'i' }
4723 };
4724
4725 static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = {
4726 { { OPERAND_arr }, 'o' },
4727 { { OPERAND_ars }, 'i' },
4728 { { OPERAND_ai4const }, 'i' }
4729 };
4730
4731 static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = {
4732 { { OPERAND_ars }, 'i' },
4733 { { OPERAND_uimm6 }, 'i' }
4734 };
4735
4736 static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = {
4737 { { OPERAND_art }, 'o' },
4738 { { OPERAND_ars }, 'i' },
4739 { { OPERAND_lsi4x4 }, 'i' }
4740 };
4741
4742 static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = {
4743 { { OPERAND_art }, 'o' },
4744 { { OPERAND_ars }, 'i' }
4745 };
4746
4747 static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = {
4748 { { OPERAND_ars }, 'o' },
4749 { { OPERAND_simm7 }, 'i' }
4750 };
4751
4752 static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = {
4753 { { OPERAND__ars_invisible }, 'i' }
4754 };
4755
4756 static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = {
4757 { { OPERAND_art }, 'i' },
4758 { { OPERAND_ars }, 'i' },
4759 { { OPERAND_lsi4x4 }, 'i' }
4760 };
4761
4762 static xtensa_arg_internal Iclass_rur_threadptr_args[] = {
4763 { { OPERAND_arr }, 'o' }
4764 };
4765
4766 static xtensa_arg_internal Iclass_rur_threadptr_stateArgs[] = {
4767 { { STATE_THREADPTR }, 'i' }
4768 };
4769
4770 static xtensa_arg_internal Iclass_wur_threadptr_args[] = {
4771 { { OPERAND_art }, 'i' }
4772 };
4773
4774 static xtensa_arg_internal Iclass_wur_threadptr_stateArgs[] = {
4775 { { STATE_THREADPTR }, 'o' }
4776 };
4777
4778 static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = {
4779 { { OPERAND_art }, 'o' },
4780 { { OPERAND_ars }, 'i' },
4781 { { OPERAND_simm8 }, 'i' }
4782 };
4783
4784 static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = {
4785 { { OPERAND_art }, 'o' },
4786 { { OPERAND_ars }, 'i' },
4787 { { OPERAND_simm8x256 }, 'i' }
4788 };
4789
4790 static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = {
4791 { { OPERAND_arr }, 'o' },
4792 { { OPERAND_ars }, 'i' },
4793 { { OPERAND_art }, 'i' }
4794 };
4795
4796 static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = {
4797 { { OPERAND_arr }, 'o' },
4798 { { OPERAND_ars }, 'i' },
4799 { { OPERAND_art }, 'i' }
4800 };
4801
4802 static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = {
4803 { { OPERAND_ars }, 'i' },
4804 { { OPERAND_b4const }, 'i' },
4805 { { OPERAND_label8 }, 'i' }
4806 };
4807
4808 static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = {
4809 { { OPERAND_ars }, 'i' },
4810 { { OPERAND_bbi }, 'i' },
4811 { { OPERAND_label8 }, 'i' }
4812 };
4813
4814 static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = {
4815 { { OPERAND_ars }, 'i' },
4816 { { OPERAND_b4constu }, 'i' },
4817 { { OPERAND_label8 }, 'i' }
4818 };
4819
4820 static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = {
4821 { { OPERAND_ars }, 'i' },
4822 { { OPERAND_art }, 'i' },
4823 { { OPERAND_label8 }, 'i' }
4824 };
4825
4826 static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = {
4827 { { OPERAND_ars }, 'i' },
4828 { { OPERAND_label12 }, 'i' }
4829 };
4830
4831 static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = {
4832 { { OPERAND_soffsetx4 }, 'i' },
4833 { { OPERAND_ar0 }, 'o' }
4834 };
4835
4836 static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = {
4837 { { OPERAND_ars }, 'i' },
4838 { { OPERAND_ar0 }, 'o' }
4839 };
4840
4841 static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = {
4842 { { OPERAND_arr }, 'o' },
4843 { { OPERAND_art }, 'i' },
4844 { { OPERAND_sae }, 'i' },
4845 { { OPERAND_op2p1 }, 'i' }
4846 };
4847
4848 static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = {
4849 { { OPERAND_soffset }, 'i' }
4850 };
4851
4852 static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = {
4853 { { OPERAND_ars }, 'i' }
4854 };
4855
4856 static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = {
4857 { { OPERAND_art }, 'o' },
4858 { { OPERAND_ars }, 'i' },
4859 { { OPERAND_uimm8x2 }, 'i' }
4860 };
4861
4862 static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = {
4863 { { OPERAND_art }, 'o' },
4864 { { OPERAND_ars }, 'i' },
4865 { { OPERAND_uimm8x2 }, 'i' }
4866 };
4867
4868 static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = {
4869 { { OPERAND_art }, 'o' },
4870 { { OPERAND_ars }, 'i' },
4871 { { OPERAND_uimm8x4 }, 'i' }
4872 };
4873
4874 static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = {
4875 { { OPERAND_art }, 'o' },
4876 { { OPERAND_uimm16x4 }, 'i' }
4877 };
4878
4879 static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = {
4880 { { OPERAND_art }, 'o' },
4881 { { OPERAND_ars }, 'i' },
4882 { { OPERAND_uimm8 }, 'i' }
4883 };
4884
4885 static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = {
4886 { { OPERAND_ars }, 'i' },
4887 { { OPERAND_ulabel8 }, 'i' }
4888 };
4889
4890 static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = {
4891 { { STATE_LBEG }, 'o' },
4892 { { STATE_LEND }, 'o' },
4893 { { STATE_LCOUNT }, 'o' }
4894 };
4895
4896 static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = {
4897 { { OPERAND_ars }, 'i' },
4898 { { OPERAND_ulabel8 }, 'i' }
4899 };
4900
4901 static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = {
4902 { { STATE_LBEG }, 'o' },
4903 { { STATE_LEND }, 'o' },
4904 { { STATE_LCOUNT }, 'o' }
4905 };
4906
4907 static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = {
4908 { { OPERAND_art }, 'o' },
4909 { { OPERAND_simm12b }, 'i' }
4910 };
4911
4912 static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = {
4913 { { OPERAND_arr }, 'm' },
4914 { { OPERAND_ars }, 'i' },
4915 { { OPERAND_art }, 'i' }
4916 };
4917
4918 static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = {
4919 { { OPERAND_arr }, 'o' },
4920 { { OPERAND_art }, 'i' }
4921 };
4922
4923 static xtensa_arg_internal Iclass_xt_iclass_return_args[] = {
4924 { { OPERAND__ars_invisible }, 'i' }
4925 };
4926
4927 static xtensa_arg_internal Iclass_xt_iclass_simcall_args[] = {
4928 { { OPERAND_immt }, 'i' }
4929 };
4930
4931 static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = {
4932 { { OPERAND_art }, 'i' },
4933 { { OPERAND_ars }, 'i' },
4934 { { OPERAND_uimm8x2 }, 'i' }
4935 };
4936
4937 static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = {
4938 { { OPERAND_art }, 'i' },
4939 { { OPERAND_ars }, 'i' },
4940 { { OPERAND_uimm8x4 }, 'i' }
4941 };
4942
4943 static xtensa_arg_internal Iclass_xt_iclass_s32nb_args[] = {
4944 { { OPERAND_art }, 'i' },
4945 { { OPERAND_ars }, 'i' },
4946 { { OPERAND_uimmrx4 }, 'i' }
4947 };
4948
4949 static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = {
4950 { { OPERAND_art }, 'i' },
4951 { { OPERAND_ars }, 'i' },
4952 { { OPERAND_uimm8 }, 'i' }
4953 };
4954
4955 static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = {
4956 { { OPERAND_ars }, 'i' }
4957 };
4958
4959 static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = {
4960 { { STATE_SAR }, 'o' }
4961 };
4962
4963 static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = {
4964 { { OPERAND_sas }, 'i' }
4965 };
4966
4967 static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = {
4968 { { STATE_SAR }, 'o' }
4969 };
4970
4971 static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = {
4972 { { OPERAND_arr }, 'o' },
4973 { { OPERAND_ars }, 'i' }
4974 };
4975
4976 static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = {
4977 { { STATE_SAR }, 'i' }
4978 };
4979
4980 static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = {
4981 { { OPERAND_arr }, 'o' },
4982 { { OPERAND_ars }, 'i' },
4983 { { OPERAND_art }, 'i' }
4984 };
4985
4986 static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = {
4987 { { STATE_SAR }, 'i' }
4988 };
4989
4990 static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = {
4991 { { OPERAND_arr }, 'o' },
4992 { { OPERAND_art }, 'i' }
4993 };
4994
4995 static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = {
4996 { { STATE_SAR }, 'i' }
4997 };
4998
4999 static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = {
5000 { { OPERAND_arr }, 'o' },
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