| 1 | /* |
| 2 | * xtensa/config/core-matmap.h -- Memory access and translation mapping |
| 3 | * parameters (CHAL) of the Xtensa processor core configuration. |
| 4 | * |
| 5 | * If you are using Xtensa Tools, see <xtensa/config/core.h> (which includes |
| 6 | * this file) for more details. |
| 7 | * |
| 8 | * In the Xtensa processor products released to date, all parameters |
| 9 | * defined in this file are derivable (at least in theory) from |
| 10 | * information contained in the core-isa.h header file. |
| 11 | * In particular, the following core configuration parameters are relevant: |
| 12 | * XCHAL_HAVE_CACHEATTR |
| 13 | * XCHAL_HAVE_MIMIC_CACHEATTR |
| 14 | * XCHAL_HAVE_XLT_CACHEATTR |
| 15 | * XCHAL_HAVE_PTP_MMU |
| 16 | * XCHAL_ITLB_ARF_ENTRIES_LOG2 |
| 17 | * XCHAL_DTLB_ARF_ENTRIES_LOG2 |
| 18 | * XCHAL_DCACHE_IS_WRITEBACK |
| 19 | * XCHAL_ICACHE_SIZE (presence of I-cache) |
| 20 | * XCHAL_DCACHE_SIZE (presence of D-cache) |
| 21 | * XCHAL_HW_VERSION_MAJOR |
| 22 | * XCHAL_HW_VERSION_MINOR |
| 23 | */ |
| 24 | |
| 25 | /* Copyright (c) 1999-2010 Tensilica Inc. |
| 26 | |
| 27 | Permission is hereby granted, free of charge, to any person obtaining |
| 28 | a copy of this software and associated documentation files (the |
| 29 | "Software"), to deal in the Software without restriction, including |
| 30 | without limitation the rights to use, copy, modify, merge, publish, |
| 31 | distribute, sublicense, and/or sell copies of the Software, and to |
| 32 | permit persons to whom the Software is furnished to do so, subject to |
| 33 | the following conditions: |
| 34 | |
| 35 | The above copyright notice and this permission notice shall be included |
| 36 | in all copies or substantial portions of the Software. |
| 37 | |
| 38 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
| 39 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 40 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
| 41 | IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY |
| 42 | CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| 43 | TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
| 44 | SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ |
| 45 | |
| 46 | #ifndef XTENSA_CONFIG_CORE_MATMAP_H |
| 47 | #define XTENSA_CONFIG_CORE_MATMAP_H |
| 48 | |
| 49 | /*---------------------------------------------------------------------- |
| 50 | CACHE (MEMORY ACCESS) ATTRIBUTES |
| 51 | ----------------------------------------------------------------------*/ |
| 52 | |
| 53 | |
| 54 | /* Cache Attribute encodings -- lists of access modes for each cache attribute: */ |
| 55 | #define XCHAL_FCA_LIST XTHAL_FAM_EXCEPTION XCHAL_SEP \ |
| 56 | XTHAL_FAM_CACHED XCHAL_SEP \ |
| 57 | XTHAL_FAM_BYPASS XCHAL_SEP \ |
| 58 | XTHAL_FAM_CACHED XCHAL_SEP \ |
| 59 | XTHAL_FAM_CACHED XCHAL_SEP \ |
| 60 | XTHAL_FAM_CACHED XCHAL_SEP \ |
| 61 | XTHAL_FAM_EXCEPTION XCHAL_SEP \ |
| 62 | XTHAL_FAM_EXCEPTION XCHAL_SEP \ |
| 63 | XTHAL_FAM_EXCEPTION XCHAL_SEP \ |
| 64 | XTHAL_FAM_EXCEPTION XCHAL_SEP \ |
| 65 | XTHAL_FAM_EXCEPTION XCHAL_SEP \ |
| 66 | XTHAL_FAM_EXCEPTION XCHAL_SEP \ |
| 67 | XTHAL_FAM_EXCEPTION XCHAL_SEP \ |
| 68 | XTHAL_FAM_EXCEPTION XCHAL_SEP \ |
| 69 | XTHAL_FAM_EXCEPTION XCHAL_SEP \ |
| 70 | XTHAL_FAM_EXCEPTION |
| 71 | #define XCHAL_LCA_LIST XTHAL_LAM_CACHED_NOALLOC XCHAL_SEP \ |
| 72 | XTHAL_LAM_CACHED XCHAL_SEP \ |
| 73 | XTHAL_LAM_BYPASSG XCHAL_SEP \ |
| 74 | XTHAL_LAM_EXCEPTION XCHAL_SEP \ |
| 75 | XTHAL_LAM_CACHED XCHAL_SEP \ |
| 76 | XTHAL_LAM_CACHED XCHAL_SEP \ |
| 77 | XTHAL_LAM_EXCEPTION XCHAL_SEP \ |
| 78 | XTHAL_LAM_EXCEPTION XCHAL_SEP \ |
| 79 | XTHAL_LAM_EXCEPTION XCHAL_SEP \ |
| 80 | XTHAL_LAM_EXCEPTION XCHAL_SEP \ |
| 81 | XTHAL_LAM_EXCEPTION XCHAL_SEP \ |
| 82 | XTHAL_LAM_EXCEPTION XCHAL_SEP \ |
| 83 | XTHAL_LAM_EXCEPTION XCHAL_SEP \ |
| 84 | XTHAL_LAM_EXCEPTION XCHAL_SEP \ |
| 85 | XTHAL_LAM_ISOLATE XCHAL_SEP \ |
| 86 | XTHAL_LAM_EXCEPTION |
| 87 | #define XCHAL_SCA_LIST XTHAL_SAM_WRITETHRU XCHAL_SEP \ |
| 88 | XTHAL_SAM_WRITETHRU XCHAL_SEP \ |
| 89 | XTHAL_SAM_BYPASS XCHAL_SEP \ |
| 90 | XTHAL_SAM_EXCEPTION XCHAL_SEP \ |
| 91 | XTHAL_SAM_WRITEBACK XCHAL_SEP \ |
| 92 | XTHAL_SAM_WRITEBACK_NOALLOC XCHAL_SEP \ |
| 93 | XTHAL_SAM_EXCEPTION XCHAL_SEP \ |
| 94 | XTHAL_SAM_EXCEPTION XCHAL_SEP \ |
| 95 | XTHAL_SAM_EXCEPTION XCHAL_SEP \ |
| 96 | XTHAL_SAM_EXCEPTION XCHAL_SEP \ |
| 97 | XTHAL_SAM_EXCEPTION XCHAL_SEP \ |
| 98 | XTHAL_SAM_EXCEPTION XCHAL_SEP \ |
| 99 | XTHAL_SAM_EXCEPTION XCHAL_SEP \ |
| 100 | XTHAL_SAM_EXCEPTION XCHAL_SEP \ |
| 101 | XTHAL_SAM_ISOLATE XCHAL_SEP \ |
| 102 | XTHAL_SAM_EXCEPTION |
| 103 | |
| 104 | |
| 105 | /* |
| 106 | * Specific encoded cache attribute values of general interest. |
| 107 | * If a specific cache mode is not available, the closest available |
| 108 | * one is returned instead (eg. writethru instead of writeback, |
| 109 | * bypass instead of writethru). |
| 110 | */ |
| 111 | #define XCHAL_CA_BYPASS 2 /* cache disabled (bypassed) mode */ |
| 112 | #define XCHAL_CA_WRITETHRU 1 /* cache enabled (write-through) mode */ |
| 113 | #define XCHAL_CA_WRITEBACK 4 /* cache enabled (write-back) mode */ |
| 114 | #define XCHAL_CA_WRITEBACK_NOALLOC 4 /* cache enabled (write-back no-allocate) mode */ |
| 115 | #define XCHAL_CA_ILLEGAL 15 /* no access allowed (all cause exceptions) mode */ |
| 116 | #define XCHAL_CA_ISOLATE 14 /* cache isolate (accesses go to cache not memory) mode */ |
| 117 | |
| 118 | |
| 119 | /*---------------------------------------------------------------------- |
| 120 | MMU |
| 121 | ----------------------------------------------------------------------*/ |
| 122 | |
| 123 | /* |
| 124 | * General notes on MMU parameters. |
| 125 | * |
| 126 | * Terminology: |
| 127 | * ASID = address-space ID (acts as an "extension" of virtual addresses) |
| 128 | * VPN = virtual page number |
| 129 | * PPN = physical page number |
| 130 | * CA = encoded cache attribute (access modes) |
| 131 | * TLB = translation look-aside buffer (term is stretched somewhat here) |
| 132 | * I = instruction (fetch accesses) |
| 133 | * D = data (load and store accesses) |
| 134 | * way = each TLB (ITLB and DTLB) consists of a number of "ways" |
| 135 | * that simultaneously match the virtual address of an access; |
| 136 | * a TLB successfully translates a virtual address if exactly |
| 137 | * one way matches the vaddr; if none match, it is a miss; |
| 138 | * if multiple match, one gets a "multihit" exception; |
| 139 | * each way can be independently configured in terms of number of |
| 140 | * entries, page sizes, which fields are writable or constant, etc. |
| 141 | * set = group of contiguous ways with exactly identical parameters |
| 142 | * ARF = auto-refill; hardware services a 1st-level miss by loading a PTE |
| 143 | * from the page table and storing it in one of the auto-refill ways; |
| 144 | * if this PTE load also misses, a miss exception is posted for s/w. |
| 145 | * min-wired = a "min-wired" way can be used to map a single (minimum-sized) |
| 146 | * page arbitrarily under program control; it has a single entry, |
| 147 | * is non-auto-refill (some other way(s) must be auto-refill), |
| 148 | * all its fields (VPN, PPN, ASID, CA) are all writable, and it |
| 149 | * supports the XCHAL_MMU_MIN_PTE_PAGE_SIZE page size (a current |
| 150 | * restriction is that this be the only page size it supports). |
| 151 | * |
| 152 | * TLB way entries are virtually indexed. |
| 153 | * TLB ways that support multiple page sizes: |
| 154 | * - must have all writable VPN and PPN fields; |
| 155 | * - can only use one page size at any given time (eg. setup at startup), |
| 156 | * selected by the respective ITLBCFG or DTLBCFG special register, |
| 157 | * whose bits n*4+3 .. n*4 index the list of page sizes for way n |
| 158 | * (XCHAL_xTLB_SETm_PAGESZ_LOG2_LIST for set m corresponding to way n); |
| 159 | * this list may be sparse for auto-refill ways because auto-refill |
| 160 | * ways have independent lists of supported page sizes sharing a |
| 161 | * common encoding with PTE entries; the encoding is the index into |
| 162 | * this list; unsupported sizes for a given way are zero in the list; |
| 163 | * selecting unsupported sizes results in undefined hardware behaviour; |
| 164 | * - is only possible for ways 0 thru 7 (due to ITLBCFG/DTLBCFG definition). |
| 165 | */ |
| 166 | |
| 167 | #define XCHAL_MMU_ASID_INVALID 0 /* ASID value indicating invalid address space */ |
| 168 | #define XCHAL_MMU_ASID_KERNEL 0 /* ASID value indicating kernel (ring 0) address space */ |
| 169 | #define XCHAL_MMU_SR_BITS 0 /* number of size-restriction bits supported */ |
| 170 | #define XCHAL_MMU_CA_BITS 4 /* number of bits needed to hold cache attribute encoding */ |
| 171 | #define XCHAL_MMU_MAX_PTE_PAGE_SIZE 29 /* max page size in a PTE structure (log2) */ |
| 172 | #define XCHAL_MMU_MIN_PTE_PAGE_SIZE 29 /* min page size in a PTE structure (log2) */ |
| 173 | |
| 174 | |
| 175 | /*** Instruction TLB: ***/ |
| 176 | |
| 177 | #define XCHAL_ITLB_WAY_BITS 0 /* number of bits holding the ways */ |
| 178 | #define XCHAL_ITLB_WAYS 1 /* number of ways (n-way set-associative TLB) */ |
| 179 | #define XCHAL_ITLB_ARF_WAYS 0 /* number of auto-refill ways */ |
| 180 | #define XCHAL_ITLB_SETS 1 /* number of sets (groups of ways with identical settings) */ |
| 181 | |
| 182 | /* Way set to which each way belongs: */ |
| 183 | #define XCHAL_ITLB_WAY0_SET 0 |
| 184 | |
| 185 | /* Ways sets that are used by hardware auto-refill (ARF): */ |
| 186 | #define XCHAL_ITLB_ARF_SETS 0 /* number of auto-refill sets */ |
| 187 | |
| 188 | /* Way sets that are "min-wired" (see terminology comment above): */ |
| 189 | #define XCHAL_ITLB_MINWIRED_SETS 0 /* number of "min-wired" sets */ |
| 190 | |
| 191 | |
| 192 | /* ITLB way set 0 (group of ways 0 thru 0): */ |
| 193 | #define XCHAL_ITLB_SET0_WAY 0 /* index of first way in this way set */ |
| 194 | #define XCHAL_ITLB_SET0_WAYS 1 /* number of (contiguous) ways in this way set */ |
| 195 | #define XCHAL_ITLB_SET0_ENTRIES_LOG2 3 /* log2(number of entries in this way) */ |
| 196 | #define XCHAL_ITLB_SET0_ENTRIES 8 /* number of entries in this way (always a power of 2) */ |
| 197 | #define XCHAL_ITLB_SET0_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */ |
| 198 | #define XCHAL_ITLB_SET0_PAGESIZES 1 /* number of supported page sizes in this way */ |
| 199 | #define XCHAL_ITLB_SET0_PAGESZ_BITS 0 /* number of bits to encode the page size */ |
| 200 | #define XCHAL_ITLB_SET0_PAGESZ_LOG2_MIN 29 /* log2(minimum supported page size) */ |
| 201 | #define XCHAL_ITLB_SET0_PAGESZ_LOG2_MAX 29 /* log2(maximum supported page size) */ |
| 202 | #define XCHAL_ITLB_SET0_PAGESZ_LOG2_LIST 29 /* list of log2(page size)s, separated by XCHAL_SEP; |
| 203 | 2^PAGESZ_BITS entries in list, unsupported entries are zero */ |
| 204 | #define XCHAL_ITLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */ |
| 205 | #define XCHAL_ITLB_SET0_VPN_CONSTMASK 0x00000000 /* constant VPN bits, not including entry index bits; 0 if all writable */ |
| 206 | #define XCHAL_ITLB_SET0_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */ |
| 207 | #define XCHAL_ITLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */ |
| 208 | #define XCHAL_ITLB_SET0_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */ |
| 209 | #define XCHAL_ITLB_SET0_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */ |
| 210 | #define XCHAL_ITLB_SET0_PPN_RESET 1 /* 1 if PPN reset values defined (and all writable); 0 otherwise */ |
| 211 | #define XCHAL_ITLB_SET0_CA_RESET 1 /* 1 if CA reset values defined (and all writable); 0 otherwise */ |
| 212 | /* Constant VPN values for each entry of ITLB way set 0 (because VPN_CONSTMASK is non-zero): */ |
| 213 | #define XCHAL_ITLB_SET0_E0_VPN_CONST 0x00000000 |
| 214 | #define XCHAL_ITLB_SET0_E1_VPN_CONST 0x20000000 |
| 215 | #define XCHAL_ITLB_SET0_E2_VPN_CONST 0x40000000 |
| 216 | #define XCHAL_ITLB_SET0_E3_VPN_CONST 0x60000000 |
| 217 | #define XCHAL_ITLB_SET0_E4_VPN_CONST 0x80000000 |
| 218 | #define XCHAL_ITLB_SET0_E5_VPN_CONST 0xA0000000 |
| 219 | #define XCHAL_ITLB_SET0_E6_VPN_CONST 0xC0000000 |
| 220 | #define XCHAL_ITLB_SET0_E7_VPN_CONST 0xE0000000 |
| 221 | /* Reset PPN values for each entry of ITLB way set 0 (because SET0_PPN_RESET is non-zero): */ |
| 222 | #define XCHAL_ITLB_SET0_E0_PPN_RESET 0x00000000 |
| 223 | #define XCHAL_ITLB_SET0_E1_PPN_RESET 0x20000000 |
| 224 | #define XCHAL_ITLB_SET0_E2_PPN_RESET 0x40000000 |
| 225 | #define XCHAL_ITLB_SET0_E3_PPN_RESET 0x60000000 |
| 226 | #define XCHAL_ITLB_SET0_E4_PPN_RESET 0x80000000 |
| 227 | #define XCHAL_ITLB_SET0_E5_PPN_RESET 0xA0000000 |
| 228 | #define XCHAL_ITLB_SET0_E6_PPN_RESET 0xC0000000 |
| 229 | #define XCHAL_ITLB_SET0_E7_PPN_RESET 0xE0000000 |
| 230 | /* Reset CA values for each entry of ITLB way set 0 (because SET0_CA_RESET is non-zero): */ |
| 231 | #define XCHAL_ITLB_SET0_E0_CA_RESET 0x02 |
| 232 | #define XCHAL_ITLB_SET0_E1_CA_RESET 0x02 |
| 233 | #define XCHAL_ITLB_SET0_E2_CA_RESET 0x02 |
| 234 | #define XCHAL_ITLB_SET0_E3_CA_RESET 0x02 |
| 235 | #define XCHAL_ITLB_SET0_E4_CA_RESET 0x02 |
| 236 | #define XCHAL_ITLB_SET0_E5_CA_RESET 0x02 |
| 237 | #define XCHAL_ITLB_SET0_E6_CA_RESET 0x02 |
| 238 | #define XCHAL_ITLB_SET0_E7_CA_RESET 0x02 |
| 239 | |
| 240 | |
| 241 | /*** Data TLB: ***/ |
| 242 | |
| 243 | #define XCHAL_DTLB_WAY_BITS 0 /* number of bits holding the ways */ |
| 244 | #define XCHAL_DTLB_WAYS 1 /* number of ways (n-way set-associative TLB) */ |
| 245 | #define XCHAL_DTLB_ARF_WAYS 0 /* number of auto-refill ways */ |
| 246 | #define XCHAL_DTLB_SETS 1 /* number of sets (groups of ways with identical settings) */ |
| 247 | |
| 248 | /* Way set to which each way belongs: */ |
| 249 | #define XCHAL_DTLB_WAY0_SET 0 |
| 250 | |
| 251 | /* Ways sets that are used by hardware auto-refill (ARF): */ |
| 252 | #define XCHAL_DTLB_ARF_SETS 0 /* number of auto-refill sets */ |
| 253 | |
| 254 | /* Way sets that are "min-wired" (see terminology comment above): */ |
| 255 | #define XCHAL_DTLB_MINWIRED_SETS 0 /* number of "min-wired" sets */ |
| 256 | |
| 257 | |
| 258 | /* DTLB way set 0 (group of ways 0 thru 0): */ |
| 259 | #define XCHAL_DTLB_SET0_WAY 0 /* index of first way in this way set */ |
| 260 | #define XCHAL_DTLB_SET0_WAYS 1 /* number of (contiguous) ways in this way set */ |
| 261 | #define XCHAL_DTLB_SET0_ENTRIES_LOG2 3 /* log2(number of entries in this way) */ |
| 262 | #define XCHAL_DTLB_SET0_ENTRIES 8 /* number of entries in this way (always a power of 2) */ |
| 263 | #define XCHAL_DTLB_SET0_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */ |
| 264 | #define XCHAL_DTLB_SET0_PAGESIZES 1 /* number of supported page sizes in this way */ |
| 265 | #define XCHAL_DTLB_SET0_PAGESZ_BITS 0 /* number of bits to encode the page size */ |
| 266 | #define XCHAL_DTLB_SET0_PAGESZ_LOG2_MIN 29 /* log2(minimum supported page size) */ |
| 267 | #define XCHAL_DTLB_SET0_PAGESZ_LOG2_MAX 29 /* log2(maximum supported page size) */ |
| 268 | #define XCHAL_DTLB_SET0_PAGESZ_LOG2_LIST 29 /* list of log2(page size)s, separated by XCHAL_SEP; |
| 269 | 2^PAGESZ_BITS entries in list, unsupported entries are zero */ |
| 270 | #define XCHAL_DTLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */ |
| 271 | #define XCHAL_DTLB_SET0_VPN_CONSTMASK 0x00000000 /* constant VPN bits, not including entry index bits; 0 if all writable */ |
| 272 | #define XCHAL_DTLB_SET0_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */ |
| 273 | #define XCHAL_DTLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */ |
| 274 | #define XCHAL_DTLB_SET0_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */ |
| 275 | #define XCHAL_DTLB_SET0_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */ |
| 276 | #define XCHAL_DTLB_SET0_PPN_RESET 1 /* 1 if PPN reset values defined (and all writable); 0 otherwise */ |
| 277 | #define XCHAL_DTLB_SET0_CA_RESET 1 /* 1 if CA reset values defined (and all writable); 0 otherwise */ |
| 278 | /* Constant VPN values for each entry of DTLB way set 0 (because VPN_CONSTMASK is non-zero): */ |
| 279 | #define XCHAL_DTLB_SET0_E0_VPN_CONST 0x00000000 |
| 280 | #define XCHAL_DTLB_SET0_E1_VPN_CONST 0x20000000 |
| 281 | #define XCHAL_DTLB_SET0_E2_VPN_CONST 0x40000000 |
| 282 | #define XCHAL_DTLB_SET0_E3_VPN_CONST 0x60000000 |
| 283 | #define XCHAL_DTLB_SET0_E4_VPN_CONST 0x80000000 |
| 284 | #define XCHAL_DTLB_SET0_E5_VPN_CONST 0xA0000000 |
| 285 | #define XCHAL_DTLB_SET0_E6_VPN_CONST 0xC0000000 |
| 286 | #define XCHAL_DTLB_SET0_E7_VPN_CONST 0xE0000000 |
| 287 | /* Reset PPN values for each entry of DTLB way set 0 (because SET0_PPN_RESET is non-zero): */ |
| 288 | #define XCHAL_DTLB_SET0_E0_PPN_RESET 0x00000000 |
| 289 | #define XCHAL_DTLB_SET0_E1_PPN_RESET 0x20000000 |
| 290 | #define XCHAL_DTLB_SET0_E2_PPN_RESET 0x40000000 |
| 291 | #define XCHAL_DTLB_SET0_E3_PPN_RESET 0x60000000 |
| 292 | #define XCHAL_DTLB_SET0_E4_PPN_RESET 0x80000000 |
| 293 | #define XCHAL_DTLB_SET0_E5_PPN_RESET 0xA0000000 |
| 294 | #define XCHAL_DTLB_SET0_E6_PPN_RESET 0xC0000000 |
| 295 | #define XCHAL_DTLB_SET0_E7_PPN_RESET 0xE0000000 |
| 296 | /* Reset CA values for each entry of DTLB way set 0 (because SET0_CA_RESET is non-zero): */ |
| 297 | #define XCHAL_DTLB_SET0_E0_CA_RESET 0x02 |
| 298 | #define XCHAL_DTLB_SET0_E1_CA_RESET 0x02 |
| 299 | #define XCHAL_DTLB_SET0_E2_CA_RESET 0x02 |
| 300 | #define XCHAL_DTLB_SET0_E3_CA_RESET 0x02 |
| 301 | #define XCHAL_DTLB_SET0_E4_CA_RESET 0x02 |
| 302 | #define XCHAL_DTLB_SET0_E5_CA_RESET 0x02 |
| 303 | #define XCHAL_DTLB_SET0_E6_CA_RESET 0x02 |
| 304 | #define XCHAL_DTLB_SET0_E7_CA_RESET 0x02 |
| 305 | |
| 306 | |
| 307 | |
| 308 | |
| 309 | #endif /* XTENSA_CONFIG_CORE_MATMAP_H */ |
| 310 |