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1 /* Xtensa configuration-specific ISA information.
2 Copyright 2003, 2004, 2005 Free Software Foundation, Inc.
3
4 This file is part of BFD, the Binary File Descriptor library.
5
6 This program is free software; you can redistribute it and/or
7 modify it under the terms of the GNU General Public License as
8 published by the Free Software Foundation; either version 2 of the
9 License, or (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, see
18 <https://www.gnu.org/licenses/>. */
19
20 #include "qemu/osdep.h"
21 #include "xtensa-isa.h"
22 #include "xtensa-isa-internal.h"
23
24
25 /* Sysregs. */
26
27 static xtensa_sysreg_internal sysregs[] = {
28 { "LBEG", 0, 0 },
29 { "LEND", 1, 0 },
30 { "LCOUNT", 2, 0 },
31 { "PTEVADDR", 83, 0 },
32 { "DDR", 104, 0 },
33 { "176", 176, 0 },
34 { "208", 208, 0 },
35 { "INTERRUPT", 226, 0 },
36 { "INTCLEAR", 227, 0 },
37 { "CCOUNT", 234, 0 },
38 { "PRID", 235, 0 },
39 { "ICOUNT", 236, 0 },
40 { "CCOMPARE0", 240, 0 },
41 { "CCOMPARE1", 241, 0 },
42 { "CCOMPARE2", 242, 0 },
43 { "EPC1", 177, 0 },
44 { "EPC2", 178, 0 },
45 { "EPC3", 179, 0 },
46 { "EPC4", 180, 0 },
47 { "EXCSAVE1", 209, 0 },
48 { "EXCSAVE2", 210, 0 },
49 { "EXCSAVE3", 211, 0 },
50 { "EXCSAVE4", 212, 0 },
51 { "EPS2", 194, 0 },
52 { "EPS3", 195, 0 },
53 { "EPS4", 196, 0 },
54 { "EXCCAUSE", 232, 0 },
55 { "DEPC", 192, 0 },
56 { "EXCVADDR", 238, 0 },
57 { "WINDOWBASE", 72, 0 },
58 { "WINDOWSTART", 73, 0 },
59 { "SAR", 3, 0 },
60 { "LITBASE", 5, 0 },
61 { "PS", 230, 0 },
62 { "MISC0", 244, 0 },
63 { "MISC1", 245, 0 },
64 { "INTENABLE", 228, 0 },
65 { "DBREAKA0", 144, 0 },
66 { "DBREAKC0", 160, 0 },
67 { "DBREAKA1", 145, 0 },
68 { "DBREAKC1", 161, 0 },
69 { "IBREAKA0", 128, 0 },
70 { "IBREAKA1", 129, 0 },
71 { "IBREAKENABLE", 96, 0 },
72 { "ICOUNTLEVEL", 237, 0 },
73 { "DEBUGCAUSE", 233, 0 },
74 { "RASID", 90, 0 },
75 { "ITLBCFG", 91, 0 },
76 { "DTLBCFG", 92, 0 }
77 };
78
79 #define NUM_SYSREGS 49
80 #define MAX_SPECIAL_REG 245
81 #define MAX_USER_REG 0
82
83
84 /* Processor states. */
85
86 static xtensa_state_internal states[] = {
87 { "LCOUNT", 32, 0 },
88 { "PC", 32, 0 },
89 { "ICOUNT", 32, 0 },
90 { "DDR", 32, 0 },
91 { "INTERRUPT", 17, 0 },
92 { "CCOUNT", 32, 0 },
93 { "XTSYNC", 1, 0 },
94 { "EPC1", 32, 0 },
95 { "EPC2", 32, 0 },
96 { "EPC3", 32, 0 },
97 { "EPC4", 32, 0 },
98 { "EXCSAVE1", 32, 0 },
99 { "EXCSAVE2", 32, 0 },
100 { "EXCSAVE3", 32, 0 },
101 { "EXCSAVE4", 32, 0 },
102 { "EPS2", 15, 0 },
103 { "EPS3", 15, 0 },
104 { "EPS4", 15, 0 },
105 { "EXCCAUSE", 6, 0 },
106 { "PSINTLEVEL", 4, 0 },
107 { "PSUM", 1, 0 },
108 { "PSWOE", 1, 0 },
109 { "PSRING", 2, 0 },
110 { "PSEXCM", 1, 0 },
111 { "DEPC", 32, 0 },
112 { "EXCVADDR", 32, 0 },
113 { "WindowBase", 4, 0 },
114 { "WindowStart", 16, 0 },
115 { "PSCALLINC", 2, 0 },
116 { "PSOWB", 4, 0 },
117 { "LBEG", 32, 0 },
118 { "LEND", 32, 0 },
119 { "SAR", 6, 0 },
120 { "LITBADDR", 20, 0 },
121 { "LITBEN", 1, 0 },
122 { "MISC0", 32, 0 },
123 { "MISC1", 32, 0 },
124 { "InOCDMode", 1, 0 },
125 { "INTENABLE", 17, 0 },
126 { "DBREAKA0", 32, 0 },
127 { "DBREAKC0", 8, 0 },
128 { "DBREAKA1", 32, 0 },
129 { "DBREAKC1", 8, 0 },
130 { "IBREAKA0", 32, 0 },
131 { "IBREAKA1", 32, 0 },
132 { "IBREAKENABLE", 2, 0 },
133 { "ICOUNTLEVEL", 4, 0 },
134 { "DEBUGCAUSE", 6, 0 },
135 { "DBNUM", 4, 0 },
136 { "CCOMPARE0", 32, 0 },
137 { "CCOMPARE1", 32, 0 },
138 { "CCOMPARE2", 32, 0 },
139 { "ASID3", 8, 0 },
140 { "ASID2", 8, 0 },
141 { "ASID1", 8, 0 },
142 { "INSTPGSZID4", 2, 0 },
143 { "DATAPGSZID4", 2, 0 },
144 { "PTBASE", 10, 0 }
145 };
146
147 #define NUM_STATES 58
148
149 /* Macros for xtensa_state numbers (for use in iclasses because the
150 state numbers are not available when the iclass table is generated). */
151
152 #define STATE_LCOUNT 0
153 #define STATE_PC 1
154 #define STATE_ICOUNT 2
155 #define STATE_DDR 3
156 #define STATE_INTERRUPT 4
157 #define STATE_CCOUNT 5
158 #define STATE_XTSYNC 6
159 #define STATE_EPC1 7
160 #define STATE_EPC2 8
161 #define STATE_EPC3 9
162 #define STATE_EPC4 10
163 #define STATE_EXCSAVE1 11
164 #define STATE_EXCSAVE2 12
165 #define STATE_EXCSAVE3 13
166 #define STATE_EXCSAVE4 14
167 #define STATE_EPS2 15
168 #define STATE_EPS3 16
169 #define STATE_EPS4 17
170 #define STATE_EXCCAUSE 18
171 #define STATE_PSINTLEVEL 19
172 #define STATE_PSUM 20
173 #define STATE_PSWOE 21
174 #define STATE_PSRING 22
175 #define STATE_PSEXCM 23
176 #define STATE_DEPC 24
177 #define STATE_EXCVADDR 25
178 #define STATE_WindowBase 26
179 #define STATE_WindowStart 27
180 #define STATE_PSCALLINC 28
181 #define STATE_PSOWB 29
182 #define STATE_LBEG 30
183 #define STATE_LEND 31
184 #define STATE_SAR 32
185 #define STATE_LITBADDR 33
186 #define STATE_LITBEN 34
187 #define STATE_MISC0 35
188 #define STATE_MISC1 36
189 #define STATE_InOCDMode 37
190 #define STATE_INTENABLE 38
191 #define STATE_DBREAKA0 39
192 #define STATE_DBREAKC0 40
193 #define STATE_DBREAKA1 41
194 #define STATE_DBREAKC1 42
195 #define STATE_IBREAKA0 43
196 #define STATE_IBREAKA1 44
197 #define STATE_IBREAKENABLE 45
198 #define STATE_ICOUNTLEVEL 46
199 #define STATE_DEBUGCAUSE 47
200 #define STATE_DBNUM 48
201 #define STATE_CCOMPARE0 49
202 #define STATE_CCOMPARE1 50
203 #define STATE_CCOMPARE2 51
204 #define STATE_ASID3 52
205 #define STATE_ASID2 53
206 #define STATE_ASID1 54
207 #define STATE_INSTPGSZID4 55
208 #define STATE_DATAPGSZID4 56
209 #define STATE_PTBASE 57
210
211
212 /* Field definitions. */
213
214 static unsigned
215 Field_t_Slot_inst_get (const xtensa_insnbuf insn)
216 {
217 unsigned tie_t = 0;
218 tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
219 return tie_t;
220 }
221
222 static void
223 Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
224 {
225 uint32 tie_t;
226 tie_t = (val << 28) >> 28;
227 insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
228 }
229
230 static unsigned
231 Field_s_Slot_inst_get (const xtensa_insnbuf insn)
232 {
233 unsigned tie_t = 0;
234 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
235 return tie_t;
236 }
237
238 static void
239 Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
240 {
241 uint32 tie_t;
242 tie_t = (val << 28) >> 28;
243 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
244 }
245
246 static unsigned
247 Field_r_Slot_inst_get (const xtensa_insnbuf insn)
248 {
249 unsigned tie_t = 0;
250 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
251 return tie_t;
252 }
253
254 static void
255 Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
256 {
257 uint32 tie_t;
258 tie_t = (val << 28) >> 28;
259 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
260 }
261
262 static unsigned
263 Field_op2_Slot_inst_get (const xtensa_insnbuf insn)
264 {
265 unsigned tie_t = 0;
266 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
267 return tie_t;
268 }
269
270 static void
271 Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
272 {
273 uint32 tie_t;
274 tie_t = (val << 28) >> 28;
275 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
276 }
277
278 static unsigned
279 Field_op1_Slot_inst_get (const xtensa_insnbuf insn)
280 {
281 unsigned tie_t = 0;
282 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
283 return tie_t;
284 }
285
286 static void
287 Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
288 {
289 uint32 tie_t;
290 tie_t = (val << 28) >> 28;
291 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
292 }
293
294 static unsigned
295 Field_op0_Slot_inst_get (const xtensa_insnbuf insn)
296 {
297 unsigned tie_t = 0;
298 tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28);
299 return tie_t;
300 }
301
302 static void
303 Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
304 {
305 uint32 tie_t;
306 tie_t = (val << 28) >> 28;
307 insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20);
308 }
309
310 static unsigned
311 Field_n_Slot_inst_get (const xtensa_insnbuf insn)
312 {
313 unsigned tie_t = 0;
314 tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30);
315 return tie_t;
316 }
317
318 static void
319 Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
320 {
321 uint32 tie_t;
322 tie_t = (val << 30) >> 30;
323 insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18);
324 }
325
326 static unsigned
327 Field_m_Slot_inst_get (const xtensa_insnbuf insn)
328 {
329 unsigned tie_t = 0;
330 tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30);
331 return tie_t;
332 }
333
334 static void
335 Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
336 {
337 uint32 tie_t;
338 tie_t = (val << 30) >> 30;
339 insn[0] = (insn[0] & ~0x30000) | (tie_t << 16);
340 }
341
342 static unsigned
343 Field_sr_Slot_inst_get (const xtensa_insnbuf insn)
344 {
345 unsigned tie_t = 0;
346 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
347 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
348 return tie_t;
349 }
350
351 static void
352 Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
353 {
354 uint32 tie_t;
355 tie_t = (val << 28) >> 28;
356 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
357 tie_t = (val << 24) >> 28;
358 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
359 }
360
361 static unsigned
362 Field_thi3_Slot_inst_get (const xtensa_insnbuf insn)
363 {
364 unsigned tie_t = 0;
365 tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29);
366 return tie_t;
367 }
368
369 static void
370 Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
371 {
372 uint32 tie_t;
373 tie_t = (val << 29) >> 29;
374 insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17);
375 }
376
377 static unsigned
378 Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn)
379 {
380 unsigned tie_t = 0;
381 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
382 return tie_t;
383 }
384
385 static void
386 Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
387 {
388 uint32 tie_t;
389 tie_t = (val << 28) >> 28;
390 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
391 }
392
393 static unsigned
394 Field_t_Slot_inst16b_get (const xtensa_insnbuf insn)
395 {
396 unsigned tie_t = 0;
397 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
398 return tie_t;
399 }
400
401 static void
402 Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
403 {
404 uint32 tie_t;
405 tie_t = (val << 28) >> 28;
406 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
407 }
408
409 static unsigned
410 Field_r_Slot_inst16b_get (const xtensa_insnbuf insn)
411 {
412 unsigned tie_t = 0;
413 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
414 return tie_t;
415 }
416
417 static void
418 Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
419 {
420 uint32 tie_t;
421 tie_t = (val << 28) >> 28;
422 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
423 }
424
425 static unsigned
426 Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn)
427 {
428 unsigned tie_t = 0;
429 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
430 return tie_t;
431 }
432
433 static void
434 Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
435 {
436 uint32 tie_t;
437 tie_t = (val << 28) >> 28;
438 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
439 }
440
441 static unsigned
442 Field_z_Slot_inst16b_get (const xtensa_insnbuf insn)
443 {
444 unsigned tie_t = 0;
445 tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31);
446 return tie_t;
447 }
448
449 static void
450 Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
451 {
452 uint32 tie_t;
453 tie_t = (val << 31) >> 31;
454 insn[0] = (insn[0] & ~0x400) | (tie_t << 10);
455 }
456
457 static unsigned
458 Field_i_Slot_inst16b_get (const xtensa_insnbuf insn)
459 {
460 unsigned tie_t = 0;
461 tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
462 return tie_t;
463 }
464
465 static void
466 Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
467 {
468 uint32 tie_t;
469 tie_t = (val << 31) >> 31;
470 insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
471 }
472
473 static unsigned
474 Field_s_Slot_inst16b_get (const xtensa_insnbuf insn)
475 {
476 unsigned tie_t = 0;
477 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
478 return tie_t;
479 }
480
481 static void
482 Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
483 {
484 uint32 tie_t;
485 tie_t = (val << 28) >> 28;
486 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
487 }
488
489 static unsigned
490 Field_t_Slot_inst16a_get (const xtensa_insnbuf insn)
491 {
492 unsigned tie_t = 0;
493 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
494 return tie_t;
495 }
496
497 static void
498 Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
499 {
500 uint32 tie_t;
501 tie_t = (val << 28) >> 28;
502 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
503 }
504
505 static unsigned
506 Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn)
507 {
508 unsigned tie_t = 0;
509 tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
510 return tie_t;
511 }
512
513 static void
514 Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
515 {
516 uint32 tie_t;
517 tie_t = (val << 31) >> 31;
518 insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
519 }
520
521 static unsigned
522 Field_bbi_Slot_inst_get (const xtensa_insnbuf insn)
523 {
524 unsigned tie_t = 0;
525 tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
526 tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
527 return tie_t;
528 }
529
530 static void
531 Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
532 {
533 uint32 tie_t;
534 tie_t = (val << 28) >> 28;
535 insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
536 tie_t = (val << 27) >> 31;
537 insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
538 }
539
540 static unsigned
541 Field_imm12_Slot_inst_get (const xtensa_insnbuf insn)
542 {
543 unsigned tie_t = 0;
544 tie_t = (tie_t << 12) | ((insn[0] << 20) >> 20);
545 return tie_t;
546 }
547
548 static void
549 Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
550 {
551 uint32 tie_t;
552 tie_t = (val << 20) >> 20;
553 insn[0] = (insn[0] & ~0xfff) | (tie_t << 0);
554 }
555
556 static unsigned
557 Field_imm8_Slot_inst_get (const xtensa_insnbuf insn)
558 {
559 unsigned tie_t = 0;
560 tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24);
561 return tie_t;
562 }
563
564 static void
565 Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
566 {
567 uint32 tie_t;
568 tie_t = (val << 24) >> 24;
569 insn[0] = (insn[0] & ~0xff) | (tie_t << 0);
570 }
571
572 static unsigned
573 Field_s_Slot_inst16a_get (const xtensa_insnbuf insn)
574 {
575 unsigned tie_t = 0;
576 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
577 return tie_t;
578 }
579
580 static void
581 Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
582 {
583 uint32 tie_t;
584 tie_t = (val << 28) >> 28;
585 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
586 }
587
588 static unsigned
589 Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn)
590 {
591 unsigned tie_t = 0;
592 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
593 tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24);
594 return tie_t;
595 }
596
597 static void
598 Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
599 {
600 uint32 tie_t;
601 tie_t = (val << 24) >> 24;
602 insn[0] = (insn[0] & ~0xff) | (tie_t << 0);
603 tie_t = (val << 20) >> 28;
604 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
605 }
606
607 static unsigned
608 Field_imm16_Slot_inst_get (const xtensa_insnbuf insn)
609 {
610 unsigned tie_t = 0;
611 tie_t = (tie_t << 16) | ((insn[0] << 16) >> 16);
612 return tie_t;
613 }
614
615 static void
616 Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
617 {
618 uint32 tie_t;
619 tie_t = (val << 16) >> 16;
620 insn[0] = (insn[0] & ~0xffff) | (tie_t << 0);
621 }
622
623 static unsigned
624 Field_offset_Slot_inst_get (const xtensa_insnbuf insn)
625 {
626 unsigned tie_t = 0;
627 tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14);
628 return tie_t;
629 }
630
631 static void
632 Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
633 {
634 uint32 tie_t;
635 tie_t = (val << 14) >> 14;
636 insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0);
637 }
638
639 static unsigned
640 Field_r_Slot_inst16a_get (const xtensa_insnbuf insn)
641 {
642 unsigned tie_t = 0;
643 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
644 return tie_t;
645 }
646
647 static void
648 Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
649 {
650 uint32 tie_t;
651 tie_t = (val << 28) >> 28;
652 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
653 }
654
655 static unsigned
656 Field_sa4_Slot_inst_get (const xtensa_insnbuf insn)
657 {
658 unsigned tie_t = 0;
659 tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
660 return tie_t;
661 }
662
663 static void
664 Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
665 {
666 uint32 tie_t;
667 tie_t = (val << 31) >> 31;
668 insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
669 }
670
671 static unsigned
672 Field_sae4_Slot_inst_get (const xtensa_insnbuf insn)
673 {
674 unsigned tie_t = 0;
675 tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
676 return tie_t;
677 }
678
679 static void
680 Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
681 {
682 uint32 tie_t;
683 tie_t = (val << 31) >> 31;
684 insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
685 }
686
687 static unsigned
688 Field_sae_Slot_inst_get (const xtensa_insnbuf insn)
689 {
690 unsigned tie_t = 0;
691 tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
692 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
693 return tie_t;
694 }
695
696 static void
697 Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
698 {
699 uint32 tie_t;
700 tie_t = (val << 28) >> 28;
701 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
702 tie_t = (val << 27) >> 31;
703 insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
704 }
705
706 static unsigned
707 Field_sal_Slot_inst_get (const xtensa_insnbuf insn)
708 {
709 unsigned tie_t = 0;
710 tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
711 tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
712 return tie_t;
713 }
714
715 static void
716 Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
717 {
718 uint32 tie_t;
719 tie_t = (val << 28) >> 28;
720 insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
721 tie_t = (val << 27) >> 31;
722 insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
723 }
724
725 static unsigned
726 Field_sargt_Slot_inst_get (const xtensa_insnbuf insn)
727 {
728 unsigned tie_t = 0;
729 tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
730 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
731 return tie_t;
732 }
733
734 static void
735 Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
736 {
737 uint32 tie_t;
738 tie_t = (val << 28) >> 28;
739 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
740 tie_t = (val << 27) >> 31;
741 insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
742 }
743
744 static unsigned
745 Field_sas4_Slot_inst_get (const xtensa_insnbuf insn)
746 {
747 unsigned tie_t = 0;
748 tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
749 return tie_t;
750 }
751
752 static void
753 Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
754 {
755 uint32 tie_t;
756 tie_t = (val << 31) >> 31;
757 insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
758 }
759
760 static unsigned
761 Field_sas_Slot_inst_get (const xtensa_insnbuf insn)
762 {
763 unsigned tie_t = 0;
764 tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
765 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
766 return tie_t;
767 }
768
769 static void
770 Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
771 {
772 uint32 tie_t;
773 tie_t = (val << 28) >> 28;
774 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
775 tie_t = (val << 27) >> 31;
776 insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
777 }
778
779 static unsigned
780 Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn)
781 {
782 unsigned tie_t = 0;
783 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
784 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
785 return tie_t;
786 }
787
788 static void
789 Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
790 {
791 uint32 tie_t;
792 tie_t = (val << 28) >> 28;
793 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
794 tie_t = (val << 24) >> 28;
795 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
796 }
797
798 static unsigned
799 Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn)
800 {
801 unsigned tie_t = 0;
802 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
803 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
804 return tie_t;
805 }
806
807 static void
808 Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
809 {
810 uint32 tie_t;
811 tie_t = (val << 28) >> 28;
812 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
813 tie_t = (val << 24) >> 28;
814 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
815 }
816
817 static unsigned
818 Field_st_Slot_inst_get (const xtensa_insnbuf insn)
819 {
820 unsigned tie_t = 0;
821 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
822 tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
823 return tie_t;
824 }
825
826 static void
827 Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
828 {
829 uint32 tie_t;
830 tie_t = (val << 28) >> 28;
831 insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
832 tie_t = (val << 24) >> 28;
833 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
834 }
835
836 static unsigned
837 Field_st_Slot_inst16a_get (const xtensa_insnbuf insn)
838 {
839 unsigned tie_t = 0;
840 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
841 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
842 return tie_t;
843 }
844
845 static void
846 Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
847 {
848 uint32 tie_t;
849 tie_t = (val << 28) >> 28;
850 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
851 tie_t = (val << 24) >> 28;
852 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
853 }
854
855 static unsigned
856 Field_st_Slot_inst16b_get (const xtensa_insnbuf insn)
857 {
858 unsigned tie_t = 0;
859 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
860 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
861 return tie_t;
862 }
863
864 static void
865 Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
866 {
867 uint32 tie_t;
868 tie_t = (val << 28) >> 28;
869 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
870 tie_t = (val << 24) >> 28;
871 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
872 }
873
874 static unsigned
875 Field_imm4_Slot_inst_get (const xtensa_insnbuf insn)
876 {
877 unsigned tie_t = 0;
878 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
879 return tie_t;
880 }
881
882 static void
883 Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
884 {
885 uint32 tie_t;
886 tie_t = (val << 28) >> 28;
887 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
888 }
889
890 static unsigned
891 Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn)
892 {
893 unsigned tie_t = 0;
894 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
895 return tie_t;
896 }
897
898 static void
899 Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
900 {
901 uint32 tie_t;
902 tie_t = (val << 28) >> 28;
903 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
904 }
905
906 static unsigned
907 Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn)
908 {
909 unsigned tie_t = 0;
910 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
911 return tie_t;
912 }
913
914 static void
915 Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
916 {
917 uint32 tie_t;
918 tie_t = (val << 28) >> 28;
919 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
920 }
921
922 static unsigned
923 Field_mn_Slot_inst_get (const xtensa_insnbuf insn)
924 {
925 unsigned tie_t = 0;
926 tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30);
927 tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30);
928 return tie_t;
929 }
930
931 static void
932 Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
933 {
934 uint32 tie_t;
935 tie_t = (val << 30) >> 30;
936 insn[0] = (insn[0] & ~0x30000) | (tie_t << 16);
937 tie_t = (val << 28) >> 30;
938 insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18);
939 }
940
941 static unsigned
942 Field_i_Slot_inst16a_get (const xtensa_insnbuf insn)
943 {
944 unsigned tie_t = 0;
945 tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
946 return tie_t;
947 }
948
949 static void
950 Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
951 {
952 uint32 tie_t;
953 tie_t = (val << 31) >> 31;
954 insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
955 }
956
957 static unsigned
958 Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn)
959 {
960 unsigned tie_t = 0;
961 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
962 return tie_t;
963 }
964
965 static void
966 Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
967 {
968 uint32 tie_t;
969 tie_t = (val << 28) >> 28;
970 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
971 }
972
973 static unsigned
974 Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn)
975 {
976 unsigned tie_t = 0;
977 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
978 return tie_t;
979 }
980
981 static void
982 Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
983 {
984 uint32 tie_t;
985 tie_t = (val << 28) >> 28;
986 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
987 }
988
989 static unsigned
990 Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn)
991 {
992 unsigned tie_t = 0;
993 tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
994 return tie_t;
995 }
996
997 static void
998 Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
999 {
1000 uint32 tie_t;
1001 tie_t = (val << 30) >> 30;
1002 insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
1003 }
1004
1005 static unsigned
1006 Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn)
1007 {
1008 unsigned tie_t = 0;
1009 tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
1010 return tie_t;
1011 }
1012
1013 static void
1014 Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1015 {
1016 uint32 tie_t;
1017 tie_t = (val << 30) >> 30;
1018 insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
1019 }
1020
1021 static unsigned
1022 Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn)
1023 {
1024 unsigned tie_t = 0;
1025 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1026 return tie_t;
1027 }
1028
1029 static void
1030 Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1031 {
1032 uint32 tie_t;
1033 tie_t = (val << 28) >> 28;
1034 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1035 }
1036
1037 static unsigned
1038 Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn)
1039 {
1040 unsigned tie_t = 0;
1041 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1042 return tie_t;
1043 }
1044
1045 static void
1046 Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1047 {
1048 uint32 tie_t;
1049 tie_t = (val << 28) >> 28;
1050 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1051 }
1052
1053 static unsigned
1054 Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn)
1055 {
1056 unsigned tie_t = 0;
1057 tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
1058 return tie_t;
1059 }
1060
1061 static void
1062 Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1063 {
1064 uint32 tie_t;
1065 tie_t = (val << 29) >> 29;
1066 insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
1067 }
1068
1069 static unsigned
1070 Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn)
1071 {
1072 unsigned tie_t = 0;
1073 tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
1074 return tie_t;
1075 }
1076
1077 static void
1078 Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1079 {
1080 uint32 tie_t;
1081 tie_t = (val << 29) >> 29;
1082 insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
1083 }
1084
1085 static unsigned
1086 Field_z_Slot_inst16a_get (const xtensa_insnbuf insn)
1087 {
1088 unsigned tie_t = 0;
1089 tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31);
1090 return tie_t;
1091 }
1092
1093 static void
1094 Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1095 {
1096 uint32 tie_t;
1097 tie_t = (val << 31) >> 31;
1098 insn[0] = (insn[0] & ~0x400) | (tie_t << 10);
1099 }
1100
1101 static unsigned
1102 Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn)
1103 {
1104 unsigned tie_t = 0;
1105 tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
1106 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1107 return tie_t;
1108 }
1109
1110 static void
1111 Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1112 {
1113 uint32 tie_t;
1114 tie_t = (val << 28) >> 28;
1115 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1116 tie_t = (val << 26) >> 30;
1117 insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
1118 }
1119
1120 static unsigned
1121 Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn)
1122 {
1123 unsigned tie_t = 0;
1124 tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
1125 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1126 return tie_t;
1127 }
1128
1129 static void
1130 Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1131 {
1132 uint32 tie_t;
1133 tie_t = (val << 28) >> 28;
1134 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1135 tie_t = (val << 26) >> 30;
1136 insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
1137 }
1138
1139 static unsigned
1140 Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn)
1141 {
1142 unsigned tie_t = 0;
1143 tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
1144 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1145 return tie_t;
1146 }
1147
1148 static void
1149 Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1150 {
1151 uint32 tie_t;
1152 tie_t = (val << 28) >> 28;
1153 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1154 tie_t = (val << 25) >> 29;
1155 insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
1156 }
1157
1158 static unsigned
1159 Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn)
1160 {
1161 unsigned tie_t = 0;
1162 tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
1163 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1164 return tie_t;
1165 }
1166
1167 static void
1168 Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1169 {
1170 uint32 tie_t;
1171 tie_t = (val << 28) >> 28;
1172 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1173 tie_t = (val << 25) >> 29;
1174 insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
1175 }
1176
1177 static void
1178 Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED,
1179 uint32 val ATTRIBUTE_UNUSED)
1180 {
1181 /* Do nothing. */
1182 }
1183
1184 static unsigned
1185 Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1186 {
1187 return 0;
1188 }
1189
1190 static unsigned
1191 Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1192 {
1193 return 4;
1194 }
1195
1196 static unsigned
1197 Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1198 {
1199 return 8;
1200 }
1201
1202 static unsigned
1203 Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1204 {
1205 return 12;
1206 }
1207
1208
1209 /* Functional units. */
1210
1211 static xtensa_funcUnit_internal funcUnits[] = {
1212
1213 };
1214
1215
1216 /* Register files. */
1217
1218 static xtensa_regfile_internal regfiles[] = {
1219 { "AR", "a", 0, 32, 64 }
1220 };
1221
1222
1223 /* Interfaces. */
1224
1225 static xtensa_interface_internal interfaces[] = {
1226
1227 };
1228
1229
1230 /* Constant tables. */
1231
1232 /* constant table ai4c */
1233 static const unsigned CONST_TBL_ai4c_0[] = {
1234 0xffffffff,
1235 0x1,
1236 0x2,
1237 0x3,
1238 0x4,
1239 0x5,
1240 0x6,
1241 0x7,
1242 0x8,
1243 0x9,
1244 0xa,
1245 0xb,
1246 0xc,
1247 0xd,
1248 0xe,
1249 0xf,
1250 0
1251 };
1252
1253 /* constant table b4c */
1254 static const unsigned CONST_TBL_b4c_0[] = {
1255 0xffffffff,
1256 0x1,
1257 0x2,
1258 0x3,
1259 0x4,
1260 0x5,
1261 0x6,
1262 0x7,
1263 0x8,
1264 0xa,
1265 0xc,
1266 0x10,
1267 0x20,
1268 0x40,
1269 0x80,
1270 0x100,
1271 0
1272 };
1273
1274 /* constant table b4cu */
1275 static const unsigned CONST_TBL_b4cu_0[] = {
1276 0x8000,
1277 0x10000,
1278 0x2,
1279 0x3,
1280 0x4,
1281 0x5,
1282 0x6,
1283 0x7,
1284 0x8,
1285 0xa,
1286 0xc,
1287 0x10,
1288 0x20,
1289 0x40,
1290 0x80,
1291 0x100,
1292 0
1293 };
1294
1295
1296 /* Instruction operands. */
1297
1298 static int
1299 Operand_soffsetx4_decode (uint32 *valp)
1300 {
1301 unsigned soffsetx4_0, offset_0;
1302 offset_0 = *valp & 0x3ffff;
1303 soffsetx4_0 = 0x4 + ((((int) offset_0 << 14) >> 14) << 2);
1304 *valp = soffsetx4_0;
1305 return 0;
1306 }
1307
1308 static int
1309 Operand_soffsetx4_encode (uint32 *valp)
1310 {
1311 unsigned offset_0, soffsetx4_0;
1312 soffsetx4_0 = *valp;
1313 offset_0 = ((soffsetx4_0 - 0x4) >> 2) & 0x3ffff;
1314 *valp = offset_0;
1315 return 0;
1316 }
1317
1318 static int
1319 Operand_soffsetx4_ator (uint32 *valp, uint32 pc)
1320 {
1321 *valp -= (pc & ~0x3);
1322 return 0;
1323 }
1324
1325 static int
1326 Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc)
1327 {
1328 *valp += (pc & ~0x3);
1329 return 0;
1330 }
1331
1332 static int
1333 Operand_uimm12x8_decode (uint32 *valp)
1334 {
1335 unsigned uimm12x8_0, imm12_0;
1336 imm12_0 = *valp & 0xfff;
1337 uimm12x8_0 = imm12_0 << 3;
1338 *valp = uimm12x8_0;
1339 return 0;
1340 }
1341
1342 static int
1343 Operand_uimm12x8_encode (uint32 *valp)
1344 {
1345 unsigned imm12_0, uimm12x8_0;
1346 uimm12x8_0 = *valp;
1347 imm12_0 = ((uimm12x8_0 >> 3) & 0xfff);
1348 *valp = imm12_0;
1349 return 0;
1350 }
1351
1352 static int
1353 Operand_simm4_decode (uint32 *valp)
1354 {
1355 unsigned simm4_0, mn_0;
1356 mn_0 = *valp & 0xf;
1357 simm4_0 = ((int) mn_0 << 28) >> 28;
1358 *valp = simm4_0;
1359 return 0;
1360 }
1361
1362 static int
1363 Operand_simm4_encode (uint32 *valp)
1364 {
1365 unsigned mn_0, simm4_0;
1366 simm4_0 = *valp;
1367 mn_0 = (simm4_0 & 0xf);
1368 *valp = mn_0;
1369 return 0;
1370 }
1371
1372 static int
1373 Operand_arr_decode (uint32 *valp ATTRIBUTE_UNUSED)
1374 {
1375 return 0;
1376 }
1377
1378 static int
1379 Operand_arr_encode (uint32 *valp)
1380 {
1381 return (*valp & ~0xf) != 0;
1382 }
1383
1384 static int
1385 Operand_ars_decode (uint32 *valp ATTRIBUTE_UNUSED)
1386 {
1387 return 0;
1388 }
1389
1390 static int
1391 Operand_ars_encode (uint32 *valp)
1392 {
1393 return (*valp & ~0xf) != 0;
1394 }
1395
1396 static int
1397 Operand_art_decode (uint32 *valp ATTRIBUTE_UNUSED)
1398 {
1399 return 0;
1400 }
1401
1402 static int
1403 Operand_art_encode (uint32 *valp)
1404 {
1405 return (*valp & ~0xf) != 0;
1406 }
1407
1408 static int
1409 Operand_ar0_decode (uint32 *valp ATTRIBUTE_UNUSED)
1410 {
1411 return 0;
1412 }
1413
1414 static int
1415 Operand_ar0_encode (uint32 *valp)
1416 {
1417 return (*valp & ~0x3f) != 0;
1418 }
1419
1420 static int
1421 Operand_ar4_decode (uint32 *valp ATTRIBUTE_UNUSED)
1422 {
1423 return 0;
1424 }
1425
1426 static int
1427 Operand_ar4_encode (uint32 *valp)
1428 {
1429 return (*valp & ~0x3f) != 0;
1430 }
1431
1432 static int
1433 Operand_ar8_decode (uint32 *valp ATTRIBUTE_UNUSED)
1434 {
1435 return 0;
1436 }
1437
1438 static int
1439 Operand_ar8_encode (uint32 *valp)
1440 {
1441 return (*valp & ~0x3f) != 0;
1442 }
1443
1444 static int
1445 Operand_ar12_decode (uint32 *valp ATTRIBUTE_UNUSED)
1446 {
1447 return 0;
1448 }
1449
1450 static int
1451 Operand_ar12_encode (uint32 *valp)
1452 {
1453 return (*valp & ~0x3f) != 0;
1454 }
1455
1456 static int
1457 Operand_ars_entry_decode (uint32 *valp ATTRIBUTE_UNUSED)
1458 {
1459 return 0;
1460 }
1461
1462 static int
1463 Operand_ars_entry_encode (uint32 *valp)
1464 {
1465 return (*valp & ~0x3f) != 0;
1466 }
1467
1468 static int
1469 Operand_immrx4_decode (uint32 *valp)
1470 {
1471 unsigned immrx4_0, r_0;
1472 r_0 = *valp & 0xf;
1473 immrx4_0 = ((((0xfffffff)) << 4) | r_0) << 2;
1474 *valp = immrx4_0;
1475 return 0;
1476 }
1477
1478 static int
1479 Operand_immrx4_encode (uint32 *valp)
1480 {
1481 unsigned r_0, immrx4_0;
1482 immrx4_0 = *valp;
1483 r_0 = ((immrx4_0 >> 2) & 0xf);
1484 *valp = r_0;
1485 return 0;
1486 }
1487
1488 static int
1489 Operand_lsi4x4_decode (uint32 *valp)
1490 {
1491 unsigned lsi4x4_0, r_0;
1492 r_0 = *valp & 0xf;
1493 lsi4x4_0 = r_0 << 2;
1494 *valp = lsi4x4_0;
1495 return 0;
1496 }
1497
1498 static int
1499 Operand_lsi4x4_encode (uint32 *valp)
1500 {
1501 unsigned r_0, lsi4x4_0;
1502 lsi4x4_0 = *valp;
1503 r_0 = ((lsi4x4_0 >> 2) & 0xf);
1504 *valp = r_0;
1505 return 0;
1506 }
1507
1508 static int
1509 Operand_simm7_decode (uint32 *valp)
1510 {
1511 unsigned simm7_0, imm7_0;
1512 imm7_0 = *valp & 0x7f;
1513 simm7_0 = ((((-((((imm7_0 >> 6) & 1)) & (((imm7_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | imm7_0;
1514 *valp = simm7_0;
1515 return 0;
1516 }
1517
1518 static int
1519 Operand_simm7_encode (uint32 *valp)
1520 {
1521 unsigned imm7_0, simm7_0;
1522 simm7_0 = *valp;
1523 imm7_0 = (simm7_0 & 0x7f);
1524 *valp = imm7_0;
1525 return 0;
1526 }
1527
1528 static int
1529 Operand_uimm6_decode (uint32 *valp)
1530 {
1531 unsigned uimm6_0, imm6_0;
1532 imm6_0 = *valp & 0x3f;
1533 uimm6_0 = 0x4 + ((((0)) << 6) | imm6_0);
1534 *valp = uimm6_0;
1535 return 0;
1536 }
1537
1538 static int
1539 Operand_uimm6_encode (uint32 *valp)
1540 {
1541 unsigned imm6_0, uimm6_0;
1542 uimm6_0 = *valp;
1543 imm6_0 = (uimm6_0 - 0x4) & 0x3f;
1544 *valp = imm6_0;
1545 return 0;
1546 }
1547
1548 static int
1549 Operand_uimm6_ator (uint32 *valp, uint32 pc)
1550 {
1551 *valp -= pc;
1552 return 0;
1553 }
1554
1555 static int
1556 Operand_uimm6_rtoa (uint32 *valp, uint32 pc)
1557 {
1558 *valp += pc;
1559 return 0;
1560 }
1561
1562 static int
1563 Operand_ai4const_decode (uint32 *valp)
1564 {
1565 unsigned ai4const_0, t_0;
1566 t_0 = *valp & 0xf;
1567 ai4const_0 = CONST_TBL_ai4c_0[t_0 & 0xf];
1568 *valp = ai4const_0;
1569 return 0;
1570 }
1571
1572 static int
1573 Operand_ai4const_encode (uint32 *valp)
1574 {
1575 unsigned t_0, ai4const_0;
1576 ai4const_0 = *valp;
1577 switch (ai4const_0)
1578 {
1579 case 0xffffffff: t_0 = 0; break;
1580 case 0x1: t_0 = 0x1; break;
1581 case 0x2: t_0 = 0x2; break;
1582 case 0x3: t_0 = 0x3; break;
1583 case 0x4: t_0 = 0x4; break;
1584 case 0x5: t_0 = 0x5; break;
1585 case 0x6: t_0 = 0x6; break;
1586 case 0x7: t_0 = 0x7; break;
1587 case 0x8: t_0 = 0x8; break;
1588 case 0x9: t_0 = 0x9; break;
1589 case 0xa: t_0 = 0xa; break;
1590 case 0xb: t_0 = 0xb; break;
1591 case 0xc: t_0 = 0xc; break;
1592 case 0xd: t_0 = 0xd; break;
1593 case 0xe: t_0 = 0xe; break;
1594 default: t_0 = 0xf; break;
1595 }
1596 *valp = t_0;
1597 return 0;
1598 }
1599
1600 static int
1601 Operand_b4const_decode (uint32 *valp)
1602 {
1603 unsigned b4const_0, r_0;
1604 r_0 = *valp & 0xf;
1605 b4const_0 = CONST_TBL_b4c_0[r_0 & 0xf];
1606 *valp = b4const_0;
1607 return 0;
1608 }
1609
1610 static int
1611 Operand_b4const_encode (uint32 *valp)
1612 {
1613 unsigned r_0, b4const_0;
1614 b4const_0 = *valp;
1615 switch (b4const_0)
1616 {
1617 case 0xffffffff: r_0 = 0; break;
1618 case 0x1: r_0 = 0x1; break;
1619 case 0x2: r_0 = 0x2; break;
1620 case 0x3: r_0 = 0x3; break;
1621 case 0x4: r_0 = 0x4; break;
1622 case 0x5: r_0 = 0x5; break;
1623 case 0x6: r_0 = 0x6; break;
1624 case 0x7: r_0 = 0x7; break;
1625 case 0x8: r_0 = 0x8; break;
1626 case 0xa: r_0 = 0x9; break;
1627 case 0xc: r_0 = 0xa; break;
1628 case 0x10: r_0 = 0xb; break;
1629 case 0x20: r_0 = 0xc; break;
1630 case 0x40: r_0 = 0xd; break;
1631 case 0x80: r_0 = 0xe; break;
1632 default: r_0 = 0xf; break;
1633 }
1634 *valp = r_0;
1635 return 0;
1636 }
1637
1638 static int
1639 Operand_b4constu_decode (uint32 *valp)
1640 {
1641 unsigned b4constu_0, r_0;
1642 r_0 = *valp & 0xf;
1643 b4constu_0 = CONST_TBL_b4cu_0[r_0 & 0xf];
1644 *valp = b4constu_0;
1645 return 0;
1646 }
1647
1648 static int
1649 Operand_b4constu_encode (uint32 *valp)
1650 {
1651 unsigned r_0, b4constu_0;
1652 b4constu_0 = *valp;
1653 switch (b4constu_0)
1654 {
1655 case 0x8000: r_0 = 0; break;
1656 case 0x10000: r_0 = 0x1; break;
1657 case 0x2: r_0 = 0x2; break;
1658 case 0x3: r_0 = 0x3; break;
1659 case 0x4: r_0 = 0x4; break;
1660 case 0x5: r_0 = 0x5; break;
1661 case 0x6: r_0 = 0x6; break;
1662 case 0x7: r_0 = 0x7; break;
1663 case 0x8: r_0 = 0x8; break;
1664 case 0xa: r_0 = 0x9; break;
1665 case 0xc: r_0 = 0xa; break;
1666 case 0x10: r_0 = 0xb; break;
1667 case 0x20: r_0 = 0xc; break;
1668 case 0x40: r_0 = 0xd; break;
1669 case 0x80: r_0 = 0xe; break;
1670 default: r_0 = 0xf; break;
1671 }
1672 *valp = r_0;
1673 return 0;
1674 }
1675
1676 static int
1677 Operand_uimm8_decode (uint32 *valp)
1678 {
1679 unsigned uimm8_0, imm8_0;
1680 imm8_0 = *valp & 0xff;
1681 uimm8_0 = imm8_0;
1682 *valp = uimm8_0;
1683 return 0;
1684 }
1685
1686 static int
1687 Operand_uimm8_encode (uint32 *valp)
1688 {
1689 unsigned imm8_0, uimm8_0;
1690 uimm8_0 = *valp;
1691 imm8_0 = (uimm8_0 & 0xff);
1692 *valp = imm8_0;
1693 return 0;
1694 }
1695
1696 static int
1697 Operand_uimm8x2_decode (uint32 *valp)
1698 {
1699 unsigned uimm8x2_0, imm8_0;
1700 imm8_0 = *valp & 0xff;
1701 uimm8x2_0 = imm8_0 << 1;
1702 *valp = uimm8x2_0;
1703 return 0;
1704 }
1705
1706 static int
1707 Operand_uimm8x2_encode (uint32 *valp)
1708 {
1709 unsigned imm8_0, uimm8x2_0;
1710 uimm8x2_0 = *valp;
1711 imm8_0 = ((uimm8x2_0 >> 1) & 0xff);
1712 *valp = imm8_0;
1713 return 0;
1714 }
1715
1716 static int
1717 Operand_uimm8x4_decode (uint32 *valp)
1718 {
1719 unsigned uimm8x4_0, imm8_0;
1720 imm8_0 = *valp & 0xff;
1721 uimm8x4_0 = imm8_0 << 2;
1722 *valp = uimm8x4_0;
1723 return 0;
1724 }
1725
1726 static int
1727 Operand_uimm8x4_encode (uint32 *valp)
1728 {
1729 unsigned imm8_0, uimm8x4_0;
1730 uimm8x4_0 = *valp;
1731 imm8_0 = ((uimm8x4_0 >> 2) & 0xff);
1732 *valp = imm8_0;
1733 return 0;
1734 }
1735
1736 static int
1737 Operand_uimm4x16_decode (uint32 *valp)
1738 {
1739 unsigned uimm4x16_0, op2_0;
1740 op2_0 = *valp & 0xf;
1741 uimm4x16_0 = op2_0 << 4;
1742 *valp = uimm4x16_0;
1743 return 0;
1744 }
1745
1746 static int
1747 Operand_uimm4x16_encode (uint32 *valp)
1748 {
1749 unsigned op2_0, uimm4x16_0;
1750 uimm4x16_0 = *valp;
1751 op2_0 = ((uimm4x16_0 >> 4) & 0xf);
1752 *valp = op2_0;
1753 return 0;
1754 }
1755
1756 static int
1757 Operand_simm8_decode (uint32 *valp)
1758 {
1759 unsigned simm8_0, imm8_0;
1760 imm8_0 = *valp & 0xff;
1761 simm8_0 = ((int) imm8_0 << 24) >> 24;
1762 *valp = simm8_0;
1763 return 0;
1764 }
1765
1766 static int
1767 Operand_simm8_encode (uint32 *valp)
1768 {
1769 unsigned imm8_0, simm8_0;
1770 simm8_0 = *valp;
1771 imm8_0 = (simm8_0 & 0xff);
1772 *valp = imm8_0;
1773 return 0;
1774 }
1775
1776 static int
1777 Operand_simm8x256_decode (uint32 *valp)
1778 {
1779 unsigned simm8x256_0, imm8_0;
1780 imm8_0 = *valp & 0xff;
1781 simm8x256_0 = (((int) imm8_0 << 24) >> 24) << 8;
1782 *valp = simm8x256_0;
1783 return 0;
1784 }
1785
1786 static int
1787 Operand_simm8x256_encode (uint32 *valp)
1788 {
1789 unsigned imm8_0, simm8x256_0;
1790 simm8x256_0 = *valp;
1791 imm8_0 = ((simm8x256_0 >> 8) & 0xff);
1792 *valp = imm8_0;
1793 return 0;
1794 }
1795
1796 static int
1797 Operand_simm12b_decode (uint32 *valp)
1798 {
1799 unsigned simm12b_0, imm12b_0;
1800 imm12b_0 = *valp & 0xfff;
1801 simm12b_0 = ((int) imm12b_0 << 20) >> 20;
1802 *valp = simm12b_0;
1803 return 0;
1804 }
1805
1806 static int
1807 Operand_simm12b_encode (uint32 *valp)
1808 {
1809 unsigned imm12b_0, simm12b_0;
1810 simm12b_0 = *valp;
1811 imm12b_0 = (simm12b_0 & 0xfff);
1812 *valp = imm12b_0;
1813 return 0;
1814 }
1815
1816 static int
1817 Operand_msalp32_decode (uint32 *valp)
1818 {
1819 unsigned msalp32_0, sal_0;
1820 sal_0 = *valp & 0x1f;
1821 msalp32_0 = 0x20 - sal_0;
1822 *valp = msalp32_0;
1823 return 0;
1824 }
1825
1826 static int
1827 Operand_msalp32_encode (uint32 *valp)
1828 {
1829 unsigned sal_0, msalp32_0;
1830 msalp32_0 = *valp;
1831 sal_0 = (0x20 - msalp32_0) & 0x1f;
1832 *valp = sal_0;
1833 return 0;
1834 }
1835
1836 static int
1837 Operand_op2p1_decode (uint32 *valp)
1838 {
1839 unsigned op2p1_0, op2_0;
1840 op2_0 = *valp & 0xf;
1841 op2p1_0 = op2_0 + 0x1;
1842 *valp = op2p1_0;
1843 return 0;
1844 }
1845
1846 static int
1847 Operand_op2p1_encode (uint32 *valp)
1848 {
1849 unsigned op2_0, op2p1_0;
1850 op2p1_0 = *valp;
1851 op2_0 = (op2p1_0 - 0x1) & 0xf;
1852 *valp = op2_0;
1853 return 0;
1854 }
1855
1856 static int
1857 Operand_label8_decode (uint32 *valp)
1858 {
1859 unsigned label8_0, imm8_0;
1860 imm8_0 = *valp & 0xff;
1861 label8_0 = 0x4 + (((int) imm8_0 << 24) >> 24);
1862 *valp = label8_0;
1863 return 0;
1864 }
1865
1866 static int
1867 Operand_label8_encode (uint32 *valp)
1868 {
1869 unsigned imm8_0, label8_0;
1870 label8_0 = *valp;
1871 imm8_0 = (label8_0 - 0x4) & 0xff;
1872 *valp = imm8_0;
1873 return 0;
1874 }
1875
1876 static int
1877 Operand_label8_ator (uint32 *valp, uint32 pc)
1878 {
1879 *valp -= pc;
1880 return 0;
1881 }
1882
1883 static int
1884 Operand_label8_rtoa (uint32 *valp, uint32 pc)
1885 {
1886 *valp += pc;
1887 return 0;
1888 }
1889
1890 static int
1891 Operand_ulabel8_decode (uint32 *valp)
1892 {
1893 unsigned ulabel8_0, imm8_0;
1894 imm8_0 = *valp & 0xff;
1895 ulabel8_0 = 0x4 + ((((0)) << 8) | imm8_0);
1896 *valp = ulabel8_0;
1897 return 0;
1898 }
1899
1900 static int
1901 Operand_ulabel8_encode (uint32 *valp)
1902 {
1903 unsigned imm8_0, ulabel8_0;
1904 ulabel8_0 = *valp;
1905 imm8_0 = (ulabel8_0 - 0x4) & 0xff;
1906 *valp = imm8_0;
1907 return 0;
1908 }
1909
1910 static int
1911 Operand_ulabel8_ator (uint32 *valp, uint32 pc)
1912 {
1913 *valp -= pc;
1914 return 0;
1915 }
1916
1917 static int
1918 Operand_ulabel8_rtoa (uint32 *valp, uint32 pc)
1919 {
1920 *valp += pc;
1921 return 0;
1922 }
1923
1924 static int
1925 Operand_label12_decode (uint32 *valp)
1926 {
1927 unsigned label12_0, imm12_0;
1928 imm12_0 = *valp & 0xfff;
1929 label12_0 = 0x4 + (((int) imm12_0 << 20) >> 20);
1930 *valp = label12_0;
1931 return 0;
1932 }
1933
1934 static int
1935 Operand_label12_encode (uint32 *valp)
1936 {
1937 unsigned imm12_0, label12_0;
1938 label12_0 = *valp;
1939 imm12_0 = (label12_0 - 0x4) & 0xfff;
1940 *valp = imm12_0;
1941 return 0;
1942 }
1943
1944 static int
1945 Operand_label12_ator (uint32 *valp, uint32 pc)
1946 {
1947 *valp -= pc;
1948 return 0;
1949 }
1950
1951 static int
1952 Operand_label12_rtoa (uint32 *valp, uint32 pc)
1953 {
1954 *valp += pc;
1955 return 0;
1956 }
1957
1958 static int
1959 Operand_soffset_decode (uint32 *valp)
1960 {
1961 unsigned soffset_0, offset_0;
1962 offset_0 = *valp & 0x3ffff;
1963 soffset_0 = 0x4 + (((int) offset_0 << 14) >> 14);
1964 *valp = soffset_0;
1965 return 0;
1966 }
1967
1968 static int
1969 Operand_soffset_encode (uint32 *valp)
1970 {
1971 unsigned offset_0, soffset_0;
1972 soffset_0 = *valp;
1973 offset_0 = (soffset_0 - 0x4) & 0x3ffff;
1974 *valp = offset_0;
1975 return 0;
1976 }
1977
1978 static int
1979 Operand_soffset_ator (uint32 *valp, uint32 pc)
1980 {
1981 *valp -= pc;
1982 return 0;
1983 }
1984
1985 static int
1986 Operand_soffset_rtoa (uint32 *valp, uint32 pc)
1987 {
1988 *valp += pc;
1989 return 0;
1990 }
1991
1992 static int
1993 Operand_uimm16x4_decode (uint32 *valp)
1994 {
1995 unsigned uimm16x4_0, imm16_0;
1996 imm16_0 = *valp & 0xffff;
1997 uimm16x4_0 = ((((0xffff)) << 16) | imm16_0) << 2;
1998 *valp = uimm16x4_0;
1999 return 0;
2000 }
2001
2002 static int
2003 Operand_uimm16x4_encode (uint32 *valp)
2004 {
2005 unsigned imm16_0, uimm16x4_0;
2006 uimm16x4_0 = *valp;
2007 imm16_0 = (uimm16x4_0 >> 2) & 0xffff;
2008 *valp = imm16_0;
2009 return 0;
2010 }
2011
2012 static int
2013 Operand_uimm16x4_ator (uint32 *valp, uint32 pc)
2014 {
2015 *valp -= ((pc + 3) & ~0x3);
2016 return 0;
2017 }
2018
2019 static int
2020 Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc)
2021 {
2022 *valp += ((pc + 3) & ~0x3);
2023 return 0;
2024 }
2025
2026 static int
2027 Operand_immt_decode (uint32 *valp)
2028 {
2029 unsigned immt_0, t_0;
2030 t_0 = *valp & 0xf;
2031 immt_0 = t_0;
2032 *valp = immt_0;
2033 return 0;
2034 }
2035
2036 static int
2037 Operand_immt_encode (uint32 *valp)
2038 {
2039 unsigned t_0, immt_0;
2040 immt_0 = *valp;
2041 t_0 = immt_0 & 0xf;
2042 *valp = t_0;
2043 return 0;
2044 }
2045
2046 static int
2047 Operand_imms_decode (uint32 *valp)
2048 {
2049 unsigned imms_0, s_0;
2050 s_0 = *valp & 0xf;
2051 imms_0 = s_0;
2052 *valp = imms_0;
2053 return 0;
2054 }
2055
2056 static int
2057 Operand_imms_encode (uint32 *valp)
2058 {
2059 unsigned s_0, imms_0;
2060 imms_0 = *valp;
2061 s_0 = imms_0 & 0xf;
2062 *valp = s_0;
2063 return 0;
2064 }
2065
2066 static xtensa_operand_internal operands[] = {
2067 { "soffsetx4", 10, -1, 0,
2068 XTENSA_OPERAND_IS_PCRELATIVE,
2069 Operand_soffsetx4_encode, Operand_soffsetx4_decode,
2070 Operand_soffsetx4_ator, Operand_soffsetx4_rtoa },
2071 { "uimm12x8", 3, -1, 0,
2072 0,
2073 Operand_uimm12x8_encode, Operand_uimm12x8_decode,
2074 0, 0 },
2075 { "simm4", 26, -1, 0,
2076 0,
2077 Operand_simm4_encode, Operand_simm4_decode,
2078 0, 0 },
2079 { "arr", 14, 0, 1,
2080 XTENSA_OPERAND_IS_REGISTER,
2081 Operand_arr_encode, Operand_arr_decode,
2082 0, 0 },
2083 { "ars", 5, 0, 1,
2084 XTENSA_OPERAND_IS_REGISTER,
2085 Operand_ars_encode, Operand_ars_decode,
2086 0, 0 },
2087 { "*ars_invisible", 5, 0, 1,
2088 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2089 Operand_ars_encode, Operand_ars_decode,
2090 0, 0 },
2091 { "art", 0, 0, 1,
2092 XTENSA_OPERAND_IS_REGISTER,
2093 Operand_art_encode, Operand_art_decode,
2094 0, 0 },
2095 { "ar0", 35, 0, 1,
2096 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2097 Operand_ar0_encode, Operand_ar0_decode,
2098 0, 0 },
2099 { "ar4", 36, 0, 1,
2100 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2101 Operand_ar4_encode, Operand_ar4_decode,
2102 0, 0 },
2103 { "ar8", 37, 0, 1,
2104 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2105 Operand_ar8_encode, Operand_ar8_decode,
2106 0, 0 },
2107 { "ar12", 38, 0, 1,
2108 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2109 Operand_ar12_encode, Operand_ar12_decode,
2110 0, 0 },
2111 { "ars_entry", 5, 0, 1,
2112 XTENSA_OPERAND_IS_REGISTER,
2113 Operand_ars_entry_encode, Operand_ars_entry_decode,
2114 0, 0 },
2115 { "immrx4", 14, -1, 0,
2116 0,
2117 Operand_immrx4_encode, Operand_immrx4_decode,
2118 0, 0 },
2119 { "lsi4x4", 14, -1, 0,
2120 0,
2121 Operand_lsi4x4_encode, Operand_lsi4x4_decode,
2122 0, 0 },
2123 { "simm7", 34, -1, 0,
2124 0,
2125 Operand_simm7_encode, Operand_simm7_decode,
2126 0, 0 },
2127 { "uimm6", 33, -1, 0,
2128 XTENSA_OPERAND_IS_PCRELATIVE,
2129 Operand_uimm6_encode, Operand_uimm6_decode,
2130 Operand_uimm6_ator, Operand_uimm6_rtoa },
2131 { "ai4const", 0, -1, 0,
2132 0,
2133 Operand_ai4const_encode, Operand_ai4const_decode,
2134 0, 0 },
2135 { "b4const", 14, -1, 0,
2136 0,
2137 Operand_b4const_encode, Operand_b4const_decode,
2138 0, 0 },
2139 { "b4constu", 14, -1, 0,
2140 0,
2141 Operand_b4constu_encode, Operand_b4constu_decode,
2142 0, 0 },
2143 { "uimm8", 4, -1, 0,
2144 0,
2145 Operand_uimm8_encode, Operand_uimm8_decode,
2146 0, 0 },
2147 { "uimm8x2", 4, -1, 0,
2148 0,
2149 Operand_uimm8x2_encode, Operand_uimm8x2_decode,
2150 0, 0 },
2151 { "uimm8x4", 4, -1, 0,
2152 0,
2153 Operand_uimm8x4_encode, Operand_uimm8x4_decode,
2154 0, 0 },
2155 { "uimm4x16", 13, -1, 0,
2156 0,
2157 Operand_uimm4x16_encode, Operand_uimm4x16_decode,
2158 0, 0 },
2159 { "simm8", 4, -1, 0,
2160 0,
2161 Operand_simm8_encode, Operand_simm8_decode,
2162 0, 0 },
2163 { "simm8x256", 4, -1, 0,
2164 0,
2165 Operand_simm8x256_encode, Operand_simm8x256_decode,
2166 0, 0 },
2167 { "simm12b", 6, -1, 0,
2168 0,
2169 Operand_simm12b_encode, Operand_simm12b_decode,
2170 0, 0 },
2171 { "msalp32", 18, -1, 0,
2172 0,
2173 Operand_msalp32_encode, Operand_msalp32_decode,
2174 0, 0 },
2175 { "op2p1", 13, -1, 0,
2176 0,
2177 Operand_op2p1_encode, Operand_op2p1_decode,
2178 0, 0 },
2179 { "label8", 4, -1, 0,
2180 XTENSA_OPERAND_IS_PCRELATIVE,
2181 Operand_label8_encode, Operand_label8_decode,
2182 Operand_label8_ator, Operand_label8_rtoa },
2183 { "ulabel8", 4, -1, 0,
2184 XTENSA_OPERAND_IS_PCRELATIVE,
2185 Operand_ulabel8_encode, Operand_ulabel8_decode,
2186 Operand_ulabel8_ator, Operand_ulabel8_rtoa },
2187 { "label12", 3, -1, 0,
2188 XTENSA_OPERAND_IS_PCRELATIVE,
2189 Operand_label12_encode, Operand_label12_decode,
2190 Operand_label12_ator, Operand_label12_rtoa },
2191 { "soffset", 10, -1, 0,
2192 XTENSA_OPERAND_IS_PCRELATIVE,
2193 Operand_soffset_encode, Operand_soffset_decode,
2194 Operand_soffset_ator, Operand_soffset_rtoa },
2195 { "uimm16x4", 7, -1, 0,
2196 XTENSA_OPERAND_IS_PCRELATIVE,
2197 Operand_uimm16x4_encode, Operand_uimm16x4_decode,
2198 Operand_uimm16x4_ator, Operand_uimm16x4_rtoa },
2199 { "immt", 0, -1, 0,
2200 0,
2201 Operand_immt_encode, Operand_immt_decode,
2202 0, 0 },
2203 { "imms", 5, -1, 0,
2204 0,
2205 Operand_imms_encode, Operand_imms_decode,
2206 0, 0 },
2207 { "t", 0, -1, 0, 0, 0, 0, 0, 0 },
2208 { "bbi4", 1, -1, 0, 0, 0, 0, 0, 0 },
2209 { "bbi", 2, -1, 0, 0, 0, 0, 0, 0 },
2210 { "imm12", 3, -1, 0, 0, 0, 0, 0, 0 },
2211 { "imm8", 4, -1, 0, 0, 0, 0, 0, 0 },
2212 { "s", 5, -1, 0, 0, 0, 0, 0, 0 },
2213 { "imm12b", 6, -1, 0, 0, 0, 0, 0, 0 },
2214 { "imm16", 7, -1, 0, 0, 0, 0, 0, 0 },
2215 { "m", 8, -1, 0, 0, 0, 0, 0, 0 },
2216 { "n", 9, -1, 0, 0, 0, 0, 0, 0 },
2217 { "offset", 10, -1, 0, 0, 0, 0, 0, 0 },
2218 { "op0", 11, -1, 0, 0, 0, 0, 0, 0 },
2219 { "op1", 12, -1, 0, 0, 0, 0, 0, 0 },
2220 { "op2", 13, -1, 0, 0, 0, 0, 0, 0 },
2221 { "r", 14, -1, 0, 0, 0, 0, 0, 0 },
2222 { "sa4", 15, -1, 0, 0, 0, 0, 0, 0 },
2223 { "sae4", 16, -1, 0, 0, 0, 0, 0, 0 },
2224 { "sae", 17, -1, 0, 0, 0, 0, 0, 0 },
2225 { "sal", 18, -1, 0, 0, 0, 0, 0, 0 },
2226 { "sargt", 19, -1, 0, 0, 0, 0, 0, 0 },
2227 { "sas4", 20, -1, 0, 0, 0, 0, 0, 0 },
2228 { "sas", 21, -1, 0, 0, 0, 0, 0, 0 },
2229 { "sr", 22, -1, 0, 0, 0, 0, 0, 0 },
2230 { "st", 23, -1, 0, 0, 0, 0, 0, 0 },
2231 { "thi3", 24, -1, 0, 0, 0, 0, 0, 0 },
2232 { "imm4", 25, -1, 0, 0, 0, 0, 0, 0 },
2233 { "mn", 26, -1, 0, 0, 0, 0, 0, 0 },
2234 { "i", 27, -1, 0, 0, 0, 0, 0, 0 },
2235 { "imm6lo", 28, -1, 0, 0, 0, 0, 0, 0 },
2236 { "imm6hi", 29, -1, 0, 0, 0, 0, 0, 0 },
2237 { "imm7lo", 30, -1, 0, 0, 0, 0, 0, 0 },
2238 { "imm7hi", 31, -1, 0, 0, 0, 0, 0, 0 },
2239 { "z", 32, -1, 0, 0, 0, 0, 0, 0 },
2240 { "imm6", 33, -1, 0, 0, 0, 0, 0, 0 },
2241 { "imm7", 34, -1, 0, 0, 0, 0, 0, 0 }
2242 };
2243
2244
2245 /* Iclass table. */
2246
2247 static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = {
2248 { { STATE_PSRING }, 'i' },
2249 { { STATE_PSEXCM }, 'm' },
2250 { { STATE_EPC1 }, 'i' }
2251 };
2252
2253 static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = {
2254 { { STATE_PSEXCM }, 'i' },
2255 { { STATE_PSRING }, 'i' },
2256 { { STATE_DEPC }, 'i' }
2257 };
2258
2259 static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = {
2260 { { 0 /* soffsetx4 */ }, 'i' },
2261 { { 10 /* ar12 */ }, 'o' }
2262 };
2263
2264 static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = {
2265 { { STATE_PSCALLINC }, 'o' }
2266 };
2267
2268 static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = {
2269 { { 0 /* soffsetx4 */ }, 'i' },
2270 { { 9 /* ar8 */ }, 'o' }
2271 };
2272
2273 static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = {
2274 { { STATE_PSCALLINC }, 'o' }
2275 };
2276
2277 static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = {
2278 { { 0 /* soffsetx4 */ }, 'i' },
2279 { { 8 /* ar4 */ }, 'o' }
2280 };
2281
2282 static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = {
2283 { { STATE_PSCALLINC }, 'o' }
2284 };
2285
2286 static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = {
2287 { { 4 /* ars */ }, 'i' },
2288 { { 10 /* ar12 */ }, 'o' }
2289 };
2290
2291 static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = {
2292 { { STATE_PSCALLINC }, 'o' }
2293 };
2294
2295 static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = {
2296 { { 4 /* ars */ }, 'i' },
2297 { { 9 /* ar8 */ }, 'o' }
2298 };
2299
2300 static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = {
2301 { { STATE_PSCALLINC }, 'o' }
2302 };
2303
2304 static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = {
2305 { { 4 /* ars */ }, 'i' },
2306 { { 8 /* ar4 */ }, 'o' }
2307 };
2308
2309 static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = {
2310 { { STATE_PSCALLINC }, 'o' }
2311 };
2312
2313 static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = {
2314 { { 11 /* ars_entry */ }, 's' },
2315 { { 4 /* ars */ }, 'i' },
2316 { { 1 /* uimm12x8 */ }, 'i' }
2317 };
2318
2319 static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = {
2320 { { STATE_PSCALLINC }, 'i' },
2321 { { STATE_PSEXCM }, 'i' },
2322 { { STATE_PSWOE }, 'i' },
2323 { { STATE_WindowBase }, 'm' },
2324 { { STATE_WindowStart }, 'm' }
2325 };
2326
2327 static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = {
2328 { { 6 /* art */ }, 'o' },
2329 { { 4 /* ars */ }, 'i' }
2330 };
2331
2332 static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = {
2333 { { STATE_WindowBase }, 'i' },
2334 { { STATE_WindowStart }, 'i' }
2335 };
2336
2337 static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = {
2338 { { 2 /* simm4 */ }, 'i' }
2339 };
2340
2341 static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = {
2342 { { STATE_PSEXCM }, 'i' },
2343 { { STATE_PSRING }, 'i' },
2344 { { STATE_WindowBase }, 'm' }
2345 };
2346
2347 static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = {
2348 { { 5 /* *ars_invisible */ }, 'i' }
2349 };
2350
2351 static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = {
2352 { { STATE_WindowBase }, 'm' },
2353 { { STATE_WindowStart }, 'm' },
2354 { { STATE_PSEXCM }, 'i' },
2355 { { STATE_PSWOE }, 'i' }
2356 };
2357
2358 static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = {
2359 { { STATE_EPC1 }, 'i' },
2360 { { STATE_PSEXCM }, 'm' },
2361 { { STATE_PSRING }, 'i' },
2362 { { STATE_WindowBase }, 'm' },
2363 { { STATE_WindowStart }, 'm' },
2364 { { STATE_PSOWB }, 'i' }
2365 };
2366
2367 static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = {
2368 { { 6 /* art */ }, 'o' },
2369 { { 4 /* ars */ }, 'i' },
2370 { { 12 /* immrx4 */ }, 'i' }
2371 };
2372
2373 static xtensa_arg_internal Iclass_xt_iclass_l32e_stateArgs[] = {
2374 { { STATE_PSEXCM }, 'i' },
2375 { { STATE_PSRING }, 'i' }
2376 };
2377
2378 static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = {
2379 { { 6 /* art */ }, 'i' },
2380 { { 4 /* ars */ }, 'i' },
2381 { { 12 /* immrx4 */ }, 'i' }
2382 };
2383
2384 static xtensa_arg_internal Iclass_xt_iclass_s32e_stateArgs[] = {
2385 { { STATE_PSEXCM }, 'i' },
2386 { { STATE_PSRING }, 'i' }
2387 };
2388
2389 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = {
2390 { { 6 /* art */ }, 'o' }
2391 };
2392
2393 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = {
2394 { { STATE_PSEXCM }, 'i' },
2395 { { STATE_PSRING }, 'i' },
2396 { { STATE_WindowBase }, 'i' }
2397 };
2398
2399 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = {
2400 { { 6 /* art */ }, 'i' }
2401 };
2402
2403 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = {
2404 { { STATE_PSEXCM }, 'i' },
2405 { { STATE_PSRING }, 'i' },
2406 { { STATE_WindowBase }, 'o' }
2407 };
2408
2409 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = {
2410 { { 6 /* art */ }, 'm' }
2411 };
2412
2413 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = {
2414 { { STATE_PSEXCM }, 'i' },
2415 { { STATE_PSRING }, 'i' },
2416 { { STATE_WindowBase }, 'm' }
2417 };
2418
2419 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = {
2420 { { 6 /* art */ }, 'o' }
2421 };
2422
2423 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = {
2424 { { STATE_PSEXCM }, 'i' },
2425 { { STATE_PSRING }, 'i' },
2426 { { STATE_WindowStart }, 'i' }
2427 };
2428
2429 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = {
2430 { { 6 /* art */ }, 'i' }
2431 };
2432
2433 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = {
2434 { { STATE_PSEXCM }, 'i' },
2435 { { STATE_PSRING }, 'i' },
2436 { { STATE_WindowStart }, 'o' }
2437 };
2438
2439 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = {
2440 { { 6 /* art */ }, 'm' }
2441 };
2442
2443 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = {
2444 { { STATE_PSEXCM }, 'i' },
2445 { { STATE_PSRING }, 'i' },
2446 { { STATE_WindowStart }, 'm' }
2447 };
2448
2449 static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = {
2450 { { 3 /* arr */ }, 'o' },
2451 { { 4 /* ars */ }, 'i' },
2452 { { 6 /* art */ }, 'i' }
2453 };
2454
2455 static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = {
2456 { { 3 /* arr */ }, 'o' },
2457 { { 4 /* ars */ }, 'i' },
2458 { { 16 /* ai4const */ }, 'i' }
2459 };
2460
2461 static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = {
2462 { { 4 /* ars */ }, 'i' },
2463 { { 15 /* uimm6 */ }, 'i' }
2464 };
2465
2466 static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = {
2467 { { 6 /* art */ }, 'o' },
2468 { { 4 /* ars */ }, 'i' },
2469 { { 13 /* lsi4x4 */ }, 'i' }
2470 };
2471
2472 static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = {
2473 { { 6 /* art */ }, 'o' },
2474 { { 4 /* ars */ }, 'i' }
2475 };
2476
2477 static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = {
2478 { { 4 /* ars */ }, 'o' },
2479 { { 14 /* simm7 */ }, 'i' }
2480 };
2481
2482 static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = {
2483 { { 5 /* *ars_invisible */ }, 'i' }
2484 };
2485
2486 static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = {
2487 { { 6 /* art */ }, 'i' },
2488 { { 4 /* ars */ }, 'i' },
2489 { { 13 /* lsi4x4 */ }, 'i' }
2490 };
2491
2492 static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = {
2493 { { 6 /* art */ }, 'o' },
2494 { { 4 /* ars */ }, 'i' },
2495 { { 23 /* simm8 */ }, 'i' }
2496 };
2497
2498 static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = {
2499 { { 6 /* art */ }, 'o' },
2500 { { 4 /* ars */ }, 'i' },
2501 { { 24 /* simm8x256 */ }, 'i' }
2502 };
2503
2504 static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = {
2505 { { 3 /* arr */ }, 'o' },
2506 { { 4 /* ars */ }, 'i' },
2507 { { 6 /* art */ }, 'i' }
2508 };
2509
2510 static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = {
2511 { { 3 /* arr */ }, 'o' },
2512 { { 4 /* ars */ }, 'i' },
2513 { { 6 /* art */ }, 'i' }
2514 };
2515
2516 static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = {
2517 { { 4 /* ars */ }, 'i' },
2518 { { 17 /* b4const */ }, 'i' },
2519 { { 28 /* label8 */ }, 'i' }
2520 };
2521
2522 static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = {
2523 { { 4 /* ars */ }, 'i' },
2524 { { 37 /* bbi */ }, 'i' },
2525 { { 28 /* label8 */ }, 'i' }
2526 };
2527
2528 static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = {
2529 { { 4 /* ars */ }, 'i' },
2530 { { 18 /* b4constu */ }, 'i' },
2531 { { 28 /* label8 */ }, 'i' }
2532 };
2533
2534 static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = {
2535 { { 4 /* ars */ }, 'i' },
2536 { { 6 /* art */ }, 'i' },
2537 { { 28 /* label8 */ }, 'i' }
2538 };
2539
2540 static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = {
2541 { { 4 /* ars */ }, 'i' },
2542 { { 30 /* label12 */ }, 'i' }
2543 };
2544
2545 static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = {
2546 { { 0 /* soffsetx4 */ }, 'i' },
2547 { { 7 /* ar0 */ }, 'o' }
2548 };
2549
2550 static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = {
2551 { { 4 /* ars */ }, 'i' },
2552 { { 7 /* ar0 */ }, 'o' }
2553 };
2554
2555 static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = {
2556 { { 3 /* arr */ }, 'o' },
2557 { { 6 /* art */ }, 'i' },
2558 { { 52 /* sae */ }, 'i' },
2559 { { 27 /* op2p1 */ }, 'i' }
2560 };
2561
2562 static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = {
2563 { { 31 /* soffset */ }, 'i' }
2564 };
2565
2566 static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = {
2567 { { 4 /* ars */ }, 'i' }
2568 };
2569
2570 static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = {
2571 { { 6 /* art */ }, 'o' },
2572 { { 4 /* ars */ }, 'i' },
2573 { { 20 /* uimm8x2 */ }, 'i' }
2574 };
2575
2576 static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = {
2577 { { 6 /* art */ }, 'o' },
2578 { { 4 /* ars */ }, 'i' },
2579 { { 20 /* uimm8x2 */ }, 'i' }
2580 };
2581
2582 static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = {
2583 { { 6 /* art */ }, 'o' },
2584 { { 4 /* ars */ }, 'i' },
2585 { { 21 /* uimm8x4 */ }, 'i' }
2586 };
2587
2588 static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = {
2589 { { 6 /* art */ }, 'o' },
2590 { { 32 /* uimm16x4 */ }, 'i' }
2591 };
2592
2593 static xtensa_arg_internal Iclass_xt_iclass_l32r_stateArgs[] = {
2594 { { STATE_LITBADDR }, 'i' },
2595 { { STATE_LITBEN }, 'i' }
2596 };
2597
2598 static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = {
2599 { { 6 /* art */ }, 'o' },
2600 { { 4 /* ars */ }, 'i' },
2601 { { 19 /* uimm8 */ }, 'i' }
2602 };
2603
2604 static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = {
2605 { { 4 /* ars */ }, 'i' },
2606 { { 29 /* ulabel8 */ }, 'i' }
2607 };
2608
2609 static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = {
2610 { { STATE_LBEG }, 'o' },
2611 { { STATE_LEND }, 'o' },
2612 { { STATE_LCOUNT }, 'o' }
2613 };
2614
2615 static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = {
2616 { { 4 /* ars */ }, 'i' },
2617 { { 29 /* ulabel8 */ }, 'i' }
2618 };
2619
2620 static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = {
2621 { { STATE_LBEG }, 'o' },
2622 { { STATE_LEND }, 'o' },
2623 { { STATE_LCOUNT }, 'o' }
2624 };
2625
2626 static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = {
2627 { { 6 /* art */ }, 'o' },
2628 { { 25 /* simm12b */ }, 'i' }
2629 };
2630
2631 static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = {
2632 { { 3 /* arr */ }, 'm' },
2633 { { 4 /* ars */ }, 'i' },
2634 { { 6 /* art */ }, 'i' }
2635 };
2636
2637 static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = {
2638 { { 3 /* arr */ }, 'o' },
2639 { { 6 /* art */ }, 'i' }
2640 };
2641
2642 static xtensa_arg_internal Iclass_xt_iclass_return_args[] = {
2643 { { 5 /* *ars_invisible */ }, 'i' }
2644 };
2645
2646 static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = {
2647 { { 6 /* art */ }, 'i' },
2648 { { 4 /* ars */ }, 'i' },
2649 { { 20 /* uimm8x2 */ }, 'i' }
2650 };
2651
2652 static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = {
2653 { { 6 /* art */ }, 'i' },
2654 { { 4 /* ars */ }, 'i' },
2655 { { 21 /* uimm8x4 */ }, 'i' }
2656 };
2657
2658 static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = {
2659 { { 6 /* art */ }, 'i' },
2660 { { 4 /* ars */ }, 'i' },
2661 { { 19 /* uimm8 */ }, 'i' }
2662 };
2663
2664 static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = {
2665 { { 4 /* ars */ }, 'i' }
2666 };
2667
2668 static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = {
2669 { { STATE_SAR }, 'o' }
2670 };
2671
2672 static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = {
2673 { { 56 /* sas */ }, 'i' }
2674 };
2675
2676 static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = {
2677 { { STATE_SAR }, 'o' }
2678 };
2679
2680 static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = {
2681 { { 3 /* arr */ }, 'o' },
2682 { { 4 /* ars */ }, 'i' }
2683 };
2684
2685 static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = {
2686 { { STATE_SAR }, 'i' }
2687 };
2688
2689 static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = {
2690 { { 3 /* arr */ }, 'o' },
2691 { { 4 /* ars */ }, 'i' },
2692 { { 6 /* art */ }, 'i' }
2693 };
2694
2695 static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = {
2696 { { STATE_SAR }, 'i' }
2697 };
2698
2699 static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = {
2700 { { 3 /* arr */ }, 'o' },
2701 { { 6 /* art */ }, 'i' }
2702 };
2703
2704 static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = {
2705 { { STATE_SAR }, 'i' }
2706 };
2707
2708 static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = {
2709 { { 3 /* arr */ }, 'o' },
2710 { { 4 /* ars */ }, 'i' },
2711 { { 26 /* msalp32 */ }, 'i' }
2712 };
2713
2714 static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = {
2715 { { 3 /* arr */ }, 'o' },
2716 { { 6 /* art */ }, 'i' },
2717 { { 54 /* sargt */ }, 'i' }
2718 };
2719
2720 static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = {
2721 { { 3 /* arr */ }, 'o' },
2722 { { 6 /* art */ }, 'i' },
2723 { { 40 /* s */ }, 'i' }
2724 };
2725
2726 static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = {
2727 { { STATE_XTSYNC }, 'i' }
2728 };
2729
2730 static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = {
2731 { { 6 /* art */ }, 'o' },
2732 { { 40 /* s */ }, 'i' }
2733 };
2734
2735 static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = {
2736 { { STATE_PSWOE }, 'i' },
2737 { { STATE_PSCALLINC }, 'i' },
2738 { { STATE_PSOWB }, 'i' },
2739 { { STATE_PSRING }, 'i' },
2740 { { STATE_PSUM }, 'i' },
2741 { { STATE_PSEXCM }, 'i' },
2742 { { STATE_PSINTLEVEL }, 'm' }
2743 };
2744
2745 static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = {
2746 { { 6 /* art */ }, 'o' }
2747 };
2748
2749 static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = {
2750 { { STATE_LEND }, 'i' }
2751 };
2752
2753 static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = {
2754 { { 6 /* art */ }, 'i' }
2755 };
2756
2757 static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = {
2758 { { STATE_LEND }, 'o' }
2759 };
2760
2761 static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = {
2762 { { 6 /* art */ }, 'm' }
2763 };
2764
2765 static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = {
2766 { { STATE_LEND }, 'm' }
2767 };
2768
2769 static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = {
2770 { { 6 /* art */ }, 'o' }
2771 };
2772
2773 static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = {
2774 { { STATE_LCOUNT }, 'i' }
2775 };
2776
2777 static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = {
2778 { { 6 /* art */ }, 'i' }
2779 };
2780
2781 static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = {
2782 { { STATE_XTSYNC }, 'o' },
2783 { { STATE_LCOUNT }, 'o' }
2784 };
2785
2786 static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = {
2787 { { 6 /* art */ }, 'm' }
2788 };
2789
2790 static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = {
2791 { { STATE_XTSYNC }, 'o' },
2792 { { STATE_LCOUNT }, 'm' }
2793 };
2794
2795 static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = {
2796 { { 6 /* art */ }, 'o' }
2797 };
2798
2799 static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = {
2800 { { STATE_LBEG }, 'i' }
2801 };
2802
2803 static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = {
2804 { { 6 /* art */ }, 'i' }
2805 };
2806
2807 static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = {
2808 { { STATE_LBEG }, 'o' }
2809 };
2810
2811 static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = {
2812 { { 6 /* art */ }, 'm' }
2813 };
2814
2815 static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = {
2816 { { STATE_LBEG }, 'm' }
2817 };
2818
2819 static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = {
2820 { { 6 /* art */ }, 'o' }
2821 };
2822
2823 static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = {
2824 { { STATE_SAR }, 'i' }
2825 };
2826
2827 static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = {
2828 { { 6 /* art */ }, 'i' }
2829 };
2830
2831 static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = {
2832 { { STATE_SAR }, 'o' },
2833 { { STATE_XTSYNC }, 'o' }
2834 };
2835
2836 static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = {
2837 { { 6 /* art */ }, 'm' }
2838 };
2839
2840 static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = {
2841 { { STATE_SAR }, 'm' }
2842 };
2843
2844 static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = {
2845 { { 6 /* art */ }, 'o' }
2846 };
2847
2848 static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_stateArgs[] = {
2849 { { STATE_LITBADDR }, 'i' },
2850 { { STATE_LITBEN }, 'i' }
2851 };
2852
2853 static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = {
2854 { { 6 /* art */ }, 'i' }
2855 };
2856
2857 static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_stateArgs[] = {
2858 { { STATE_LITBADDR }, 'o' },
2859 { { STATE_LITBEN }, 'o' }
2860 };
2861
2862 static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = {
2863 { { 6 /* art */ }, 'm' }
2864 };
2865
2866 static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_stateArgs[] = {
2867 { { STATE_LITBADDR }, 'm' },
2868 { { STATE_LITBEN }, 'm' }
2869 };
2870
2871 static xtensa_arg_internal Iclass_xt_iclass_rsr_176_args[] = {
2872 { { 6 /* art */ }, 'o' }
2873 };
2874
2875 static xtensa_arg_internal Iclass_xt_iclass_rsr_176_stateArgs[] = {
2876 { { STATE_PSEXCM }, 'i' },
2877 { { STATE_PSRING }, 'i' }
2878 };
2879
2880 static xtensa_arg_internal Iclass_xt_iclass_rsr_208_args[] = {
2881 { { 6 /* art */ }, 'o' }
2882 };
2883
2884 static xtensa_arg_internal Iclass_xt_iclass_rsr_208_stateArgs[] = {
2885 { { STATE_PSEXCM }, 'i' },
2886 { { STATE_PSRING }, 'i' }
2887 };
2888
2889 static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = {
2890 { { 6 /* art */ }, 'o' }
2891 };
2892
2893 static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = {
2894 { { STATE_PSWOE }, 'i' },
2895 { { STATE_PSCALLINC }, 'i' },
2896 { { STATE_PSOWB }, 'i' },
2897 { { STATE_PSRING }, 'i' },
2898 { { STATE_PSUM }, 'i' },
2899 { { STATE_PSEXCM }, 'i' },
2900 { { STATE_PSINTLEVEL }, 'i' }
2901 };
2902
2903 static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = {
2904 { { 6 /* art */ }, 'i' }
2905 };
2906
2907 static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = {
2908 { { STATE_PSWOE }, 'o' },
2909 { { STATE_PSCALLINC }, 'o' },
2910 { { STATE_PSOWB }, 'o' },
2911 { { STATE_PSRING }, 'm' },
2912 { { STATE_PSUM }, 'o' },
2913 { { STATE_PSEXCM }, 'm' },
2914 { { STATE_PSINTLEVEL }, 'o' }
2915 };
2916
2917 static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = {
2918 { { 6 /* art */ }, 'm' }
2919 };
2920
2921 static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = {
2922 { { STATE_PSWOE }, 'm' },
2923 { { STATE_PSCALLINC }, 'm' },
2924 { { STATE_PSOWB }, 'm' },
2925 { { STATE_PSRING }, 'm' },
2926 { { STATE_PSUM }, 'm' },
2927 { { STATE_PSEXCM }, 'm' },
2928 { { STATE_PSINTLEVEL }, 'm' }
2929 };
2930
2931 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = {
2932 { { 6 /* art */ }, 'o' }
2933 };
2934
2935 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = {
2936 { { STATE_PSEXCM }, 'i' },
2937 { { STATE_PSRING }, 'i' },
2938 { { STATE_EPC1 }, 'i' }
2939 };
2940
2941 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = {
2942 { { 6 /* art */ }, 'i' }
2943 };
2944
2945 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = {
2946 { { STATE_PSEXCM }, 'i' },
2947 { { STATE_PSRING }, 'i' },
2948 { { STATE_EPC1 }, 'o' }
2949 };
2950
2951 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = {
2952 { { 6 /* art */ }, 'm' }
2953 };
2954
2955 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = {
2956 { { STATE_PSEXCM }, 'i' },
2957 { { STATE_PSRING }, 'i' },
2958 { { STATE_EPC1 }, 'm' }
2959 };
2960
2961 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = {
2962 { { 6 /* art */ }, 'o' }
2963 };
2964
2965 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = {
2966 { { STATE_PSEXCM }, 'i' },
2967 { { STATE_PSRING }, 'i' },
2968 { { STATE_EXCSAVE1 }, 'i' }
2969 };
2970
2971 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = {
2972 { { 6 /* art */ }, 'i' }
2973 };
2974
2975 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = {
2976 { { STATE_PSEXCM }, 'i' },
2977 { { STATE_PSRING }, 'i' },
2978 { { STATE_EXCSAVE1 }, 'o' }
2979 };
2980
2981 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = {
2982 { { 6 /* art */ }, 'm' }
2983 };
2984
2985 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = {
2986 { { STATE_PSEXCM }, 'i' },
2987 { { STATE_PSRING }, 'i' },
2988 { { STATE_EXCSAVE1 }, 'm' }
2989 };
2990
2991 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = {
2992 { { 6 /* art */ }, 'o' }
2993 };
2994
2995 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = {
2996 { { STATE_PSEXCM }, 'i' },
2997 { { STATE_PSRING }, 'i' },
2998 { { STATE_EPC2 }, 'i' }
2999 };
3000
3001 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = {
3002 { { 6 /* art */ }, 'i' }
3003 };
3004
3005 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = {
3006 { { STATE_PSEXCM }, 'i' },
3007 { { STATE_PSRING }, 'i' },
3008 { { STATE_EPC2 }, 'o' }
3009 };
3010
3011 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = {
3012 { { 6 /* art */ }, 'm' }
3013 };
3014
3015 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = {
3016 { { STATE_PSEXCM }, 'i' },
3017 { { STATE_PSRING }, 'i' },
3018 { { STATE_EPC2 }, 'm' }
3019 };
3020
3021 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = {
3022 { { 6 /* art */ }, 'o' }
3023 };
3024
3025 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = {
3026 { { STATE_PSEXCM }, 'i' },
3027 { { STATE_PSRING }, 'i' },
3028 { { STATE_EXCSAVE2 }, 'i' }
3029 };
3030
3031 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = {
3032 { { 6 /* art */ }, 'i' }
3033 };
3034
3035 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = {
3036 { { STATE_PSEXCM }, 'i' },
3037 { { STATE_PSRING }, 'i' },
3038 { { STATE_EXCSAVE2 }, 'o' }
3039 };
3040
3041 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = {
3042 { { 6 /* art */ }, 'm' }
3043 };
3044
3045 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = {
3046 { { STATE_PSEXCM }, 'i' },
3047 { { STATE_PSRING }, 'i' },
3048 { { STATE_EXCSAVE2 }, 'm' }
3049 };
3050
3051 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = {
3052 { { 6 /* art */ }, 'o' }
3053 };
3054
3055 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = {
3056 { { STATE_PSEXCM }, 'i' },
3057 { { STATE_PSRING }, 'i' },
3058 { { STATE_EPC3 }, 'i' }
3059 };
3060
3061 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = {
3062 { { 6 /* art */ }, 'i' }
3063 };
3064
3065 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = {
3066 { { STATE_PSEXCM }, 'i' },
3067 { { STATE_PSRING }, 'i' },
3068 { { STATE_EPC3 }, 'o' }
3069 };
3070
3071 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = {
3072 { { 6 /* art */ }, 'm' }
3073 };
3074
3075 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = {
3076 { { STATE_PSEXCM }, 'i' },
3077 { { STATE_PSRING }, 'i' },
3078 { { STATE_EPC3 }, 'm' }
3079 };
3080
3081 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = {
3082 { { 6 /* art */ }, 'o' }
3083 };
3084
3085 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = {
3086 { { STATE_PSEXCM }, 'i' },
3087 { { STATE_PSRING }, 'i' },
3088 { { STATE_EXCSAVE3 }, 'i' }
3089 };
3090
3091 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = {
3092 { { 6 /* art */ }, 'i' }
3093 };
3094
3095 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = {
3096 { { STATE_PSEXCM }, 'i' },
3097 { { STATE_PSRING }, 'i' },
3098 { { STATE_EXCSAVE3 }, 'o' }
3099 };
3100
3101 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = {
3102 { { 6 /* art */ }, 'm' }
3103 };
3104
3105 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = {
3106 { { STATE_PSEXCM }, 'i' },
3107 { { STATE_PSRING }, 'i' },
3108 { { STATE_EXCSAVE3 }, 'm' }
3109 };
3110
3111 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = {
3112 { { 6 /* art */ }, 'o' }
3113 };
3114
3115 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = {
3116 { { STATE_PSEXCM }, 'i' },
3117 { { STATE_PSRING }, 'i' },
3118 { { STATE_EPC4 }, 'i' }
3119 };
3120
3121 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = {
3122 { { 6 /* art */ }, 'i' }
3123 };
3124
3125 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = {
3126 { { STATE_PSEXCM }, 'i' },
3127 { { STATE_PSRING }, 'i' },
3128 { { STATE_EPC4 }, 'o' }
3129 };
3130
3131 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = {
3132 { { 6 /* art */ }, 'm' }
3133 };
3134
3135 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = {
3136 { { STATE_PSEXCM }, 'i' },
3137 { { STATE_PSRING }, 'i' },
3138 { { STATE_EPC4 }, 'm' }
3139 };
3140
3141 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = {
3142 { { 6 /* art */ }, 'o' }
3143 };
3144
3145 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = {
3146 { { STATE_PSEXCM }, 'i' },
3147 { { STATE_PSRING }, 'i' },
3148 { { STATE_EXCSAVE4 }, 'i' }
3149 };
3150
3151 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = {
3152 { { 6 /* art */ }, 'i' }
3153 };
3154
3155 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = {
3156 { { STATE_PSEXCM }, 'i' },
3157 { { STATE_PSRING }, 'i' },
3158 { { STATE_EXCSAVE4 }, 'o' }
3159 };
3160
3161 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = {
3162 { { 6 /* art */ }, 'm' }
3163 };
3164
3165 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = {
3166 { { STATE_PSEXCM }, 'i' },
3167 { { STATE_PSRING }, 'i' },
3168 { { STATE_EXCSAVE4 }, 'm' }
3169 };
3170
3171 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = {
3172 { { 6 /* art */ }, 'o' }
3173 };
3174
3175 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = {
3176 { { STATE_PSEXCM }, 'i' },
3177 { { STATE_PSRING }, 'i' },
3178 { { STATE_EPS2 }, 'i' }
3179 };
3180
3181 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = {
3182 { { 6 /* art */ }, 'i' }
3183 };
3184
3185 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = {
3186 { { STATE_PSEXCM }, 'i' },
3187 { { STATE_PSRING }, 'i' },
3188 { { STATE_EPS2 }, 'o' }
3189 };
3190
3191 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = {
3192 { { 6 /* art */ }, 'm' }
3193 };
3194
3195 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = {
3196 { { STATE_PSEXCM }, 'i' },
3197 { { STATE_PSRING }, 'i' },
3198 { { STATE_EPS2 }, 'm' }
3199 };
3200
3201 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = {
3202 { { 6 /* art */ }, 'o' }
3203 };
3204
3205 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = {
3206 { { STATE_PSEXCM }, 'i' },
3207 { { STATE_PSRING }, 'i' },
3208 { { STATE_EPS3 }, 'i' }
3209 };
3210
3211 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = {
3212 { { 6 /* art */ }, 'i' }
3213 };
3214
3215 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = {
3216 { { STATE_PSEXCM }, 'i' },
3217 { { STATE_PSRING }, 'i' },
3218 { { STATE_EPS3 }, 'o' }
3219 };
3220
3221 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = {
3222 { { 6 /* art */ }, 'm' }
3223 };
3224
3225 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = {
3226 { { STATE_PSEXCM }, 'i' },
3227 { { STATE_PSRING }, 'i' },
3228 { { STATE_EPS3 }, 'm' }
3229 };
3230
3231 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = {
3232 { { 6 /* art */ }, 'o' }
3233 };
3234
3235 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = {
3236 { { STATE_PSEXCM }, 'i' },
3237 { { STATE_PSRING }, 'i' },
3238 { { STATE_EPS4 }, 'i' }
3239 };
3240
3241 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = {
3242 { { 6 /* art */ }, 'i' }
3243 };
3244
3245 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = {
3246 { { STATE_PSEXCM }, 'i' },
3247 { { STATE_PSRING }, 'i' },
3248 { { STATE_EPS4 }, 'o' }
3249 };
3250
3251 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = {
3252 { { 6 /* art */ }, 'm' }
3253 };
3254
3255 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = {
3256 { { STATE_PSEXCM }, 'i' },
3257 { { STATE_PSRING }, 'i' },
3258 { { STATE_EPS4 }, 'm' }
3259 };
3260
3261 static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = {
3262 { { 6 /* art */ }, 'o' }
3263 };
3264
3265 static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = {
3266 { { STATE_PSEXCM }, 'i' },
3267 { { STATE_PSRING }, 'i' },
3268 { { STATE_EXCVADDR }, 'i' }
3269 };
3270
3271 static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = {
3272 { { 6 /* art */ }, 'i' }
3273 };
3274
3275 static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = {
3276 { { STATE_PSEXCM }, 'i' },
3277 { { STATE_PSRING }, 'i' },
3278 { { STATE_EXCVADDR }, 'o' }
3279 };
3280
3281 static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = {
3282 { { 6 /* art */ }, 'm' }
3283 };
3284
3285 static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = {
3286 { { STATE_PSEXCM }, 'i' },
3287 { { STATE_PSRING }, 'i' },
3288 { { STATE_EXCVADDR }, 'm' }
3289 };
3290
3291 static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = {
3292 { { 6 /* art */ }, 'o' }
3293 };
3294
3295 static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = {
3296 { { STATE_PSEXCM }, 'i' },
3297 { { STATE_PSRING }, 'i' },
3298 { { STATE_DEPC }, 'i' }
3299 };
3300
3301 static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = {
3302 { { 6 /* art */ }, 'i' }
3303 };
3304
3305 static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = {
3306 { { STATE_PSEXCM }, 'i' },
3307 { { STATE_PSRING }, 'i' },
3308 { { STATE_DEPC }, 'o' }
3309 };
3310
3311 static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = {
3312 { { 6 /* art */ }, 'm' }
3313 };
3314
3315 static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = {
3316 { { STATE_PSEXCM }, 'i' },
3317 { { STATE_PSRING }, 'i' },
3318 { { STATE_DEPC }, 'm' }
3319 };
3320
3321 static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = {
3322 { { 6 /* art */ }, 'o' }
3323 };
3324
3325 static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = {
3326 { { STATE_PSEXCM }, 'i' },
3327 { { STATE_PSRING }, 'i' },
3328 { { STATE_EXCCAUSE }, 'i' },
3329 { { STATE_XTSYNC }, 'i' }
3330 };
3331
3332 static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = {
3333 { { 6 /* art */ }, 'i' }
3334 };
3335
3336 static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = {
3337 { { STATE_PSEXCM }, 'i' },
3338 { { STATE_PSRING }, 'i' },
3339 { { STATE_EXCCAUSE }, 'o' }
3340 };
3341
3342 static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = {
3343 { { 6 /* art */ }, 'm' }
3344 };
3345
3346 static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = {
3347 { { STATE_PSEXCM }, 'i' },
3348 { { STATE_PSRING }, 'i' },
3349 { { STATE_EXCCAUSE }, 'm' }
3350 };
3351
3352 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = {
3353 { { 6 /* art */ }, 'o' }
3354 };
3355
3356 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = {
3357 { { STATE_PSEXCM }, 'i' },
3358 { { STATE_PSRING }, 'i' },
3359 { { STATE_MISC0 }, 'i' }
3360 };
3361
3362 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = {
3363 { { 6 /* art */ }, 'i' }
3364 };
3365
3366 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = {
3367 { { STATE_PSEXCM }, 'i' },
3368 { { STATE_PSRING }, 'i' },
3369 { { STATE_MISC0 }, 'o' }
3370 };
3371
3372 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = {
3373 { { 6 /* art */ }, 'm' }
3374 };
3375
3376 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = {
3377 { { STATE_PSEXCM }, 'i' },
3378 { { STATE_PSRING }, 'i' },
3379 { { STATE_MISC0 }, 'm' }
3380 };
3381
3382 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = {
3383 { { 6 /* art */ }, 'o' }
3384 };
3385
3386 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = {
3387 { { STATE_PSEXCM }, 'i' },
3388 { { STATE_PSRING }, 'i' },
3389 { { STATE_MISC1 }, 'i' }
3390 };
3391
3392 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = {
3393 { { 6 /* art */ }, 'i' }
3394 };
3395
3396 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = {
3397 { { STATE_PSEXCM }, 'i' },
3398 { { STATE_PSRING }, 'i' },
3399 { { STATE_MISC1 }, 'o' }
3400 };
3401
3402 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = {
3403 { { 6 /* art */ }, 'm' }
3404 };
3405
3406 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = {
3407 { { STATE_PSEXCM }, 'i' },
3408 { { STATE_PSRING }, 'i' },
3409 { { STATE_MISC1 }, 'm' }
3410 };
3411
3412 static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = {
3413 { { 6 /* art */ }, 'o' }
3414 };
3415
3416 static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_stateArgs[] = {
3417 { { STATE_PSEXCM }, 'i' },
3418 { { STATE_PSRING }, 'i' }
3419 };
3420
3421 static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = {
3422 { { 40 /* s */ }, 'i' }
3423 };
3424
3425 static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = {
3426 { { STATE_PSWOE }, 'o' },
3427 { { STATE_PSCALLINC }, 'o' },
3428 { { STATE_PSOWB }, 'o' },
3429 { { STATE_PSRING }, 'm' },
3430 { { STATE_PSUM }, 'o' },
3431 { { STATE_PSEXCM }, 'm' },
3432 { { STATE_PSINTLEVEL }, 'o' },
3433 { { STATE_EPC1 }, 'i' },
3434 { { STATE_EPC2 }, 'i' },
3435 { { STATE_EPC3 }, 'i' },
3436 { { STATE_EPC4 }, 'i' },
3437 { { STATE_EPS2 }, 'i' },
3438 { { STATE_EPS3 }, 'i' },
3439 { { STATE_EPS4 }, 'i' },
3440 { { STATE_InOCDMode }, 'm' }
3441 };
3442
3443 static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = {
3444 { { 40 /* s */ }, 'i' }
3445 };
3446
3447 static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = {
3448 { { STATE_PSEXCM }, 'i' },
3449 { { STATE_PSRING }, 'i' },
3450 { { STATE_PSINTLEVEL }, 'o' }
3451 };
3452
3453 static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = {
3454 { { 6 /* art */ }, 'o' }
3455 };
3456
3457 static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = {
3458 { { STATE_PSEXCM }, 'i' },
3459 { { STATE_PSRING }, 'i' },
3460 { { STATE_INTERRUPT }, 'i' }
3461 };
3462
3463 static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = {
3464 { { 6 /* art */ }, 'i' }
3465 };
3466
3467 static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = {
3468 { { STATE_PSEXCM }, 'i' },
3469 { { STATE_PSRING }, 'i' },
3470 { { STATE_XTSYNC }, 'o' },
3471 { { STATE_INTERRUPT }, 'm' }
3472 };
3473
3474 static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = {
3475 { { 6 /* art */ }, 'i' }
3476 };
3477
3478 static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = {
3479 { { STATE_PSEXCM }, 'i' },
3480 { { STATE_PSRING }, 'i' },
3481 { { STATE_XTSYNC }, 'o' },
3482 { { STATE_INTERRUPT }, 'm' }
3483 };
3484
3485 static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = {
3486 { { 6 /* art */ }, 'o' }
3487 };
3488
3489 static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = {
3490 { { STATE_PSEXCM }, 'i' },
3491 { { STATE_PSRING }, 'i' },
3492 { { STATE_INTENABLE }, 'i' }
3493 };
3494
3495 static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = {
3496 { { 6 /* art */ }, 'i' }
3497 };
3498
3499 static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = {
3500 { { STATE_PSEXCM }, 'i' },
3501 { { STATE_PSRING }, 'i' },
3502 { { STATE_INTENABLE }, 'o' }
3503 };
3504
3505 static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = {
3506 { { 6 /* art */ }, 'm' }
3507 };
3508
3509 static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = {
3510 { { STATE_PSEXCM }, 'i' },
3511 { { STATE_PSRING }, 'i' },
3512 { { STATE_INTENABLE }, 'm' }
3513 };
3514
3515 static xtensa_arg_internal Iclass_xt_iclass_break_args[] = {
3516 { { 34 /* imms */ }, 'i' },
3517 { { 33 /* immt */ }, 'i' }
3518 };
3519
3520 static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = {
3521 { { STATE_PSEXCM }, 'i' },
3522 { { STATE_PSINTLEVEL }, 'i' }
3523 };
3524
3525 static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = {
3526 { { 34 /* imms */ }, 'i' }
3527 };
3528
3529 static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = {
3530 { { STATE_PSEXCM }, 'i' },
3531 { { STATE_PSINTLEVEL }, 'i' }
3532 };
3533
3534 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = {
3535 { { 6 /* art */ }, 'o' }
3536 };
3537
3538 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = {
3539 { { STATE_PSEXCM }, 'i' },
3540 { { STATE_PSRING }, 'i' },
3541 { { STATE_DBREAKA0 }, 'i' }
3542 };
3543
3544 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = {
3545 { { 6 /* art */ }, 'i' }
3546 };
3547
3548 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = {
3549 { { STATE_PSEXCM }, 'i' },
3550 { { STATE_PSRING }, 'i' },
3551 { { STATE_DBREAKA0 }, 'o' },
3552 { { STATE_XTSYNC }, 'o' }
3553 };
3554
3555 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = {
3556 { { 6 /* art */ }, 'm' }
3557 };
3558
3559 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = {
3560 { { STATE_PSEXCM }, 'i' },
3561 { { STATE_PSRING }, 'i' },
3562 { { STATE_DBREAKA0 }, 'm' },
3563 { { STATE_XTSYNC }, 'o' }
3564 };
3565
3566 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = {
3567 { { 6 /* art */ }, 'o' }
3568 };
3569
3570 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = {
3571 { { STATE_PSEXCM }, 'i' },
3572 { { STATE_PSRING }, 'i' },
3573 { { STATE_DBREAKC0 }, 'i' }
3574 };
3575
3576 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = {
3577 { { 6 /* art */ }, 'i' }
3578 };
3579
3580 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = {
3581 { { STATE_PSEXCM }, 'i' },
3582 { { STATE_PSRING }, 'i' },
3583 { { STATE_DBREAKC0 }, 'o' },
3584 { { STATE_XTSYNC }, 'o' }
3585 };
3586
3587 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = {
3588 { { 6 /* art */ }, 'm' }
3589 };
3590
3591 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = {
3592 { { STATE_PSEXCM }, 'i' },
3593 { { STATE_PSRING }, 'i' },
3594 { { STATE_DBREAKC0 }, 'm' },
3595 { { STATE_XTSYNC }, 'o' }
3596 };
3597
3598 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = {
3599 { { 6 /* art */ }, 'o' }
3600 };
3601
3602 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = {
3603 { { STATE_PSEXCM }, 'i' },
3604 { { STATE_PSRING }, 'i' },
3605 { { STATE_DBREAKA1 }, 'i' }
3606 };
3607
3608 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = {
3609 { { 6 /* art */ }, 'i' }
3610 };
3611
3612 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = {
3613 { { STATE_PSEXCM }, 'i' },
3614 { { STATE_PSRING }, 'i' },
3615 { { STATE_DBREAKA1 }, 'o' },
3616 { { STATE_XTSYNC }, 'o' }
3617 };
3618
3619 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = {
3620 { { 6 /* art */ }, 'm' }
3621 };
3622
3623 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = {
3624 { { STATE_PSEXCM }, 'i' },
3625 { { STATE_PSRING }, 'i' },
3626 { { STATE_DBREAKA1 }, 'm' },
3627 { { STATE_XTSYNC }, 'o' }
3628 };
3629
3630 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = {
3631 { { 6 /* art */ }, 'o' }
3632 };
3633
3634 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = {
3635 { { STATE_PSEXCM }, 'i' },
3636 { { STATE_PSRING }, 'i' },
3637 { { STATE_DBREAKC1 }, 'i' }
3638 };
3639
3640 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = {
3641 { { 6 /* art */ }, 'i' }
3642 };
3643
3644 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = {
3645 { { STATE_PSEXCM }, 'i' },
3646 { { STATE_PSRING }, 'i' },
3647 { { STATE_DBREAKC1 }, 'o' },
3648 { { STATE_XTSYNC }, 'o' }
3649 };
3650
3651 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = {
3652 { { 6 /* art */ }, 'm' }
3653 };
3654
3655 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = {
3656 { { STATE_PSEXCM }, 'i' },
3657 { { STATE_PSRING }, 'i' },
3658 { { STATE_DBREAKC1 }, 'm' },
3659 { { STATE_XTSYNC }, 'o' }
3660 };
3661
3662 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = {
3663 { { 6 /* art */ }, 'o' }
3664 };
3665
3666 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = {
3667 { { STATE_PSEXCM }, 'i' },
3668 { { STATE_PSRING }, 'i' },
3669 { { STATE_IBREAKA0 }, 'i' }
3670 };
3671
3672 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = {
3673 { { 6 /* art */ }, 'i' }
3674 };
3675
3676 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = {
3677 { { STATE_PSEXCM }, 'i' },
3678 { { STATE_PSRING }, 'i' },
3679 { { STATE_IBREAKA0 }, 'o' }
3680 };
3681
3682 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = {
3683 { { 6 /* art */ }, 'm' }
3684 };
3685
3686 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = {
3687 { { STATE_PSEXCM }, 'i' },
3688 { { STATE_PSRING }, 'i' },
3689 { { STATE_IBREAKA0 }, 'm' }
3690 };
3691
3692 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = {
3693 { { 6 /* art */ }, 'o' }
3694 };
3695
3696 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = {
3697 { { STATE_PSEXCM }, 'i' },
3698 { { STATE_PSRING }, 'i' },
3699 { { STATE_IBREAKA1 }, 'i' }
3700 };
3701
3702 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = {
3703 { { 6 /* art */ }, 'i' }
3704 };
3705
3706 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = {
3707 { { STATE_PSEXCM }, 'i' },
3708 { { STATE_PSRING }, 'i' },
3709 { { STATE_IBREAKA1 }, 'o' }
3710 };
3711
3712 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = {
3713 { { 6 /* art */ }, 'm' }
3714 };
3715
3716 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = {
3717 { { STATE_PSEXCM }, 'i' },
3718 { { STATE_PSRING }, 'i' },
3719 { { STATE_IBREAKA1 }, 'm' }
3720 };
3721
3722 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = {
3723 { { 6 /* art */ }, 'o' }
3724 };
3725
3726 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = {
3727 { { STATE_PSEXCM }, 'i' },
3728 { { STATE_PSRING }, 'i' },
3729 { { STATE_IBREAKENABLE }, 'i' }
3730 };
3731
3732 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = {
3733 { { 6 /* art */ }, 'i' }
3734 };
3735
3736 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = {
3737 { { STATE_PSEXCM }, 'i' },
3738 { { STATE_PSRING }, 'i' },
3739 { { STATE_IBREAKENABLE }, 'o' }
3740 };
3741
3742 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = {
3743 { { 6 /* art */ }, 'm' }
3744 };
3745
3746 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = {
3747 { { STATE_PSEXCM }, 'i' },
3748 { { STATE_PSRING }, 'i' },
3749 { { STATE_IBREAKENABLE }, 'm' }
3750 };
3751
3752 static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = {
3753 { { 6 /* art */ }, 'o' }
3754 };
3755
3756 static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = {
3757 { { STATE_PSEXCM }, 'i' },
3758 { { STATE_PSRING }, 'i' },
3759 { { STATE_DEBUGCAUSE }, 'i' },
3760 { { STATE_DBNUM }, 'i' }
3761 };
3762
3763 static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = {
3764 { { 6 /* art */ }, 'i' }
3765 };
3766
3767 static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = {
3768 { { STATE_PSEXCM }, 'i' },
3769 { { STATE_PSRING }, 'i' },
3770 { { STATE_DEBUGCAUSE }, 'o' },
3771 { { STATE_DBNUM }, 'o' }
3772 };
3773
3774 static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = {
3775 { { 6 /* art */ }, 'm' }
3776 };
3777
3778 static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = {
3779 { { STATE_PSEXCM }, 'i' },
3780 { { STATE_PSRING }, 'i' },
3781 { { STATE_DEBUGCAUSE }, 'm' },
3782 { { STATE_DBNUM }, 'm' }
3783 };
3784
3785 static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = {
3786 { { 6 /* art */ }, 'o' }
3787 };
3788
3789 static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = {
3790 { { STATE_PSEXCM }, 'i' },
3791 { { STATE_PSRING }, 'i' },
3792 { { STATE_ICOUNT }, 'i' }
3793 };
3794
3795 static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = {
3796 { { 6 /* art */ }, 'i' }
3797 };
3798
3799 static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = {
3800 { { STATE_PSEXCM }, 'i' },
3801 { { STATE_PSRING }, 'i' },
3802 { { STATE_XTSYNC }, 'o' },
3803 { { STATE_ICOUNT }, 'o' }
3804 };
3805
3806 static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = {
3807 { { 6 /* art */ }, 'm' }
3808 };
3809
3810 static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = {
3811 { { STATE_PSEXCM }, 'i' },
3812 { { STATE_PSRING }, 'i' },
3813 { { STATE_XTSYNC }, 'o' },
3814 { { STATE_ICOUNT }, 'm' }
3815 };
3816
3817 static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = {
3818 { { 6 /* art */ }, 'o' }
3819 };
3820
3821 static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = {
3822 { { STATE_PSEXCM }, 'i' },
3823 { { STATE_PSRING }, 'i' },
3824 { { STATE_ICOUNTLEVEL }, 'i' }
3825 };
3826
3827 static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = {
3828 { { 6 /* art */ }, 'i' }
3829 };
3830
3831 static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = {
3832 { { STATE_PSEXCM }, 'i' },
3833 { { STATE_PSRING }, 'i' },
3834 { { STATE_ICOUNTLEVEL }, 'o' }
3835 };
3836
3837 static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = {
3838 { { 6 /* art */ }, 'm' }
3839 };
3840
3841 static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = {
3842 { { STATE_PSEXCM }, 'i' },
3843 { { STATE_PSRING }, 'i' },
3844 { { STATE_ICOUNTLEVEL }, 'm' }
3845 };
3846
3847 static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = {
3848 { { 6 /* art */ }, 'o' }
3849 };
3850
3851 static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = {
3852 { { STATE_PSEXCM }, 'i' },
3853 { { STATE_PSRING }, 'i' },
3854 { { STATE_DDR }, 'i' }
3855 };
3856
3857 static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = {
3858 { { 6 /* art */ }, 'i' }
3859 };
3860
3861 static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = {
3862 { { STATE_PSEXCM }, 'i' },
3863 { { STATE_PSRING }, 'i' },
3864 { { STATE_XTSYNC }, 'o' },
3865 { { STATE_DDR }, 'o' }
3866 };
3867
3868 static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = {
3869 { { 6 /* art */ }, 'm' }
3870 };
3871
3872 static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = {
3873 { { STATE_PSEXCM }, 'i' },
3874 { { STATE_PSRING }, 'i' },
3875 { { STATE_XTSYNC }, 'o' },
3876 { { STATE_DDR }, 'm' }
3877 };
3878
3879 static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = {
3880 { { STATE_InOCDMode }, 'm' },
3881 { { STATE_EPC4 }, 'i' },
3882 { { STATE_PSWOE }, 'o' },
3883 { { STATE_PSCALLINC }, 'o' },
3884 { { STATE_PSOWB }, 'o' },
3885 { { STATE_PSRING }, 'o' },
3886 { { STATE_PSUM }, 'o' },
3887 { { STATE_PSEXCM }, 'o' },
3888 { { STATE_PSINTLEVEL }, 'o' },
3889 { { STATE_EPS4 }, 'i' }
3890 };
3891
3892 static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = {
3893 { { STATE_InOCDMode }, 'm' }
3894 };
3895
3896 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = {
3897 { { 6 /* art */ }, 'o' }
3898 };
3899
3900 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = {
3901 { { STATE_PSEXCM }, 'i' },
3902 { { STATE_PSRING }, 'i' },
3903 { { STATE_CCOUNT }, 'i' }
3904 };
3905
3906 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = {
3907 { { 6 /* art */ }, 'i' }
3908 };
3909
3910 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = {
3911 { { STATE_PSEXCM }, 'i' },
3912 { { STATE_PSRING }, 'i' },
3913 { { STATE_XTSYNC }, 'o' },
3914 { { STATE_CCOUNT }, 'o' }
3915 };
3916
3917 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = {
3918 { { 6 /* art */ }, 'm' }
3919 };
3920
3921 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = {
3922 { { STATE_PSEXCM }, 'i' },
3923 { { STATE_PSRING }, 'i' },
3924 { { STATE_XTSYNC }, 'o' },
3925 { { STATE_CCOUNT }, 'm' }
3926 };
3927
3928 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = {
3929 { { 6 /* art */ }, 'o' }
3930 };
3931
3932 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = {
3933 { { STATE_PSEXCM }, 'i' },
3934 { { STATE_PSRING }, 'i' },
3935 { { STATE_CCOMPARE0 }, 'i' }
3936 };
3937
3938 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = {
3939 { { 6 /* art */ }, 'i' }
3940 };
3941
3942 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = {
3943 { { STATE_PSEXCM }, 'i' },
3944 { { STATE_PSRING }, 'i' },
3945 { { STATE_CCOMPARE0 }, 'o' },
3946 { { STATE_INTERRUPT }, 'm' }
3947 };
3948
3949 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = {
3950 { { 6 /* art */ }, 'm' }
3951 };
3952
3953 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = {
3954 { { STATE_PSEXCM }, 'i' },
3955 { { STATE_PSRING }, 'i' },
3956 { { STATE_CCOMPARE0 }, 'm' },
3957 { { STATE_INTERRUPT }, 'm' }
3958 };
3959
3960 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = {
3961 { { 6 /* art */ }, 'o' }
3962 };
3963
3964 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = {
3965 { { STATE_PSEXCM }, 'i' },
3966 { { STATE_PSRING }, 'i' },
3967 { { STATE_CCOMPARE1 }, 'i' }
3968 };
3969
3970 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = {
3971 { { 6 /* art */ }, 'i' }
3972 };
3973
3974 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = {
3975 { { STATE_PSEXCM }, 'i' },
3976 { { STATE_PSRING }, 'i' },
3977 { { STATE_CCOMPARE1 }, 'o' },
3978 { { STATE_INTERRUPT }, 'm' }
3979 };
3980
3981 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = {
3982 { { 6 /* art */ }, 'm' }
3983 };
3984
3985 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = {
3986 { { STATE_PSEXCM }, 'i' },
3987 { { STATE_PSRING }, 'i' },
3988 { { STATE_CCOMPARE1 }, 'm' },
3989 { { STATE_INTERRUPT }, 'm' }
3990 };
3991
3992 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = {
3993 { { 6 /* art */ }, 'o' }
3994 };
3995
3996 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = {
3997 { { STATE_PSEXCM }, 'i' },
3998 { { STATE_PSRING }, 'i' },
3999 { { STATE_CCOMPARE2 }, 'i' }
4000 };
4001
4002 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = {
4003 { { 6 /* art */ }, 'i' }
4004 };
4005
4006 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = {
4007 { { STATE_PSEXCM }, 'i' },
4008 { { STATE_PSRING }, 'i' },
4009 { { STATE_CCOMPARE2 }, 'o' },
4010 { { STATE_INTERRUPT }, 'm' }
4011 };
4012
4013 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = {
4014 { { 6 /* art */ }, 'm' }
4015 };
4016
4017 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = {
4018 { { STATE_PSEXCM }, 'i' },
4019 { { STATE_PSRING }, 'i' },
4020 { { STATE_CCOMPARE2 }, 'm' },
4021 { { STATE_INTERRUPT }, 'm' }
4022 };
4023
4024 static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = {
4025 { { 4 /* ars */ }, 'i' },
4026 { { 21 /* uimm8x4 */ }, 'i' }
4027 };
4028
4029 static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = {
4030 { { 4 /* ars */ }, 'i' },
4031 { { 21 /* uimm8x4 */ }, 'i' }
4032 };
4033
4034 static xtensa_arg_internal Iclass_xt_iclass_icache_inv_stateArgs[] = {
4035 { { STATE_PSEXCM }, 'i' },
4036 { { STATE_PSRING }, 'i' }
4037 };
4038
4039 static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = {
4040 { { 6 /* art */ }, 'o' },
4041 { { 4 /* ars */ }, 'i' }
4042 };
4043
4044 static xtensa_arg_internal Iclass_xt_iclass_licx_stateArgs[] = {
4045 { { STATE_PSEXCM }, 'i' },
4046 { { STATE_PSRING }, 'i' }
4047 };
4048
4049 static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = {
4050 { { 6 /* art */ }, 'i' },
4051 { { 4 /* ars */ }, 'i' }
4052 };
4053
4054 static xtensa_arg_internal Iclass_xt_iclass_sicx_stateArgs[] = {
4055 { { STATE_PSEXCM }, 'i' },
4056 { { STATE_PSRING }, 'i' }
4057 };
4058
4059 static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = {
4060 { { 4 /* ars */ }, 'i' },
4061 { { 21 /* uimm8x4 */ }, 'i' }
4062 };
4063
4064 static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args[] = {
4065 { { 4 /* ars */ }, 'i' },
4066 { { 22 /* uimm4x16 */ }, 'i' }
4067 };
4068
4069 static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_stateArgs[] = {
4070 { { STATE_PSEXCM }, 'i' },
4071 { { STATE_PSRING }, 'i' }
4072 };
4073
4074 static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = {
4075 { { 4 /* ars */ }, 'i' },
4076 { { 21 /* uimm8x4 */ }, 'i' }
4077 };
4078
4079 static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_stateArgs[] = {
4080 { { STATE_PSEXCM }, 'i' },
4081 { { STATE_PSRING }, 'i' }
4082 };
4083
4084 static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = {
4085 { { 4 /* ars */ }, 'i' },
4086 { { 21 /* uimm8x4 */ }, 'i' }
4087 };
4088
4089 static xtensa_arg_internal Iclass_xt_iclass_sdct_args[] = {
4090 { { 6 /* art */ }, 'i' },
4091 { { 4 /* ars */ }, 'i' }
4092 };
4093
4094 static xtensa_arg_internal Iclass_xt_iclass_sdct_stateArgs[] = {
4095 { { STATE_PSEXCM }, 'i' },
4096 { { STATE_PSRING }, 'i' }
4097 };
4098
4099 static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = {
4100 { { 6 /* art */ }, 'o' },
4101 { { 4 /* ars */ }, 'i' }
4102 };
4103
4104 static xtensa_arg_internal Iclass_xt_iclass_ldct_stateArgs[] = {
4105 { { STATE_PSEXCM }, 'i' },
4106 { { STATE_PSRING }, 'i' }
4107 };
4108
4109 static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_args[] = {
4110 { { 6 /* art */ }, 'i' }
4111 };
4112
4113 static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_stateArgs[] = {
4114 { { STATE_PSEXCM }, 'i' },
4115 { { STATE_PSRING }, 'i' },
4116 { { STATE_PTBASE }, 'o' },
4117 { { STATE_XTSYNC }, 'o' }
4118 };
4119
4120 static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_args[] = {
4121 { { 6 /* art */ }, 'o' }
4122 };
4123
4124 static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_stateArgs[] = {
4125 { { STATE_PSEXCM }, 'i' },
4126 { { STATE_PSRING }, 'i' },
4127 { { STATE_PTBASE }, 'i' },
4128 { { STATE_EXCVADDR }, 'i' }
4129 };
4130
4131 static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_args[] = {
4132 { { 6 /* art */ }, 'm' }
4133 };
4134
4135 static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_stateArgs[] = {
4136 { { STATE_PSEXCM }, 'i' },
4137 { { STATE_PSRING }, 'i' },
4138 { { STATE_PTBASE }, 'm' },
4139 { { STATE_EXCVADDR }, 'i' },
4140 { { STATE_XTSYNC }, 'o' }
4141 };
4142
4143 static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_args[] = {
4144 { { 6 /* art */ }, 'o' }
4145 };
4146
4147 static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_stateArgs[] = {
4148 { { STATE_PSEXCM }, 'i' },
4149 { { STATE_PSRING }, 'i' },
4150 { { STATE_ASID3 }, 'i' },
4151 { { STATE_ASID2 }, 'i' },
4152 { { STATE_ASID1 }, 'i' }
4153 };
4154
4155 static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_args[] = {
4156 { { 6 /* art */ }, 'i' }
4157 };
4158
4159 static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_stateArgs[] = {
4160 { { STATE_XTSYNC }, 'o' },
4161 { { STATE_PSEXCM }, 'i' },
4162 { { STATE_PSRING }, 'i' },
4163 { { STATE_ASID3 }, 'o' },
4164 { { STATE_ASID2 }, 'o' },
4165 { { STATE_ASID1 }, 'o' }
4166 };
4167
4168 static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_args[] = {
4169 { { 6 /* art */ }, 'm' }
4170 };
4171
4172 static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_stateArgs[] = {
4173 { { STATE_XTSYNC }, 'o' },
4174 { { STATE_PSEXCM }, 'i' },
4175 { { STATE_PSRING }, 'i' },
4176 { { STATE_ASID3 }, 'm' },
4177 { { STATE_ASID2 }, 'm' },
4178 { { STATE_ASID1 }, 'm' }
4179 };
4180
4181 static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_args[] = {
4182 { { 6 /* art */ }, 'o' }
4183 };
4184
4185 static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_stateArgs[] = {
4186 { { STATE_PSEXCM }, 'i' },
4187 { { STATE_PSRING }, 'i' },
4188 { { STATE_INSTPGSZID4 }, 'i' }
4189 };
4190
4191 static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_args[] = {
4192 { { 6 /* art */ }, 'i' }
4193 };
4194
4195 static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_stateArgs[] = {
4196 { { STATE_XTSYNC }, 'o' },
4197 { { STATE_PSEXCM }, 'i' },
4198 { { STATE_PSRING }, 'i' },
4199 { { STATE_INSTPGSZID4 }, 'o' }
4200 };
4201
4202 static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_args[] = {
4203 { { 6 /* art */ }, 'm' }
4204 };
4205
4206 static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_stateArgs[] = {
4207 { { STATE_XTSYNC }, 'o' },
4208 { { STATE_PSEXCM }, 'i' },
4209 { { STATE_PSRING }, 'i' },
4210 { { STATE_INSTPGSZID4 }, 'm' }
4211 };
4212
4213 static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_args[] = {
4214 { { 6 /* art */ }, 'o' }
4215 };
4216
4217 static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_stateArgs[] = {
4218 { { STATE_PSEXCM }, 'i' },
4219 { { STATE_PSRING }, 'i' },
4220 { { STATE_DATAPGSZID4 }, 'i' }
4221 };
4222
4223 static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_args[] = {
4224 { { 6 /* art */ }, 'i' }
4225 };
4226
4227 static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_stateArgs[] = {
4228 { { STATE_XTSYNC }, 'o' },
4229 { { STATE_PSEXCM }, 'i' },
4230 { { STATE_PSRING }, 'i' },
4231 { { STATE_DATAPGSZID4 }, 'o' }
4232 };
4233
4234 static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_args[] = {
4235 { { 6 /* art */ }, 'm' }
4236 };
4237
4238 static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_stateArgs[] = {
4239 { { STATE_XTSYNC }, 'o' },
4240 { { STATE_PSEXCM }, 'i' },
4241 { { STATE_PSRING }, 'i' },
4242 { { STATE_DATAPGSZID4 }, 'm' }
4243 };
4244
4245 static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = {
4246 { { 4 /* ars */ }, 'i' }
4247 };
4248
4249 static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = {
4250 { { STATE_PSEXCM }, 'i' },
4251 { { STATE_PSRING }, 'i' },
4252 { { STATE_XTSYNC }, 'o' }
4253 };
4254
4255 static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = {
4256 { { 6 /* art */ }, 'o' },
4257 { { 4 /* ars */ }, 'i' }
4258 };
4259
4260 static xtensa_arg_internal Iclass_xt_iclass_rdtlb_stateArgs[] = {
4261 { { STATE_PSEXCM }, 'i' },
4262 { { STATE_PSRING }, 'i' }
4263 };
4264
4265 static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = {
4266 { { 6 /* art */ }, 'i' },
4267 { { 4 /* ars */ }, 'i' }
4268 };
4269
4270 static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = {
4271 { { STATE_PSEXCM }, 'i' },
4272 { { STATE_PSRING }, 'i' },
4273 { { STATE_XTSYNC }, 'o' }
4274 };
4275
4276 static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = {
4277 { { 4 /* ars */ }, 'i' }
4278 };
4279
4280 static xtensa_arg_internal Iclass_xt_iclass_iitlb_stateArgs[] = {
4281 { { STATE_PSEXCM }, 'i' },
4282 { { STATE_PSRING }, 'i' }
4283 };
4284
4285 static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = {
4286 { { 6 /* art */ }, 'o' },
4287 { { 4 /* ars */ }, 'i' }
4288 };
4289
4290 static xtensa_arg_internal Iclass_xt_iclass_ritlb_stateArgs[] = {
4291 { { STATE_PSEXCM }, 'i' },
4292 { { STATE_PSRING }, 'i' }
4293 };
4294
4295 static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = {
4296 { { 6 /* art */ }, 'i' },
4297 { { 4 /* ars */ }, 'i' }
4298 };
4299
4300 static xtensa_arg_internal Iclass_xt_iclass_witlb_stateArgs[] = {
4301 { { STATE_PSEXCM }, 'i' },
4302 { { STATE_PSRING }, 'i' }
4303 };
4304
4305 static xtensa_arg_internal Iclass_xt_iclass_ldpte_stateArgs[] = {
4306 { { STATE_PTBASE }, 'i' },
4307 { { STATE_EXCVADDR }, 'i' }
4308 };
4309
4310 static xtensa_arg_internal Iclass_xt_iclass_hwwitlba_stateArgs[] = {
4311 { { STATE_EXCVADDR }, 'i' }
4312 };
4313
4314 static xtensa_arg_internal Iclass_xt_iclass_hwwdtlba_stateArgs[] = {
4315 { { STATE_EXCVADDR }, 'i' }
4316 };
4317
4318 static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = {
4319 { { 6 /* art */ }, 'o' },
4320 { { 4 /* ars */ }, 'i' }
4321 };
4322
4323 static xtensa_iclass_internal iclasses[] = {
4324 { 0, 0 /* xt_iclass_excw */,
4325 0, 0, 0, 0 },
4326 { 0, 0 /* xt_iclass_rfe */,
4327 3, Iclass_xt_iclass_rfe_stateArgs, 0, 0 },
4328 { 0, 0 /* xt_iclass_rfde */,
4329 3, Iclass_xt_iclass_rfde_stateArgs, 0, 0 },
4330 { 0, 0 /* xt_iclass_syscall */,
4331 0, 0, 0, 0 },
4332 { 0, 0 /* xt_iclass_simcall */,
4333 0, 0, 0, 0 },
4334 { 2, Iclass_xt_iclass_call12_args,
4335 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 },
4336 { 2, Iclass_xt_iclass_call8_args,
4337 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 },
4338 { 2, Iclass_xt_iclass_call4_args,
4339 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 },
4340 { 2, Iclass_xt_iclass_callx12_args,
4341 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 },
4342 { 2, Iclass_xt_iclass_callx8_args,
4343 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 },
4344 { 2, Iclass_xt_iclass_callx4_args,
4345 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 },
4346 { 3, Iclass_xt_iclass_entry_args,
4347 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 },
4348 { 2, Iclass_xt_iclass_movsp_args,
4349 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 },
4350 { 1, Iclass_xt_iclass_rotw_args,
4351 3, Iclass_xt_iclass_rotw_stateArgs, 0, 0 },
4352 { 1, Iclass_xt_iclass_retw_args,
4353 4, Iclass_xt_iclass_retw_stateArgs, 0, 0 },
4354 { 0, 0 /* xt_iclass_rfwou */,
4355 6, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 },
4356 { 3, Iclass_xt_iclass_l32e_args,
4357 2, Iclass_xt_iclass_l32e_stateArgs, 0, 0 },
4358 { 3, Iclass_xt_iclass_s32e_args,
4359 2, Iclass_xt_iclass_s32e_stateArgs, 0, 0 },
4360 { 1, Iclass_xt_iclass_rsr_windowbase_args,
4361 3, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 },
4362 { 1, Iclass_xt_iclass_wsr_windowbase_args,
4363 3, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 },
4364 { 1, Iclass_xt_iclass_xsr_windowbase_args,
4365 3, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 },
4366 { 1, Iclass_xt_iclass_rsr_windowstart_args,
4367 3, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 },
4368 { 1, Iclass_xt_iclass_wsr_windowstart_args,
4369 3, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 },
4370 { 1, Iclass_xt_iclass_xsr_windowstart_args,
4371 3, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 },
4372 { 3, Iclass_xt_iclass_add_n_args,
4373 0, 0, 0, 0 },
4374 { 3, Iclass_xt_iclass_addi_n_args,
4375 0, 0, 0, 0 },
4376 { 2, Iclass_xt_iclass_bz6_args,
4377 0, 0, 0, 0 },
4378 { 0, 0 /* xt_iclass_ill_n */,
4379 0, 0, 0, 0 },
4380 { 3, Iclass_xt_iclass_loadi4_args,
4381 0, 0, 0, 0 },
4382 { 2, Iclass_xt_iclass_mov_n_args,
4383 0, 0, 0, 0 },
4384 { 2, Iclass_xt_iclass_movi_n_args,
4385 0, 0, 0, 0 },
4386 { 0, 0 /* xt_iclass_nopn */,
4387 0, 0, 0, 0 },
4388 { 1, Iclass_xt_iclass_retn_args,
4389 0, 0, 0, 0 },
4390 { 3, Iclass_xt_iclass_storei4_args,
4391 0, 0, 0, 0 },
4392 { 3, Iclass_xt_iclass_addi_args,
4393 0, 0, 0, 0 },
4394 { 3, Iclass_xt_iclass_addmi_args,
4395 0, 0, 0, 0 },
4396 { 3, Iclass_xt_iclass_addsub_args,
4397 0, 0, 0, 0 },
4398 { 3, Iclass_xt_iclass_bit_args,
4399 0, 0, 0, 0 },
4400 { 3, Iclass_xt_iclass_bsi8_args,
4401 0, 0, 0, 0 },
4402 { 3, Iclass_xt_iclass_bsi8b_args,
4403 0, 0, 0, 0 },
4404 { 3, Iclass_xt_iclass_bsi8u_args,
4405 0, 0, 0, 0 },
4406 { 3, Iclass_xt_iclass_bst8_args,
4407 0, 0, 0, 0 },
4408 { 2, Iclass_xt_iclass_bsz12_args,
4409 0, 0, 0, 0 },
4410 { 2, Iclass_xt_iclass_call0_args,
4411 0, 0, 0, 0 },
4412 { 2, Iclass_xt_iclass_callx0_args,
4413 0, 0, 0, 0 },
4414 { 4, Iclass_xt_iclass_exti_args,
4415 0, 0, 0, 0 },
4416 { 0, 0 /* xt_iclass_ill */,
4417 0, 0, 0, 0 },
4418 { 1, Iclass_xt_iclass_jump_args,
4419 0, 0, 0, 0 },
4420 { 1, Iclass_xt_iclass_jumpx_args,
4421 0, 0, 0, 0 },
4422 { 3, Iclass_xt_iclass_l16ui_args,
4423 0, 0, 0, 0 },
4424 { 3, Iclass_xt_iclass_l16si_args,
4425 0, 0, 0, 0 },
4426 { 3, Iclass_xt_iclass_l32i_args,
4427 0, 0, 0, 0 },
4428 { 2, Iclass_xt_iclass_l32r_args,
4429 2, Iclass_xt_iclass_l32r_stateArgs, 0, 0 },
4430 { 3, Iclass_xt_iclass_l8i_args,
4431 0, 0, 0, 0 },
4432 { 2, Iclass_xt_iclass_loop_args,
4433 3, Iclass_xt_iclass_loop_stateArgs, 0, 0 },
4434 { 2, Iclass_xt_iclass_loopz_args,
4435 3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 },
4436 { 2, Iclass_xt_iclass_movi_args,
4437 0, 0, 0, 0 },
4438 { 3, Iclass_xt_iclass_movz_args,
4439 0, 0, 0, 0 },
4440 { 2, Iclass_xt_iclass_neg_args,
4441 0, 0, 0, 0 },
4442 { 0, 0 /* xt_iclass_nop */,
4443 0, 0, 0, 0 },
4444 { 1, Iclass_xt_iclass_return_args,
4445 0, 0, 0, 0 },
4446 { 3, Iclass_xt_iclass_s16i_args,
4447 0, 0, 0, 0 },
4448 { 3, Iclass_xt_iclass_s32i_args,
4449 0, 0, 0, 0 },
4450 { 3, Iclass_xt_iclass_s8i_args,
4451 0, 0, 0, 0 },
4452 { 1, Iclass_xt_iclass_sar_args,
4453 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 },
4454 { 1, Iclass_xt_iclass_sari_args,
4455 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 },
4456 { 2, Iclass_xt_iclass_shifts_args,
4457 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 },
4458 { 3, Iclass_xt_iclass_shiftst_args,
4459 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 },
4460 { 2, Iclass_xt_iclass_shiftt_args,
4461 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 },
4462 { 3, Iclass_xt_iclass_slli_args,
4463 0, 0, 0, 0 },
4464 { 3, Iclass_xt_iclass_srai_args,
4465 0, 0, 0, 0 },
4466 { 3, Iclass_xt_iclass_srli_args,
4467 0, 0, 0, 0 },
4468 { 0, 0 /* xt_iclass_memw */,
4469 0, 0, 0, 0 },
4470 { 0, 0 /* xt_iclass_extw */,
4471 0, 0, 0, 0 },
4472 { 0, 0 /* xt_iclass_isync */,
4473 0, 0, 0, 0 },
4474 { 0, 0 /* xt_iclass_sync */,
4475 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 },
4476 { 2, Iclass_xt_iclass_rsil_args,
4477 7, Iclass_xt_iclass_rsil_stateArgs, 0, 0 },
4478 { 1, Iclass_xt_iclass_rsr_lend_args,
4479 1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 },
4480 { 1, Iclass_xt_iclass_wsr_lend_args,
4481 1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 },
4482 { 1, Iclass_xt_iclass_xsr_lend_args,
4483 1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 },
4484 { 1, Iclass_xt_iclass_rsr_lcount_args,
4485 1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 },
4486 { 1, Iclass_xt_iclass_wsr_lcount_args,
4487 2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 },
4488 { 1, Iclass_xt_iclass_xsr_lcount_args,
4489 2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 },
4490 { 1, Iclass_xt_iclass_rsr_lbeg_args,
4491 1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 },
4492 { 1, Iclass_xt_iclass_wsr_lbeg_args,
4493 1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 },
4494 { 1, Iclass_xt_iclass_xsr_lbeg_args,
4495 1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 },
4496 { 1, Iclass_xt_iclass_rsr_sar_args,
4497 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 },
4498 { 1, Iclass_xt_iclass_wsr_sar_args,
4499 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 },
4500 { 1, Iclass_xt_iclass_xsr_sar_args,
4501 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 },
4502 { 1, Iclass_xt_iclass_rsr_litbase_args,
4503 2, Iclass_xt_iclass_rsr_litbase_stateArgs, 0, 0 },
4504 { 1, Iclass_xt_iclass_wsr_litbase_args,
4505 2, Iclass_xt_iclass_wsr_litbase_stateArgs, 0, 0 },
4506 { 1, Iclass_xt_iclass_xsr_litbase_args,
4507 2, Iclass_xt_iclass_xsr_litbase_stateArgs, 0, 0 },
4508 { 1, Iclass_xt_iclass_rsr_176_args,
4509 2, Iclass_xt_iclass_rsr_176_stateArgs, 0, 0 },
4510 { 1, Iclass_xt_iclass_rsr_208_args,
4511 2, Iclass_xt_iclass_rsr_208_stateArgs, 0, 0 },
4512 { 1, Iclass_xt_iclass_rsr_ps_args,
4513 7, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 },
4514 { 1, Iclass_xt_iclass_wsr_ps_args,
4515 7, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 },
4516 { 1, Iclass_xt_iclass_xsr_ps_args,
4517 7, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 },
4518 { 1, Iclass_xt_iclass_rsr_epc1_args,
4519 3, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 },
4520 { 1, Iclass_xt_iclass_wsr_epc1_args,
4521 3, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 },
4522 { 1, Iclass_xt_iclass_xsr_epc1_args,
4523 3, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 },
4524 { 1, Iclass_xt_iclass_rsr_excsave1_args,
4525 3, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 },
4526 { 1, Iclass_xt_iclass_wsr_excsave1_args,
4527 3, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 },
4528 { 1, Iclass_xt_iclass_xsr_excsave1_args,
4529 3, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 },
4530 { 1, Iclass_xt_iclass_rsr_epc2_args,
4531 3, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 },
4532 { 1, Iclass_xt_iclass_wsr_epc2_args,
4533 3, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 },
4534 { 1, Iclass_xt_iclass_xsr_epc2_args,
4535 3, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 },
4536 { 1, Iclass_xt_iclass_rsr_excsave2_args,
4537 3, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 },
4538 { 1, Iclass_xt_iclass_wsr_excsave2_args,
4539 3, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 },
4540 { 1, Iclass_xt_iclass_xsr_excsave2_args,
4541 3, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 },
4542 { 1, Iclass_xt_iclass_rsr_epc3_args,
4543 3, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 },
4544 { 1, Iclass_xt_iclass_wsr_epc3_args,
4545 3, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 },
4546 { 1, Iclass_xt_iclass_xsr_epc3_args,
4547 3, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 },
4548 { 1, Iclass_xt_iclass_rsr_excsave3_args,
4549 3, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 },
4550 { 1, Iclass_xt_iclass_wsr_excsave3_args,
4551 3, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 },
4552 { 1, Iclass_xt_iclass_xsr_excsave3_args,
4553 3, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 },
4554 { 1, Iclass_xt_iclass_rsr_epc4_args,
4555 3, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 },
4556 { 1, Iclass_xt_iclass_wsr_epc4_args,
4557 3, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 },
4558 { 1, Iclass_xt_iclass_xsr_epc4_args,
4559 3, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 },
4560 { 1, Iclass_xt_iclass_rsr_excsave4_args,
4561 3, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 },
4562 { 1, Iclass_xt_iclass_wsr_excsave4_args,
4563 3, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 },
4564 { 1, Iclass_xt_iclass_xsr_excsave4_args,
4565 3, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 },
4566 { 1, Iclass_xt_iclass_rsr_eps2_args,
4567 3, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 },
4568 { 1, Iclass_xt_iclass_wsr_eps2_args,
4569 3, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 },
4570 { 1, Iclass_xt_iclass_xsr_eps2_args,
4571 3, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 },
4572 { 1, Iclass_xt_iclass_rsr_eps3_args,
4573 3, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 },
4574 { 1, Iclass_xt_iclass_wsr_eps3_args,
4575 3, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 },
4576 { 1, Iclass_xt_iclass_xsr_eps3_args,
4577 3, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 },
4578 { 1, Iclass_xt_iclass_rsr_eps4_args,
4579 3, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 },
4580 { 1, Iclass_xt_iclass_wsr_eps4_args,
4581 3, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 },
4582 { 1, Iclass_xt_iclass_xsr_eps4_args,
4583 3, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 },
4584 { 1, Iclass_xt_iclass_rsr_excvaddr_args,
4585 3, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 },
4586 { 1, Iclass_xt_iclass_wsr_excvaddr_args,
4587 3, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 },
4588 { 1, Iclass_xt_iclass_xsr_excvaddr_args,
4589 3, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 },
4590 { 1, Iclass_xt_iclass_rsr_depc_args,
4591 3, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 },
4592 { 1, Iclass_xt_iclass_wsr_depc_args,
4593 3, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 },
4594 { 1, Iclass_xt_iclass_xsr_depc_args,
4595 3, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 },
4596 { 1, Iclass_xt_iclass_rsr_exccause_args,
4597 4, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 },
4598 { 1, Iclass_xt_iclass_wsr_exccause_args,
4599 3, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 },
4600 { 1, Iclass_xt_iclass_xsr_exccause_args,
4601 3, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 },
4602 { 1, Iclass_xt_iclass_rsr_misc0_args,
4603 3, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 },
4604 { 1, Iclass_xt_iclass_wsr_misc0_args,
4605 3, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 },
4606 { 1, Iclass_xt_iclass_xsr_misc0_args,
4607 3, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 },
4608 { 1, Iclass_xt_iclass_rsr_misc1_args,
4609 3, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 },
4610 { 1, Iclass_xt_iclass_wsr_misc1_args,
4611 3, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 },
4612 { 1, Iclass_xt_iclass_xsr_misc1_args,
4613 3, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 },
4614 { 1, Iclass_xt_iclass_rsr_prid_args,
4615 2, Iclass_xt_iclass_rsr_prid_stateArgs, 0, 0 },
4616 { 1, Iclass_xt_iclass_rfi_args,
4617 15, Iclass_xt_iclass_rfi_stateArgs, 0, 0 },
4618 { 1, Iclass_xt_iclass_wait_args,
4619 3, Iclass_xt_iclass_wait_stateArgs, 0, 0 },
4620 { 1, Iclass_xt_iclass_rsr_interrupt_args,
4621 3, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 },
4622 { 1, Iclass_xt_iclass_wsr_intset_args,
4623 4, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 },
4624 { 1, Iclass_xt_iclass_wsr_intclear_args,
4625 4, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 },
4626 { 1, Iclass_xt_iclass_rsr_intenable_args,
4627 3, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 },
4628 { 1, Iclass_xt_iclass_wsr_intenable_args,
4629 3, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 },
4630 { 1, Iclass_xt_iclass_xsr_intenable_args,
4631 3, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 },
4632 { 2, Iclass_xt_iclass_break_args,
4633 2, Iclass_xt_iclass_break_stateArgs, 0, 0 },
4634 { 1, Iclass_xt_iclass_break_n_args,
4635 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 },
4636 { 1, Iclass_xt_iclass_rsr_dbreaka0_args,
4637 3, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 },
4638 { 1, Iclass_xt_iclass_wsr_dbreaka0_args,
4639 4, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 },
4640 { 1, Iclass_xt_iclass_xsr_dbreaka0_args,
4641 4, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 },
4642 { 1, Iclass_xt_iclass_rsr_dbreakc0_args,
4643 3, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 },
4644 { 1, Iclass_xt_iclass_wsr_dbreakc0_args,
4645 4, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 },
4646 { 1, Iclass_xt_iclass_xsr_dbreakc0_args,
4647 4, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 },
4648 { 1, Iclass_xt_iclass_rsr_dbreaka1_args,
4649 3, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 },
4650 { 1, Iclass_xt_iclass_wsr_dbreaka1_args,
4651 4, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 },
4652 { 1, Iclass_xt_iclass_xsr_dbreaka1_args,
4653 4, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 },
4654 { 1, Iclass_xt_iclass_rsr_dbreakc1_args,
4655 3, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 },
4656 { 1, Iclass_xt_iclass_wsr_dbreakc1_args,
4657 4, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 },
4658 { 1, Iclass_xt_iclass_xsr_dbreakc1_args,
4659 4, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 },
4660 { 1, Iclass_xt_iclass_rsr_ibreaka0_args,
4661 3, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 },
4662 { 1, Iclass_xt_iclass_wsr_ibreaka0_args,
4663 3, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 },
4664 { 1, Iclass_xt_iclass_xsr_ibreaka0_args,
4665 3, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 },
4666 { 1, Iclass_xt_iclass_rsr_ibreaka1_args,
4667 3, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 },
4668 { 1, Iclass_xt_iclass_wsr_ibreaka1_args,
4669 3, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 },
4670 { 1, Iclass_xt_iclass_xsr_ibreaka1_args,
4671 3, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 },
4672 { 1, Iclass_xt_iclass_rsr_ibreakenable_args,
4673 3, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 },
4674 { 1, Iclass_xt_iclass_wsr_ibreakenable_args,
4675 3, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 },
4676 { 1, Iclass_xt_iclass_xsr_ibreakenable_args,
4677 3, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 },
4678 { 1, Iclass_xt_iclass_rsr_debugcause_args,
4679 4, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 },
4680 { 1, Iclass_xt_iclass_wsr_debugcause_args,
4681 4, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 },
4682 { 1, Iclass_xt_iclass_xsr_debugcause_args,
4683 4, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 },
4684 { 1, Iclass_xt_iclass_rsr_icount_args,
4685 3, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 },
4686 { 1, Iclass_xt_iclass_wsr_icount_args,
4687 4, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 },
4688 { 1, Iclass_xt_iclass_xsr_icount_args,
4689 4, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 },
4690 { 1, Iclass_xt_iclass_rsr_icountlevel_args,
4691 3, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 },
4692 { 1, Iclass_xt_iclass_wsr_icountlevel_args,
4693 3, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 },
4694 { 1, Iclass_xt_iclass_xsr_icountlevel_args,
4695 3, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 },
4696 { 1, Iclass_xt_iclass_rsr_ddr_args,
4697 3, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 },
4698 { 1, Iclass_xt_iclass_wsr_ddr_args,
4699 4, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 },
4700 { 1, Iclass_xt_iclass_xsr_ddr_args,
4701 4, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 },
4702 { 0, 0 /* xt_iclass_rfdo */,
4703 10, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 },
4704 { 0, 0 /* xt_iclass_rfdd */,
4705 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 },
4706 { 1, Iclass_xt_iclass_rsr_ccount_args,
4707 3, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 },
4708 { 1, Iclass_xt_iclass_wsr_ccount_args,
4709 4, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 },
4710 { 1, Iclass_xt_iclass_xsr_ccount_args,
4711 4, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 },
4712 { 1, Iclass_xt_iclass_rsr_ccompare0_args,
4713 3, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 },
4714 { 1, Iclass_xt_iclass_wsr_ccompare0_args,
4715 4, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 },
4716 { 1, Iclass_xt_iclass_xsr_ccompare0_args,
4717 4, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 },
4718 { 1, Iclass_xt_iclass_rsr_ccompare1_args,
4719 3, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 },
4720 { 1, Iclass_xt_iclass_wsr_ccompare1_args,
4721 4, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 },
4722 { 1, Iclass_xt_iclass_xsr_ccompare1_args,
4723 4, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 },
4724 { 1, Iclass_xt_iclass_rsr_ccompare2_args,
4725 3, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 },
4726 { 1, Iclass_xt_iclass_wsr_ccompare2_args,
4727 4, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 },
4728 { 1, Iclass_xt_iclass_xsr_ccompare2_args,
4729 4, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 },
4730 { 2, Iclass_xt_iclass_icache_args,
4731 0, 0, 0, 0 },
4732 { 2, Iclass_xt_iclass_icache_inv_args,
4733 2, Iclass_xt_iclass_icache_inv_stateArgs, 0, 0 },
4734 { 2, Iclass_xt_iclass_licx_args,
4735 2, Iclass_xt_iclass_licx_stateArgs, 0, 0 },
4736 { 2, Iclass_xt_iclass_sicx_args,
4737 2, Iclass_xt_iclass_sicx_stateArgs, 0, 0 },
4738 { 2, Iclass_xt_iclass_dcache_args,
4739 0, 0, 0, 0 },
4740 { 2, Iclass_xt_iclass_dcache_ind_args,
4741 2, Iclass_xt_iclass_dcache_ind_stateArgs, 0, 0 },
4742 { 2, Iclass_xt_iclass_dcache_inv_args,
4743 2, Iclass_xt_iclass_dcache_inv_stateArgs, 0, 0 },
4744 { 2, Iclass_xt_iclass_dpf_args,
4745 0, 0, 0, 0 },
4746 { 2, Iclass_xt_iclass_sdct_args,
4747 2, Iclass_xt_iclass_sdct_stateArgs, 0, 0 },
4748 { 2, Iclass_xt_iclass_ldct_args,
4749 2, Iclass_xt_iclass_ldct_stateArgs, 0, 0 },
4750 { 1, Iclass_xt_iclass_wsr_ptevaddr_args,
4751 4, Iclass_xt_iclass_wsr_ptevaddr_stateArgs, 0, 0 },
4752 { 1, Iclass_xt_iclass_rsr_ptevaddr_args,
4753 4, Iclass_xt_iclass_rsr_ptevaddr_stateArgs, 0, 0 },
4754 { 1, Iclass_xt_iclass_xsr_ptevaddr_args,
4755 5, Iclass_xt_iclass_xsr_ptevaddr_stateArgs, 0, 0 },
4756 { 1, Iclass_xt_iclass_rsr_rasid_args,
4757 5, Iclass_xt_iclass_rsr_rasid_stateArgs, 0, 0 },
4758 { 1, Iclass_xt_iclass_wsr_rasid_args,
4759 6, Iclass_xt_iclass_wsr_rasid_stateArgs, 0, 0 },
4760 { 1, Iclass_xt_iclass_xsr_rasid_args,
4761 6, Iclass_xt_iclass_xsr_rasid_stateArgs, 0, 0 },
4762 { 1, Iclass_xt_iclass_rsr_itlbcfg_args,
4763 3, Iclass_xt_iclass_rsr_itlbcfg_stateArgs, 0, 0 },
4764 { 1, Iclass_xt_iclass_wsr_itlbcfg_args,
4765 4, Iclass_xt_iclass_wsr_itlbcfg_stateArgs, 0, 0 },
4766 { 1, Iclass_xt_iclass_xsr_itlbcfg_args,
4767 4, Iclass_xt_iclass_xsr_itlbcfg_stateArgs, 0, 0 },
4768 { 1, Iclass_xt_iclass_rsr_dtlbcfg_args,
4769 3, Iclass_xt_iclass_rsr_dtlbcfg_stateArgs, 0, 0 },
4770 { 1, Iclass_xt_iclass_wsr_dtlbcfg_args,
4771 4, Iclass_xt_iclass_wsr_dtlbcfg_stateArgs, 0, 0 },
4772 { 1, Iclass_xt_iclass_xsr_dtlbcfg_args,
4773 4, Iclass_xt_iclass_xsr_dtlbcfg_stateArgs, 0, 0 },
4774 { 1, Iclass_xt_iclass_idtlb_args,
4775 3, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 },
4776 { 2, Iclass_xt_iclass_rdtlb_args,
4777 2, Iclass_xt_iclass_rdtlb_stateArgs, 0, 0 },
4778 { 2, Iclass_xt_iclass_wdtlb_args,
4779 3, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 },
4780 { 1, Iclass_xt_iclass_iitlb_args,
4781 2, Iclass_xt_iclass_iitlb_stateArgs, 0, 0 },
4782 { 2, Iclass_xt_iclass_ritlb_args,
4783 2, Iclass_xt_iclass_ritlb_stateArgs, 0, 0 },
4784 { 2, Iclass_xt_iclass_witlb_args,
4785 2, Iclass_xt_iclass_witlb_stateArgs, 0, 0 },
4786 { 0, 0 /* xt_iclass_ldpte */,
4787 2, Iclass_xt_iclass_ldpte_stateArgs, 0, 0 },
4788 { 0, 0 /* xt_iclass_hwwitlba */,
4789 1, Iclass_xt_iclass_hwwitlba_stateArgs, 0, 0 },
4790 { 0, 0 /* xt_iclass_hwwdtlba */,
4791 1, Iclass_xt_iclass_hwwdtlba_stateArgs, 0, 0 },
4792 { 2, Iclass_xt_iclass_nsa_args,
4793 0, 0, 0, 0 }
4794 };
4795
4796
4797 /* Opcode encodings. */
4798
4799 static void
4800 Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf)
4801 {
4802 slotbuf[0] = 0x80200;
4803 }
4804
4805 static void
4806 Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf)
4807 {
4808 slotbuf[0] = 0x300;
4809 }
4810
4811 static void
4812 Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf)
4813 {
4814 slotbuf[0] = 0x2300;
4815 }
4816
4817 static void
4818 Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf)
4819 {
4820 slotbuf[0] = 0x500;
4821 }
4822
4823 static void
4824 Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf)
4825 {
4826 slotbuf[0] = 0x1500;
4827 }
4828
4829 static void
4830 Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf)
4831 {
4832 slotbuf[0] = 0x5c0000;
4833 }
4834
4835 static void
4836 Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf)
4837 {
4838 slotbuf[0] = 0x580000;
4839 }
4840
4841 static void
4842 Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf)
4843 {
4844 slotbuf[0] = 0x540000;
4845 }
4846
4847 static void
4848 Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf)
4849 {
4850 slotbuf[0] = 0xf0000;
4851 }
4852
4853 static void
4854 Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
4855 {
4856 slotbuf[0] = 0xb0000;
4857 }
4858
4859 static void
4860 Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
4861 {
4862 slotbuf[0] = 0x70000;
4863 }
4864
4865 static void
4866 Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf)
4867 {
4868 slotbuf[0] = 0x6c0000;
4869 }
4870
4871 static void
4872 Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf)
4873 {
4874 slotbuf[0] = 0x100;
4875 }
4876
4877 static void
4878 Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf)
4879 {
4880 slotbuf[0] = 0x804;
4881 }
4882
4883 static void
4884 Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf)
4885 {
4886 slotbuf[0] = 0x60000;
4887 }
4888
4889 static void
4890 Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
4891 {
4892 slotbuf[0] = 0xd10f;
4893 }
4894
4895 static void
4896 Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
4897 {
4898 slotbuf[0] = 0x4300;
4899 }
4900
4901 static void
4902 Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf)
4903 {
4904 slotbuf[0] = 0x5300;
4905 }
4906
4907 static void
4908 Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
4909 {
4910 slotbuf[0] = 0x90;
4911 }
4912
4913 static void
4914 Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
4915 {
4916 slotbuf[0] = 0x94;
4917 }
4918
4919 static void
4920 Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
4921 {
4922 slotbuf[0] = 0x4830;
4923 }
4924
4925 static void
4926 Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
4927 {
4928 slotbuf[0] = 0x4831;
4929 }
4930
4931 static void
4932 Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
4933 {
4934 slotbuf[0] = 0x4816;
4935 }
4936
4937 static void
4938 Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
4939 {
4940 slotbuf[0] = 0x4930;
4941 }
4942
4943 static void
4944 Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
4945 {
4946 slotbuf[0] = 0x4931;
4947 }
4948
4949 static void
4950 Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
4951 {
4952 slotbuf[0] = 0x4916;
4953 }
4954
4955 static void
4956 Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
4957 {
4958 slotbuf[0] = 0xa000;
4959 }
4960
4961 static void
4962 Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
4963 {
4964 slotbuf[0] = 0xb000;
4965 }
4966
4967 static void
4968 Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
4969 {
4970 slotbuf[0] = 0xc800;
4971 }
4972
4973 static void
4974 Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
4975 {
4976 slotbuf[0] = 0xcc00;
4977 }
4978
4979 static void
4980 Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
4981 {
4982 slotbuf[0] = 0xd60f;
4983 }
4984
4985 static void
4986 Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
4987 {
4988 slotbuf[0] = 0x8000;
4989 }
4990
4991 static void
4992 Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
4993 {
4994 slotbuf[0] = 0xd000;
4995 }
4996
4997 static void
4998 Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
4999 {
5000 slotbuf[0] = 0xc000;
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