| 1 | /* |
| 2 | * QEMU Xtensa CPU |
| 3 | * |
| 4 | * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. |
| 5 | * Copyright (c) 2012 SUSE LINUX Products GmbH |
| 6 | * All rights reserved. |
| 7 | * |
| 8 | * Redistribution and use in source and binary forms, with or without |
| 9 | * modification, are permitted provided that the following conditions are met: |
| 10 | * * Redistributions of source code must retain the above copyright |
| 11 | * notice, this list of conditions and the following disclaimer. |
| 12 | * * Redistributions in binary form must reproduce the above copyright |
| 13 | * notice, this list of conditions and the following disclaimer in the |
| 14 | * documentation and/or other materials provided with the distribution. |
| 15 | * * Neither the name of the Open Source and Linux Lab nor the |
| 16 | * names of its contributors may be used to endorse or promote products |
| 17 | * derived from this software without specific prior written permission. |
| 18 | * |
| 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 20 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 21 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 22 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY |
| 23 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 24 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 25 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 26 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 27 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 28 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #include "qemu/osdep.h" |
| 32 | #include "qapi/error.h" |
| 33 | #include "exec/cpu-defs.h" |
| 34 | #include "cpu.h" |
| 35 | #include "fpu/softfloat.h" |
| 36 | #include "qemu/module.h" |
| 37 | #include "migration/vmstate.h" |
| 38 | #include "hw/core/qdev-clock.h" |
| 39 | #include "accel/tcg/cpu-ops.h" |
| 40 | #ifndef CONFIG_USER_ONLY |
| 41 | #include "system/memory.h" |
| 42 | #endif |
| 43 | |
| 44 | |
| 45 | static void xtensa_cpu_set_pc(CPUState *cs, vaddr value) |
| 46 | { |
| 47 | XtensaCPU *cpu = XTENSA_CPU(cs); |
| 48 | |
| 49 | cpu->env.pc = value; |
| 50 | } |
| 51 | |
| 52 | static vaddr xtensa_cpu_get_pc(CPUState *cs) |
| 53 | { |
| 54 | XtensaCPU *cpu = XTENSA_CPU(cs); |
| 55 | |
| 56 | return cpu->env.pc; |
| 57 | } |
| 58 | |
| 59 | static TCGTBCPUState xtensa_get_tb_cpu_state(CPUState *cs) |
| 60 | { |
| 61 | CPUXtensaState *env = cpu_env(cs); |
| 62 | uint32_t flags = 0; |
| 63 | uint64_t cs_base = 0; |
| 64 | |
| 65 | flags |= xtensa_get_ring(env); |
| 66 | if (env->sregs[PS] & PS_EXCM) { |
| 67 | flags |= XTENSA_TBFLAG_EXCM; |
| 68 | } else if (xtensa_option_enabled(env->config, XTENSA_OPTION_LOOP)) { |
| 69 | uint64_t lend_dist = |
| 70 | env->sregs[LEND] - (env->pc & -(1u << TARGET_PAGE_BITS)); |
| 71 | |
| 72 | /* |
| 73 | * 0 in the csbase_lend field means that there may not be a loopback |
| 74 | * for any instruction that starts inside this page. Any other value |
| 75 | * means that an instruction that ends at this offset from the page |
| 76 | * start may loop back and will need loopback code to be generated. |
| 77 | * |
| 78 | * lend_dist is 0 when LEND points to the start of the page, but |
| 79 | * no instruction that starts inside this page may end at offset 0, |
| 80 | * so it's still correct. |
| 81 | * |
| 82 | * When an instruction ends at a page boundary it may only start in |
| 83 | * the previous page. lend_dist will be encoded as TARGET_PAGE_SIZE |
| 84 | * for the TB that contains this instruction. |
| 85 | */ |
| 86 | if (lend_dist < (1u << TARGET_PAGE_BITS) + env->config->max_insn_size) { |
| 87 | uint64_t lbeg_off = env->sregs[LEND] - env->sregs[LBEG]; |
| 88 | |
| 89 | cs_base = lend_dist; |
| 90 | if (lbeg_off < 256) { |
| 91 | cs_base |= lbeg_off << XTENSA_CSBASE_LBEG_OFF_SHIFT; |
| 92 | } |
| 93 | } |
| 94 | } |
| 95 | if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) && |
| 96 | (env->sregs[LITBASE] & 1)) { |
| 97 | flags |= XTENSA_TBFLAG_LITBASE; |
| 98 | } |
| 99 | if (xtensa_option_enabled(env->config, XTENSA_OPTION_DEBUG)) { |
| 100 | if (xtensa_get_cintlevel(env) < env->config->debug_level) { |
| 101 | flags |= XTENSA_TBFLAG_DEBUG; |
| 102 | } |
| 103 | if (xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) { |
| 104 | flags |= XTENSA_TBFLAG_ICOUNT; |
| 105 | } |
| 106 | } |
| 107 | if (xtensa_option_enabled(env->config, XTENSA_OPTION_COPROCESSOR)) { |
| 108 | flags |= env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT; |
| 109 | } |
| 110 | if (xtensa_option_enabled(env->config, XTENSA_OPTION_WINDOWED_REGISTER) && |
| 111 | (env->sregs[PS] & (PS_WOE | PS_EXCM)) == PS_WOE) { |
| 112 | uint32_t windowstart = xtensa_replicate_windowstart(env) >> |
| 113 | (env->sregs[WINDOW_BASE] + 1); |
| 114 | uint32_t w = ctz32(windowstart | 0x8); |
| 115 | |
| 116 | flags |= (w << XTENSA_TBFLAG_WINDOW_SHIFT) | XTENSA_TBFLAG_CWOE; |
| 117 | flags |= extract32(env->sregs[PS], PS_CALLINC_SHIFT, |
| 118 | PS_CALLINC_LEN) << XTENSA_TBFLAG_CALLINC_SHIFT; |
| 119 | } else { |
| 120 | flags |= 3 << XTENSA_TBFLAG_WINDOW_SHIFT; |
| 121 | } |
| 122 | if (env->yield_needed) { |
| 123 | flags |= XTENSA_TBFLAG_YIELD; |
| 124 | } |
| 125 | |
| 126 | return (TCGTBCPUState){ |
| 127 | .pc = env->pc, |
| 128 | .flags = flags, |
| 129 | .cs_base = cs_base, |
| 130 | }; |
| 131 | } |
| 132 | |
| 133 | static void xtensa_restore_state_to_opc(CPUState *cs, |
| 134 | const TranslationBlock *tb, |
| 135 | const uint64_t *data) |
| 136 | { |
| 137 | XtensaCPU *cpu = XTENSA_CPU(cs); |
| 138 | |
| 139 | cpu->env.pc = data[0]; |
| 140 | } |
| 141 | |
| 142 | #ifndef CONFIG_USER_ONLY |
| 143 | static bool xtensa_cpu_has_work(CPUState *cs) |
| 144 | { |
| 145 | CPUXtensaState *env = cpu_env(cs); |
| 146 | |
| 147 | return !env->runstall && env->pending_irq_level; |
| 148 | } |
| 149 | #endif /* !CONFIG_USER_ONLY */ |
| 150 | |
| 151 | static int xtensa_cpu_mmu_index(CPUState *cs, bool ifetch) |
| 152 | { |
| 153 | return xtensa_get_cring(cpu_env(cs)); |
| 154 | } |
| 155 | |
| 156 | #ifdef CONFIG_USER_ONLY |
| 157 | static bool abi_call0; |
| 158 | |
| 159 | void xtensa_set_abi_call0(void) |
| 160 | { |
| 161 | abi_call0 = true; |
| 162 | } |
| 163 | |
| 164 | bool xtensa_abi_call0(void) |
| 165 | { |
| 166 | return abi_call0; |
| 167 | } |
| 168 | #endif |
| 169 | |
| 170 | static void xtensa_cpu_reset_hold(Object *obj, ResetType type) |
| 171 | { |
| 172 | CPUState *cs = CPU(obj); |
| 173 | XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(obj); |
| 174 | CPUXtensaState *env = cpu_env(cs); |
| 175 | bool dfpu = xtensa_option_enabled(env->config, |
| 176 | XTENSA_OPTION_DFP_COPROCESSOR); |
| 177 | |
| 178 | if (xcc->parent_phases.hold) { |
| 179 | xcc->parent_phases.hold(obj, type); |
| 180 | } |
| 181 | |
| 182 | env->pc = env->config->exception_vector[EXC_RESET0 + env->static_vectors]; |
| 183 | env->sregs[LITBASE] &= ~1; |
| 184 | #ifndef CONFIG_USER_ONLY |
| 185 | env->sregs[PS] = xtensa_option_enabled(env->config, |
| 186 | XTENSA_OPTION_INTERRUPT) ? 0x1f : 0x10; |
| 187 | env->pending_irq_level = 0; |
| 188 | #else |
| 189 | env->sregs[PS] = PS_UM | (3 << PS_RING_SHIFT); |
| 190 | if (xtensa_option_enabled(env->config, |
| 191 | XTENSA_OPTION_WINDOWED_REGISTER) && |
| 192 | !xtensa_abi_call0()) { |
| 193 | env->sregs[PS] |= PS_WOE; |
| 194 | } |
| 195 | env->sregs[CPENABLE] = 0xff; |
| 196 | #endif |
| 197 | env->sregs[VECBASE] = env->config->vecbase; |
| 198 | env->sregs[IBREAKENABLE] = 0; |
| 199 | env->sregs[MEMCTL] = MEMCTL_IL0EN & env->config->memctl_mask; |
| 200 | env->sregs[ATOMCTL] = xtensa_option_enabled(env->config, |
| 201 | XTENSA_OPTION_ATOMCTL) ? 0x28 : 0x15; |
| 202 | env->sregs[CONFIGID0] = env->config->configid[0]; |
| 203 | env->sregs[CONFIGID1] = env->config->configid[1]; |
| 204 | env->exclusive_addr = -1; |
| 205 | |
| 206 | #ifndef CONFIG_USER_ONLY |
| 207 | reset_mmu(env); |
| 208 | cs->halted = env->runstall; |
| 209 | #endif |
| 210 | /* For inf * 0 + NaN, return the input NaN */ |
| 211 | set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); |
| 212 | set_snan_rule(dfpu ? float_snan_bit_is_zero : float_snan_never, |
| 213 | &env->fp_status); |
| 214 | /* Default NaN value: sign bit clear, set frac msb */ |
| 215 | set_float_default_nan_pattern(0b01000000, &env->fp_status); |
| 216 | xtensa_use_first_nan(env, !dfpu); |
| 217 | } |
| 218 | |
| 219 | static ObjectClass *xtensa_cpu_class_by_name(const char *cpu_model) |
| 220 | { |
| 221 | ObjectClass *oc; |
| 222 | char *typename; |
| 223 | |
| 224 | typename = g_strdup_printf(XTENSA_CPU_TYPE_NAME("%s"), cpu_model); |
| 225 | oc = object_class_by_name(typename); |
| 226 | g_free(typename); |
| 227 | |
| 228 | return oc; |
| 229 | } |
| 230 | |
| 231 | static void xtensa_cpu_disas_set_info(const CPUState *cs, |
| 232 | disassemble_info *info) |
| 233 | { |
| 234 | XtensaCPU *cpu = XTENSA_CPU(cs); |
| 235 | |
| 236 | info->private_data = cpu->env.config->isa; |
| 237 | info->print_insn = print_insn_xtensa; |
| 238 | info->endian = TARGET_BIG_ENDIAN ? BFD_ENDIAN_BIG |
| 239 | : BFD_ENDIAN_LITTLE; |
| 240 | } |
| 241 | |
| 242 | static void xtensa_cpu_realizefn(DeviceState *dev, Error **errp) |
| 243 | { |
| 244 | CPUState *cs = CPU(dev); |
| 245 | XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(dev); |
| 246 | Error *local_err = NULL; |
| 247 | |
| 248 | #ifndef CONFIG_USER_ONLY |
| 249 | CPUXtensaState *env = &XTENSA_CPU(dev)->env; |
| 250 | |
| 251 | env->address_space_er = g_malloc(sizeof(*env->address_space_er)); |
| 252 | env->system_er = g_malloc(sizeof(*env->system_er)); |
| 253 | memory_region_init_io(env->system_er, OBJECT(dev), NULL, env, "er", |
| 254 | UINT64_C(0x100000000)); |
| 255 | address_space_init(env->address_space_er, env->system_er, "ER"); |
| 256 | |
| 257 | xtensa_irq_init(&XTENSA_CPU(dev)->env); |
| 258 | #endif |
| 259 | |
| 260 | cpu_common_realize(cs, &local_err); |
| 261 | if (local_err != NULL) { |
| 262 | error_propagate(errp, local_err); |
| 263 | return; |
| 264 | } |
| 265 | |
| 266 | cs->gdb_num_regs = xcc->config->gdb_regmap.num_regs; |
| 267 | |
| 268 | qemu_init_vcpu(cs); |
| 269 | |
| 270 | xcc->parent_realize(dev, errp); |
| 271 | } |
| 272 | |
| 273 | static void xtensa_cpu_initfn(Object *obj) |
| 274 | { |
| 275 | XtensaCPU *cpu = XTENSA_CPU(obj); |
| 276 | XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(obj); |
| 277 | CPUXtensaState *env = &cpu->env; |
| 278 | |
| 279 | env->config = xcc->config; |
| 280 | |
| 281 | #ifndef CONFIG_USER_ONLY |
| 282 | cpu->clock = qdev_init_clock_in(DEVICE(obj), "clk-in", NULL, cpu, 0); |
| 283 | clock_set_hz(cpu->clock, env->config->clock_freq_khz * 1000); |
| 284 | #endif |
| 285 | } |
| 286 | |
| 287 | XtensaCPU *xtensa_cpu_create_with_clock(const char *cpu_type, Clock *cpu_refclk) |
| 288 | { |
| 289 | DeviceState *cpu; |
| 290 | |
| 291 | cpu = qdev_new(cpu_type); |
| 292 | qdev_connect_clock_in(cpu, "clk-in", cpu_refclk); |
| 293 | qdev_realize(cpu, NULL, &error_abort); |
| 294 | |
| 295 | return XTENSA_CPU(cpu); |
| 296 | } |
| 297 | |
| 298 | #ifndef CONFIG_USER_ONLY |
| 299 | static const VMStateDescription vmstate_xtensa_cpu = { |
| 300 | .name = "cpu", |
| 301 | .unmigratable = 1, |
| 302 | }; |
| 303 | |
| 304 | #include "hw/core/sysemu-cpu-ops.h" |
| 305 | |
| 306 | static const struct SysemuCPUOps xtensa_sysemu_ops = { |
| 307 | .has_work = xtensa_cpu_has_work, |
| 308 | .get_phys_addr_debug = xtensa_cpu_get_phys_addr_debug, |
| 309 | }; |
| 310 | #endif |
| 311 | |
| 312 | static const TCGCPUOps xtensa_tcg_ops = { |
| 313 | /* Xtensa processors have a weak memory model */ |
| 314 | .guest_default_memory_order = 0, |
| 315 | .mttcg_supported = true, |
| 316 | |
| 317 | .initialize = xtensa_translate_init, |
| 318 | .translate_code = xtensa_translate_code, |
| 319 | .debug_excp_handler = xtensa_breakpoint_handler, |
| 320 | .get_tb_cpu_state = xtensa_get_tb_cpu_state, |
| 321 | .restore_state_to_opc = xtensa_restore_state_to_opc, |
| 322 | .mmu_index = xtensa_cpu_mmu_index, |
| 323 | |
| 324 | #ifndef CONFIG_USER_ONLY |
| 325 | .tlb_fill = xtensa_cpu_tlb_fill, |
| 326 | .pointer_wrap = cpu_pointer_wrap_uint32, |
| 327 | .cpu_exec_interrupt = xtensa_cpu_exec_interrupt, |
| 328 | .cpu_exec_halt = xtensa_cpu_has_work, |
| 329 | .cpu_exec_reset = cpu_reset, |
| 330 | .do_interrupt = xtensa_cpu_do_interrupt, |
| 331 | .do_transaction_failed = xtensa_cpu_do_transaction_failed, |
| 332 | .do_unaligned_access = xtensa_cpu_do_unaligned_access, |
| 333 | .debug_check_breakpoint = xtensa_debug_check_breakpoint, |
| 334 | #endif /* !CONFIG_USER_ONLY */ |
| 335 | }; |
| 336 | |
| 337 | static void xtensa_cpu_class_init(ObjectClass *oc, const void *data) |
| 338 | { |
| 339 | DeviceClass *dc = DEVICE_CLASS(oc); |
| 340 | CPUClass *cc = CPU_CLASS(oc); |
| 341 | XtensaCPUClass *xcc = XTENSA_CPU_CLASS(cc); |
| 342 | ResettableClass *rc = RESETTABLE_CLASS(oc); |
| 343 | |
| 344 | device_class_set_parent_realize(dc, xtensa_cpu_realizefn, |
| 345 | &xcc->parent_realize); |
| 346 | |
| 347 | resettable_class_set_parent_phases(rc, NULL, xtensa_cpu_reset_hold, NULL, |
| 348 | &xcc->parent_phases); |
| 349 | |
| 350 | cc->class_by_name = xtensa_cpu_class_by_name; |
| 351 | cc->dump_state = xtensa_cpu_dump_state; |
| 352 | cc->set_pc = xtensa_cpu_set_pc; |
| 353 | cc->get_pc = xtensa_cpu_get_pc; |
| 354 | cc->gdb_read_register = xtensa_cpu_gdb_read_register; |
| 355 | cc->gdb_write_register = xtensa_cpu_gdb_write_register; |
| 356 | cc->gdb_stop_before_watchpoint = true; |
| 357 | #ifndef CONFIG_USER_ONLY |
| 358 | cc->sysemu_ops = &xtensa_sysemu_ops; |
| 359 | dc->vmsd = &vmstate_xtensa_cpu; |
| 360 | #endif |
| 361 | cc->disas_set_info = xtensa_cpu_disas_set_info; |
| 362 | cc->tcg_ops = &xtensa_tcg_ops; |
| 363 | } |
| 364 | |
| 365 | static const TypeInfo xtensa_cpu_type_info = { |
| 366 | .name = TYPE_XTENSA_CPU, |
| 367 | .parent = TYPE_CPU, |
| 368 | .instance_size = sizeof(XtensaCPU), |
| 369 | .instance_align = __alignof(XtensaCPU), |
| 370 | .instance_init = xtensa_cpu_initfn, |
| 371 | .abstract = true, |
| 372 | .class_size = sizeof(XtensaCPUClass), |
| 373 | .class_init = xtensa_cpu_class_init, |
| 374 | }; |
| 375 | |
| 376 | static void xtensa_cpu_register_types(void) |
| 377 | { |
| 378 | type_register_static(&xtensa_cpu_type_info); |
| 379 | } |
| 380 | |
| 381 | type_init(xtensa_cpu_register_types) |