| 1 | /* |
| 2 | * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. |
| 3 | * All rights reserved. |
| 4 | * |
| 5 | * Redistribution and use in source and binary forms, with or without |
| 6 | * modification, are permitted provided that the following conditions are met: |
| 7 | * * Redistributions of source code must retain the above copyright |
| 8 | * notice, this list of conditions and the following disclaimer. |
| 9 | * * Redistributions in binary form must reproduce the above copyright |
| 10 | * notice, this list of conditions and the following disclaimer in the |
| 11 | * documentation and/or other materials provided with the distribution. |
| 12 | * * Neither the name of the Open Source and Linux Lab nor the |
| 13 | * names of its contributors may be used to endorse or promote products |
| 14 | * derived from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 17 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 18 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY |
| 20 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 21 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 22 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 23 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 24 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 25 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 26 | */ |
| 27 | |
| 28 | #ifndef XTENSA_CPU_H |
| 29 | #define XTENSA_CPU_H |
| 30 | |
| 31 | #include "cpu-qom.h" |
| 32 | #include "qemu/cpu-float.h" |
| 33 | #include "exec/cpu-common.h" |
| 34 | #include "exec/cpu-interrupt.h" |
| 35 | #include "hw/core/clock.h" |
| 36 | #include "xtensa-isa.h" |
| 37 | |
| 38 | enum { |
| 39 | /* Additional instructions */ |
| 40 | XTENSA_OPTION_CODE_DENSITY, |
| 41 | XTENSA_OPTION_LOOP, |
| 42 | XTENSA_OPTION_EXTENDED_L32R, |
| 43 | XTENSA_OPTION_16_BIT_IMUL, |
| 44 | XTENSA_OPTION_32_BIT_IMUL, |
| 45 | XTENSA_OPTION_32_BIT_IMUL_HIGH, |
| 46 | XTENSA_OPTION_32_BIT_IDIV, |
| 47 | XTENSA_OPTION_MAC16, |
| 48 | XTENSA_OPTION_MISC_OP_NSA, |
| 49 | XTENSA_OPTION_MISC_OP_MINMAX, |
| 50 | XTENSA_OPTION_MISC_OP_SEXT, |
| 51 | XTENSA_OPTION_MISC_OP_CLAMPS, |
| 52 | XTENSA_OPTION_COPROCESSOR, |
| 53 | XTENSA_OPTION_BOOLEAN, |
| 54 | XTENSA_OPTION_FP_COPROCESSOR, |
| 55 | XTENSA_OPTION_DFP_COPROCESSOR, |
| 56 | XTENSA_OPTION_DFPU_SINGLE_ONLY, |
| 57 | XTENSA_OPTION_MP_SYNCHRO, |
| 58 | XTENSA_OPTION_CONDITIONAL_STORE, |
| 59 | XTENSA_OPTION_ATOMCTL, |
| 60 | XTENSA_OPTION_DEPBITS, |
| 61 | |
| 62 | /* Interrupts and exceptions */ |
| 63 | XTENSA_OPTION_EXCEPTION, |
| 64 | XTENSA_OPTION_RELOCATABLE_VECTOR, |
| 65 | XTENSA_OPTION_UNALIGNED_EXCEPTION, |
| 66 | XTENSA_OPTION_INTERRUPT, |
| 67 | XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, |
| 68 | XTENSA_OPTION_TIMER_INTERRUPT, |
| 69 | |
| 70 | /* Local memory */ |
| 71 | XTENSA_OPTION_ICACHE, |
| 72 | XTENSA_OPTION_ICACHE_TEST, |
| 73 | XTENSA_OPTION_ICACHE_INDEX_LOCK, |
| 74 | XTENSA_OPTION_DCACHE, |
| 75 | XTENSA_OPTION_DCACHE_TEST, |
| 76 | XTENSA_OPTION_DCACHE_INDEX_LOCK, |
| 77 | XTENSA_OPTION_IRAM, |
| 78 | XTENSA_OPTION_IROM, |
| 79 | XTENSA_OPTION_DRAM, |
| 80 | XTENSA_OPTION_DROM, |
| 81 | XTENSA_OPTION_XLMI, |
| 82 | XTENSA_OPTION_HW_ALIGNMENT, |
| 83 | XTENSA_OPTION_MEMORY_ECC_PARITY, |
| 84 | |
| 85 | /* Memory protection and translation */ |
| 86 | XTENSA_OPTION_REGION_PROTECTION, |
| 87 | XTENSA_OPTION_REGION_TRANSLATION, |
| 88 | XTENSA_OPTION_MPU, |
| 89 | XTENSA_OPTION_MMU, |
| 90 | XTENSA_OPTION_CACHEATTR, |
| 91 | |
| 92 | /* Other */ |
| 93 | XTENSA_OPTION_WINDOWED_REGISTER, |
| 94 | XTENSA_OPTION_PROCESSOR_INTERFACE, |
| 95 | XTENSA_OPTION_MISC_SR, |
| 96 | XTENSA_OPTION_THREAD_POINTER, |
| 97 | XTENSA_OPTION_PROCESSOR_ID, |
| 98 | XTENSA_OPTION_DEBUG, |
| 99 | XTENSA_OPTION_TRACE_PORT, |
| 100 | XTENSA_OPTION_EXTERN_REGS, |
| 101 | }; |
| 102 | |
| 103 | enum { |
| 104 | EXPSTATE = 230, |
| 105 | THREADPTR = 231, |
| 106 | FCR = 232, |
| 107 | FSR = 233, |
| 108 | }; |
| 109 | |
| 110 | enum { |
| 111 | LBEG = 0, |
| 112 | LEND = 1, |
| 113 | LCOUNT = 2, |
| 114 | SAR = 3, |
| 115 | BR = 4, |
| 116 | LITBASE = 5, |
| 117 | SCOMPARE1 = 12, |
| 118 | ACCLO = 16, |
| 119 | ACCHI = 17, |
| 120 | MR = 32, |
| 121 | PREFCTL = 40, |
| 122 | WINDOW_BASE = 72, |
| 123 | WINDOW_START = 73, |
| 124 | PTEVADDR = 83, |
| 125 | MMID = 89, |
| 126 | RASID = 90, |
| 127 | MPUENB = 90, |
| 128 | ITLBCFG = 91, |
| 129 | DTLBCFG = 92, |
| 130 | MPUCFG = 92, |
| 131 | ERACCESS = 95, |
| 132 | IBREAKENABLE = 96, |
| 133 | MEMCTL = 97, |
| 134 | CACHEATTR = 98, |
| 135 | CACHEADRDIS = 98, |
| 136 | ATOMCTL = 99, |
| 137 | DDR = 104, |
| 138 | MEPC = 106, |
| 139 | MEPS = 107, |
| 140 | MESAVE = 108, |
| 141 | MESR = 109, |
| 142 | MECR = 110, |
| 143 | MEVADDR = 111, |
| 144 | IBREAKA = 128, |
| 145 | DBREAKA = 144, |
| 146 | DBREAKC = 160, |
| 147 | CONFIGID0 = 176, |
| 148 | EPC1 = 177, |
| 149 | DEPC = 192, |
| 150 | EPS2 = 194, |
| 151 | CONFIGID1 = 208, |
| 152 | EXCSAVE1 = 209, |
| 153 | CPENABLE = 224, |
| 154 | INTSET = 226, |
| 155 | INTCLEAR = 227, |
| 156 | INTENABLE = 228, |
| 157 | PS = 230, |
| 158 | VECBASE = 231, |
| 159 | EXCCAUSE = 232, |
| 160 | DEBUGCAUSE = 233, |
| 161 | CCOUNT = 234, |
| 162 | PRID = 235, |
| 163 | ICOUNT = 236, |
| 164 | ICOUNTLEVEL = 237, |
| 165 | EXCVADDR = 238, |
| 166 | CCOMPARE = 240, |
| 167 | MISC = 244, |
| 168 | }; |
| 169 | |
| 170 | #define PS_INTLEVEL 0xf |
| 171 | #define PS_INTLEVEL_SHIFT 0 |
| 172 | |
| 173 | #define PS_EXCM 0x10 |
| 174 | #define PS_UM 0x20 |
| 175 | |
| 176 | #define PS_RING 0xc0 |
| 177 | #define PS_RING_SHIFT 6 |
| 178 | |
| 179 | #define PS_OWB 0xf00 |
| 180 | #define PS_OWB_SHIFT 8 |
| 181 | #define PS_OWB_LEN 4 |
| 182 | |
| 183 | #define PS_CALLINC 0x30000 |
| 184 | #define PS_CALLINC_SHIFT 16 |
| 185 | #define PS_CALLINC_LEN 2 |
| 186 | |
| 187 | #define PS_WOE 0x40000 |
| 188 | |
| 189 | #define DEBUGCAUSE_IC 0x1 |
| 190 | #define DEBUGCAUSE_IB 0x2 |
| 191 | #define DEBUGCAUSE_DB 0x4 |
| 192 | #define DEBUGCAUSE_BI 0x8 |
| 193 | #define DEBUGCAUSE_BN 0x10 |
| 194 | #define DEBUGCAUSE_DI 0x20 |
| 195 | #define DEBUGCAUSE_DBNUM 0xf00 |
| 196 | #define DEBUGCAUSE_DBNUM_SHIFT 8 |
| 197 | |
| 198 | #define DBREAKC_SB 0x80000000 |
| 199 | #define DBREAKC_LB 0x40000000 |
| 200 | #define DBREAKC_SB_LB (DBREAKC_SB | DBREAKC_LB) |
| 201 | #define DBREAKC_MASK 0x3f |
| 202 | |
| 203 | #define MEMCTL_INIT 0x00800000 |
| 204 | #define MEMCTL_IUSEWAYS_SHIFT 18 |
| 205 | #define MEMCTL_IUSEWAYS_LEN 5 |
| 206 | #define MEMCTL_IUSEWAYS_MASK 0x007c0000 |
| 207 | #define MEMCTL_DALLOCWAYS_SHIFT 13 |
| 208 | #define MEMCTL_DALLOCWAYS_LEN 5 |
| 209 | #define MEMCTL_DALLOCWAYS_MASK 0x0003e000 |
| 210 | #define MEMCTL_DUSEWAYS_SHIFT 8 |
| 211 | #define MEMCTL_DUSEWAYS_LEN 5 |
| 212 | #define MEMCTL_DUSEWAYS_MASK 0x00001f00 |
| 213 | #define MEMCTL_ISNP 0x4 |
| 214 | #define MEMCTL_DSNP 0x2 |
| 215 | #define MEMCTL_IL0EN 0x1 |
| 216 | |
| 217 | #define MAX_INSN_LENGTH 64 |
| 218 | #define MAX_INSNBUF_LENGTH \ |
| 219 | ((MAX_INSN_LENGTH + sizeof(xtensa_insnbuf_word) - 1) / \ |
| 220 | sizeof(xtensa_insnbuf_word)) |
| 221 | #define MAX_INSN_SLOTS 32 |
| 222 | #define MAX_OPCODE_ARGS 16 |
| 223 | #define MAX_NAREG 64 |
| 224 | #define MAX_NINTERRUPT 32 |
| 225 | #define MAX_NLEVEL 6 |
| 226 | #define MAX_NNMI 1 |
| 227 | #define MAX_NCCOMPARE 3 |
| 228 | #define MAX_TLB_WAY_SIZE 8 |
| 229 | #define MAX_NDBREAK 2 |
| 230 | #define MAX_NIBREAK 2 |
| 231 | #define MAX_NMEMORY 4 |
| 232 | #define MAX_MPU_FOREGROUND_SEGMENTS 32 |
| 233 | |
| 234 | #define REGION_PAGE_MASK 0xe0000000 |
| 235 | |
| 236 | #define PAGE_CACHE_MASK 0x700 |
| 237 | #define PAGE_CACHE_SHIFT 8 |
| 238 | #define PAGE_CACHE_INVALID 0x000 |
| 239 | #define PAGE_CACHE_BYPASS 0x100 |
| 240 | #define PAGE_CACHE_WT 0x200 |
| 241 | #define PAGE_CACHE_WB 0x400 |
| 242 | #define PAGE_CACHE_ISOLATE 0x600 |
| 243 | |
| 244 | enum { |
| 245 | /* Static vectors */ |
| 246 | EXC_RESET0, |
| 247 | EXC_RESET1, |
| 248 | EXC_MEMORY_ERROR, |
| 249 | |
| 250 | /* Dynamic vectors */ |
| 251 | EXC_WINDOW_OVERFLOW4, |
| 252 | EXC_WINDOW_UNDERFLOW4, |
| 253 | EXC_WINDOW_OVERFLOW8, |
| 254 | EXC_WINDOW_UNDERFLOW8, |
| 255 | EXC_WINDOW_OVERFLOW12, |
| 256 | EXC_WINDOW_UNDERFLOW12, |
| 257 | EXC_IRQ, |
| 258 | EXC_KERNEL, |
| 259 | EXC_USER, |
| 260 | EXC_DOUBLE, |
| 261 | EXC_DEBUG, |
| 262 | EXC_MAX |
| 263 | }; |
| 264 | |
| 265 | enum { |
| 266 | ILLEGAL_INSTRUCTION_CAUSE = 0, |
| 267 | SYSCALL_CAUSE, |
| 268 | INSTRUCTION_FETCH_ERROR_CAUSE, |
| 269 | LOAD_STORE_ERROR_CAUSE, |
| 270 | LEVEL1_INTERRUPT_CAUSE, |
| 271 | ALLOCA_CAUSE, |
| 272 | INTEGER_DIVIDE_BY_ZERO_CAUSE, |
| 273 | PC_VALUE_ERROR_CAUSE, |
| 274 | PRIVILEGED_CAUSE, |
| 275 | LOAD_STORE_ALIGNMENT_CAUSE, |
| 276 | EXTERNAL_REG_PRIVILEGE_CAUSE, |
| 277 | EXCLUSIVE_ERROR_CAUSE, |
| 278 | INSTR_PIF_DATA_ERROR_CAUSE, |
| 279 | LOAD_STORE_PIF_DATA_ERROR_CAUSE, |
| 280 | INSTR_PIF_ADDR_ERROR_CAUSE, |
| 281 | LOAD_STORE_PIF_ADDR_ERROR_CAUSE, |
| 282 | INST_TLB_MISS_CAUSE, |
| 283 | INST_TLB_MULTI_HIT_CAUSE, |
| 284 | INST_FETCH_PRIVILEGE_CAUSE, |
| 285 | INST_FETCH_PROHIBITED_CAUSE = 20, |
| 286 | LOAD_STORE_TLB_MISS_CAUSE = 24, |
| 287 | LOAD_STORE_TLB_MULTI_HIT_CAUSE, |
| 288 | LOAD_STORE_PRIVILEGE_CAUSE, |
| 289 | LOAD_PROHIBITED_CAUSE = 28, |
| 290 | STORE_PROHIBITED_CAUSE, |
| 291 | |
| 292 | COPROCESSOR0_DISABLED = 32, |
| 293 | }; |
| 294 | |
| 295 | typedef enum { |
| 296 | INTTYPE_LEVEL, |
| 297 | INTTYPE_EDGE, |
| 298 | INTTYPE_NMI, |
| 299 | INTTYPE_SOFTWARE, |
| 300 | INTTYPE_TIMER, |
| 301 | INTTYPE_DEBUG, |
| 302 | INTTYPE_WRITE_ERR, |
| 303 | INTTYPE_PROFILING, |
| 304 | INTTYPE_IDMA_DONE, |
| 305 | INTTYPE_IDMA_ERR, |
| 306 | INTTYPE_GS_ERR, |
| 307 | INTTYPE_MAX |
| 308 | } interrupt_type; |
| 309 | |
| 310 | typedef struct CPUArchState CPUXtensaState; |
| 311 | |
| 312 | typedef struct xtensa_tlb_entry { |
| 313 | uint32_t vaddr; |
| 314 | uint32_t paddr; |
| 315 | uint8_t asid; |
| 316 | uint8_t attr; |
| 317 | bool variable; |
| 318 | } xtensa_tlb_entry; |
| 319 | |
| 320 | typedef struct xtensa_tlb { |
| 321 | unsigned nways; |
| 322 | const unsigned way_size[10]; |
| 323 | bool varway56; |
| 324 | unsigned nrefillentries; |
| 325 | } xtensa_tlb; |
| 326 | |
| 327 | typedef struct xtensa_mpu_entry { |
| 328 | uint32_t vaddr; |
| 329 | uint32_t attr; |
| 330 | } xtensa_mpu_entry; |
| 331 | |
| 332 | typedef struct XtensaGdbReg { |
| 333 | int targno; |
| 334 | unsigned flags; |
| 335 | int type; |
| 336 | int group; |
| 337 | unsigned size; |
| 338 | } XtensaGdbReg; |
| 339 | |
| 340 | typedef struct XtensaGdbRegmap { |
| 341 | int num_regs; |
| 342 | int num_core_regs; |
| 343 | /* PC + a + ar + sr + ur */ |
| 344 | XtensaGdbReg reg[1 + 16 + 64 + 256 + 256]; |
| 345 | } XtensaGdbRegmap; |
| 346 | |
| 347 | typedef struct XtensaCcompareTimer { |
| 348 | CPUXtensaState *env; |
| 349 | QEMUTimer *timer; |
| 350 | } XtensaCcompareTimer; |
| 351 | |
| 352 | typedef struct XtensaMemory { |
| 353 | unsigned num; |
| 354 | struct XtensaMemoryRegion { |
| 355 | uint32_t addr; |
| 356 | uint32_t size; |
| 357 | } location[MAX_NMEMORY]; |
| 358 | } XtensaMemory; |
| 359 | |
| 360 | typedef struct opcode_arg { |
| 361 | uint32_t imm; |
| 362 | uint32_t raw_imm; |
| 363 | void *in; |
| 364 | void *out; |
| 365 | uint32_t num_bits; |
| 366 | } OpcodeArg; |
| 367 | |
| 368 | typedef struct DisasContext DisasContext; |
| 369 | typedef void (*XtensaOpcodeOp)(DisasContext *dc, const OpcodeArg arg[], |
| 370 | const uint32_t par[]); |
| 371 | typedef uint32_t (*XtensaOpcodeUintTest)(DisasContext *dc, |
| 372 | const OpcodeArg arg[], |
| 373 | const uint32_t par[]); |
| 374 | |
| 375 | enum { |
| 376 | XTENSA_OP_ILL = 0x1, |
| 377 | XTENSA_OP_PRIVILEGED = 0x2, |
| 378 | XTENSA_OP_SYSCALL = 0x4, |
| 379 | XTENSA_OP_DEBUG_BREAK = 0x8, |
| 380 | |
| 381 | XTENSA_OP_OVERFLOW = 0x10, |
| 382 | XTENSA_OP_UNDERFLOW = 0x20, |
| 383 | XTENSA_OP_ALLOCA = 0x40, |
| 384 | XTENSA_OP_COPROCESSOR = 0x80, |
| 385 | |
| 386 | XTENSA_OP_DIVIDE_BY_ZERO = 0x100, |
| 387 | |
| 388 | /* Postprocessing flags */ |
| 389 | XTENSA_OP_CHECK_INTERRUPTS = 0x200, |
| 390 | XTENSA_OP_EXIT_TB_M1 = 0x400, |
| 391 | XTENSA_OP_EXIT_TB_0 = 0x800, |
| 392 | XTENSA_OP_SYNC_REGISTER_WINDOW = 0x1000, |
| 393 | |
| 394 | XTENSA_OP_POSTPROCESS = |
| 395 | XTENSA_OP_CHECK_INTERRUPTS | |
| 396 | XTENSA_OP_EXIT_TB_M1 | |
| 397 | XTENSA_OP_EXIT_TB_0 | |
| 398 | XTENSA_OP_SYNC_REGISTER_WINDOW, |
| 399 | |
| 400 | XTENSA_OP_NAME_ARRAY = 0x8000, |
| 401 | |
| 402 | XTENSA_OP_CONTROL_FLOW = 0x10000, |
| 403 | XTENSA_OP_STORE = 0x20000, |
| 404 | XTENSA_OP_LOAD = 0x40000, |
| 405 | XTENSA_OP_LOAD_STORE = |
| 406 | XTENSA_OP_LOAD | XTENSA_OP_STORE, |
| 407 | }; |
| 408 | |
| 409 | typedef struct XtensaOpcodeOps { |
| 410 | const void *name; |
| 411 | XtensaOpcodeOp translate; |
| 412 | XtensaOpcodeUintTest test_exceptions; |
| 413 | XtensaOpcodeUintTest test_overflow; |
| 414 | const uint32_t *par; |
| 415 | uint32_t op_flags; |
| 416 | uint32_t coprocessor; |
| 417 | } XtensaOpcodeOps; |
| 418 | |
| 419 | typedef struct XtensaOpcodeTranslators { |
| 420 | unsigned num_opcodes; |
| 421 | const XtensaOpcodeOps *opcode; |
| 422 | } XtensaOpcodeTranslators; |
| 423 | |
| 424 | extern const XtensaOpcodeTranslators xtensa_core_opcodes; |
| 425 | extern const XtensaOpcodeTranslators xtensa_fpu2000_opcodes; |
| 426 | extern const XtensaOpcodeTranslators xtensa_fpu_opcodes; |
| 427 | |
| 428 | typedef struct XtensaConfig { |
| 429 | const char *name; |
| 430 | uint64_t options; |
| 431 | XtensaGdbRegmap gdb_regmap; |
| 432 | unsigned nareg; |
| 433 | int excm_level; |
| 434 | int ndepc; |
| 435 | unsigned inst_fetch_width; |
| 436 | unsigned max_insn_size; |
| 437 | uint32_t vecbase; |
| 438 | uint32_t exception_vector[EXC_MAX]; |
| 439 | unsigned ninterrupt; |
| 440 | unsigned nlevel; |
| 441 | unsigned nmi_level; |
| 442 | uint32_t interrupt_vector[MAX_NLEVEL + MAX_NNMI + 1]; |
| 443 | uint32_t level_mask[MAX_NLEVEL + MAX_NNMI + 1]; |
| 444 | uint32_t inttype_mask[INTTYPE_MAX]; |
| 445 | struct { |
| 446 | uint32_t level; |
| 447 | interrupt_type inttype; |
| 448 | } interrupt[MAX_NINTERRUPT]; |
| 449 | unsigned nccompare; |
| 450 | uint32_t timerint[MAX_NCCOMPARE]; |
| 451 | unsigned nextint; |
| 452 | unsigned extint[MAX_NINTERRUPT]; |
| 453 | |
| 454 | unsigned debug_level; |
| 455 | unsigned nibreak; |
| 456 | unsigned ndbreak; |
| 457 | |
| 458 | unsigned icache_ways; |
| 459 | unsigned dcache_ways; |
| 460 | unsigned dcache_line_bytes; |
| 461 | uint32_t memctl_mask; |
| 462 | |
| 463 | XtensaMemory instrom; |
| 464 | XtensaMemory instram; |
| 465 | XtensaMemory datarom; |
| 466 | XtensaMemory dataram; |
| 467 | XtensaMemory sysrom; |
| 468 | XtensaMemory sysram; |
| 469 | |
| 470 | unsigned hw_version; |
| 471 | uint32_t configid[2]; |
| 472 | |
| 473 | void *isa_internal; |
| 474 | xtensa_isa isa; |
| 475 | XtensaOpcodeOps **opcode_ops; |
| 476 | const XtensaOpcodeTranslators **opcode_translators; |
| 477 | xtensa_regfile a_regfile; |
| 478 | void ***regfile; |
| 479 | |
| 480 | uint32_t clock_freq_khz; |
| 481 | |
| 482 | xtensa_tlb itlb; |
| 483 | xtensa_tlb dtlb; |
| 484 | |
| 485 | uint32_t mpu_align; |
| 486 | unsigned n_mpu_fg_segments; |
| 487 | unsigned n_mpu_bg_segments; |
| 488 | const xtensa_mpu_entry *mpu_bg; |
| 489 | |
| 490 | bool use_first_nan; |
| 491 | } XtensaConfig; |
| 492 | |
| 493 | typedef struct XtensaConfigList { |
| 494 | XtensaConfig *config; |
| 495 | struct XtensaConfigList *next; |
| 496 | } XtensaConfigList; |
| 497 | |
| 498 | #if HOST_BIG_ENDIAN |
| 499 | enum { |
| 500 | FP_F32_HIGH, |
| 501 | FP_F32_LOW, |
| 502 | }; |
| 503 | #else |
| 504 | enum { |
| 505 | FP_F32_LOW, |
| 506 | FP_F32_HIGH, |
| 507 | }; |
| 508 | #endif |
| 509 | |
| 510 | struct CPUArchState { |
| 511 | const XtensaConfig *config; |
| 512 | uint32_t regs[16]; |
| 513 | uint32_t pc; |
| 514 | uint32_t sregs[256]; |
| 515 | uint32_t uregs[256]; |
| 516 | uint32_t phys_regs[MAX_NAREG]; |
| 517 | union { |
| 518 | float32 f32[2]; |
| 519 | float64 f64; |
| 520 | } fregs[16]; |
| 521 | float_status fp_status; |
| 522 | uint32_t windowbase_next; |
| 523 | uint32_t exclusive_addr; |
| 524 | uint32_t exclusive_val; |
| 525 | |
| 526 | #ifndef CONFIG_USER_ONLY |
| 527 | xtensa_tlb_entry itlb[7][MAX_TLB_WAY_SIZE]; |
| 528 | xtensa_tlb_entry dtlb[10][MAX_TLB_WAY_SIZE]; |
| 529 | xtensa_mpu_entry mpu_fg[MAX_MPU_FOREGROUND_SEGMENTS]; |
| 530 | unsigned autorefill_idx; |
| 531 | bool runstall; |
| 532 | AddressSpace *address_space_er; |
| 533 | MemoryRegion *system_er; |
| 534 | int pending_irq_level; /* level of last raised IRQ */ |
| 535 | qemu_irq *irq_inputs; |
| 536 | qemu_irq ext_irq_inputs[MAX_NINTERRUPT]; |
| 537 | qemu_irq runstall_irq; |
| 538 | XtensaCcompareTimer ccompare[MAX_NCCOMPARE]; |
| 539 | uint64_t time_base; |
| 540 | uint64_t ccount_time; |
| 541 | uint32_t ccount_base; |
| 542 | #endif |
| 543 | |
| 544 | int yield_needed; |
| 545 | unsigned static_vectors; |
| 546 | |
| 547 | /* Watchpoints for DBREAK registers */ |
| 548 | struct CPUWatchpoint *cpu_watchpoint[MAX_NDBREAK]; |
| 549 | /* Breakpoints for IBREAK registers */ |
| 550 | struct CPUBreakpoint *cpu_breakpoint[MAX_NIBREAK]; |
| 551 | }; |
| 552 | |
| 553 | /** |
| 554 | * XtensaCPU: |
| 555 | * @env: #CPUXtensaState |
| 556 | * |
| 557 | * An Xtensa CPU. |
| 558 | */ |
| 559 | struct ArchCPU { |
| 560 | CPUState parent_obj; |
| 561 | |
| 562 | CPUXtensaState env; |
| 563 | Clock *clock; |
| 564 | }; |
| 565 | |
| 566 | /** |
| 567 | * XtensaCPUClass: |
| 568 | * @parent_realize: The parent class' realize handler. |
| 569 | * @parent_phases: The parent class' reset phase handlers. |
| 570 | * @config: The CPU core configuration. |
| 571 | * |
| 572 | * An Xtensa CPU model. |
| 573 | */ |
| 574 | struct XtensaCPUClass { |
| 575 | CPUClass parent_class; |
| 576 | |
| 577 | DeviceRealize parent_realize; |
| 578 | ResettablePhases parent_phases; |
| 579 | |
| 580 | const XtensaConfig *config; |
| 581 | }; |
| 582 | |
| 583 | #ifndef CONFIG_USER_ONLY |
| 584 | bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, |
| 585 | MMUAccessType access_type, int mmu_idx, |
| 586 | bool probe, uintptr_t retaddr); |
| 587 | void xtensa_cpu_do_interrupt(CPUState *cpu); |
| 588 | bool xtensa_cpu_exec_interrupt(CPUState *cpu, int interrupt_request); |
| 589 | void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, |
| 590 | unsigned size, MMUAccessType access_type, |
| 591 | int mmu_idx, MemTxAttrs attrs, |
| 592 | MemTxResult response, uintptr_t retaddr); |
| 593 | hwaddr xtensa_cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr); |
| 594 | bool xtensa_debug_check_breakpoint(CPUState *cs); |
| 595 | #endif |
| 596 | void xtensa_cpu_dump_state(CPUState *cpu, FILE *f, int flags); |
| 597 | void xtensa_count_regs(const XtensaConfig *config, |
| 598 | unsigned *n_regs, unsigned *n_core_regs); |
| 599 | int xtensa_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); |
| 600 | int xtensa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); |
| 601 | G_NORETURN void xtensa_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, |
| 602 | MMUAccessType access_type, int mmu_idx, |
| 603 | uintptr_t retaddr); |
| 604 | |
| 605 | #define CPU_RESOLVING_TYPE TYPE_XTENSA_CPU |
| 606 | |
| 607 | #if TARGET_BIG_ENDIAN |
| 608 | #define XTENSA_DEFAULT_CPU_MODEL "fsf" |
| 609 | #define XTENSA_DEFAULT_CPU_NOMMU_MODEL "fsf" |
| 610 | #else |
| 611 | #define XTENSA_DEFAULT_CPU_MODEL "dc232b" |
| 612 | #define XTENSA_DEFAULT_CPU_NOMMU_MODEL "de212" |
| 613 | #endif |
| 614 | #define XTENSA_DEFAULT_CPU_TYPE \ |
| 615 | XTENSA_CPU_TYPE_NAME(XTENSA_DEFAULT_CPU_MODEL) |
| 616 | #define XTENSA_DEFAULT_CPU_NOMMU_TYPE \ |
| 617 | XTENSA_CPU_TYPE_NAME(XTENSA_DEFAULT_CPU_NOMMU_MODEL) |
| 618 | |
| 619 | void xtensa_collect_sr_names(const XtensaConfig *config); |
| 620 | void xtensa_translate_init(void); |
| 621 | void xtensa_translate_code(CPUState *cs, TranslationBlock *tb, |
| 622 | int *max_insns, vaddr pc, void *host_pc); |
| 623 | void **xtensa_get_regfile_by_name(const char *name, int entries, int bits); |
| 624 | void xtensa_breakpoint_handler(CPUState *cs); |
| 625 | void xtensa_register_core(XtensaConfigList *node); |
| 626 | void xtensa_sim_open_console(Chardev *chr); |
| 627 | void check_interrupts(CPUXtensaState *s); |
| 628 | void xtensa_irq_init(CPUXtensaState *env); |
| 629 | qemu_irq *xtensa_get_extints(CPUXtensaState *env); |
| 630 | qemu_irq xtensa_get_runstall(CPUXtensaState *env); |
| 631 | void xtensa_sync_window_from_phys(CPUXtensaState *env); |
| 632 | void xtensa_sync_phys_from_window(CPUXtensaState *env); |
| 633 | void xtensa_rotate_window(CPUXtensaState *env, uint32_t delta); |
| 634 | void xtensa_restore_owb(CPUXtensaState *env); |
| 635 | void debug_exception_env(CPUXtensaState *new_env, uint32_t cause); |
| 636 | |
| 637 | static inline void xtensa_select_static_vectors(CPUXtensaState *env, |
| 638 | unsigned n) |
| 639 | { |
| 640 | assert(n < 2); |
| 641 | env->static_vectors = n; |
| 642 | } |
| 643 | void xtensa_runstall(CPUXtensaState *env, bool runstall); |
| 644 | |
| 645 | uint32_t cpu_get_fsr(CPUXtensaState *env); |
| 646 | void cpu_set_fcr(CPUXtensaState *env, uint32_t v); |
| 647 | void cpu_set_fsr(CPUXtensaState *env, uint32_t v); |
| 648 | |
| 649 | #define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt)) |
| 650 | #define XTENSA_OPTION_ALL (~(uint64_t)0) |
| 651 | |
| 652 | static inline bool xtensa_option_bits_enabled(const XtensaConfig *config, |
| 653 | uint64_t opt) |
| 654 | { |
| 655 | return (config->options & opt) != 0; |
| 656 | } |
| 657 | |
| 658 | static inline bool xtensa_option_enabled(const XtensaConfig *config, int opt) |
| 659 | { |
| 660 | return xtensa_option_bits_enabled(config, XTENSA_OPTION_BIT(opt)); |
| 661 | } |
| 662 | |
| 663 | static inline int xtensa_get_cintlevel(const CPUXtensaState *env) |
| 664 | { |
| 665 | int level = (env->sregs[PS] & PS_INTLEVEL) >> PS_INTLEVEL_SHIFT; |
| 666 | if ((env->sregs[PS] & PS_EXCM) && env->config->excm_level > level) { |
| 667 | level = env->config->excm_level; |
| 668 | } |
| 669 | return level; |
| 670 | } |
| 671 | |
| 672 | static inline int xtensa_get_ring(const CPUXtensaState *env) |
| 673 | { |
| 674 | if (xtensa_option_bits_enabled(env->config, |
| 675 | XTENSA_OPTION_BIT(XTENSA_OPTION_MMU) | |
| 676 | XTENSA_OPTION_BIT(XTENSA_OPTION_MPU))) { |
| 677 | return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT; |
| 678 | } else { |
| 679 | return 0; |
| 680 | } |
| 681 | } |
| 682 | |
| 683 | static inline int xtensa_get_cring(const CPUXtensaState *env) |
| 684 | { |
| 685 | if (xtensa_option_bits_enabled(env->config, |
| 686 | XTENSA_OPTION_BIT(XTENSA_OPTION_MMU) | |
| 687 | XTENSA_OPTION_BIT(XTENSA_OPTION_MPU)) && |
| 688 | (env->sregs[PS] & PS_EXCM) == 0) { |
| 689 | return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT; |
| 690 | } else { |
| 691 | return 0; |
| 692 | } |
| 693 | } |
| 694 | |
| 695 | #ifndef CONFIG_USER_ONLY |
| 696 | int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb, |
| 697 | uint32_t vaddr, int is_write, int mmu_idx, |
| 698 | uint32_t *paddr, uint32_t *page_size, unsigned *access); |
| 699 | void reset_mmu(CPUXtensaState *env); |
| 700 | void dump_mmu(CPUXtensaState *env); |
| 701 | |
| 702 | static inline MemoryRegion *xtensa_get_er_region(CPUXtensaState *env) |
| 703 | { |
| 704 | return env->system_er; |
| 705 | } |
| 706 | #else |
| 707 | void xtensa_set_abi_call0(void); |
| 708 | bool xtensa_abi_call0(void); |
| 709 | #endif |
| 710 | |
| 711 | static inline uint32_t xtensa_replicate_windowstart(CPUXtensaState *env) |
| 712 | { |
| 713 | return env->sregs[WINDOW_START] | |
| 714 | (env->sregs[WINDOW_START] << env->config->nareg / 4); |
| 715 | } |
| 716 | |
| 717 | /* MMU modes definitions */ |
| 718 | #define MMU_USER_IDX 3 |
| 719 | |
| 720 | #define XTENSA_TBFLAG_RING_MASK 0x3 |
| 721 | #define XTENSA_TBFLAG_EXCM 0x4 |
| 722 | #define XTENSA_TBFLAG_LITBASE 0x8 |
| 723 | #define XTENSA_TBFLAG_DEBUG 0x10 |
| 724 | #define XTENSA_TBFLAG_ICOUNT 0x20 |
| 725 | #define XTENSA_TBFLAG_CPENABLE_MASK 0x3fc0 |
| 726 | #define XTENSA_TBFLAG_CPENABLE_SHIFT 6 |
| 727 | #define XTENSA_TBFLAG_WINDOW_MASK 0x18000 |
| 728 | #define XTENSA_TBFLAG_WINDOW_SHIFT 15 |
| 729 | #define XTENSA_TBFLAG_YIELD 0x20000 |
| 730 | #define XTENSA_TBFLAG_CWOE 0x40000 |
| 731 | #define XTENSA_TBFLAG_CALLINC_MASK 0x180000 |
| 732 | #define XTENSA_TBFLAG_CALLINC_SHIFT 19 |
| 733 | |
| 734 | #define XTENSA_CSBASE_LEND_MASK 0x0000ffff |
| 735 | #define XTENSA_CSBASE_LEND_SHIFT 0 |
| 736 | #define XTENSA_CSBASE_LBEG_OFF_MASK 0x00ff0000 |
| 737 | #define XTENSA_CSBASE_LBEG_OFF_SHIFT 16 |
| 738 | |
| 739 | XtensaCPU *xtensa_cpu_create_with_clock(const char *cpu_type, |
| 740 | Clock *cpu_refclk); |
| 741 | |
| 742 | /* |
| 743 | * Set the NaN propagation rule for future FPU operations: |
| 744 | * use_first is true to pick the first NaN as the result if both |
| 745 | * inputs are NaNs, false to pick the second. |
| 746 | */ |
| 747 | void xtensa_use_first_nan(CPUXtensaState *env, bool use_first); |
| 748 | #endif |