| 1 | /* |
| 2 | * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. |
| 3 | * All rights reserved. |
| 4 | * |
| 5 | * Redistribution and use in source and binary forms, with or without |
| 6 | * modification, are permitted provided that the following conditions are met: |
| 7 | * * Redistributions of source code must retain the above copyright |
| 8 | * notice, this list of conditions and the following disclaimer. |
| 9 | * * Redistributions in binary form must reproduce the above copyright |
| 10 | * notice, this list of conditions and the following disclaimer in the |
| 11 | * documentation and/or other materials provided with the distribution. |
| 12 | * * Neither the name of the Open Source and Linux Lab nor the |
| 13 | * names of its contributors may be used to endorse or promote products |
| 14 | * derived from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 17 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 18 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY |
| 20 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 21 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 22 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 23 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 24 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 25 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 26 | */ |
| 27 | |
| 28 | #include "qemu/osdep.h" |
| 29 | #include "qemu/log.h" |
| 30 | #include "cpu.h" |
| 31 | #include "exec/cputlb.h" |
| 32 | #include "exec/target_page.h" |
| 33 | #include "gdbstub/helpers.h" |
| 34 | #include "exec/helper-proto.h" |
| 35 | #include "accel/tcg/cpu-loop.h" |
| 36 | #include "qemu/error-report.h" |
| 37 | #include "qemu/qemu-print.h" |
| 38 | #include "qemu/host-utils.h" |
| 39 | |
| 40 | static struct XtensaConfigList *xtensa_cores; |
| 41 | |
| 42 | static void add_translator_to_hash(GHashTable *translator, |
| 43 | const char *name, |
| 44 | const XtensaOpcodeOps *opcode) |
| 45 | { |
| 46 | if (!g_hash_table_insert(translator, (void *)name, (void *)opcode)) { |
| 47 | error_report("Multiple definitions of '%s' opcode in a single table", |
| 48 | name); |
| 49 | } |
| 50 | } |
| 51 | |
| 52 | static GHashTable *hash_opcode_translators(const XtensaOpcodeTranslators *t) |
| 53 | { |
| 54 | unsigned i, j; |
| 55 | GHashTable *translator = g_hash_table_new(g_str_hash, g_str_equal); |
| 56 | |
| 57 | for (i = 0; i < t->num_opcodes; ++i) { |
| 58 | if (t->opcode[i].op_flags & XTENSA_OP_NAME_ARRAY) { |
| 59 | const char * const *name = t->opcode[i].name; |
| 60 | |
| 61 | for (j = 0; name[j]; ++j) { |
| 62 | add_translator_to_hash(translator, |
| 63 | (void *)name[j], |
| 64 | (void *)(t->opcode + i)); |
| 65 | } |
| 66 | } else { |
| 67 | add_translator_to_hash(translator, |
| 68 | (void *)t->opcode[i].name, |
| 69 | (void *)(t->opcode + i)); |
| 70 | } |
| 71 | } |
| 72 | return translator; |
| 73 | } |
| 74 | |
| 75 | static XtensaOpcodeOps * |
| 76 | xtensa_find_opcode_ops(const XtensaOpcodeTranslators *t, |
| 77 | const char *name) |
| 78 | { |
| 79 | static GHashTable *translators; |
| 80 | GHashTable *translator; |
| 81 | |
| 82 | if (translators == NULL) { |
| 83 | translators = g_hash_table_new(g_direct_hash, g_direct_equal); |
| 84 | } |
| 85 | translator = g_hash_table_lookup(translators, t); |
| 86 | if (translator == NULL) { |
| 87 | translator = hash_opcode_translators(t); |
| 88 | g_hash_table_insert(translators, (void *)t, translator); |
| 89 | } |
| 90 | return g_hash_table_lookup(translator, name); |
| 91 | } |
| 92 | |
| 93 | static void init_libisa(XtensaConfig *config) |
| 94 | { |
| 95 | unsigned i, j; |
| 96 | unsigned opcodes; |
| 97 | unsigned formats; |
| 98 | unsigned regfiles; |
| 99 | |
| 100 | config->isa = xtensa_isa_init(config->isa_internal, NULL, NULL); |
| 101 | assert(xtensa_isa_maxlength(config->isa) <= MAX_INSN_LENGTH); |
| 102 | assert(xtensa_insnbuf_size(config->isa) <= MAX_INSNBUF_LENGTH); |
| 103 | opcodes = xtensa_isa_num_opcodes(config->isa); |
| 104 | formats = xtensa_isa_num_formats(config->isa); |
| 105 | regfiles = xtensa_isa_num_regfiles(config->isa); |
| 106 | config->opcode_ops = g_new(XtensaOpcodeOps *, opcodes); |
| 107 | |
| 108 | for (i = 0; i < formats; ++i) { |
| 109 | assert(xtensa_format_num_slots(config->isa, i) <= MAX_INSN_SLOTS); |
| 110 | } |
| 111 | |
| 112 | for (i = 0; i < opcodes; ++i) { |
| 113 | const char *opc_name = xtensa_opcode_name(config->isa, i); |
| 114 | XtensaOpcodeOps *ops = NULL; |
| 115 | |
| 116 | assert(xtensa_opcode_num_operands(config->isa, i) <= MAX_OPCODE_ARGS); |
| 117 | if (!config->opcode_translators) { |
| 118 | ops = xtensa_find_opcode_ops(&xtensa_core_opcodes, opc_name); |
| 119 | } else { |
| 120 | for (j = 0; !ops && config->opcode_translators[j]; ++j) { |
| 121 | ops = xtensa_find_opcode_ops(config->opcode_translators[j], |
| 122 | opc_name); |
| 123 | } |
| 124 | } |
| 125 | #ifdef DEBUG |
| 126 | if (ops == NULL) { |
| 127 | fprintf(stderr, |
| 128 | "opcode translator not found for %s's opcode '%s'\n", |
| 129 | config->name, opc_name); |
| 130 | } |
| 131 | #endif |
| 132 | config->opcode_ops[i] = ops; |
| 133 | } |
| 134 | config->a_regfile = xtensa_regfile_lookup(config->isa, "AR"); |
| 135 | |
| 136 | config->regfile = g_new(void **, regfiles); |
| 137 | for (i = 0; i < regfiles; ++i) { |
| 138 | const char *name = xtensa_regfile_name(config->isa, i); |
| 139 | int entries = xtensa_regfile_num_entries(config->isa, i); |
| 140 | int bits = xtensa_regfile_num_bits(config->isa, i); |
| 141 | |
| 142 | config->regfile[i] = xtensa_get_regfile_by_name(name, entries, bits); |
| 143 | #ifdef DEBUG |
| 144 | if (config->regfile[i] == NULL) { |
| 145 | fprintf(stderr, "regfile '%s' not found for %s\n", |
| 146 | name, config->name); |
| 147 | } |
| 148 | #endif |
| 149 | } |
| 150 | xtensa_collect_sr_names(config); |
| 151 | } |
| 152 | |
| 153 | static void xtensa_finalize_config(XtensaConfig *config) |
| 154 | { |
| 155 | if (config->isa_internal) { |
| 156 | init_libisa(config); |
| 157 | } |
| 158 | |
| 159 | if (config->gdb_regmap.num_regs == 0 || |
| 160 | config->gdb_regmap.num_core_regs == 0) { |
| 161 | unsigned n_regs = 0; |
| 162 | unsigned n_core_regs = 0; |
| 163 | |
| 164 | xtensa_count_regs(config, &n_regs, &n_core_regs); |
| 165 | if (config->gdb_regmap.num_regs == 0) { |
| 166 | config->gdb_regmap.num_regs = n_regs; |
| 167 | } |
| 168 | if (config->gdb_regmap.num_core_regs == 0) { |
| 169 | config->gdb_regmap.num_core_regs = n_core_regs; |
| 170 | } |
| 171 | } |
| 172 | } |
| 173 | |
| 174 | static void xtensa_core_class_init(ObjectClass *oc, const void *data) |
| 175 | { |
| 176 | CPUClass *cc = CPU_CLASS(oc); |
| 177 | XtensaCPUClass *xcc = XTENSA_CPU_CLASS(oc); |
| 178 | const XtensaConfig *config = data; |
| 179 | |
| 180 | xcc->config = config; |
| 181 | |
| 182 | /* |
| 183 | * Use num_core_regs to see only non-privileged registers in an unmodified |
| 184 | * gdb. Use num_regs to see all registers. gdb modification is required |
| 185 | * for that: reset bit 0 in the 'flags' field of the registers definitions |
| 186 | * in the gdb/xtensa-config.c inside gdb source tree or inside gdb overlay. |
| 187 | */ |
| 188 | cc->gdb_num_core_regs = config->gdb_regmap.num_regs; |
| 189 | } |
| 190 | |
| 191 | void xtensa_register_core(XtensaConfigList *node) |
| 192 | { |
| 193 | TypeInfo type = { |
| 194 | .parent = TYPE_XTENSA_CPU, |
| 195 | .class_init = xtensa_core_class_init, |
| 196 | .class_data = node->config, |
| 197 | }; |
| 198 | |
| 199 | xtensa_finalize_config(node->config); |
| 200 | |
| 201 | node->next = xtensa_cores; |
| 202 | xtensa_cores = node; |
| 203 | type.name = g_strdup_printf(XTENSA_CPU_TYPE_NAME("%s"), node->config->name); |
| 204 | type_register_static(&type); |
| 205 | g_free((gpointer)type.name); |
| 206 | } |
| 207 | |
| 208 | static uint32_t check_hw_breakpoints(CPUXtensaState *env) |
| 209 | { |
| 210 | unsigned i; |
| 211 | |
| 212 | for (i = 0; i < env->config->ndbreak; ++i) { |
| 213 | if (env->cpu_watchpoint[i] && |
| 214 | env->cpu_watchpoint[i]->flags & BP_WATCHPOINT_HIT) { |
| 215 | return DEBUGCAUSE_DB | (i << DEBUGCAUSE_DBNUM_SHIFT); |
| 216 | } |
| 217 | } |
| 218 | return 0; |
| 219 | } |
| 220 | |
| 221 | void xtensa_breakpoint_handler(CPUState *cs) |
| 222 | { |
| 223 | CPUXtensaState *env = cpu_env(cs); |
| 224 | |
| 225 | if (cs->watchpoint_hit) { |
| 226 | if (cs->watchpoint_hit->flags & BP_CPU) { |
| 227 | uint32_t cause; |
| 228 | |
| 229 | cs->watchpoint_hit = NULL; |
| 230 | cause = check_hw_breakpoints(env); |
| 231 | if (cause) { |
| 232 | debug_exception_env(env, cause); |
| 233 | } |
| 234 | cpu_loop_exit_noexc(cs); |
| 235 | } |
| 236 | } else { |
| 237 | if (cpu_breakpoint_test(cs, env->pc, BP_GDB) |
| 238 | || !cpu_breakpoint_test(cs, env->pc, BP_CPU)) { |
| 239 | return; |
| 240 | } |
| 241 | if (env->sregs[ICOUNT] == 0xffffffff && |
| 242 | xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) { |
| 243 | debug_exception_env(env, DEBUGCAUSE_IC); |
| 244 | } else { |
| 245 | debug_exception_env(env, DEBUGCAUSE_IB); |
| 246 | } |
| 247 | cpu_loop_exit_noexc(cs); |
| 248 | } |
| 249 | } |
| 250 | |
| 251 | #ifndef CONFIG_USER_ONLY |
| 252 | void xtensa_cpu_do_unaligned_access(CPUState *cs, |
| 253 | vaddr addr, MMUAccessType access_type, |
| 254 | int mmu_idx, uintptr_t retaddr) |
| 255 | { |
| 256 | XtensaCPU *cpu = XTENSA_CPU(cs); |
| 257 | CPUXtensaState *env = &cpu->env; |
| 258 | |
| 259 | assert(xtensa_option_enabled(env->config, |
| 260 | XTENSA_OPTION_UNALIGNED_EXCEPTION)); |
| 261 | cpu_restore_state(CPU(cpu), retaddr); |
| 262 | HELPER(exception_cause_vaddr)(env, |
| 263 | env->pc, LOAD_STORE_ALIGNMENT_CAUSE, |
| 264 | addr); |
| 265 | } |
| 266 | |
| 267 | bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, |
| 268 | MMUAccessType access_type, int mmu_idx, |
| 269 | bool probe, uintptr_t retaddr) |
| 270 | { |
| 271 | CPUXtensaState *env = cpu_env(cs); |
| 272 | uint32_t paddr; |
| 273 | uint32_t page_size; |
| 274 | unsigned access; |
| 275 | int ret = xtensa_get_physical_addr(env, true, address, access_type, |
| 276 | mmu_idx, &paddr, &page_size, &access); |
| 277 | |
| 278 | qemu_log_mask(CPU_LOG_MMU, "%s(%08" VADDR_PRIx |
| 279 | ", %d, %d) -> %08x, ret = %d\n", |
| 280 | __func__, address, access_type, mmu_idx, paddr, ret); |
| 281 | |
| 282 | if (ret == 0) { |
| 283 | tlb_set_page(cs, |
| 284 | address & TARGET_PAGE_MASK, |
| 285 | paddr & TARGET_PAGE_MASK, |
| 286 | access, mmu_idx, page_size); |
| 287 | return true; |
| 288 | } else if (probe) { |
| 289 | return false; |
| 290 | } else { |
| 291 | cpu_restore_state(cs, retaddr); |
| 292 | HELPER(exception_cause_vaddr)(env, env->pc, ret, address); |
| 293 | } |
| 294 | } |
| 295 | |
| 296 | void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, |
| 297 | unsigned size, MMUAccessType access_type, |
| 298 | int mmu_idx, MemTxAttrs attrs, |
| 299 | MemTxResult response, uintptr_t retaddr) |
| 300 | { |
| 301 | CPUXtensaState *env = cpu_env(cs); |
| 302 | |
| 303 | cpu_restore_state(cs, retaddr); |
| 304 | HELPER(exception_cause_vaddr)(env, env->pc, |
| 305 | access_type == MMU_INST_FETCH ? |
| 306 | INSTR_PIF_ADDR_ERROR_CAUSE : |
| 307 | LOAD_STORE_PIF_ADDR_ERROR_CAUSE, |
| 308 | addr); |
| 309 | } |
| 310 | |
| 311 | void xtensa_runstall(CPUXtensaState *env, bool runstall) |
| 312 | { |
| 313 | CPUState *cpu = env_cpu(env); |
| 314 | |
| 315 | env->runstall = runstall; |
| 316 | cpu->halted = runstall; |
| 317 | if (runstall) { |
| 318 | cpu_interrupt(cpu, CPU_INTERRUPT_HALT); |
| 319 | } else { |
| 320 | qemu_cpu_kick(cpu); |
| 321 | } |
| 322 | } |
| 323 | #endif /* !CONFIG_USER_ONLY */ |