| 1 | /* |
| 2 | * Xtensa ISA: |
| 3 | * http://www.tensilica.com/products/literature-docs/documentation/xtensa-isa-databook.htm |
| 4 | * |
| 5 | * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. |
| 6 | * All rights reserved. |
| 7 | * |
| 8 | * Redistribution and use in source and binary forms, with or without |
| 9 | * modification, are permitted provided that the following conditions are met: |
| 10 | * * Redistributions of source code must retain the above copyright |
| 11 | * notice, this list of conditions and the following disclaimer. |
| 12 | * * Redistributions in binary form must reproduce the above copyright |
| 13 | * notice, this list of conditions and the following disclaimer in the |
| 14 | * documentation and/or other materials provided with the distribution. |
| 15 | * * Neither the name of the Open Source and Linux Lab nor the |
| 16 | * names of its contributors may be used to endorse or promote products |
| 17 | * derived from this software without specific prior written permission. |
| 18 | * |
| 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 20 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 21 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 22 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY |
| 23 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 24 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 25 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 26 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 27 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 28 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #include "qemu/osdep.h" |
| 32 | |
| 33 | #include "cpu.h" |
| 34 | #include "tcg/tcg-op.h" |
| 35 | #include "qemu/log.h" |
| 36 | #include "qemu/qemu-print.h" |
| 37 | #include "exec/translator.h" |
| 38 | #include "exec/translation-block.h" |
| 39 | #include "exec/target_page.h" |
| 40 | #include "exec/helper-proto.h" |
| 41 | #include "exec/helper-gen.h" |
| 42 | #include "exec/log.h" |
| 43 | #ifndef CONFIG_USER_ONLY |
| 44 | #include "semihosting/semihost.h" |
| 45 | #endif |
| 46 | |
| 47 | #define HELPER_H "helper.h" |
| 48 | #include "exec/helper-info.c.inc" |
| 49 | #undef HELPER_H |
| 50 | |
| 51 | |
| 52 | struct DisasContext { |
| 53 | DisasContextBase base; |
| 54 | const XtensaConfig *config; |
| 55 | uint32_t pc; |
| 56 | int cring; |
| 57 | int ring; |
| 58 | uint32_t lbeg_off; |
| 59 | uint32_t lend; |
| 60 | |
| 61 | bool sar_5bit; |
| 62 | bool sar_m32_5bit; |
| 63 | TCGv_i32 sar_m32; |
| 64 | |
| 65 | unsigned window; |
| 66 | unsigned callinc; |
| 67 | bool cwoe; |
| 68 | |
| 69 | bool debug; |
| 70 | bool icount; |
| 71 | TCGv_i32 next_icount; |
| 72 | |
| 73 | unsigned cpenable; |
| 74 | |
| 75 | uint32_t op_flags; |
| 76 | xtensa_insnbuf_word insnbuf[MAX_INSNBUF_LENGTH]; |
| 77 | xtensa_insnbuf_word slotbuf[MAX_INSNBUF_LENGTH]; |
| 78 | }; |
| 79 | |
| 80 | static TCGv_i32 cpu_pc; |
| 81 | static TCGv_i32 cpu_R[16]; |
| 82 | static TCGv_i32 cpu_FR[16]; |
| 83 | static TCGv_i64 cpu_FRD[16]; |
| 84 | static TCGv_i32 cpu_MR[4]; |
| 85 | static TCGv_i32 cpu_BR[16]; |
| 86 | static TCGv_i32 cpu_BR4[4]; |
| 87 | static TCGv_i32 cpu_BR8[2]; |
| 88 | static TCGv_i32 cpu_SR[256]; |
| 89 | static TCGv_i32 cpu_UR[256]; |
| 90 | static TCGv_i32 cpu_windowbase_next; |
| 91 | static TCGv_i32 cpu_exclusive_addr; |
| 92 | static TCGv_i32 cpu_exclusive_val; |
| 93 | |
| 94 | static GHashTable *xtensa_regfile_table; |
| 95 | |
| 96 | static char *sr_name[256]; |
| 97 | static char *ur_name[256]; |
| 98 | |
| 99 | void xtensa_collect_sr_names(const XtensaConfig *config) |
| 100 | { |
| 101 | xtensa_isa isa = config->isa; |
| 102 | int n = xtensa_isa_num_sysregs(isa); |
| 103 | int i; |
| 104 | |
| 105 | for (i = 0; i < n; ++i) { |
| 106 | int sr = xtensa_sysreg_number(isa, i); |
| 107 | |
| 108 | if (sr >= 0 && sr < 256) { |
| 109 | const char *name = xtensa_sysreg_name(isa, i); |
| 110 | char **pname = |
| 111 | (xtensa_sysreg_is_user(isa, i) ? ur_name : sr_name) + sr; |
| 112 | |
| 113 | if (*pname) { |
| 114 | if (strstr(*pname, name) == NULL) { |
| 115 | char *new_name = g_strdup_printf("%s/%s", *pname, name); |
| 116 | g_free(*pname); |
| 117 | *pname = new_name; |
| 118 | } |
| 119 | } else { |
| 120 | *pname = g_strdup(name); |
| 121 | } |
| 122 | } |
| 123 | } |
| 124 | } |
| 125 | |
| 126 | void xtensa_translate_init(void) |
| 127 | { |
| 128 | static const char * const regnames[] = { |
| 129 | "ar0", "ar1", "ar2", "ar3", |
| 130 | "ar4", "ar5", "ar6", "ar7", |
| 131 | "ar8", "ar9", "ar10", "ar11", |
| 132 | "ar12", "ar13", "ar14", "ar15", |
| 133 | }; |
| 134 | static const char * const fregnames[] = { |
| 135 | "f0", "f1", "f2", "f3", |
| 136 | "f4", "f5", "f6", "f7", |
| 137 | "f8", "f9", "f10", "f11", |
| 138 | "f12", "f13", "f14", "f15", |
| 139 | }; |
| 140 | static const char * const mregnames[] = { |
| 141 | "m0", "m1", "m2", "m3", |
| 142 | }; |
| 143 | static const char * const bregnames[] = { |
| 144 | "b0", "b1", "b2", "b3", |
| 145 | "b4", "b5", "b6", "b7", |
| 146 | "b8", "b9", "b10", "b11", |
| 147 | "b12", "b13", "b14", "b15", |
| 148 | }; |
| 149 | int i; |
| 150 | |
| 151 | cpu_pc = tcg_global_mem_new_i32(tcg_env, |
| 152 | offsetof(CPUXtensaState, pc), "pc"); |
| 153 | |
| 154 | for (i = 0; i < 16; i++) { |
| 155 | cpu_R[i] = tcg_global_mem_new_i32(tcg_env, |
| 156 | offsetof(CPUXtensaState, regs[i]), |
| 157 | regnames[i]); |
| 158 | } |
| 159 | |
| 160 | for (i = 0; i < 16; i++) { |
| 161 | cpu_FR[i] = tcg_global_mem_new_i32(tcg_env, |
| 162 | offsetof(CPUXtensaState, |
| 163 | fregs[i].f32[FP_F32_LOW]), |
| 164 | fregnames[i]); |
| 165 | } |
| 166 | |
| 167 | for (i = 0; i < 16; i++) { |
| 168 | cpu_FRD[i] = tcg_global_mem_new_i64(tcg_env, |
| 169 | offsetof(CPUXtensaState, |
| 170 | fregs[i].f64), |
| 171 | fregnames[i]); |
| 172 | } |
| 173 | |
| 174 | for (i = 0; i < 4; i++) { |
| 175 | cpu_MR[i] = tcg_global_mem_new_i32(tcg_env, |
| 176 | offsetof(CPUXtensaState, |
| 177 | sregs[MR + i]), |
| 178 | mregnames[i]); |
| 179 | } |
| 180 | |
| 181 | for (i = 0; i < 16; i++) { |
| 182 | cpu_BR[i] = tcg_global_mem_new_i32(tcg_env, |
| 183 | offsetof(CPUXtensaState, |
| 184 | sregs[BR]), |
| 185 | bregnames[i]); |
| 186 | if (i % 4 == 0) { |
| 187 | cpu_BR4[i / 4] = tcg_global_mem_new_i32(tcg_env, |
| 188 | offsetof(CPUXtensaState, |
| 189 | sregs[BR]), |
| 190 | bregnames[i]); |
| 191 | } |
| 192 | if (i % 8 == 0) { |
| 193 | cpu_BR8[i / 8] = tcg_global_mem_new_i32(tcg_env, |
| 194 | offsetof(CPUXtensaState, |
| 195 | sregs[BR]), |
| 196 | bregnames[i]); |
| 197 | } |
| 198 | } |
| 199 | |
| 200 | for (i = 0; i < 256; ++i) { |
| 201 | if (sr_name[i]) { |
| 202 | cpu_SR[i] = tcg_global_mem_new_i32(tcg_env, |
| 203 | offsetof(CPUXtensaState, |
| 204 | sregs[i]), |
| 205 | sr_name[i]); |
| 206 | } |
| 207 | } |
| 208 | |
| 209 | for (i = 0; i < 256; ++i) { |
| 210 | if (ur_name[i]) { |
| 211 | cpu_UR[i] = tcg_global_mem_new_i32(tcg_env, |
| 212 | offsetof(CPUXtensaState, |
| 213 | uregs[i]), |
| 214 | ur_name[i]); |
| 215 | } |
| 216 | } |
| 217 | |
| 218 | cpu_windowbase_next = |
| 219 | tcg_global_mem_new_i32(tcg_env, |
| 220 | offsetof(CPUXtensaState, windowbase_next), |
| 221 | "windowbase_next"); |
| 222 | cpu_exclusive_addr = |
| 223 | tcg_global_mem_new_i32(tcg_env, |
| 224 | offsetof(CPUXtensaState, exclusive_addr), |
| 225 | "exclusive_addr"); |
| 226 | cpu_exclusive_val = |
| 227 | tcg_global_mem_new_i32(tcg_env, |
| 228 | offsetof(CPUXtensaState, exclusive_val), |
| 229 | "exclusive_val"); |
| 230 | } |
| 231 | |
| 232 | void **xtensa_get_regfile_by_name(const char *name, int entries, int bits) |
| 233 | { |
| 234 | char *geometry_name; |
| 235 | void **res; |
| 236 | |
| 237 | if (xtensa_regfile_table == NULL) { |
| 238 | xtensa_regfile_table = g_hash_table_new(g_str_hash, g_str_equal); |
| 239 | /* |
| 240 | * AR is special. Xtensa translator uses it as a current register |
| 241 | * window, but configuration overlays represent it as a complete |
| 242 | * physical register file. |
| 243 | */ |
| 244 | g_hash_table_insert(xtensa_regfile_table, |
| 245 | (void *)"AR 16x32", (void *)cpu_R); |
| 246 | g_hash_table_insert(xtensa_regfile_table, |
| 247 | (void *)"AR 32x32", (void *)cpu_R); |
| 248 | g_hash_table_insert(xtensa_regfile_table, |
| 249 | (void *)"AR 64x32", (void *)cpu_R); |
| 250 | |
| 251 | g_hash_table_insert(xtensa_regfile_table, |
| 252 | (void *)"MR 4x32", (void *)cpu_MR); |
| 253 | |
| 254 | g_hash_table_insert(xtensa_regfile_table, |
| 255 | (void *)"FR 16x32", (void *)cpu_FR); |
| 256 | g_hash_table_insert(xtensa_regfile_table, |
| 257 | (void *)"FR 16x64", (void *)cpu_FRD); |
| 258 | |
| 259 | g_hash_table_insert(xtensa_regfile_table, |
| 260 | (void *)"BR 16x1", (void *)cpu_BR); |
| 261 | g_hash_table_insert(xtensa_regfile_table, |
| 262 | (void *)"BR4 4x4", (void *)cpu_BR4); |
| 263 | g_hash_table_insert(xtensa_regfile_table, |
| 264 | (void *)"BR8 2x8", (void *)cpu_BR8); |
| 265 | } |
| 266 | |
| 267 | geometry_name = g_strdup_printf("%s %dx%d", name, entries, bits); |
| 268 | res = (void **)g_hash_table_lookup(xtensa_regfile_table, geometry_name); |
| 269 | g_free(geometry_name); |
| 270 | return res; |
| 271 | } |
| 272 | |
| 273 | static inline bool option_enabled(DisasContext *dc, int opt) |
| 274 | { |
| 275 | return xtensa_option_enabled(dc->config, opt); |
| 276 | } |
| 277 | |
| 278 | static void init_sar_tracker(DisasContext *dc) |
| 279 | { |
| 280 | dc->sar_5bit = false; |
| 281 | dc->sar_m32_5bit = false; |
| 282 | dc->sar_m32 = NULL; |
| 283 | } |
| 284 | |
| 285 | static void gen_right_shift_sar(DisasContext *dc, TCGv_i32 sa) |
| 286 | { |
| 287 | tcg_gen_andi_i32(cpu_SR[SAR], sa, 0x1f); |
| 288 | if (dc->sar_m32_5bit) { |
| 289 | tcg_gen_discard_i32(dc->sar_m32); |
| 290 | } |
| 291 | dc->sar_5bit = true; |
| 292 | dc->sar_m32_5bit = false; |
| 293 | } |
| 294 | |
| 295 | static void gen_left_shift_sar(DisasContext *dc, TCGv_i32 sa) |
| 296 | { |
| 297 | if (!dc->sar_m32) { |
| 298 | dc->sar_m32 = tcg_temp_new_i32(); |
| 299 | } |
| 300 | tcg_gen_andi_i32(dc->sar_m32, sa, 0x1f); |
| 301 | tcg_gen_sub_i32(cpu_SR[SAR], tcg_constant_i32(32), dc->sar_m32); |
| 302 | dc->sar_5bit = false; |
| 303 | dc->sar_m32_5bit = true; |
| 304 | } |
| 305 | |
| 306 | static void gen_exception(DisasContext *dc, int excp) |
| 307 | { |
| 308 | gen_helper_exception(tcg_env, tcg_constant_i32(excp)); |
| 309 | } |
| 310 | |
| 311 | static void gen_exception_cause(DisasContext *dc, uint32_t cause) |
| 312 | { |
| 313 | TCGv_i32 pc = tcg_constant_i32(dc->pc); |
| 314 | gen_helper_exception_cause(tcg_env, pc, tcg_constant_i32(cause)); |
| 315 | if (cause == ILLEGAL_INSTRUCTION_CAUSE || |
| 316 | cause == SYSCALL_CAUSE) { |
| 317 | dc->base.is_jmp = DISAS_NORETURN; |
| 318 | } |
| 319 | } |
| 320 | |
| 321 | static void gen_debug_exception(DisasContext *dc, uint32_t cause) |
| 322 | { |
| 323 | TCGv_i32 pc = tcg_constant_i32(dc->pc); |
| 324 | gen_helper_debug_exception(tcg_env, pc, tcg_constant_i32(cause)); |
| 325 | if (cause & (DEBUGCAUSE_IB | DEBUGCAUSE_BI | DEBUGCAUSE_BN)) { |
| 326 | dc->base.is_jmp = DISAS_NORETURN; |
| 327 | } |
| 328 | } |
| 329 | |
| 330 | static bool gen_check_privilege(DisasContext *dc) |
| 331 | { |
| 332 | #ifndef CONFIG_USER_ONLY |
| 333 | if (!dc->cring) { |
| 334 | return true; |
| 335 | } |
| 336 | #endif |
| 337 | gen_exception_cause(dc, PRIVILEGED_CAUSE); |
| 338 | dc->base.is_jmp = DISAS_NORETURN; |
| 339 | return false; |
| 340 | } |
| 341 | |
| 342 | static bool gen_check_cpenable(DisasContext *dc, uint32_t cp_mask) |
| 343 | { |
| 344 | cp_mask &= ~dc->cpenable; |
| 345 | |
| 346 | if (option_enabled(dc, XTENSA_OPTION_COPROCESSOR) && cp_mask) { |
| 347 | gen_exception_cause(dc, COPROCESSOR0_DISABLED + ctz32(cp_mask)); |
| 348 | dc->base.is_jmp = DISAS_NORETURN; |
| 349 | return false; |
| 350 | } |
| 351 | return true; |
| 352 | } |
| 353 | |
| 354 | static int gen_postprocess(DisasContext *dc, int slot); |
| 355 | |
| 356 | static void gen_jump_slot(DisasContext *dc, TCGv dest, int slot) |
| 357 | { |
| 358 | tcg_gen_mov_i32(cpu_pc, dest); |
| 359 | if (dc->icount) { |
| 360 | tcg_gen_mov_i32(cpu_SR[ICOUNT], dc->next_icount); |
| 361 | } |
| 362 | if (dc->op_flags & XTENSA_OP_POSTPROCESS) { |
| 363 | slot = gen_postprocess(dc, slot); |
| 364 | } |
| 365 | if (slot >= 0) { |
| 366 | tcg_gen_goto_tb(slot); |
| 367 | tcg_gen_exit_tb(dc->base.tb, slot); |
| 368 | } else { |
| 369 | tcg_gen_exit_tb(NULL, 0); |
| 370 | } |
| 371 | dc->base.is_jmp = DISAS_NORETURN; |
| 372 | } |
| 373 | |
| 374 | static void gen_jump(DisasContext *dc, TCGv dest) |
| 375 | { |
| 376 | gen_jump_slot(dc, dest, -1); |
| 377 | } |
| 378 | |
| 379 | static int adjust_jump_slot(DisasContext *dc, uint32_t dest, int slot) |
| 380 | { |
| 381 | return translator_use_goto_tb(&dc->base, dest) ? slot : -1; |
| 382 | } |
| 383 | |
| 384 | static void gen_jumpi(DisasContext *dc, uint32_t dest, int slot) |
| 385 | { |
| 386 | gen_jump_slot(dc, tcg_constant_i32(dest), |
| 387 | adjust_jump_slot(dc, dest, slot)); |
| 388 | } |
| 389 | |
| 390 | static void gen_callw_slot(DisasContext *dc, int callinc, TCGv_i32 dest, |
| 391 | int slot) |
| 392 | { |
| 393 | tcg_gen_deposit_i32(cpu_SR[PS], cpu_SR[PS], |
| 394 | tcg_constant_i32(callinc), PS_CALLINC_SHIFT, PS_CALLINC_LEN); |
| 395 | tcg_gen_movi_i32(cpu_R[callinc << 2], |
| 396 | (callinc << 30) | (dc->base.pc_next & 0x3fffffff)); |
| 397 | gen_jump_slot(dc, dest, slot); |
| 398 | } |
| 399 | |
| 400 | static bool gen_check_loop_end(DisasContext *dc, int slot) |
| 401 | { |
| 402 | if (dc->base.pc_next == dc->lend) { |
| 403 | TCGLabel *label = gen_new_label(); |
| 404 | |
| 405 | tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_SR[LCOUNT], 0, label); |
| 406 | tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_SR[LCOUNT], 1); |
| 407 | if (dc->lbeg_off) { |
| 408 | gen_jumpi(dc, dc->base.pc_next - dc->lbeg_off, slot); |
| 409 | } else { |
| 410 | gen_jump(dc, cpu_SR[LBEG]); |
| 411 | } |
| 412 | gen_set_label(label); |
| 413 | gen_jumpi(dc, dc->base.pc_next, -1); |
| 414 | return true; |
| 415 | } |
| 416 | return false; |
| 417 | } |
| 418 | |
| 419 | static void gen_jumpi_check_loop_end(DisasContext *dc, int slot) |
| 420 | { |
| 421 | if (!gen_check_loop_end(dc, slot)) { |
| 422 | gen_jumpi(dc, dc->base.pc_next, slot); |
| 423 | } |
| 424 | } |
| 425 | |
| 426 | static void gen_brcond(DisasContext *dc, TCGCond cond, |
| 427 | TCGv_i32 t0, TCGv_i32 t1, uint32_t addr) |
| 428 | { |
| 429 | TCGLabel *label = gen_new_label(); |
| 430 | |
| 431 | tcg_gen_brcond_i32(cond, t0, t1, label); |
| 432 | gen_jumpi_check_loop_end(dc, 0); |
| 433 | gen_set_label(label); |
| 434 | gen_jumpi(dc, addr, 1); |
| 435 | } |
| 436 | |
| 437 | static void gen_brcondi(DisasContext *dc, TCGCond cond, |
| 438 | TCGv_i32 t0, uint32_t t1, uint32_t addr) |
| 439 | { |
| 440 | gen_brcond(dc, cond, t0, tcg_constant_i32(t1), addr); |
| 441 | } |
| 442 | |
| 443 | static uint32_t test_exceptions_sr(DisasContext *dc, const OpcodeArg arg[], |
| 444 | const uint32_t par[]) |
| 445 | { |
| 446 | return xtensa_option_enabled(dc->config, par[1]) ? 0 : XTENSA_OP_ILL; |
| 447 | } |
| 448 | |
| 449 | static uint32_t test_exceptions_ccompare(DisasContext *dc, |
| 450 | const OpcodeArg arg[], |
| 451 | const uint32_t par[]) |
| 452 | { |
| 453 | unsigned n = par[0] - CCOMPARE; |
| 454 | |
| 455 | if (n >= dc->config->nccompare) { |
| 456 | return XTENSA_OP_ILL; |
| 457 | } |
| 458 | return test_exceptions_sr(dc, arg, par); |
| 459 | } |
| 460 | |
| 461 | static uint32_t test_exceptions_dbreak(DisasContext *dc, const OpcodeArg arg[], |
| 462 | const uint32_t par[]) |
| 463 | { |
| 464 | unsigned n = MAX_NDBREAK; |
| 465 | |
| 466 | if (par[0] >= DBREAKA && par[0] < DBREAKA + MAX_NDBREAK) { |
| 467 | n = par[0] - DBREAKA; |
| 468 | } |
| 469 | if (par[0] >= DBREAKC && par[0] < DBREAKC + MAX_NDBREAK) { |
| 470 | n = par[0] - DBREAKC; |
| 471 | } |
| 472 | if (n >= dc->config->ndbreak) { |
| 473 | return XTENSA_OP_ILL; |
| 474 | } |
| 475 | return test_exceptions_sr(dc, arg, par); |
| 476 | } |
| 477 | |
| 478 | static uint32_t test_exceptions_ibreak(DisasContext *dc, const OpcodeArg arg[], |
| 479 | const uint32_t par[]) |
| 480 | { |
| 481 | unsigned n = par[0] - IBREAKA; |
| 482 | |
| 483 | if (n >= dc->config->nibreak) { |
| 484 | return XTENSA_OP_ILL; |
| 485 | } |
| 486 | return test_exceptions_sr(dc, arg, par); |
| 487 | } |
| 488 | |
| 489 | static uint32_t test_exceptions_hpi(DisasContext *dc, const OpcodeArg arg[], |
| 490 | const uint32_t par[]) |
| 491 | { |
| 492 | unsigned n = MAX_NLEVEL + 1; |
| 493 | |
| 494 | if (par[0] >= EXCSAVE1 && par[0] < EXCSAVE1 + MAX_NLEVEL) { |
| 495 | n = par[0] - EXCSAVE1 + 1; |
| 496 | } |
| 497 | if (par[0] >= EPC1 && par[0] < EPC1 + MAX_NLEVEL) { |
| 498 | n = par[0] - EPC1 + 1; |
| 499 | } |
| 500 | if (par[0] >= EPS2 && par[0] < EPS2 + MAX_NLEVEL - 1) { |
| 501 | n = par[0] - EPS2 + 2; |
| 502 | } |
| 503 | if (n > dc->config->nlevel) { |
| 504 | return XTENSA_OP_ILL; |
| 505 | } |
| 506 | return test_exceptions_sr(dc, arg, par); |
| 507 | } |
| 508 | |
| 509 | static MemOp gen_load_store_alignment(DisasContext *dc, MemOp mop, |
| 510 | TCGv_i32 addr) |
| 511 | { |
| 512 | if ((mop & MO_SIZE) == MO_8) { |
| 513 | return mop; |
| 514 | } |
| 515 | if ((mop & MO_AMASK) == MO_UNALN && |
| 516 | !option_enabled(dc, XTENSA_OPTION_HW_ALIGNMENT)) { |
| 517 | mop |= MO_ALIGN; |
| 518 | } |
| 519 | if (!option_enabled(dc, XTENSA_OPTION_UNALIGNED_EXCEPTION)) { |
| 520 | tcg_gen_andi_i32(addr, addr, ~0 << memop_alignment_bits(mop)); |
| 521 | } |
| 522 | return mop; |
| 523 | } |
| 524 | |
| 525 | static bool gen_window_check(DisasContext *dc, uint32_t mask) |
| 526 | { |
| 527 | unsigned r = 31 - clz32(mask); |
| 528 | |
| 529 | if (r / 4 > dc->window) { |
| 530 | TCGv_i32 pc = tcg_constant_i32(dc->pc); |
| 531 | TCGv_i32 w = tcg_constant_i32(r / 4); |
| 532 | |
| 533 | gen_helper_window_check(tcg_env, pc, w); |
| 534 | dc->base.is_jmp = DISAS_NORETURN; |
| 535 | return false; |
| 536 | } |
| 537 | return true; |
| 538 | } |
| 539 | |
| 540 | static TCGv_i32 gen_mac16_m(TCGv_i32 v, bool hi, bool is_unsigned) |
| 541 | { |
| 542 | TCGv_i32 m = tcg_temp_new_i32(); |
| 543 | |
| 544 | if (hi) { |
| 545 | (is_unsigned ? tcg_gen_shri_i32 : tcg_gen_sari_i32)(m, v, 16); |
| 546 | } else { |
| 547 | (is_unsigned ? tcg_gen_ext16u_i32 : tcg_gen_ext16s_i32)(m, v); |
| 548 | } |
| 549 | return m; |
| 550 | } |
| 551 | |
| 552 | static void gen_zero_check(DisasContext *dc, const OpcodeArg arg[]) |
| 553 | { |
| 554 | TCGLabel *label = gen_new_label(); |
| 555 | |
| 556 | tcg_gen_brcondi_i32(TCG_COND_NE, arg[2].in, 0, label); |
| 557 | gen_exception_cause(dc, INTEGER_DIVIDE_BY_ZERO_CAUSE); |
| 558 | gen_set_label(label); |
| 559 | } |
| 560 | |
| 561 | static inline unsigned xtensa_op0_insn_len(DisasContext *dc, uint8_t op0) |
| 562 | { |
| 563 | return xtensa_isa_length_from_chars(dc->config->isa, &op0); |
| 564 | } |
| 565 | |
| 566 | static int gen_postprocess(DisasContext *dc, int slot) |
| 567 | { |
| 568 | uint32_t op_flags = dc->op_flags; |
| 569 | |
| 570 | #ifndef CONFIG_USER_ONLY |
| 571 | if (op_flags & XTENSA_OP_CHECK_INTERRUPTS) { |
| 572 | translator_io_start(&dc->base); |
| 573 | gen_helper_check_interrupts(tcg_env); |
| 574 | } |
| 575 | #endif |
| 576 | if (op_flags & XTENSA_OP_SYNC_REGISTER_WINDOW) { |
| 577 | gen_helper_sync_windowbase(tcg_env); |
| 578 | } |
| 579 | if (op_flags & XTENSA_OP_EXIT_TB_M1) { |
| 580 | slot = -1; |
| 581 | } |
| 582 | return slot; |
| 583 | } |
| 584 | |
| 585 | struct opcode_arg_copy { |
| 586 | uint32_t resource; |
| 587 | void *temp; |
| 588 | OpcodeArg *arg; |
| 589 | }; |
| 590 | |
| 591 | struct opcode_arg_info { |
| 592 | uint32_t resource; |
| 593 | int index; |
| 594 | }; |
| 595 | |
| 596 | struct slot_prop { |
| 597 | XtensaOpcodeOps *ops; |
| 598 | OpcodeArg arg[MAX_OPCODE_ARGS]; |
| 599 | struct opcode_arg_info in[MAX_OPCODE_ARGS]; |
| 600 | struct opcode_arg_info out[MAX_OPCODE_ARGS]; |
| 601 | unsigned n_in; |
| 602 | unsigned n_out; |
| 603 | uint32_t op_flags; |
| 604 | }; |
| 605 | |
| 606 | enum resource_type { |
| 607 | RES_REGFILE, |
| 608 | RES_STATE, |
| 609 | RES_MAX, |
| 610 | }; |
| 611 | |
| 612 | static uint32_t encode_resource(enum resource_type r, unsigned g, unsigned n) |
| 613 | { |
| 614 | assert(r < RES_MAX && g < 256 && n < 65536); |
| 615 | return (r << 24) | (g << 16) | n; |
| 616 | } |
| 617 | |
| 618 | static enum resource_type get_resource_type(uint32_t resource) |
| 619 | { |
| 620 | return resource >> 24; |
| 621 | } |
| 622 | |
| 623 | /* |
| 624 | * a depends on b if b must be executed before a, |
| 625 | * because a's side effects will destroy b's inputs. |
| 626 | */ |
| 627 | static bool op_depends_on(const struct slot_prop *a, |
| 628 | const struct slot_prop *b) |
| 629 | { |
| 630 | unsigned i = 0; |
| 631 | unsigned j = 0; |
| 632 | |
| 633 | if (a->op_flags & XTENSA_OP_CONTROL_FLOW) { |
| 634 | return true; |
| 635 | } |
| 636 | if ((a->op_flags & XTENSA_OP_LOAD_STORE) < |
| 637 | (b->op_flags & XTENSA_OP_LOAD_STORE)) { |
| 638 | return true; |
| 639 | } |
| 640 | while (i < a->n_out && j < b->n_in) { |
| 641 | if (a->out[i].resource < b->in[j].resource) { |
| 642 | ++i; |
| 643 | } else if (a->out[i].resource > b->in[j].resource) { |
| 644 | ++j; |
| 645 | } else { |
| 646 | return true; |
| 647 | } |
| 648 | } |
| 649 | return false; |
| 650 | } |
| 651 | |
| 652 | /* |
| 653 | * Try to break a dependency on b, append temporary register copy records |
| 654 | * to the end of copy and update n_copy in case of success. |
| 655 | * This is not always possible: e.g. control flow must always be the last, |
| 656 | * load/store must be first and state dependencies are not supported yet. |
| 657 | */ |
| 658 | static bool break_dependency(struct slot_prop *a, |
| 659 | struct slot_prop *b, |
| 660 | struct opcode_arg_copy *copy, |
| 661 | unsigned *n_copy) |
| 662 | { |
| 663 | unsigned i = 0; |
| 664 | unsigned j = 0; |
| 665 | unsigned n = *n_copy; |
| 666 | bool rv = false; |
| 667 | |
| 668 | if (a->op_flags & XTENSA_OP_CONTROL_FLOW) { |
| 669 | return false; |
| 670 | } |
| 671 | if ((a->op_flags & XTENSA_OP_LOAD_STORE) < |
| 672 | (b->op_flags & XTENSA_OP_LOAD_STORE)) { |
| 673 | return false; |
| 674 | } |
| 675 | while (i < a->n_out && j < b->n_in) { |
| 676 | if (a->out[i].resource < b->in[j].resource) { |
| 677 | ++i; |
| 678 | } else if (a->out[i].resource > b->in[j].resource) { |
| 679 | ++j; |
| 680 | } else { |
| 681 | int index = b->in[j].index; |
| 682 | |
| 683 | if (get_resource_type(a->out[i].resource) != RES_REGFILE || |
| 684 | index < 0) { |
| 685 | return false; |
| 686 | } |
| 687 | copy[n].resource = b->in[j].resource; |
| 688 | copy[n].arg = b->arg + index; |
| 689 | ++n; |
| 690 | ++j; |
| 691 | rv = true; |
| 692 | } |
| 693 | } |
| 694 | *n_copy = n; |
| 695 | return rv; |
| 696 | } |
| 697 | |
| 698 | /* |
| 699 | * Calculate evaluation order for slot opcodes. |
| 700 | * Build opcode order graph and output its nodes in topological sort order. |
| 701 | * An edge a -> b in the graph means that opcode a must be followed by |
| 702 | * opcode b. |
| 703 | */ |
| 704 | static bool tsort(struct slot_prop *slot, |
| 705 | struct slot_prop *sorted[], |
| 706 | unsigned n, |
| 707 | struct opcode_arg_copy *copy, |
| 708 | unsigned *n_copy) |
| 709 | { |
| 710 | struct tsnode { |
| 711 | unsigned n_in_edge; |
| 712 | unsigned n_out_edge; |
| 713 | unsigned out_edge[MAX_INSN_SLOTS]; |
| 714 | } node[MAX_INSN_SLOTS]; |
| 715 | |
| 716 | unsigned in[MAX_INSN_SLOTS]; |
| 717 | unsigned i, j; |
| 718 | unsigned n_in = 0; |
| 719 | unsigned n_out = 0; |
| 720 | unsigned n_edge = 0; |
| 721 | unsigned in_idx = 0; |
| 722 | unsigned node_idx = 0; |
| 723 | |
| 724 | for (i = 0; i < n; ++i) { |
| 725 | node[i].n_in_edge = 0; |
| 726 | node[i].n_out_edge = 0; |
| 727 | } |
| 728 | |
| 729 | for (i = 0; i < n; ++i) { |
| 730 | unsigned n_out_edge = 0; |
| 731 | |
| 732 | for (j = 0; j < n; ++j) { |
| 733 | if (i != j && op_depends_on(slot + j, slot + i)) { |
| 734 | node[i].out_edge[n_out_edge] = j; |
| 735 | ++node[j].n_in_edge; |
| 736 | ++n_out_edge; |
| 737 | ++n_edge; |
| 738 | } |
| 739 | } |
| 740 | node[i].n_out_edge = n_out_edge; |
| 741 | } |
| 742 | |
| 743 | for (i = 0; i < n; ++i) { |
| 744 | if (!node[i].n_in_edge) { |
| 745 | in[n_in] = i; |
| 746 | ++n_in; |
| 747 | } |
| 748 | } |
| 749 | |
| 750 | again: |
| 751 | for (; in_idx < n_in; ++in_idx) { |
| 752 | i = in[in_idx]; |
| 753 | sorted[n_out] = slot + i; |
| 754 | ++n_out; |
| 755 | for (j = 0; j < node[i].n_out_edge; ++j) { |
| 756 | --n_edge; |
| 757 | if (--node[node[i].out_edge[j]].n_in_edge == 0) { |
| 758 | in[n_in] = node[i].out_edge[j]; |
| 759 | ++n_in; |
| 760 | } |
| 761 | } |
| 762 | } |
| 763 | if (n_edge) { |
| 764 | for (; node_idx < n; ++node_idx) { |
| 765 | struct tsnode *cnode = node + node_idx; |
| 766 | |
| 767 | if (cnode->n_in_edge) { |
| 768 | for (j = 0; j < cnode->n_out_edge; ++j) { |
| 769 | unsigned k = cnode->out_edge[j]; |
| 770 | |
| 771 | if (break_dependency(slot + k, slot + node_idx, |
| 772 | copy, n_copy) && |
| 773 | --node[k].n_in_edge == 0) { |
| 774 | in[n_in] = k; |
| 775 | ++n_in; |
| 776 | --n_edge; |
| 777 | cnode->out_edge[j] = |
| 778 | cnode->out_edge[cnode->n_out_edge - 1]; |
| 779 | --cnode->n_out_edge; |
| 780 | goto again; |
| 781 | } |
| 782 | } |
| 783 | } |
| 784 | } |
| 785 | } |
| 786 | return n_edge == 0; |
| 787 | } |
| 788 | |
| 789 | static void opcode_add_resource(struct slot_prop *op, |
| 790 | uint32_t resource, char direction, |
| 791 | int index) |
| 792 | { |
| 793 | switch (direction) { |
| 794 | case 'm': |
| 795 | case 'i': |
| 796 | assert(op->n_in < ARRAY_SIZE(op->in)); |
| 797 | op->in[op->n_in].resource = resource; |
| 798 | op->in[op->n_in].index = index; |
| 799 | ++op->n_in; |
| 800 | /* fall through */ |
| 801 | case 'o': |
| 802 | if (direction == 'm' || direction == 'o') { |
| 803 | assert(op->n_out < ARRAY_SIZE(op->out)); |
| 804 | op->out[op->n_out].resource = resource; |
| 805 | op->out[op->n_out].index = index; |
| 806 | ++op->n_out; |
| 807 | } |
| 808 | break; |
| 809 | default: |
| 810 | g_assert_not_reached(); |
| 811 | } |
| 812 | } |
| 813 | |
| 814 | static int resource_compare(const void *a, const void *b) |
| 815 | { |
| 816 | const struct opcode_arg_info *pa = a; |
| 817 | const struct opcode_arg_info *pb = b; |
| 818 | |
| 819 | return pa->resource < pb->resource ? |
| 820 | -1 : (pa->resource > pb->resource ? 1 : 0); |
| 821 | } |
| 822 | |
| 823 | static int arg_copy_compare(const void *a, const void *b) |
| 824 | { |
| 825 | const struct opcode_arg_copy *pa = a; |
| 826 | const struct opcode_arg_copy *pb = b; |
| 827 | |
| 828 | return pa->resource < pb->resource ? |
| 829 | -1 : (pa->resource > pb->resource ? 1 : 0); |
| 830 | } |
| 831 | |
| 832 | static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) |
| 833 | { |
| 834 | xtensa_isa isa = dc->config->isa; |
| 835 | unsigned char b[MAX_INSN_LENGTH] = {translator_ldub(env, &dc->base, |
| 836 | dc->pc)}; |
| 837 | unsigned len = xtensa_op0_insn_len(dc, b[0]); |
| 838 | xtensa_format fmt; |
| 839 | int slot, slots; |
| 840 | unsigned i; |
| 841 | uint32_t op_flags = 0; |
| 842 | struct slot_prop slot_prop[MAX_INSN_SLOTS]; |
| 843 | struct slot_prop *ordered[MAX_INSN_SLOTS]; |
| 844 | struct opcode_arg_copy arg_copy[MAX_INSN_SLOTS * MAX_OPCODE_ARGS]; |
| 845 | unsigned n_arg_copy = 0; |
| 846 | uint32_t debug_cause = 0; |
| 847 | uint32_t windowed_register = 0; |
| 848 | uint32_t coprocessor = 0; |
| 849 | |
| 850 | if (len == XTENSA_UNDEFINED) { |
| 851 | qemu_log_mask(LOG_GUEST_ERROR, |
| 852 | "unknown instruction length (pc = %08x)\n", |
| 853 | dc->pc); |
| 854 | gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); |
| 855 | dc->base.pc_next = dc->pc + 1; |
| 856 | return; |
| 857 | } |
| 858 | |
| 859 | dc->base.pc_next = dc->pc + len; |
| 860 | for (i = 1; i < len; ++i) { |
| 861 | b[i] = translator_ldub(env, &dc->base, dc->pc + i); |
| 862 | } |
| 863 | xtensa_insnbuf_from_chars(isa, dc->insnbuf, b, len); |
| 864 | fmt = xtensa_format_decode(isa, dc->insnbuf); |
| 865 | if (fmt == XTENSA_UNDEFINED) { |
| 866 | qemu_log_mask(LOG_GUEST_ERROR, |
| 867 | "unrecognized instruction format (pc = %08x)\n", |
| 868 | dc->pc); |
| 869 | gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); |
| 870 | return; |
| 871 | } |
| 872 | slots = xtensa_format_num_slots(isa, fmt); |
| 873 | for (slot = 0; slot < slots; ++slot) { |
| 874 | xtensa_opcode opc; |
| 875 | int opnd, vopnd, opnds; |
| 876 | OpcodeArg *arg = slot_prop[slot].arg; |
| 877 | XtensaOpcodeOps *ops; |
| 878 | |
| 879 | xtensa_format_get_slot(isa, fmt, slot, dc->insnbuf, dc->slotbuf); |
| 880 | opc = xtensa_opcode_decode(isa, fmt, slot, dc->slotbuf); |
| 881 | if (opc == XTENSA_UNDEFINED) { |
| 882 | qemu_log_mask(LOG_GUEST_ERROR, |
| 883 | "unrecognized opcode in slot %d (pc = %08x)\n", |
| 884 | slot, dc->pc); |
| 885 | gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); |
| 886 | return; |
| 887 | } |
| 888 | opnds = xtensa_opcode_num_operands(isa, opc); |
| 889 | |
| 890 | for (opnd = vopnd = 0; opnd < opnds; ++opnd) { |
| 891 | void **register_file = NULL; |
| 892 | xtensa_regfile rf; |
| 893 | |
| 894 | if (xtensa_operand_is_register(isa, opc, opnd)) { |
| 895 | rf = xtensa_operand_regfile(isa, opc, opnd); |
| 896 | register_file = dc->config->regfile[rf]; |
| 897 | |
| 898 | if (rf == dc->config->a_regfile) { |
| 899 | uint32_t v; |
| 900 | |
| 901 | xtensa_operand_get_field(isa, opc, opnd, fmt, slot, |
| 902 | dc->slotbuf, &v); |
| 903 | xtensa_operand_decode(isa, opc, opnd, &v); |
| 904 | windowed_register |= 1u << v; |
| 905 | } |
| 906 | } |
| 907 | if (xtensa_operand_is_visible(isa, opc, opnd)) { |
| 908 | uint32_t v; |
| 909 | |
| 910 | xtensa_operand_get_field(isa, opc, opnd, fmt, slot, |
| 911 | dc->slotbuf, &v); |
| 912 | xtensa_operand_decode(isa, opc, opnd, &v); |
| 913 | arg[vopnd].raw_imm = v; |
| 914 | if (xtensa_operand_is_PCrelative(isa, opc, opnd)) { |
| 915 | xtensa_operand_undo_reloc(isa, opc, opnd, &v, dc->pc); |
| 916 | } |
| 917 | arg[vopnd].imm = v; |
| 918 | if (register_file) { |
| 919 | arg[vopnd].in = register_file[v]; |
| 920 | arg[vopnd].out = register_file[v]; |
| 921 | arg[vopnd].num_bits = xtensa_regfile_num_bits(isa, rf); |
| 922 | } else { |
| 923 | arg[vopnd].num_bits = 32; |
| 924 | } |
| 925 | ++vopnd; |
| 926 | } |
| 927 | } |
| 928 | ops = dc->config->opcode_ops[opc]; |
| 929 | slot_prop[slot].ops = ops; |
| 930 | |
| 931 | if (ops) { |
| 932 | op_flags |= ops->op_flags; |
| 933 | if (ops->test_exceptions) { |
| 934 | op_flags |= ops->test_exceptions(dc, arg, ops->par); |
| 935 | } |
| 936 | } else { |
| 937 | qemu_log_mask(LOG_UNIMP, |
| 938 | "unimplemented opcode '%s' in slot %d (pc = %08x)\n", |
| 939 | xtensa_opcode_name(isa, opc), slot, dc->pc); |
| 940 | op_flags |= XTENSA_OP_ILL; |
| 941 | } |
| 942 | if (op_flags & XTENSA_OP_ILL) { |
| 943 | gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); |
| 944 | return; |
| 945 | } |
| 946 | if (op_flags & XTENSA_OP_DEBUG_BREAK) { |
| 947 | debug_cause |= ops->par[0]; |
| 948 | } |
| 949 | if (ops->test_overflow) { |
| 950 | windowed_register |= ops->test_overflow(dc, arg, ops->par); |
| 951 | } |
| 952 | coprocessor |= ops->coprocessor; |
| 953 | |
| 954 | if (slots > 1) { |
| 955 | slot_prop[slot].n_in = 0; |
| 956 | slot_prop[slot].n_out = 0; |
| 957 | slot_prop[slot].op_flags = ops->op_flags & XTENSA_OP_LOAD_STORE; |
| 958 | |
| 959 | opnds = xtensa_opcode_num_operands(isa, opc); |
| 960 | |
| 961 | for (opnd = vopnd = 0; opnd < opnds; ++opnd) { |
| 962 | bool visible = xtensa_operand_is_visible(isa, opc, opnd); |
| 963 | |
| 964 | if (xtensa_operand_is_register(isa, opc, opnd)) { |
| 965 | xtensa_regfile rf = xtensa_operand_regfile(isa, opc, opnd); |
| 966 | uint32_t v = 0; |
| 967 | |
| 968 | xtensa_operand_get_field(isa, opc, opnd, fmt, slot, |
| 969 | dc->slotbuf, &v); |
| 970 | xtensa_operand_decode(isa, opc, opnd, &v); |
| 971 | opcode_add_resource(slot_prop + slot, |
| 972 | encode_resource(RES_REGFILE, rf, v), |
| 973 | xtensa_operand_inout(isa, opc, opnd), |
| 974 | visible ? vopnd : -1); |
| 975 | } |
| 976 | if (visible) { |
| 977 | ++vopnd; |
| 978 | } |
| 979 | } |
| 980 | |
| 981 | opnds = xtensa_opcode_num_stateOperands(isa, opc); |
| 982 | |
| 983 | for (opnd = 0; opnd < opnds; ++opnd) { |
| 984 | xtensa_state state = xtensa_stateOperand_state(isa, opc, opnd); |
| 985 | |
| 986 | opcode_add_resource(slot_prop + slot, |
| 987 | encode_resource(RES_STATE, 0, state), |
| 988 | xtensa_stateOperand_inout(isa, opc, opnd), |
| 989 | -1); |
| 990 | } |
| 991 | if (xtensa_opcode_is_branch(isa, opc) || |
| 992 | xtensa_opcode_is_jump(isa, opc) || |
| 993 | xtensa_opcode_is_loop(isa, opc) || |
| 994 | xtensa_opcode_is_call(isa, opc)) { |
| 995 | slot_prop[slot].op_flags |= XTENSA_OP_CONTROL_FLOW; |
| 996 | } |
| 997 | |
| 998 | qsort(slot_prop[slot].in, slot_prop[slot].n_in, |
| 999 | sizeof(slot_prop[slot].in[0]), resource_compare); |
| 1000 | qsort(slot_prop[slot].out, slot_prop[slot].n_out, |
| 1001 | sizeof(slot_prop[slot].out[0]), resource_compare); |
| 1002 | } |
| 1003 | } |
| 1004 | |
| 1005 | if (slots > 1) { |
| 1006 | if (!tsort(slot_prop, ordered, slots, arg_copy, &n_arg_copy)) { |
| 1007 | qemu_log_mask(LOG_UNIMP, |
| 1008 | "Circular resource dependencies (pc = %08x)\n", |
| 1009 | dc->pc); |
| 1010 | gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); |
| 1011 | return; |
| 1012 | } |
| 1013 | } else { |
| 1014 | ordered[0] = slot_prop + 0; |
| 1015 | } |
| 1016 | |
| 1017 | if ((op_flags & XTENSA_OP_PRIVILEGED) && |
| 1018 | !gen_check_privilege(dc)) { |
| 1019 | return; |
| 1020 | } |
| 1021 | |
| 1022 | if (op_flags & XTENSA_OP_SYSCALL) { |
| 1023 | gen_exception_cause(dc, SYSCALL_CAUSE); |
| 1024 | return; |
| 1025 | } |
| 1026 | |
| 1027 | if ((op_flags & XTENSA_OP_DEBUG_BREAK) && dc->debug) { |
| 1028 | gen_debug_exception(dc, debug_cause); |
| 1029 | return; |
| 1030 | } |
| 1031 | |
| 1032 | if (windowed_register && !gen_window_check(dc, windowed_register)) { |
| 1033 | return; |
| 1034 | } |
| 1035 | |
| 1036 | if (op_flags & XTENSA_OP_UNDERFLOW) { |
| 1037 | TCGv_i32 pc = tcg_constant_i32(dc->pc); |
| 1038 | |
| 1039 | gen_helper_test_underflow_retw(tcg_env, pc); |
| 1040 | } |
| 1041 | |
| 1042 | if (op_flags & XTENSA_OP_ALLOCA) { |
| 1043 | TCGv_i32 pc = tcg_constant_i32(dc->pc); |
| 1044 | |
| 1045 | gen_helper_movsp(tcg_env, pc); |
| 1046 | } |
| 1047 | |
| 1048 | if (coprocessor && !gen_check_cpenable(dc, coprocessor)) { |
| 1049 | return; |
| 1050 | } |
| 1051 | |
| 1052 | if (n_arg_copy) { |
| 1053 | uint32_t resource; |
| 1054 | void *temp; |
| 1055 | unsigned j; |
| 1056 | |
| 1057 | qsort(arg_copy, n_arg_copy, sizeof(*arg_copy), arg_copy_compare); |
| 1058 | for (i = j = 0; i < n_arg_copy; ++i) { |
| 1059 | if (i == 0 || arg_copy[i].resource != resource) { |
| 1060 | resource = arg_copy[i].resource; |
| 1061 | if (arg_copy[i].arg->num_bits <= 32) { |
| 1062 | temp = tcg_temp_new_i32(); |
| 1063 | tcg_gen_mov_i32(temp, arg_copy[i].arg->in); |
| 1064 | } else if (arg_copy[i].arg->num_bits <= 64) { |
| 1065 | temp = tcg_temp_new_i64(); |
| 1066 | tcg_gen_mov_i64(temp, arg_copy[i].arg->in); |
| 1067 | } else { |
| 1068 | g_assert_not_reached(); |
| 1069 | } |
| 1070 | arg_copy[i].temp = temp; |
| 1071 | |
| 1072 | if (i != j) { |
| 1073 | arg_copy[j] = arg_copy[i]; |
| 1074 | } |
| 1075 | ++j; |
| 1076 | } |
| 1077 | arg_copy[i].arg->in = temp; |
| 1078 | } |
| 1079 | n_arg_copy = j; |
| 1080 | } |
| 1081 | |
| 1082 | if (op_flags & XTENSA_OP_DIVIDE_BY_ZERO) { |
| 1083 | for (slot = 0; slot < slots; ++slot) { |
| 1084 | if (slot_prop[slot].ops->op_flags & XTENSA_OP_DIVIDE_BY_ZERO) { |
| 1085 | gen_zero_check(dc, slot_prop[slot].arg); |
| 1086 | } |
| 1087 | } |
| 1088 | } |
| 1089 | |
| 1090 | dc->op_flags = op_flags; |
| 1091 | |
| 1092 | for (slot = 0; slot < slots; ++slot) { |
| 1093 | struct slot_prop *pslot = ordered[slot]; |
| 1094 | XtensaOpcodeOps *ops = pslot->ops; |
| 1095 | |
| 1096 | ops->translate(dc, pslot->arg, ops->par); |
| 1097 | } |
| 1098 | |
| 1099 | if (dc->base.is_jmp == DISAS_NEXT) { |
| 1100 | gen_postprocess(dc, 0); |
| 1101 | dc->op_flags = 0; |
| 1102 | if (op_flags & XTENSA_OP_EXIT_TB_M1) { |
| 1103 | /* Change in mmu index, memory mapping or tb->flags; exit tb */ |
| 1104 | gen_jumpi_check_loop_end(dc, -1); |
| 1105 | } else if (op_flags & XTENSA_OP_EXIT_TB_0) { |
| 1106 | gen_jumpi_check_loop_end(dc, 0); |
| 1107 | } else { |
| 1108 | gen_check_loop_end(dc, 0); |
| 1109 | } |
| 1110 | } |
| 1111 | dc->pc = dc->base.pc_next; |
| 1112 | } |
| 1113 | |
| 1114 | static inline unsigned xtensa_insn_len(CPUXtensaState *env, DisasContext *dc) |
| 1115 | { |
| 1116 | uint8_t b0 = translator_ldub(env, &dc->base, dc->pc); |
| 1117 | return xtensa_op0_insn_len(dc, b0); |
| 1118 | } |
| 1119 | |
| 1120 | static void xtensa_tr_init_disas_context(DisasContextBase *dcbase, |
| 1121 | CPUState *cpu) |
| 1122 | { |
| 1123 | DisasContext *dc = container_of(dcbase, DisasContext, base); |
| 1124 | uint32_t tb_flags = dc->base.tb->flags; |
| 1125 | |
| 1126 | dc->config = cpu_env(cpu)->config; |
| 1127 | dc->pc = dc->base.pc_first; |
| 1128 | dc->ring = tb_flags & XTENSA_TBFLAG_RING_MASK; |
| 1129 | dc->cring = (tb_flags & XTENSA_TBFLAG_EXCM) ? 0 : dc->ring; |
| 1130 | dc->lbeg_off = (dc->base.tb->cs_base & XTENSA_CSBASE_LBEG_OFF_MASK) >> |
| 1131 | XTENSA_CSBASE_LBEG_OFF_SHIFT; |
| 1132 | dc->lend = (dc->base.tb->cs_base & XTENSA_CSBASE_LEND_MASK) + |
| 1133 | (dc->base.pc_first & TARGET_PAGE_MASK); |
| 1134 | dc->debug = tb_flags & XTENSA_TBFLAG_DEBUG; |
| 1135 | dc->icount = tb_flags & XTENSA_TBFLAG_ICOUNT; |
| 1136 | dc->cpenable = (tb_flags & XTENSA_TBFLAG_CPENABLE_MASK) >> |
| 1137 | XTENSA_TBFLAG_CPENABLE_SHIFT; |
| 1138 | dc->window = ((tb_flags & XTENSA_TBFLAG_WINDOW_MASK) >> |
| 1139 | XTENSA_TBFLAG_WINDOW_SHIFT); |
| 1140 | dc->cwoe = tb_flags & XTENSA_TBFLAG_CWOE; |
| 1141 | dc->callinc = ((tb_flags & XTENSA_TBFLAG_CALLINC_MASK) >> |
| 1142 | XTENSA_TBFLAG_CALLINC_SHIFT); |
| 1143 | init_sar_tracker(dc); |
| 1144 | } |
| 1145 | |
| 1146 | static void xtensa_tr_tb_start(DisasContextBase *dcbase, CPUState *cpu) |
| 1147 | { |
| 1148 | DisasContext *dc = container_of(dcbase, DisasContext, base); |
| 1149 | |
| 1150 | if (dc->icount) { |
| 1151 | dc->next_icount = tcg_temp_new_i32(); |
| 1152 | } |
| 1153 | } |
| 1154 | |
| 1155 | static void xtensa_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) |
| 1156 | { |
| 1157 | tcg_gen_insn_start(dcbase->pc_next, 0, 0); |
| 1158 | } |
| 1159 | |
| 1160 | static void xtensa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) |
| 1161 | { |
| 1162 | DisasContext *dc = container_of(dcbase, DisasContext, base); |
| 1163 | CPUXtensaState *env = cpu_env(cpu); |
| 1164 | vaddr page_start; |
| 1165 | |
| 1166 | /* These two conditions only apply to the first insn in the TB, |
| 1167 | but this is the first TranslateOps hook that allows exiting. */ |
| 1168 | if ((tb_cflags(dc->base.tb) & CF_USE_ICOUNT) |
| 1169 | && (dc->base.tb->flags & XTENSA_TBFLAG_YIELD)) { |
| 1170 | gen_exception(dc, EXCP_YIELD); |
| 1171 | dc->base.pc_next = dc->pc + 1; |
| 1172 | dc->base.is_jmp = DISAS_NORETURN; |
| 1173 | return; |
| 1174 | } |
| 1175 | |
| 1176 | if (dc->icount) { |
| 1177 | TCGLabel *label = gen_new_label(); |
| 1178 | |
| 1179 | tcg_gen_addi_i32(dc->next_icount, cpu_SR[ICOUNT], 1); |
| 1180 | tcg_gen_brcondi_i32(TCG_COND_NE, dc->next_icount, 0, label); |
| 1181 | tcg_gen_mov_i32(dc->next_icount, cpu_SR[ICOUNT]); |
| 1182 | if (dc->debug) { |
| 1183 | gen_debug_exception(dc, DEBUGCAUSE_IC); |
| 1184 | } |
| 1185 | gen_set_label(label); |
| 1186 | } |
| 1187 | |
| 1188 | disas_xtensa_insn(env, dc); |
| 1189 | |
| 1190 | if (dc->icount) { |
| 1191 | tcg_gen_mov_i32(cpu_SR[ICOUNT], dc->next_icount); |
| 1192 | } |
| 1193 | |
| 1194 | /* End the TB if the next insn will cross into the next page. */ |
| 1195 | page_start = dc->base.pc_first & TARGET_PAGE_MASK; |
| 1196 | if (dc->base.is_jmp == DISAS_NEXT && |
| 1197 | (dc->pc - page_start >= TARGET_PAGE_SIZE || |
| 1198 | dc->pc - page_start + xtensa_insn_len(env, dc) > TARGET_PAGE_SIZE)) { |
| 1199 | dc->base.is_jmp = DISAS_TOO_MANY; |
| 1200 | } |
| 1201 | } |
| 1202 | |
| 1203 | static void xtensa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) |
| 1204 | { |
| 1205 | DisasContext *dc = container_of(dcbase, DisasContext, base); |
| 1206 | |
| 1207 | switch (dc->base.is_jmp) { |
| 1208 | case DISAS_NORETURN: |
| 1209 | break; |
| 1210 | case DISAS_TOO_MANY: |
| 1211 | gen_jumpi(dc, dc->pc, 0); |
| 1212 | break; |
| 1213 | default: |
| 1214 | g_assert_not_reached(); |
| 1215 | } |
| 1216 | } |
| 1217 | |
| 1218 | static const TranslatorOps xtensa_translator_ops = { |
| 1219 | .init_disas_context = xtensa_tr_init_disas_context, |
| 1220 | .tb_start = xtensa_tr_tb_start, |
| 1221 | .insn_start = xtensa_tr_insn_start, |
| 1222 | .translate_insn = xtensa_tr_translate_insn, |
| 1223 | .tb_stop = xtensa_tr_tb_stop, |
| 1224 | }; |
| 1225 | |
| 1226 | void xtensa_translate_code(CPUState *cpu, TranslationBlock *tb, |
| 1227 | int *max_insns, vaddr pc, void *host_pc) |
| 1228 | { |
| 1229 | DisasContext dc = {}; |
| 1230 | translator_loop(cpu, tb, max_insns, pc, host_pc, |
| 1231 | &xtensa_translator_ops, &dc.base, |
| 1232 | TCG_TYPE_VA); |
| 1233 | } |
| 1234 | |
| 1235 | void xtensa_cpu_dump_state(CPUState *cs, FILE *f, int flags) |
| 1236 | { |
| 1237 | CPUXtensaState *env = cpu_env(cs); |
| 1238 | xtensa_isa isa = env->config->isa; |
| 1239 | int i, j; |
| 1240 | |
| 1241 | qemu_fprintf(f, "PC=%08x\n\n", env->pc); |
| 1242 | |
| 1243 | for (i = j = 0; i < xtensa_isa_num_sysregs(isa); ++i) { |
| 1244 | const uint32_t *reg = |
| 1245 | xtensa_sysreg_is_user(isa, i) ? env->uregs : env->sregs; |
| 1246 | int regno = xtensa_sysreg_number(isa, i); |
| 1247 | |
| 1248 | if (regno >= 0) { |
| 1249 | qemu_fprintf(f, "%12s=%08x%c", |
| 1250 | xtensa_sysreg_name(isa, i), |
| 1251 | reg[regno], |
| 1252 | (j++ % 4) == 3 ? '\n' : ' '); |
| 1253 | } |
| 1254 | } |
| 1255 | |
| 1256 | qemu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n"); |
| 1257 | |
| 1258 | for (i = 0; i < 16; ++i) { |
| 1259 | qemu_fprintf(f, " A%02d=%08x%c", |
| 1260 | i, env->regs[i], (i % 4) == 3 ? '\n' : ' '); |
| 1261 | } |
| 1262 | |
| 1263 | xtensa_sync_phys_from_window(env); |
| 1264 | qemu_fprintf(f, "\n"); |
| 1265 | |
| 1266 | for (i = 0; i < env->config->nareg; ++i) { |
| 1267 | qemu_fprintf(f, "AR%02d=%08x ", i, env->phys_regs[i]); |
| 1268 | if (i % 4 == 3) { |
| 1269 | bool ws = (env->sregs[WINDOW_START] & (1 << (i / 4))) != 0; |
| 1270 | bool cw = env->sregs[WINDOW_BASE] == i / 4; |
| 1271 | |
| 1272 | qemu_fprintf(f, "%c%c\n", ws ? '<' : ' ', cw ? '=' : ' '); |
| 1273 | } |
| 1274 | } |
| 1275 | |
| 1276 | if ((flags & CPU_DUMP_FPU) && |
| 1277 | xtensa_option_enabled(env->config, XTENSA_OPTION_FP_COPROCESSOR)) { |
| 1278 | qemu_fprintf(f, "\n"); |
| 1279 | |
| 1280 | for (i = 0; i < 16; ++i) { |
| 1281 | qemu_fprintf(f, "F%02d=%08x (%-+15.8e)%c", i, |
| 1282 | float32_val(env->fregs[i].f32[FP_F32_LOW]), |
| 1283 | *(float *)(env->fregs[i].f32 + FP_F32_LOW), |
| 1284 | (i % 2) == 1 ? '\n' : ' '); |
| 1285 | } |
| 1286 | } |
| 1287 | |
| 1288 | if ((flags & CPU_DUMP_FPU) && |
| 1289 | xtensa_option_enabled(env->config, XTENSA_OPTION_DFP_COPROCESSOR) && |
| 1290 | !xtensa_option_enabled(env->config, XTENSA_OPTION_DFPU_SINGLE_ONLY)) { |
| 1291 | qemu_fprintf(f, "\n"); |
| 1292 | |
| 1293 | for (i = 0; i < 16; ++i) { |
| 1294 | qemu_fprintf(f, "F%02d=%016"PRIx64" (%-+24.16le)%c", i, |
| 1295 | float64_val(env->fregs[i].f64), |
| 1296 | *(double *)(&env->fregs[i].f64), |
| 1297 | (i % 2) == 1 ? '\n' : ' '); |
| 1298 | } |
| 1299 | } |
| 1300 | } |
| 1301 | |
| 1302 | static void translate_abs(DisasContext *dc, const OpcodeArg arg[], |
| 1303 | const uint32_t par[]) |
| 1304 | { |
| 1305 | tcg_gen_abs_i32(arg[0].out, arg[1].in); |
| 1306 | } |
| 1307 | |
| 1308 | static void translate_add(DisasContext *dc, const OpcodeArg arg[], |
| 1309 | const uint32_t par[]) |
| 1310 | { |
| 1311 | tcg_gen_add_i32(arg[0].out, arg[1].in, arg[2].in); |
| 1312 | } |
| 1313 | |
| 1314 | static void translate_addi(DisasContext *dc, const OpcodeArg arg[], |
| 1315 | const uint32_t par[]) |
| 1316 | { |
| 1317 | tcg_gen_addi_i32(arg[0].out, arg[1].in, arg[2].imm); |
| 1318 | } |
| 1319 | |
| 1320 | static void translate_addx(DisasContext *dc, const OpcodeArg arg[], |
| 1321 | const uint32_t par[]) |
| 1322 | { |
| 1323 | TCGv_i32 tmp = tcg_temp_new_i32(); |
| 1324 | tcg_gen_shli_i32(tmp, arg[1].in, par[0]); |
| 1325 | tcg_gen_add_i32(arg[0].out, tmp, arg[2].in); |
| 1326 | } |
| 1327 | |
| 1328 | static void translate_all(DisasContext *dc, const OpcodeArg arg[], |
| 1329 | const uint32_t par[]) |
| 1330 | { |
| 1331 | uint32_t shift = par[1]; |
| 1332 | TCGv_i32 mask = tcg_constant_i32(((1 << shift) - 1) << arg[1].imm); |
| 1333 | TCGv_i32 tmp = tcg_temp_new_i32(); |
| 1334 | |
| 1335 | tcg_gen_and_i32(tmp, arg[1].in, mask); |
| 1336 | if (par[0]) { |
| 1337 | tcg_gen_addi_i32(tmp, tmp, 1 << arg[1].imm); |
| 1338 | } else { |
| 1339 | tcg_gen_add_i32(tmp, tmp, mask); |
| 1340 | } |
| 1341 | tcg_gen_shri_i32(tmp, tmp, arg[1].imm + shift); |
| 1342 | tcg_gen_deposit_i32(arg[0].out, arg[0].out, |
| 1343 | tmp, arg[0].imm, 1); |
| 1344 | } |
| 1345 | |
| 1346 | static void translate_and(DisasContext *dc, const OpcodeArg arg[], |
| 1347 | const uint32_t par[]) |
| 1348 | { |
| 1349 | tcg_gen_and_i32(arg[0].out, arg[1].in, arg[2].in); |
| 1350 | } |
| 1351 | |
| 1352 | static void translate_ball(DisasContext *dc, const OpcodeArg arg[], |
| 1353 | const uint32_t par[]) |
| 1354 | { |
| 1355 | TCGv_i32 tmp = tcg_temp_new_i32(); |
| 1356 | tcg_gen_and_i32(tmp, arg[0].in, arg[1].in); |
| 1357 | gen_brcond(dc, par[0], tmp, arg[1].in, arg[2].imm); |
| 1358 | } |
| 1359 | |
| 1360 | static void translate_bany(DisasContext *dc, const OpcodeArg arg[], |
| 1361 | const uint32_t par[]) |
| 1362 | { |
| 1363 | TCGv_i32 tmp = tcg_temp_new_i32(); |
| 1364 | tcg_gen_and_i32(tmp, arg[0].in, arg[1].in); |
| 1365 | gen_brcondi(dc, par[0], tmp, 0, arg[2].imm); |
| 1366 | } |
| 1367 | |
| 1368 | static void translate_b(DisasContext *dc, const OpcodeArg arg[], |
| 1369 | const uint32_t par[]) |
| 1370 | { |
| 1371 | gen_brcond(dc, par[0], arg[0].in, arg[1].in, arg[2].imm); |
| 1372 | } |
| 1373 | |
| 1374 | static void translate_bb(DisasContext *dc, const OpcodeArg arg[], |
| 1375 | const uint32_t par[]) |
| 1376 | { |
| 1377 | TCGv_i32 tmp = tcg_temp_new_i32(); |
| 1378 | |
| 1379 | tcg_gen_andi_i32(tmp, arg[1].in, 0x1f); |
| 1380 | if (TARGET_BIG_ENDIAN) { |
| 1381 | tcg_gen_shr_i32(tmp, tcg_constant_i32(0x80000000u), tmp); |
| 1382 | } else { |
| 1383 | tcg_gen_shl_i32(tmp, tcg_constant_i32(0x00000001u), tmp); |
| 1384 | } |
| 1385 | tcg_gen_and_i32(tmp, arg[0].in, tmp); |
| 1386 | gen_brcondi(dc, par[0], tmp, 0, arg[2].imm); |
| 1387 | } |
| 1388 | |
| 1389 | static void translate_bbi(DisasContext *dc, const OpcodeArg arg[], |
| 1390 | const uint32_t par[]) |
| 1391 | { |
| 1392 | TCGv_i32 tmp = tcg_temp_new_i32(); |
| 1393 | if (TARGET_BIG_ENDIAN) { |
| 1394 | tcg_gen_andi_i32(tmp, arg[0].in, 0x80000000u >> arg[1].imm); |
| 1395 | } else { |
| 1396 | tcg_gen_andi_i32(tmp, arg[0].in, 0x00000001u << arg[1].imm); |
| 1397 | } |
| 1398 | gen_brcondi(dc, par[0], tmp, 0, arg[2].imm); |
| 1399 | } |
| 1400 | |
| 1401 | static void translate_bi(DisasContext *dc, const OpcodeArg arg[], |
| 1402 | const uint32_t par[]) |
| 1403 | { |
| 1404 | gen_brcondi(dc, par[0], arg[0].in, arg[1].imm, arg[2].imm); |
| 1405 | } |
| 1406 | |
| 1407 | static void translate_bz(DisasContext *dc, const OpcodeArg arg[], |
| 1408 | const uint32_t par[]) |
| 1409 | { |
| 1410 | gen_brcondi(dc, par[0], arg[0].in, 0, arg[1].imm); |
| 1411 | } |
| 1412 | |
| 1413 | enum { |
| 1414 | BOOLEAN_AND, |
| 1415 | BOOLEAN_ANDC, |
| 1416 | BOOLEAN_OR, |
| 1417 | BOOLEAN_ORC, |
| 1418 | BOOLEAN_XOR, |
| 1419 | }; |
| 1420 | |
| 1421 | static void translate_boolean(DisasContext *dc, const OpcodeArg arg[], |
| 1422 | const uint32_t par[]) |
| 1423 | { |
| 1424 | static void (* const op[])(TCGv_i32, TCGv_i32, TCGv_i32) = { |
| 1425 | [BOOLEAN_AND] = tcg_gen_and_i32, |
| 1426 | [BOOLEAN_ANDC] = tcg_gen_andc_i32, |
| 1427 | [BOOLEAN_OR] = tcg_gen_or_i32, |
| 1428 | [BOOLEAN_ORC] = tcg_gen_orc_i32, |
| 1429 | [BOOLEAN_XOR] = tcg_gen_xor_i32, |
| 1430 | }; |
| 1431 | |
| 1432 | TCGv_i32 tmp1 = tcg_temp_new_i32(); |
| 1433 | TCGv_i32 tmp2 = tcg_temp_new_i32(); |
| 1434 | |
| 1435 | tcg_gen_shri_i32(tmp1, arg[1].in, arg[1].imm); |
| 1436 | tcg_gen_shri_i32(tmp2, arg[2].in, arg[2].imm); |
| 1437 | op[par[0]](tmp1, tmp1, tmp2); |
| 1438 | tcg_gen_deposit_i32(arg[0].out, arg[0].out, tmp1, arg[0].imm, 1); |
| 1439 | } |
| 1440 | |
| 1441 | static void translate_bp(DisasContext *dc, const OpcodeArg arg[], |
| 1442 | const uint32_t par[]) |
| 1443 | { |
| 1444 | TCGv_i32 tmp = tcg_temp_new_i32(); |
| 1445 | |
| 1446 | tcg_gen_andi_i32(tmp, arg[0].in, 1 << arg[0].imm); |
| 1447 | gen_brcondi(dc, par[0], tmp, 0, arg[1].imm); |
| 1448 | } |
| 1449 | |
| 1450 | static void translate_call0(DisasContext *dc, const OpcodeArg arg[], |
| 1451 | const uint32_t par[]) |
| 1452 | { |
| 1453 | tcg_gen_movi_i32(cpu_R[0], dc->base.pc_next); |
| 1454 | gen_jumpi(dc, arg[0].imm, 0); |
| 1455 | } |
| 1456 | |
| 1457 | static void translate_callw(DisasContext *dc, const OpcodeArg arg[], |
| 1458 | const uint32_t par[]) |
| 1459 | { |
| 1460 | TCGv_i32 tmp = tcg_constant_i32(arg[0].imm); |
| 1461 | gen_callw_slot(dc, par[0], tmp, adjust_jump_slot(dc, arg[0].imm, 0)); |
| 1462 | } |
| 1463 | |
| 1464 | static void translate_callx0(DisasContext *dc, const OpcodeArg arg[], |
| 1465 | const uint32_t par[]) |
| 1466 | { |
| 1467 | TCGv_i32 tmp = tcg_temp_new_i32(); |
| 1468 | tcg_gen_mov_i32(tmp, arg[0].in); |
| 1469 | tcg_gen_movi_i32(cpu_R[0], dc->base.pc_next); |
| 1470 | gen_jump(dc, tmp); |
| 1471 | } |
| 1472 | |
| 1473 | static void translate_callxw(DisasContext *dc, const OpcodeArg arg[], |
| 1474 | const uint32_t par[]) |
| 1475 | { |
| 1476 | TCGv_i32 tmp = tcg_temp_new_i32(); |
| 1477 | |
| 1478 | tcg_gen_mov_i32(tmp, arg[0].in); |
| 1479 | gen_callw_slot(dc, par[0], tmp, -1); |
| 1480 | } |
| 1481 | |
| 1482 | static void translate_clamps(DisasContext *dc, const OpcodeArg arg[], |
| 1483 | const uint32_t par[]) |
| 1484 | { |
| 1485 | TCGv_i32 tmp1 = tcg_constant_i32(-1u << arg[2].imm); |
| 1486 | TCGv_i32 tmp2 = tcg_constant_i32((1 << arg[2].imm) - 1); |
| 1487 | |
| 1488 | tcg_gen_smax_i32(arg[0].out, tmp1, arg[1].in); |
| 1489 | tcg_gen_smin_i32(arg[0].out, arg[0].out, tmp2); |
| 1490 | } |
| 1491 | |
| 1492 | static void translate_clrb_expstate(DisasContext *dc, const OpcodeArg arg[], |
| 1493 | const uint32_t par[]) |
| 1494 | { |
| 1495 | /* TODO: GPIO32 may be a part of coprocessor */ |
| 1496 | tcg_gen_andi_i32(cpu_UR[EXPSTATE], cpu_UR[EXPSTATE], ~(1u << arg[0].imm)); |
| 1497 | } |
| 1498 | |
| 1499 | static void translate_clrex(DisasContext *dc, const OpcodeArg arg[], |
| 1500 | const uint32_t par[]) |
| 1501 | { |
| 1502 | tcg_gen_movi_i32(cpu_exclusive_addr, -1); |
| 1503 | } |
| 1504 | |
| 1505 | static void translate_const16(DisasContext *dc, const OpcodeArg arg[], |
| 1506 | const uint32_t par[]) |
| 1507 | { |
| 1508 | TCGv_i32 c = tcg_constant_i32(arg[1].imm); |
| 1509 | |
| 1510 | tcg_gen_deposit_i32(arg[0].out, c, arg[0].in, 16, 16); |
| 1511 | } |
| 1512 | |
| 1513 | static void translate_dcache(DisasContext *dc, const OpcodeArg arg[], |
| 1514 | const uint32_t par[]) |
| 1515 | { |
| 1516 | TCGv_i32 addr = tcg_temp_new_i32(); |
| 1517 | TCGv_i32 res = tcg_temp_new_i32(); |
| 1518 | |
| 1519 | tcg_gen_addi_i32(addr, arg[0].in, arg[1].imm); |
| 1520 | tcg_gen_qemu_ld_i32(res, addr, dc->cring, MO_UB); |
| 1521 | } |
| 1522 | |
| 1523 | static void translate_depbits(DisasContext *dc, const OpcodeArg arg[], |
| 1524 | const uint32_t par[]) |
| 1525 | { |
| 1526 | tcg_gen_deposit_i32(arg[1].out, arg[1].in, arg[0].in, |
| 1527 | arg[2].imm, arg[3].imm); |
| 1528 | } |
| 1529 | |
| 1530 | static void translate_diwbuip(DisasContext *dc, const OpcodeArg arg[], |
| 1531 | const uint32_t par[]) |
| 1532 | { |
| 1533 | tcg_gen_addi_i32(arg[0].out, arg[0].in, dc->config->dcache_line_bytes); |
| 1534 | } |
| 1535 | |
| 1536 | static uint32_t test_exceptions_entry(DisasContext *dc, const OpcodeArg arg[], |
| 1537 | const uint32_t par[]) |
| 1538 | { |
| 1539 | if (arg[0].imm > 3 || !dc->cwoe) { |
| 1540 | qemu_log_mask(LOG_GUEST_ERROR, |
| 1541 | "Illegal entry instruction(pc = %08x)\n", dc->pc); |
| 1542 | return XTENSA_OP_ILL; |
| 1543 | } else { |
| 1544 | return 0; |
| 1545 | } |
| 1546 | } |
| 1547 | |
| 1548 | static uint32_t test_overflow_entry(DisasContext *dc, const OpcodeArg arg[], |
| 1549 | const uint32_t par[]) |
| 1550 | { |
| 1551 | return 1 << (dc->callinc * 4); |
| 1552 | } |
| 1553 | |
| 1554 | static void translate_entry(DisasContext *dc, const OpcodeArg arg[], |
| 1555 | const uint32_t par[]) |
| 1556 | { |
| 1557 | TCGv_i32 pc = tcg_constant_i32(dc->pc); |
| 1558 | TCGv_i32 s = tcg_constant_i32(arg[0].imm); |
| 1559 | TCGv_i32 imm = tcg_constant_i32(arg[1].imm); |
| 1560 | gen_helper_entry(tcg_env, pc, s, imm); |
| 1561 | } |
| 1562 | |
| 1563 | static void translate_extui(DisasContext *dc, const OpcodeArg arg[], |
| 1564 | const uint32_t par[]) |
| 1565 | { |
| 1566 | int maskimm = (1 << arg[3].imm) - 1; |
| 1567 | |
| 1568 | TCGv_i32 tmp = tcg_temp_new_i32(); |
| 1569 | tcg_gen_shri_i32(tmp, arg[1].in, arg[2].imm); |
| 1570 | tcg_gen_andi_i32(arg[0].out, tmp, maskimm); |
| 1571 | } |
| 1572 | |
| 1573 | static void translate_getex(DisasContext *dc, const OpcodeArg arg[], |
| 1574 | const uint32_t par[]) |
| 1575 | { |
| 1576 | TCGv_i32 tmp = tcg_temp_new_i32(); |
| 1577 | |
| 1578 | tcg_gen_extract_i32(tmp, cpu_SR[ATOMCTL], 8, 1); |
| 1579 | tcg_gen_deposit_i32(cpu_SR[ATOMCTL], cpu_SR[ATOMCTL], arg[0].in, 8, 1); |
| 1580 | tcg_gen_mov_i32(arg[0].out, tmp); |
| 1581 | } |
| 1582 | |
| 1583 | static void translate_icache(DisasContext *dc, const OpcodeArg arg[], |
| 1584 | const uint32_t par[]) |
| 1585 | { |
| 1586 | #ifndef CONFIG_USER_ONLY |
| 1587 | TCGv_i32 addr = tcg_temp_new_i32(); |
| 1588 | |
| 1589 | tcg_gen_movi_i32(cpu_pc, dc->pc); |
| 1590 | tcg_gen_addi_i32(addr, arg[0].in, arg[1].imm); |
| 1591 | gen_helper_itlb_hit_test(tcg_env, addr); |
| 1592 | #endif |
| 1593 | } |
| 1594 | |
| 1595 | static void translate_itlb(DisasContext *dc, const OpcodeArg arg[], |
| 1596 | const uint32_t par[]) |
| 1597 | { |
| 1598 | #ifndef CONFIG_USER_ONLY |
| 1599 | TCGv_i32 dtlb = tcg_constant_i32(par[0]); |
| 1600 | |
| 1601 | gen_helper_itlb(tcg_env, arg[0].in, dtlb); |
| 1602 | #endif |
| 1603 | } |
| 1604 | |
| 1605 | static void translate_j(DisasContext *dc, const OpcodeArg arg[], |
| 1606 | const uint32_t par[]) |
| 1607 | { |
| 1608 | gen_jumpi(dc, arg[0].imm, 0); |
| 1609 | } |
| 1610 | |
| 1611 | static void translate_jx(DisasContext *dc, const OpcodeArg arg[], |
| 1612 | const uint32_t par[]) |
| 1613 | { |
| 1614 | gen_jump(dc, arg[0].in); |
| 1615 | } |
| 1616 | |
| 1617 | static void translate_l32e(DisasContext *dc, const OpcodeArg arg[], |
| 1618 | const uint32_t par[]) |
| 1619 | { |
| 1620 | TCGv_i32 addr = tcg_temp_new_i32(); |
| 1621 | MemOp mop; |
| 1622 | |
| 1623 | tcg_gen_addi_i32(addr, arg[1].in, arg[2].imm); |
| 1624 | mop = gen_load_store_alignment(dc, MO_TEUL, addr); |
| 1625 | tcg_gen_qemu_ld_tl(arg[0].out, addr, dc->ring, mop); |
| 1626 | } |
| 1627 | |
| 1628 | #ifdef CONFIG_USER_ONLY |
| 1629 | static void gen_check_exclusive(DisasContext *dc, TCGv_i32 addr, bool is_write) |
| 1630 | { |
| 1631 | } |
| 1632 | #else |
| 1633 | static void gen_check_exclusive(DisasContext *dc, TCGv_i32 addr, bool is_write) |
| 1634 | { |
| 1635 | if (!option_enabled(dc, XTENSA_OPTION_MPU)) { |
| 1636 | TCGv_i32 pc = tcg_constant_i32(dc->pc); |
| 1637 | |
| 1638 | gen_helper_check_exclusive(tcg_env, pc, addr, |
| 1639 | tcg_constant_i32(is_write)); |
| 1640 | } |
| 1641 | } |
| 1642 | #endif |
| 1643 | |
| 1644 | static void translate_l32ex(DisasContext *dc, const OpcodeArg arg[], |
| 1645 | const uint32_t par[]) |
| 1646 | { |
| 1647 | TCGv_i32 addr = tcg_temp_new_i32(); |
| 1648 | MemOp mop; |
| 1649 | |
| 1650 | tcg_gen_mov_i32(addr, arg[1].in); |
| 1651 | mop = gen_load_store_alignment(dc, MO_TEUL | MO_ALIGN, addr); |
| 1652 | gen_check_exclusive(dc, addr, false); |
| 1653 | tcg_gen_qemu_ld_i32(arg[0].out, addr, dc->cring, mop); |
| 1654 | tcg_gen_mov_i32(cpu_exclusive_addr, addr); |
| 1655 | tcg_gen_mov_i32(cpu_exclusive_val, arg[0].out); |
| 1656 | } |
| 1657 | |
| 1658 | static void translate_ldst(DisasContext *dc, const OpcodeArg arg[], |
| 1659 | const uint32_t par[]) |
| 1660 | { |
| 1661 | TCGv_i32 addr = tcg_temp_new_i32(); |
| 1662 | MemOp mop; |
| 1663 | |
| 1664 | tcg_gen_addi_i32(addr, arg[1].in, arg[2].imm); |
| 1665 | mop = gen_load_store_alignment(dc, par[0], addr); |
| 1666 | |
| 1667 | if (par[2]) { |
| 1668 | if (par[1]) { |
| 1669 | tcg_gen_mb(TCG_BAR_STRL | TCG_MO_ALL); |
| 1670 | } |
| 1671 | tcg_gen_qemu_st_tl(arg[0].in, addr, dc->cring, mop); |
| 1672 | } else { |
| 1673 | tcg_gen_qemu_ld_tl(arg[0].out, addr, dc->cring, mop); |
| 1674 | if (par[1]) { |
| 1675 | tcg_gen_mb(TCG_BAR_LDAQ | TCG_MO_ALL); |
| 1676 | } |
| 1677 | } |
| 1678 | } |
| 1679 | |
| 1680 | static void translate_lct(DisasContext *dc, const OpcodeArg arg[], |
| 1681 | const uint32_t par[]) |
| 1682 | { |
| 1683 | tcg_gen_movi_i32(arg[0].out, 0); |
| 1684 | } |
| 1685 | |
| 1686 | static void translate_l32r(DisasContext *dc, const OpcodeArg arg[], |
| 1687 | const uint32_t par[]) |
| 1688 | { |
| 1689 | TCGv_i32 tmp; |
| 1690 | |
| 1691 | if (dc->base.tb->flags & XTENSA_TBFLAG_LITBASE) { |
| 1692 | tmp = tcg_temp_new(); |
| 1693 | tcg_gen_addi_i32(tmp, cpu_SR[LITBASE], arg[1].raw_imm - 1); |
| 1694 | } else { |
| 1695 | tmp = tcg_constant_i32(arg[1].imm); |
| 1696 | } |
| 1697 | tcg_gen_qemu_ld_i32(arg[0].out, tmp, dc->cring, MO_TEUL); |
| 1698 | } |
| 1699 | |
| 1700 | static void translate_loop(DisasContext *dc, const OpcodeArg arg[], |
| 1701 | const uint32_t par[]) |
| 1702 | { |
| 1703 | uint32_t lend = arg[1].imm; |
| 1704 | |
| 1705 | tcg_gen_subi_i32(cpu_SR[LCOUNT], arg[0].in, 1); |
| 1706 | tcg_gen_movi_i32(cpu_SR[LBEG], dc->base.pc_next); |
| 1707 | tcg_gen_movi_i32(cpu_SR[LEND], lend); |
| 1708 | |
| 1709 | if (par[0] != TCG_COND_NEVER) { |
| 1710 | TCGLabel *label = gen_new_label(); |
| 1711 | tcg_gen_brcondi_i32(par[0], arg[0].in, 0, label); |
| 1712 | gen_jumpi(dc, lend, 1); |
| 1713 | gen_set_label(label); |
| 1714 | } |
| 1715 | |
| 1716 | gen_jumpi(dc, dc->base.pc_next, 0); |
| 1717 | } |
| 1718 | |
| 1719 | enum { |
| 1720 | MAC16_UMUL, |
| 1721 | MAC16_MUL, |
| 1722 | MAC16_MULA, |
| 1723 | MAC16_MULS, |
| 1724 | MAC16_NONE, |
| 1725 | }; |
| 1726 | |
| 1727 | enum { |
| 1728 | MAC16_LL, |
| 1729 | MAC16_HL, |
| 1730 | MAC16_LH, |
| 1731 | MAC16_HH, |
| 1732 | |
| 1733 | MAC16_HX = 0x1, |
| 1734 | MAC16_XH = 0x2, |
| 1735 | }; |
| 1736 | |
| 1737 | static void translate_mac16(DisasContext *dc, const OpcodeArg arg[], |
| 1738 | const uint32_t par[]) |
| 1739 | { |
| 1740 | int op = par[0]; |
| 1741 | unsigned half = par[1]; |
| 1742 | uint32_t ld_offset = par[2]; |
| 1743 | unsigned off = ld_offset ? 2 : 0; |
| 1744 | TCGv_i32 vaddr = tcg_temp_new_i32(); |
| 1745 | TCGv_i32 mem32 = tcg_temp_new_i32(); |
| 1746 | |
| 1747 | if (ld_offset) { |
| 1748 | MemOp mop; |
| 1749 | |
| 1750 | tcg_gen_addi_i32(vaddr, arg[1].in, ld_offset); |
| 1751 | mop = gen_load_store_alignment(dc, MO_TEUL, vaddr); |
| 1752 | tcg_gen_qemu_ld_tl(mem32, vaddr, dc->cring, mop); |
| 1753 | } |
| 1754 | if (op != MAC16_NONE) { |
| 1755 | TCGv_i32 m1 = gen_mac16_m(arg[off].in, |
| 1756 | half & MAC16_HX, op == MAC16_UMUL); |
| 1757 | TCGv_i32 m2 = gen_mac16_m(arg[off + 1].in, |
| 1758 | half & MAC16_XH, op == MAC16_UMUL); |
| 1759 | |
| 1760 | if (op == MAC16_MUL || op == MAC16_UMUL) { |
| 1761 | tcg_gen_mul_i32(cpu_SR[ACCLO], m1, m2); |
| 1762 | if (op == MAC16_UMUL) { |
| 1763 | tcg_gen_movi_i32(cpu_SR[ACCHI], 0); |
| 1764 | } else { |
| 1765 | tcg_gen_sari_i32(cpu_SR[ACCHI], cpu_SR[ACCLO], 31); |
| 1766 | } |
| 1767 | } else { |
| 1768 | TCGv_i32 lo = tcg_temp_new_i32(); |
| 1769 | TCGv_i32 hi = tcg_temp_new_i32(); |
| 1770 | |
| 1771 | tcg_gen_mul_i32(lo, m1, m2); |
| 1772 | tcg_gen_sari_i32(hi, lo, 31); |
| 1773 | if (op == MAC16_MULA) { |
| 1774 | tcg_gen_add2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI], |
| 1775 | cpu_SR[ACCLO], cpu_SR[ACCHI], |
| 1776 | lo, hi); |
| 1777 | } else { |
| 1778 | tcg_gen_sub2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI], |
| 1779 | cpu_SR[ACCLO], cpu_SR[ACCHI], |
| 1780 | lo, hi); |
| 1781 | } |
| 1782 | tcg_gen_ext8s_i32(cpu_SR[ACCHI], cpu_SR[ACCHI]); |
| 1783 | } |
| 1784 | } |
| 1785 | if (ld_offset) { |
| 1786 | tcg_gen_mov_i32(arg[1].out, vaddr); |
| 1787 | tcg_gen_mov_i32(cpu_SR[MR + arg[0].imm], mem32); |
| 1788 | } |
| 1789 | } |
| 1790 | |
| 1791 | static void translate_memw(DisasContext *dc, const OpcodeArg arg[], |
| 1792 | const uint32_t par[]) |
| 1793 | { |
| 1794 | tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL); |
| 1795 | } |
| 1796 | |
| 1797 | static void translate_smin(DisasContext *dc, const OpcodeArg arg[], |
| 1798 | const uint32_t par[]) |
| 1799 | { |
| 1800 | tcg_gen_smin_i32(arg[0].out, arg[1].in, arg[2].in); |
| 1801 | } |
| 1802 | |
| 1803 | static void translate_umin(DisasContext *dc, const OpcodeArg arg[], |
| 1804 | const uint32_t par[]) |
| 1805 | { |
| 1806 | tcg_gen_umin_i32(arg[0].out, arg[1].in, arg[2].in); |
| 1807 | } |
| 1808 | |
| 1809 | static void translate_smax(DisasContext *dc, const OpcodeArg arg[], |
| 1810 | const uint32_t par[]) |
| 1811 | { |
| 1812 | tcg_gen_smax_i32(arg[0].out, arg[1].in, arg[2].in); |
| 1813 | } |
| 1814 | |
| 1815 | static void translate_umax(DisasContext *dc, const OpcodeArg arg[], |
| 1816 | const uint32_t par[]) |
| 1817 | { |
| 1818 | tcg_gen_umax_i32(arg[0].out, arg[1].in, arg[2].in); |
| 1819 | } |
| 1820 | |
| 1821 | static void translate_mov(DisasContext *dc, const OpcodeArg arg[], |
| 1822 | const uint32_t par[]) |
| 1823 | { |
| 1824 | tcg_gen_mov_i32(arg[0].out, arg[1].in); |
| 1825 | } |
| 1826 | |
| 1827 | static void translate_movcond(DisasContext *dc, const OpcodeArg arg[], |
| 1828 | const uint32_t par[]) |
| 1829 | { |
| 1830 | TCGv_i32 zero = tcg_constant_i32(0); |
| 1831 | |
| 1832 | tcg_gen_movcond_i32(par[0], arg[0].out, |
| 1833 | arg[2].in, zero, arg[1].in, arg[0].in); |
| 1834 | } |
| 1835 | |
| 1836 | static void translate_movi(DisasContext *dc, const OpcodeArg arg[], |
| 1837 | const uint32_t par[]) |
| 1838 | { |
| 1839 | tcg_gen_movi_i32(arg[0].out, arg[1].imm); |
| 1840 | } |
| 1841 | |
| 1842 | static void translate_movp(DisasContext *dc, const OpcodeArg arg[], |
| 1843 | const uint32_t par[]) |
| 1844 | { |
| 1845 | TCGv_i32 zero = tcg_constant_i32(0); |
| 1846 | TCGv_i32 tmp = tcg_temp_new_i32(); |
| 1847 | |
| 1848 | tcg_gen_andi_i32(tmp, arg[2].in, 1 << arg[2].imm); |
| 1849 | tcg_gen_movcond_i32(par[0], |
| 1850 | arg[0].out, tmp, zero, |
| 1851 | arg[1].in, arg[0].in); |
| 1852 | } |
| 1853 | |
| 1854 | static void translate_movsp(DisasContext *dc, const OpcodeArg arg[], |
| 1855 | const uint32_t par[]) |
| 1856 | { |
| 1857 | tcg_gen_mov_i32(arg[0].out, arg[1].in); |
| 1858 | } |
| 1859 | |
| 1860 | static void translate_mul16(DisasContext *dc, const OpcodeArg arg[], |
| 1861 | const uint32_t par[]) |
| 1862 | { |
| 1863 | TCGv_i32 v1 = tcg_temp_new_i32(); |
| 1864 | TCGv_i32 v2 = tcg_temp_new_i32(); |
| 1865 | |
| 1866 | if (par[0]) { |
| 1867 | tcg_gen_ext16s_i32(v1, arg[1].in); |
| 1868 | tcg_gen_ext16s_i32(v2, arg[2].in); |
| 1869 | } else { |
| 1870 | tcg_gen_ext16u_i32(v1, arg[1].in); |
| 1871 | tcg_gen_ext16u_i32(v2, arg[2].in); |
| 1872 | } |
| 1873 | tcg_gen_mul_i32(arg[0].out, v1, v2); |
| 1874 | } |
| 1875 | |
| 1876 | static void translate_mull(DisasContext *dc, const OpcodeArg arg[], |
| 1877 | const uint32_t par[]) |
| 1878 | { |
| 1879 | tcg_gen_mul_i32(arg[0].out, arg[1].in, arg[2].in); |
| 1880 | } |
| 1881 | |
| 1882 | static void translate_mulh(DisasContext *dc, const OpcodeArg arg[], |
| 1883 | const uint32_t par[]) |
| 1884 | { |
| 1885 | TCGv_i32 lo = tcg_temp_new(); |
| 1886 | |
| 1887 | if (par[0]) { |
| 1888 | tcg_gen_muls2_i32(lo, arg[0].out, arg[1].in, arg[2].in); |
| 1889 | } else { |
| 1890 | tcg_gen_mulu2_i32(lo, arg[0].out, arg[1].in, arg[2].in); |
| 1891 | } |
| 1892 | } |
| 1893 | |
| 1894 | static void translate_neg(DisasContext *dc, const OpcodeArg arg[], |
| 1895 | const uint32_t par[]) |
| 1896 | { |
| 1897 | tcg_gen_neg_i32(arg[0].out, arg[1].in); |
| 1898 | } |
| 1899 | |
| 1900 | static void translate_nop(DisasContext *dc, const OpcodeArg arg[], |
| 1901 | const uint32_t par[]) |
| 1902 | { |
| 1903 | } |
| 1904 | |
| 1905 | static void translate_nsa(DisasContext *dc, const OpcodeArg arg[], |
| 1906 | const uint32_t par[]) |
| 1907 | { |
| 1908 | tcg_gen_clrsb_i32(arg[0].out, arg[1].in); |
| 1909 | } |
| 1910 | |
| 1911 | static void translate_nsau(DisasContext *dc, const OpcodeArg arg[], |
| 1912 | const uint32_t par[]) |
| 1913 | { |
| 1914 | tcg_gen_clzi_i32(arg[0].out, arg[1].in, 32); |
| 1915 | } |
| 1916 | |
| 1917 | static void translate_or(DisasContext *dc, const OpcodeArg arg[], |
| 1918 | const uint32_t par[]) |
| 1919 | { |
| 1920 | tcg_gen_or_i32(arg[0].out, arg[1].in, arg[2].in); |
| 1921 | } |
| 1922 | |
| 1923 | static void translate_ptlb(DisasContext *dc, const OpcodeArg arg[], |
| 1924 | const uint32_t par[]) |
| 1925 | { |
| 1926 | #ifndef CONFIG_USER_ONLY |
| 1927 | TCGv_i32 dtlb = tcg_constant_i32(par[0]); |
| 1928 | |
| 1929 | tcg_gen_movi_i32(cpu_pc, dc->pc); |
| 1930 | gen_helper_ptlb(arg[0].out, tcg_env, arg[1].in, dtlb); |
| 1931 | #endif |
| 1932 | } |
| 1933 | |
| 1934 | static void translate_pptlb(DisasContext *dc, const OpcodeArg arg[], |
| 1935 | const uint32_t par[]) |
| 1936 | { |
| 1937 | #ifndef CONFIG_USER_ONLY |
| 1938 | tcg_gen_movi_i32(cpu_pc, dc->pc); |
| 1939 | gen_helper_pptlb(arg[0].out, tcg_env, arg[1].in); |
| 1940 | #endif |
| 1941 | } |
| 1942 | |
| 1943 | static void translate_quos(DisasContext *dc, const OpcodeArg arg[], |
| 1944 | const uint32_t par[]) |
| 1945 | { |
| 1946 | TCGLabel *label1 = gen_new_label(); |
| 1947 | TCGLabel *label2 = gen_new_label(); |
| 1948 | |
| 1949 | tcg_gen_brcondi_i32(TCG_COND_NE, arg[1].in, 0x80000000, |
| 1950 | label1); |
| 1951 | tcg_gen_brcondi_i32(TCG_COND_NE, arg[2].in, 0xffffffff, |
| 1952 | label1); |
| 1953 | tcg_gen_movi_i32(arg[0].out, |
| 1954 | par[0] ? 0x80000000 : 0); |
| 1955 | tcg_gen_br(label2); |
| 1956 | gen_set_label(label1); |
| 1957 | if (par[0]) { |
| 1958 | tcg_gen_div_i32(arg[0].out, |
| 1959 | arg[1].in, arg[2].in); |
| 1960 | } else { |
| 1961 | tcg_gen_rem_i32(arg[0].out, |
| 1962 | arg[1].in, arg[2].in); |
| 1963 | } |
| 1964 | gen_set_label(label2); |
| 1965 | } |
| 1966 | |
| 1967 | static void translate_quou(DisasContext *dc, const OpcodeArg arg[], |
| 1968 | const uint32_t par[]) |
| 1969 | { |
| 1970 | tcg_gen_divu_i32(arg[0].out, |
| 1971 | arg[1].in, arg[2].in); |
| 1972 | } |
| 1973 | |
| 1974 | static void translate_read_impwire(DisasContext *dc, const OpcodeArg arg[], |
| 1975 | const uint32_t par[]) |
| 1976 | { |
| 1977 | /* TODO: GPIO32 may be a part of coprocessor */ |
| 1978 | tcg_gen_movi_i32(arg[0].out, 0); |
| 1979 | } |
| 1980 | |
| 1981 | static void translate_remu(DisasContext *dc, const OpcodeArg arg[], |
| 1982 | const uint32_t par[]) |
| 1983 | { |
| 1984 | tcg_gen_remu_i32(arg[0].out, |
| 1985 | arg[1].in, arg[2].in); |
| 1986 | } |
| 1987 | |
| 1988 | static void translate_rer(DisasContext *dc, const OpcodeArg arg[], |
| 1989 | const uint32_t par[]) |
| 1990 | { |
| 1991 | gen_helper_rer(arg[0].out, tcg_env, arg[1].in); |
| 1992 | } |
| 1993 | |
| 1994 | static void translate_ret(DisasContext *dc, const OpcodeArg arg[], |
| 1995 | const uint32_t par[]) |
| 1996 | { |
| 1997 | gen_jump(dc, cpu_R[0]); |
| 1998 | } |
| 1999 | |
| 2000 | static uint32_t test_exceptions_retw(DisasContext *dc, const OpcodeArg arg[], |
| 2001 | const uint32_t par[]) |
| 2002 | { |
| 2003 | if (!dc->cwoe) { |
| 2004 | qemu_log_mask(LOG_GUEST_ERROR, |
| 2005 | "Illegal retw instruction(pc = %08x)\n", dc->pc); |
| 2006 | return XTENSA_OP_ILL; |
| 2007 | } else { |
| 2008 | TCGv_i32 pc = tcg_constant_i32(dc->pc); |
| 2009 | |
| 2010 | gen_helper_test_ill_retw(tcg_env, pc); |
| 2011 | return 0; |
| 2012 | } |
| 2013 | } |
| 2014 | |
| 2015 | static void translate_retw(DisasContext *dc, const OpcodeArg arg[], |
| 2016 | const uint32_t par[]) |
| 2017 | { |
| 2018 | TCGv_i32 tmp = tcg_temp_new(); |
| 2019 | tcg_gen_shl_i32(tmp, tcg_constant_i32(1), cpu_SR[WINDOW_BASE]); |
| 2020 | tcg_gen_andc_i32(cpu_SR[WINDOW_START], |
| 2021 | cpu_SR[WINDOW_START], tmp); |
| 2022 | tcg_gen_movi_i32(tmp, dc->pc); |
| 2023 | tcg_gen_deposit_i32(tmp, tmp, cpu_R[0], 0, 30); |
| 2024 | gen_helper_retw(tcg_env, cpu_R[0]); |
| 2025 | gen_jump(dc, tmp); |
| 2026 | } |
| 2027 | |
| 2028 | static void translate_rfde(DisasContext *dc, const OpcodeArg arg[], |
| 2029 | const uint32_t par[]) |
| 2030 | { |
| 2031 | gen_jump(dc, cpu_SR[dc->config->ndepc ? DEPC : EPC1]); |
| 2032 | } |
| 2033 | |
| 2034 | static void translate_rfe(DisasContext *dc, const OpcodeArg arg[], |
| 2035 | const uint32_t par[]) |
| 2036 | { |
| 2037 | tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM); |
| 2038 | gen_jump(dc, cpu_SR[EPC1]); |
| 2039 | } |
| 2040 | |
| 2041 | static void translate_rfi(DisasContext *dc, const OpcodeArg arg[], |
| 2042 | const uint32_t par[]) |
| 2043 | { |
| 2044 | tcg_gen_mov_i32(cpu_SR[PS], cpu_SR[EPS2 + arg[0].imm - 2]); |
| 2045 | gen_jump(dc, cpu_SR[EPC1 + arg[0].imm - 1]); |
| 2046 | } |
| 2047 | |
| 2048 | static void translate_rfw(DisasContext *dc, const OpcodeArg arg[], |
| 2049 | const uint32_t par[]) |
| 2050 | { |
| 2051 | TCGv_i32 tmp = tcg_temp_new(); |
| 2052 | |
| 2053 | tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM); |
| 2054 | tcg_gen_shl_i32(tmp, tcg_constant_i32(1), cpu_SR[WINDOW_BASE]); |
| 2055 | |
| 2056 | if (par[0]) { |
| 2057 | tcg_gen_andc_i32(cpu_SR[WINDOW_START], |
| 2058 | cpu_SR[WINDOW_START], tmp); |
| 2059 | } else { |
| 2060 | tcg_gen_or_i32(cpu_SR[WINDOW_START], |
| 2061 | cpu_SR[WINDOW_START], tmp); |
| 2062 | } |
| 2063 | |
| 2064 | gen_helper_restore_owb(tcg_env); |
| 2065 | gen_jump(dc, cpu_SR[EPC1]); |
| 2066 | } |
| 2067 | |
| 2068 | static void translate_rotw(DisasContext *dc, const OpcodeArg arg[], |
| 2069 | const uint32_t par[]) |
| 2070 | { |
| 2071 | tcg_gen_addi_i32(cpu_windowbase_next, cpu_SR[WINDOW_BASE], arg[0].imm); |
| 2072 | } |
| 2073 | |
| 2074 | static void translate_rsil(DisasContext *dc, const OpcodeArg arg[], |
| 2075 | const uint32_t par[]) |
| 2076 | { |
| 2077 | tcg_gen_mov_i32(arg[0].out, cpu_SR[PS]); |
| 2078 | tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_INTLEVEL); |
| 2079 | tcg_gen_ori_i32(cpu_SR[PS], cpu_SR[PS], arg[1].imm); |
| 2080 | } |
| 2081 | |
| 2082 | static void translate_rsr(DisasContext *dc, const OpcodeArg arg[], |
| 2083 | const uint32_t par[]) |
| 2084 | { |
| 2085 | if (sr_name[par[0]]) { |
| 2086 | tcg_gen_mov_i32(arg[0].out, cpu_SR[par[0]]); |
| 2087 | } else { |
| 2088 | tcg_gen_movi_i32(arg[0].out, 0); |
| 2089 | } |
| 2090 | } |
| 2091 | |
| 2092 | static void translate_rsr_ccount(DisasContext *dc, const OpcodeArg arg[], |
| 2093 | const uint32_t par[]) |
| 2094 | { |
| 2095 | #ifndef CONFIG_USER_ONLY |
| 2096 | translator_io_start(&dc->base); |
| 2097 | gen_helper_update_ccount(tcg_env); |
| 2098 | tcg_gen_mov_i32(arg[0].out, cpu_SR[par[0]]); |
| 2099 | #endif |
| 2100 | } |
| 2101 | |
| 2102 | static void translate_rsr_ptevaddr(DisasContext *dc, const OpcodeArg arg[], |
| 2103 | const uint32_t par[]) |
| 2104 | { |
| 2105 | #ifndef CONFIG_USER_ONLY |
| 2106 | TCGv_i32 tmp = tcg_temp_new_i32(); |
| 2107 | |
| 2108 | tcg_gen_shri_i32(tmp, cpu_SR[EXCVADDR], 10); |
| 2109 | tcg_gen_or_i32(tmp, tmp, cpu_SR[PTEVADDR]); |
| 2110 | tcg_gen_andi_i32(arg[0].out, tmp, 0xfffffffc); |
| 2111 | #endif |
| 2112 | } |
| 2113 | |
| 2114 | static void translate_rtlb(DisasContext *dc, const OpcodeArg arg[], |
| 2115 | const uint32_t par[]) |
| 2116 | { |
| 2117 | #ifndef CONFIG_USER_ONLY |
| 2118 | static void (* const helper[])(TCGv_i32 r, TCGv_env env, TCGv_i32 a1, |
| 2119 | TCGv_i32 a2) = { |
| 2120 | gen_helper_rtlb0, |
| 2121 | gen_helper_rtlb1, |
| 2122 | }; |
| 2123 | TCGv_i32 dtlb = tcg_constant_i32(par[0]); |
| 2124 | |
| 2125 | helper[par[1]](arg[0].out, tcg_env, arg[1].in, dtlb); |
| 2126 | #endif |
| 2127 | } |
| 2128 | |
| 2129 | static void translate_rptlb0(DisasContext *dc, const OpcodeArg arg[], |
| 2130 | const uint32_t par[]) |
| 2131 | { |
| 2132 | #ifndef CONFIG_USER_ONLY |
| 2133 | gen_helper_rptlb0(arg[0].out, tcg_env, arg[1].in); |
| 2134 | #endif |
| 2135 | } |
| 2136 | |
| 2137 | static void translate_rptlb1(DisasContext *dc, const OpcodeArg arg[], |
| 2138 | const uint32_t par[]) |
| 2139 | { |
| 2140 | #ifndef CONFIG_USER_ONLY |
| 2141 | gen_helper_rptlb1(arg[0].out, tcg_env, arg[1].in); |
| 2142 | #endif |
| 2143 | } |
| 2144 | |
| 2145 | static void translate_rur(DisasContext *dc, const OpcodeArg arg[], |
| 2146 | const uint32_t par[]) |
| 2147 | { |
| 2148 | tcg_gen_mov_i32(arg[0].out, cpu_UR[par[0]]); |
| 2149 | } |
| 2150 | |
| 2151 | static void translate_setb_expstate(DisasContext *dc, const OpcodeArg arg[], |
| 2152 | const uint32_t par[]) |
| 2153 | { |
| 2154 | /* TODO: GPIO32 may be a part of coprocessor */ |
| 2155 | tcg_gen_ori_i32(cpu_UR[EXPSTATE], cpu_UR[EXPSTATE], 1u << arg[0].imm); |
| 2156 | } |
| 2157 | |
| 2158 | #ifdef CONFIG_USER_ONLY |
| 2159 | static void gen_check_atomctl(DisasContext *dc, TCGv_i32 addr) |
| 2160 | { |
| 2161 | } |
| 2162 | #else |
| 2163 | static void gen_check_atomctl(DisasContext *dc, TCGv_i32 addr) |
| 2164 | { |
| 2165 | TCGv_i32 pc = tcg_constant_i32(dc->pc); |
| 2166 | |
| 2167 | gen_helper_check_atomctl(tcg_env, pc, addr); |
| 2168 | } |
| 2169 | #endif |
| 2170 | |
| 2171 | static void translate_s32c1i(DisasContext *dc, const OpcodeArg arg[], |
| 2172 | const uint32_t par[]) |
| 2173 | { |
| 2174 | TCGv_i32 tmp = tcg_temp_new_i32(); |
| 2175 | TCGv_i32 addr = tcg_temp_new_i32(); |
| 2176 | MemOp mop; |
| 2177 | |
| 2178 | tcg_gen_mov_i32(tmp, arg[0].in); |
| 2179 | tcg_gen_addi_i32(addr, arg[1].in, arg[2].imm); |
| 2180 | mop = gen_load_store_alignment(dc, MO_TEUL | MO_ALIGN, addr); |
| 2181 | gen_check_atomctl(dc, addr); |
| 2182 | tcg_gen_atomic_cmpxchg_i32(arg[0].out, addr, cpu_SR[SCOMPARE1], |
| 2183 | tmp, dc->cring, mop); |
| 2184 | } |
| 2185 | |
| 2186 | static void translate_s32e(DisasContext *dc, const OpcodeArg arg[], |
| 2187 | const uint32_t par[]) |
| 2188 | { |
| 2189 | TCGv_i32 addr = tcg_temp_new_i32(); |
| 2190 | MemOp mop; |
| 2191 | |
| 2192 | tcg_gen_addi_i32(addr, arg[1].in, arg[2].imm); |
| 2193 | mop = gen_load_store_alignment(dc, MO_TEUL, addr); |
| 2194 | tcg_gen_qemu_st_tl(arg[0].in, addr, dc->ring, mop); |
| 2195 | } |
| 2196 | |
| 2197 | static void translate_s32ex(DisasContext *dc, const OpcodeArg arg[], |
| 2198 | const uint32_t par[]) |
| 2199 | { |
| 2200 | TCGv_i32 prev = tcg_temp_new_i32(); |
| 2201 | TCGv_i32 addr = tcg_temp_new_i32(); |
| 2202 | TCGv_i32 res = tcg_temp_new_i32(); |
| 2203 | TCGLabel *label = gen_new_label(); |
| 2204 | MemOp mop; |
| 2205 | |
| 2206 | tcg_gen_movi_i32(res, 0); |
| 2207 | tcg_gen_mov_i32(addr, arg[1].in); |
| 2208 | mop = gen_load_store_alignment(dc, MO_TEUL | MO_ALIGN, addr); |
| 2209 | tcg_gen_brcond_i32(TCG_COND_NE, addr, cpu_exclusive_addr, label); |
| 2210 | gen_check_exclusive(dc, addr, true); |
| 2211 | tcg_gen_atomic_cmpxchg_i32(prev, cpu_exclusive_addr, cpu_exclusive_val, |
| 2212 | arg[0].in, dc->cring, mop); |
| 2213 | tcg_gen_setcond_i32(TCG_COND_EQ, res, prev, cpu_exclusive_val); |
| 2214 | tcg_gen_movcond_i32(TCG_COND_EQ, cpu_exclusive_val, |
| 2215 | prev, cpu_exclusive_val, prev, cpu_exclusive_val); |
| 2216 | tcg_gen_movi_i32(cpu_exclusive_addr, -1); |
| 2217 | gen_set_label(label); |
| 2218 | tcg_gen_extract_i32(arg[0].out, cpu_SR[ATOMCTL], 8, 1); |
| 2219 | tcg_gen_deposit_i32(cpu_SR[ATOMCTL], cpu_SR[ATOMCTL], res, 8, 1); |
| 2220 | } |
| 2221 | |
| 2222 | static void translate_salt(DisasContext *dc, const OpcodeArg arg[], |
| 2223 | const uint32_t par[]) |
| 2224 | { |
| 2225 | tcg_gen_setcond_i32(par[0], |
| 2226 | arg[0].out, |
| 2227 | arg[1].in, arg[2].in); |
| 2228 | } |
| 2229 | |
| 2230 | static void translate_sext(DisasContext *dc, const OpcodeArg arg[], |
| 2231 | const uint32_t par[]) |
| 2232 | { |
| 2233 | tcg_gen_sextract_i32(arg[0].out, arg[1].in, 0, arg[2].imm + 1); |
| 2234 | } |
| 2235 | |
| 2236 | static uint32_t test_exceptions_simcall(DisasContext *dc, |
| 2237 | const OpcodeArg arg[], |
| 2238 | const uint32_t par[]) |
| 2239 | { |
| 2240 | #ifndef CONFIG_USER_ONLY |
| 2241 | if (semihosting_enabled(dc->cring != 0)) { |
| 2242 | return 0; |
| 2243 | } |
| 2244 | #endif |
| 2245 | qemu_log_mask(LOG_GUEST_ERROR, "SIMCALL but semihosting is disabled\n"); |
| 2246 | |
| 2247 | /* Between RE.2 and RE.3 simcall opcode's become nop for the hardware. */ |
| 2248 | return dc->config->hw_version <= 250002 ? XTENSA_OP_ILL : 0; |
| 2249 | } |
| 2250 | |
| 2251 | static void translate_simcall(DisasContext *dc, const OpcodeArg arg[], |
| 2252 | const uint32_t par[]) |
| 2253 | { |
| 2254 | #ifndef CONFIG_USER_ONLY |
| 2255 | if (semihosting_enabled(dc->cring != 0)) { |
| 2256 | gen_helper_simcall(tcg_env); |
| 2257 | } |
| 2258 | #endif |
| 2259 | } |
| 2260 | |
| 2261 | /* |
| 2262 | * Note: 64 bit ops are used here solely because SAR values |
| 2263 | * have range 0..63 |
| 2264 | */ |
| 2265 | #define gen_shift_reg(cmd, reg) do { \ |
| 2266 | TCGv_i64 tmp = tcg_temp_new_i64(); \ |
| 2267 | tcg_gen_extu_i32_i64(tmp, reg); \ |
| 2268 | tcg_gen_##cmd##_i64(v, v, tmp); \ |
| 2269 | tcg_gen_extrl_i64_i32(arg[0].out, v); \ |
| 2270 | } while (0) |
| 2271 | |
| 2272 | #define gen_shift(cmd) gen_shift_reg(cmd, cpu_SR[SAR]) |
| 2273 | |
| 2274 | static void translate_sll(DisasContext *dc, const OpcodeArg arg[], |
| 2275 | const uint32_t par[]) |
| 2276 | { |
| 2277 | if (dc->sar_m32_5bit) { |
| 2278 | tcg_gen_shl_i32(arg[0].out, arg[1].in, dc->sar_m32); |
| 2279 | } else { |
| 2280 | TCGv_i64 v = tcg_temp_new_i64(); |
| 2281 | TCGv_i32 s = tcg_temp_new(); |
| 2282 | tcg_gen_subfi_i32(s, 32, cpu_SR[SAR]); |
| 2283 | tcg_gen_andi_i32(s, s, 0x3f); |
| 2284 | tcg_gen_extu_i32_i64(v, arg[1].in); |
| 2285 | gen_shift_reg(shl, s); |
| 2286 | } |
| 2287 | } |
| 2288 | |
| 2289 | static void translate_slli(DisasContext *dc, const OpcodeArg arg[], |
| 2290 | const uint32_t par[]) |
| 2291 | { |
| 2292 | if (arg[2].imm == 32) { |
| 2293 | qemu_log_mask(LOG_GUEST_ERROR, "slli a%d, a%d, 32 is undefined\n", |
| 2294 | arg[0].imm, arg[1].imm); |
| 2295 | } |
| 2296 | tcg_gen_shli_i32(arg[0].out, arg[1].in, arg[2].imm & 0x1f); |
| 2297 | } |
| 2298 | |
| 2299 | static void translate_sra(DisasContext *dc, const OpcodeArg arg[], |
| 2300 | const uint32_t par[]) |
| 2301 | { |
| 2302 | if (dc->sar_m32_5bit) { |
| 2303 | tcg_gen_sar_i32(arg[0].out, arg[1].in, cpu_SR[SAR]); |
| 2304 | } else { |
| 2305 | TCGv_i64 v = tcg_temp_new_i64(); |
| 2306 | tcg_gen_ext_i32_i64(v, arg[1].in); |
| 2307 | gen_shift(sar); |
| 2308 | } |
| 2309 | } |
| 2310 | |
| 2311 | static void translate_srai(DisasContext *dc, const OpcodeArg arg[], |
| 2312 | const uint32_t par[]) |
| 2313 | { |
| 2314 | tcg_gen_sari_i32(arg[0].out, arg[1].in, arg[2].imm); |
| 2315 | } |
| 2316 | |
| 2317 | static void translate_src(DisasContext *dc, const OpcodeArg arg[], |
| 2318 | const uint32_t par[]) |
| 2319 | { |
| 2320 | TCGv_i64 v = tcg_temp_new_i64(); |
| 2321 | tcg_gen_concat_i32_i64(v, arg[2].in, arg[1].in); |
| 2322 | gen_shift(shr); |
| 2323 | } |
| 2324 | |
| 2325 | static void translate_srl(DisasContext *dc, const OpcodeArg arg[], |
| 2326 | const uint32_t par[]) |
| 2327 | { |
| 2328 | if (dc->sar_m32_5bit) { |
| 2329 | tcg_gen_shr_i32(arg[0].out, arg[1].in, cpu_SR[SAR]); |
| 2330 | } else { |
| 2331 | TCGv_i64 v = tcg_temp_new_i64(); |
| 2332 | tcg_gen_extu_i32_i64(v, arg[1].in); |
| 2333 | gen_shift(shr); |
| 2334 | } |
| 2335 | } |
| 2336 | |
| 2337 | #undef gen_shift |
| 2338 | #undef gen_shift_reg |
| 2339 | |
| 2340 | static void translate_srli(DisasContext *dc, const OpcodeArg arg[], |
| 2341 | const uint32_t par[]) |
| 2342 | { |
| 2343 | tcg_gen_shri_i32(arg[0].out, arg[1].in, arg[2].imm); |
| 2344 | } |
| 2345 | |
| 2346 | static void translate_ssa8b(DisasContext *dc, const OpcodeArg arg[], |
| 2347 | const uint32_t par[]) |
| 2348 | { |
| 2349 | TCGv_i32 tmp = tcg_temp_new_i32(); |
| 2350 | tcg_gen_shli_i32(tmp, arg[0].in, 3); |
| 2351 | gen_left_shift_sar(dc, tmp); |
| 2352 | } |
| 2353 | |
| 2354 | static void translate_ssa8l(DisasContext *dc, const OpcodeArg arg[], |
| 2355 | const uint32_t par[]) |
| 2356 | { |
| 2357 | TCGv_i32 tmp = tcg_temp_new_i32(); |
| 2358 | tcg_gen_shli_i32(tmp, arg[0].in, 3); |
| 2359 | gen_right_shift_sar(dc, tmp); |
| 2360 | } |
| 2361 | |
| 2362 | static void translate_ssai(DisasContext *dc, const OpcodeArg arg[], |
| 2363 | const uint32_t par[]) |
| 2364 | { |
| 2365 | gen_right_shift_sar(dc, tcg_constant_i32(arg[0].imm)); |
| 2366 | } |
| 2367 | |
| 2368 | static void translate_ssl(DisasContext *dc, const OpcodeArg arg[], |
| 2369 | const uint32_t par[]) |
| 2370 | { |
| 2371 | gen_left_shift_sar(dc, arg[0].in); |
| 2372 | } |
| 2373 | |
| 2374 | static void translate_ssr(DisasContext *dc, const OpcodeArg arg[], |
| 2375 | const uint32_t par[]) |
| 2376 | { |
| 2377 | gen_right_shift_sar(dc, arg[0].in); |
| 2378 | } |
| 2379 | |
| 2380 | static void translate_sub(DisasContext *dc, const OpcodeArg arg[], |
| 2381 | const uint32_t par[]) |
| 2382 | { |
| 2383 | tcg_gen_sub_i32(arg[0].out, arg[1].in, arg[2].in); |
| 2384 | } |
| 2385 | |
| 2386 | static void translate_subx(DisasContext *dc, const OpcodeArg arg[], |
| 2387 | const uint32_t par[]) |
| 2388 | { |
| 2389 | TCGv_i32 tmp = tcg_temp_new_i32(); |
| 2390 | tcg_gen_shli_i32(tmp, arg[1].in, par[0]); |
| 2391 | tcg_gen_sub_i32(arg[0].out, tmp, arg[2].in); |
| 2392 | } |
| 2393 | |
| 2394 | static void translate_waiti(DisasContext *dc, const OpcodeArg arg[], |
| 2395 | const uint32_t par[]) |
| 2396 | { |
| 2397 | #ifndef CONFIG_USER_ONLY |
| 2398 | TCGv_i32 pc = tcg_constant_i32(dc->base.pc_next); |
| 2399 | |
| 2400 | translator_io_start(&dc->base); |
| 2401 | gen_helper_waiti(tcg_env, pc, tcg_constant_i32(arg[0].imm)); |
| 2402 | #endif |
| 2403 | } |
| 2404 | |
| 2405 | static void translate_wtlb(DisasContext *dc, const OpcodeArg arg[], |
| 2406 | const uint32_t par[]) |
| 2407 | { |
| 2408 | #ifndef CONFIG_USER_ONLY |
| 2409 | TCGv_i32 dtlb = tcg_constant_i32(par[0]); |
| 2410 | |
| 2411 | gen_helper_wtlb(tcg_env, arg[0].in, arg[1].in, dtlb); |
| 2412 | #endif |
| 2413 | } |
| 2414 | |
| 2415 | static void translate_wptlb(DisasContext *dc, const OpcodeArg arg[], |
| 2416 | const uint32_t par[]) |
| 2417 | { |
| 2418 | #ifndef CONFIG_USER_ONLY |
| 2419 | gen_helper_wptlb(tcg_env, arg[0].in, arg[1].in); |
| 2420 | #endif |
| 2421 | } |
| 2422 | |
| 2423 | static void translate_wer(DisasContext *dc, const OpcodeArg arg[], |
| 2424 | const uint32_t par[]) |
| 2425 | { |
| 2426 | gen_helper_wer(tcg_env, arg[0].in, arg[1].in); |
| 2427 | } |
| 2428 | |
| 2429 | static void translate_wrmsk_expstate(DisasContext *dc, const OpcodeArg arg[], |
| 2430 | const uint32_t par[]) |
| 2431 | { |
| 2432 | /* TODO: GPIO32 may be a part of coprocessor */ |
| 2433 | tcg_gen_and_i32(cpu_UR[EXPSTATE], arg[0].in, arg[1].in); |
| 2434 | } |
| 2435 | |
| 2436 | static void translate_wsr(DisasContext *dc, const OpcodeArg arg[], |
| 2437 | const uint32_t par[]) |
| 2438 | { |
| 2439 | if (sr_name[par[0]]) { |
| 2440 | tcg_gen_mov_i32(cpu_SR[par[0]], arg[0].in); |
| 2441 | } |
| 2442 | } |
| 2443 | |
| 2444 | static void translate_wsr_mask(DisasContext *dc, const OpcodeArg arg[], |
| 2445 | const uint32_t par[]) |
| 2446 | { |
| 2447 | if (sr_name[par[0]]) { |
| 2448 | tcg_gen_andi_i32(cpu_SR[par[0]], arg[0].in, par[2]); |
| 2449 | } |
| 2450 | } |
| 2451 | |
| 2452 | static void translate_wsr_acchi(DisasContext *dc, const OpcodeArg arg[], |
| 2453 | const uint32_t par[]) |
| 2454 | { |
| 2455 | tcg_gen_ext8s_i32(cpu_SR[par[0]], arg[0].in); |
| 2456 | } |
| 2457 | |
| 2458 | static void translate_wsr_ccompare(DisasContext *dc, const OpcodeArg arg[], |
| 2459 | const uint32_t par[]) |
| 2460 | { |
| 2461 | #ifndef CONFIG_USER_ONLY |
| 2462 | uint32_t id = par[0] - CCOMPARE; |
| 2463 | |
| 2464 | assert(id < dc->config->nccompare); |
| 2465 | translator_io_start(&dc->base); |
| 2466 | tcg_gen_mov_i32(cpu_SR[par[0]], arg[0].in); |
| 2467 | gen_helper_update_ccompare(tcg_env, tcg_constant_i32(id)); |
| 2468 | #endif |
| 2469 | } |
| 2470 | |
| 2471 | static void translate_wsr_ccount(DisasContext *dc, const OpcodeArg arg[], |
| 2472 | const uint32_t par[]) |
| 2473 | { |
| 2474 | #ifndef CONFIG_USER_ONLY |
| 2475 | translator_io_start(&dc->base); |
| 2476 | gen_helper_wsr_ccount(tcg_env, arg[0].in); |
| 2477 | #endif |
| 2478 | } |
| 2479 | |
| 2480 | static void translate_wsr_dbreaka(DisasContext *dc, const OpcodeArg arg[], |
| 2481 | const uint32_t par[]) |
| 2482 | { |
| 2483 | #ifndef CONFIG_USER_ONLY |
| 2484 | unsigned id = par[0] - DBREAKA; |
| 2485 | |
| 2486 | assert(id < dc->config->ndbreak); |
| 2487 | gen_helper_wsr_dbreaka(tcg_env, tcg_constant_i32(id), arg[0].in); |
| 2488 | #endif |
| 2489 | } |
| 2490 | |
| 2491 | static void translate_wsr_dbreakc(DisasContext *dc, const OpcodeArg arg[], |
| 2492 | const uint32_t par[]) |
| 2493 | { |
| 2494 | #ifndef CONFIG_USER_ONLY |
| 2495 | unsigned id = par[0] - DBREAKC; |
| 2496 | |
| 2497 | assert(id < dc->config->ndbreak); |
| 2498 | gen_helper_wsr_dbreakc(tcg_env, tcg_constant_i32(id), arg[0].in); |
| 2499 | #endif |
| 2500 | } |
| 2501 | |
| 2502 | static void translate_wsr_ibreaka(DisasContext *dc, const OpcodeArg arg[], |
| 2503 | const uint32_t par[]) |
| 2504 | { |
| 2505 | #ifndef CONFIG_USER_ONLY |
| 2506 | unsigned id = par[0] - IBREAKA; |
| 2507 | |
| 2508 | assert(id < dc->config->nibreak); |
| 2509 | gen_helper_wsr_ibreaka(tcg_env, tcg_constant_i32(id), arg[0].in); |
| 2510 | #endif |
| 2511 | } |
| 2512 | |
| 2513 | static void translate_wsr_ibreakenable(DisasContext *dc, const OpcodeArg arg[], |
| 2514 | const uint32_t par[]) |
| 2515 | { |
| 2516 | #ifndef CONFIG_USER_ONLY |
| 2517 | gen_helper_wsr_ibreakenable(tcg_env, arg[0].in); |
| 2518 | #endif |
| 2519 | } |
| 2520 | |
| 2521 | static void translate_wsr_icount(DisasContext *dc, const OpcodeArg arg[], |
| 2522 | const uint32_t par[]) |
| 2523 | { |
| 2524 | #ifndef CONFIG_USER_ONLY |
| 2525 | if (dc->icount) { |
| 2526 | tcg_gen_mov_i32(dc->next_icount, arg[0].in); |
| 2527 | } else { |
| 2528 | tcg_gen_mov_i32(cpu_SR[par[0]], arg[0].in); |
| 2529 | } |
| 2530 | #endif |
| 2531 | } |
| 2532 | |
| 2533 | static void translate_wsr_intclear(DisasContext *dc, const OpcodeArg arg[], |
| 2534 | const uint32_t par[]) |
| 2535 | { |
| 2536 | #ifndef CONFIG_USER_ONLY |
| 2537 | gen_helper_intclear(tcg_env, arg[0].in); |
| 2538 | #endif |
| 2539 | } |
| 2540 | |
| 2541 | static void translate_wsr_intset(DisasContext *dc, const OpcodeArg arg[], |
| 2542 | const uint32_t par[]) |
| 2543 | { |
| 2544 | #ifndef CONFIG_USER_ONLY |
| 2545 | gen_helper_intset(tcg_env, arg[0].in); |
| 2546 | #endif |
| 2547 | } |
| 2548 | |
| 2549 | static void translate_wsr_memctl(DisasContext *dc, const OpcodeArg arg[], |
| 2550 | const uint32_t par[]) |
| 2551 | { |
| 2552 | #ifndef CONFIG_USER_ONLY |
| 2553 | gen_helper_wsr_memctl(tcg_env, arg[0].in); |
| 2554 | #endif |
| 2555 | } |
| 2556 | |
| 2557 | static void translate_wsr_mpuenb(DisasContext *dc, const OpcodeArg arg[], |
| 2558 | const uint32_t par[]) |
| 2559 | { |
| 2560 | #ifndef CONFIG_USER_ONLY |
| 2561 | gen_helper_wsr_mpuenb(tcg_env, arg[0].in); |
| 2562 | #endif |
| 2563 | } |
| 2564 | |
| 2565 | static void translate_wsr_ps(DisasContext *dc, const OpcodeArg arg[], |
| 2566 | const uint32_t par[]) |
| 2567 | { |
| 2568 | #ifndef CONFIG_USER_ONLY |
| 2569 | uint32_t mask = PS_WOE | PS_CALLINC | PS_OWB | |
| 2570 | PS_UM | PS_EXCM | PS_INTLEVEL; |
| 2571 | |
| 2572 | if (option_enabled(dc, XTENSA_OPTION_MMU) || |
| 2573 | option_enabled(dc, XTENSA_OPTION_MPU)) { |
| 2574 | mask |= PS_RING; |
| 2575 | } |
| 2576 | tcg_gen_andi_i32(cpu_SR[par[0]], arg[0].in, mask); |
| 2577 | #endif |
| 2578 | } |
| 2579 | |
| 2580 | static void translate_wsr_rasid(DisasContext *dc, const OpcodeArg arg[], |
| 2581 | const uint32_t par[]) |
| 2582 | { |
| 2583 | #ifndef CONFIG_USER_ONLY |
| 2584 | gen_helper_wsr_rasid(tcg_env, arg[0].in); |
| 2585 | #endif |
| 2586 | } |
| 2587 | |
| 2588 | static void translate_wsr_sar(DisasContext *dc, const OpcodeArg arg[], |
| 2589 | const uint32_t par[]) |
| 2590 | { |
| 2591 | tcg_gen_andi_i32(cpu_SR[par[0]], arg[0].in, 0x3f); |
| 2592 | if (dc->sar_m32_5bit) { |
| 2593 | tcg_gen_discard_i32(dc->sar_m32); |
| 2594 | } |
| 2595 | dc->sar_5bit = false; |
| 2596 | dc->sar_m32_5bit = false; |
| 2597 | } |
| 2598 | |
| 2599 | static void translate_wsr_windowbase(DisasContext *dc, const OpcodeArg arg[], |
| 2600 | const uint32_t par[]) |
| 2601 | { |
| 2602 | #ifndef CONFIG_USER_ONLY |
| 2603 | tcg_gen_mov_i32(cpu_windowbase_next, arg[0].in); |
| 2604 | #endif |
| 2605 | } |
| 2606 | |
| 2607 | static void translate_wsr_windowstart(DisasContext *dc, const OpcodeArg arg[], |
| 2608 | const uint32_t par[]) |
| 2609 | { |
| 2610 | #ifndef CONFIG_USER_ONLY |
| 2611 | tcg_gen_andi_i32(cpu_SR[par[0]], arg[0].in, |
| 2612 | (1 << dc->config->nareg / 4) - 1); |
| 2613 | #endif |
| 2614 | } |
| 2615 | |
| 2616 | static void translate_wur(DisasContext *dc, const OpcodeArg arg[], |
| 2617 | const uint32_t par[]) |
| 2618 | { |
| 2619 | tcg_gen_mov_i32(cpu_UR[par[0]], arg[0].in); |
| 2620 | } |
| 2621 | |
| 2622 | static void translate_xor(DisasContext *dc, const OpcodeArg arg[], |
| 2623 | const uint32_t par[]) |
| 2624 | { |
| 2625 | tcg_gen_xor_i32(arg[0].out, arg[1].in, arg[2].in); |
| 2626 | } |
| 2627 | |
| 2628 | static void translate_xsr(DisasContext *dc, const OpcodeArg arg[], |
| 2629 | const uint32_t par[]) |
| 2630 | { |
| 2631 | if (sr_name[par[0]]) { |
| 2632 | TCGv_i32 tmp = tcg_temp_new_i32(); |
| 2633 | |
| 2634 | tcg_gen_mov_i32(tmp, arg[0].in); |
| 2635 | tcg_gen_mov_i32(arg[0].out, cpu_SR[par[0]]); |
| 2636 | tcg_gen_mov_i32(cpu_SR[par[0]], tmp); |
| 2637 | } else { |
| 2638 | tcg_gen_movi_i32(arg[0].out, 0); |
| 2639 | } |
| 2640 | } |
| 2641 | |
| 2642 | static void translate_xsr_mask(DisasContext *dc, const OpcodeArg arg[], |
| 2643 | const uint32_t par[]) |
| 2644 | { |
| 2645 | if (sr_name[par[0]]) { |
| 2646 | TCGv_i32 tmp = tcg_temp_new_i32(); |
| 2647 | |
| 2648 | tcg_gen_mov_i32(tmp, arg[0].in); |
| 2649 | tcg_gen_mov_i32(arg[0].out, cpu_SR[par[0]]); |
| 2650 | tcg_gen_andi_i32(cpu_SR[par[0]], tmp, par[2]); |
| 2651 | } else { |
| 2652 | tcg_gen_movi_i32(arg[0].out, 0); |
| 2653 | } |
| 2654 | } |
| 2655 | |
| 2656 | static void translate_xsr_ccount(DisasContext *dc, const OpcodeArg arg[], |
| 2657 | const uint32_t par[]) |
| 2658 | { |
| 2659 | #ifndef CONFIG_USER_ONLY |
| 2660 | TCGv_i32 tmp = tcg_temp_new_i32(); |
| 2661 | |
| 2662 | translator_io_start(&dc->base); |
| 2663 | gen_helper_update_ccount(tcg_env); |
| 2664 | tcg_gen_mov_i32(tmp, cpu_SR[par[0]]); |
| 2665 | gen_helper_wsr_ccount(tcg_env, arg[0].in); |
| 2666 | tcg_gen_mov_i32(arg[0].out, tmp); |
| 2667 | |
| 2668 | #endif |
| 2669 | } |
| 2670 | |
| 2671 | #define gen_translate_xsr(name) \ |
| 2672 | static void translate_xsr_##name(DisasContext *dc, const OpcodeArg arg[], \ |
| 2673 | const uint32_t par[]) \ |
| 2674 | { \ |
| 2675 | TCGv_i32 tmp = tcg_temp_new_i32(); \ |
| 2676 | \ |
| 2677 | if (sr_name[par[0]]) { \ |
| 2678 | tcg_gen_mov_i32(tmp, cpu_SR[par[0]]); \ |
| 2679 | } else { \ |
| 2680 | tcg_gen_movi_i32(tmp, 0); \ |
| 2681 | } \ |
| 2682 | translate_wsr_##name(dc, arg, par); \ |
| 2683 | tcg_gen_mov_i32(arg[0].out, tmp); \ |
| 2684 | } |
| 2685 | |
| 2686 | gen_translate_xsr(acchi) |
| 2687 | gen_translate_xsr(ccompare) |
| 2688 | gen_translate_xsr(dbreaka) |
| 2689 | gen_translate_xsr(dbreakc) |
| 2690 | gen_translate_xsr(ibreaka) |
| 2691 | gen_translate_xsr(ibreakenable) |
| 2692 | gen_translate_xsr(icount) |
| 2693 | gen_translate_xsr(memctl) |
| 2694 | gen_translate_xsr(mpuenb) |
| 2695 | gen_translate_xsr(ps) |
| 2696 | gen_translate_xsr(rasid) |
| 2697 | gen_translate_xsr(sar) |
| 2698 | gen_translate_xsr(windowbase) |
| 2699 | gen_translate_xsr(windowstart) |
| 2700 | |
| 2701 | #undef gen_translate_xsr |
| 2702 | |
| 2703 | static const XtensaOpcodeOps core_ops[] = { |
| 2704 | { |
| 2705 | .name = "abs", |
| 2706 | .translate = translate_abs, |
| 2707 | }, { |
| 2708 | .name = (const char * const[]) { |
| 2709 | "add", "add.n", NULL, |
| 2710 | }, |
| 2711 | .translate = translate_add, |
| 2712 | .op_flags = XTENSA_OP_NAME_ARRAY, |
| 2713 | }, { |
| 2714 | .name = (const char * const[]) { |
| 2715 | "addi", "addi.n", NULL, |
| 2716 | }, |
| 2717 | .translate = translate_addi, |
| 2718 | .op_flags = XTENSA_OP_NAME_ARRAY, |
| 2719 | }, { |
| 2720 | .name = "addmi", |
| 2721 | .translate = translate_addi, |
| 2722 | }, { |
| 2723 | .name = "addx2", |
| 2724 | .translate = translate_addx, |
| 2725 | .par = (const uint32_t[]){1}, |
| 2726 | }, { |
| 2727 | .name = "addx4", |
| 2728 | .translate = translate_addx, |
| 2729 | .par = (const uint32_t[]){2}, |
| 2730 | }, { |
| 2731 | .name = "addx8", |
| 2732 | .translate = translate_addx, |
| 2733 | .par = (const uint32_t[]){3}, |
| 2734 | }, { |
| 2735 | .name = "all4", |
| 2736 | .translate = translate_all, |
| 2737 | .par = (const uint32_t[]){true, 4}, |
| 2738 | }, { |
| 2739 | .name = "all8", |
| 2740 | .translate = translate_all, |
| 2741 | .par = (const uint32_t[]){true, 8}, |
| 2742 | }, { |
| 2743 | .name = "and", |
| 2744 | .translate = translate_and, |
| 2745 | }, { |
| 2746 | .name = "andb", |
| 2747 | .translate = translate_boolean, |
| 2748 | .par = (const uint32_t[]){BOOLEAN_AND}, |
| 2749 | }, { |
| 2750 | .name = "andbc", |
| 2751 | .translate = translate_boolean, |
| 2752 | .par = (const uint32_t[]){BOOLEAN_ANDC}, |
| 2753 | }, { |
| 2754 | .name = "any4", |
| 2755 | .translate = translate_all, |
| 2756 | .par = (const uint32_t[]){false, 4}, |
| 2757 | }, { |
| 2758 | .name = "any8", |
| 2759 | .translate = translate_all, |
| 2760 | .par = (const uint32_t[]){false, 8}, |
| 2761 | }, { |
| 2762 | .name = (const char * const[]) { |
| 2763 | "ball", "ball.w15", "ball.w18", NULL, |
| 2764 | }, |
| 2765 | .translate = translate_ball, |
| 2766 | .par = (const uint32_t[]){TCG_COND_EQ}, |
| 2767 | .op_flags = XTENSA_OP_NAME_ARRAY, |
| 2768 | }, { |
| 2769 | .name = (const char * const[]) { |
| 2770 | "bany", "bany.w15", "bany.w18", NULL, |
| 2771 | }, |
| 2772 | .translate = translate_bany, |
| 2773 | .par = (const uint32_t[]){TCG_COND_NE}, |
| 2774 | .op_flags = XTENSA_OP_NAME_ARRAY, |
| 2775 | }, { |
| 2776 | .name = (const char * const[]) { |
| 2777 | "bbc", "bbc.w15", "bbc.w18", NULL, |
| 2778 | }, |
| 2779 | .translate = translate_bb, |
| 2780 | .par = (const uint32_t[]){TCG_COND_EQ}, |
| 2781 | .op_flags = XTENSA_OP_NAME_ARRAY, |
| 2782 | }, { |
| 2783 | .name = (const char * const[]) { |
| 2784 | "bbci", "bbci.w15", "bbci.w18", NULL, |
| 2785 | }, |
| 2786 | .translate = translate_bbi, |
| 2787 | .par = (const uint32_t[]){TCG_COND_EQ}, |
| 2788 | .op_flags = XTENSA_OP_NAME_ARRAY, |
| 2789 | }, { |
| 2790 | .name = (const char * const[]) { |
| 2791 | "bbs", "bbs.w15", "bbs.w18", NULL, |
| 2792 | }, |
| 2793 | .translate = translate_bb, |
| 2794 | .par = (const uint32_t[]){TCG_COND_NE}, |
| 2795 | .op_flags = XTENSA_OP_NAME_ARRAY, |
| 2796 | }, { |
| 2797 | .name = (const char * const[]) { |
| 2798 | "bbsi", "bbsi.w15", "bbsi.w18", NULL, |
| 2799 | }, |
| 2800 | .translate = translate_bbi, |
| 2801 | .par = (const uint32_t[]){TCG_COND_NE}, |
| 2802 | .op_flags = XTENSA_OP_NAME_ARRAY, |
| 2803 | }, { |
| 2804 | .name = (const char * const[]) { |
| 2805 | "beq", "beq.w15", "beq.w18", NULL, |
| 2806 | }, |
| 2807 | .translate = translate_b, |
| 2808 | .par = (const uint32_t[]){TCG_COND_EQ}, |
| 2809 | .op_flags = XTENSA_OP_NAME_ARRAY, |
| 2810 | }, { |
| 2811 | .name = (const char * const[]) { |
| 2812 | "beqi", "beqi.w15", "beqi.w18", NULL, |
| 2813 | }, |
| 2814 | .translate = translate_bi, |
| 2815 | .par = (const uint32_t[]){TCG_COND_EQ}, |
| 2816 | .op_flags = XTENSA_OP_NAME_ARRAY, |
| 2817 | }, { |
| 2818 | .name = (const char * const[]) { |
| 2819 | "beqz", "beqz.n", "beqz.w15", "beqz.w18", NULL, |
| 2820 | }, |
| 2821 | .translate = translate_bz, |
| 2822 | .par = (const uint32_t[]){TCG_COND_EQ}, |
| 2823 | .op_flags = XTENSA_OP_NAME_ARRAY, |
| 2824 | }, { |
| 2825 | .name = "bf", |
| 2826 | .translate = translate_bp, |
| 2827 | .par = (const uint32_t[]){TCG_COND_EQ}, |
| 2828 | }, { |
| 2829 | .name = (const char * const[]) { |
| 2830 | "bge", "bge.w15", "bge.w18", NULL, |
| 2831 | }, |
| 2832 | .translate = translate_b, |
| 2833 | .par = (const uint32_t[]){TCG_COND_GE}, |
| 2834 | .op_flags = XTENSA_OP_NAME_ARRAY, |
| 2835 | }, { |
| 2836 | .name = (const char * const[]) { |
| 2837 | "bgei", "bgei.w15", "bgei.w18", NULL, |
| 2838 | }, |
| 2839 | .translate = translate_bi, |
| 2840 | .par = (const uint32_t[]){TCG_COND_GE}, |
| 2841 | .op_flags = XTENSA_OP_NAME_ARRAY, |
| 2842 | }, { |
| 2843 | .name = (const char * const[]) { |
| 2844 | "bgeu", "bgeu.w15", "bgeu.w18", NULL, |
| 2845 | }, |
| 2846 | .translate = translate_b, |
| 2847 | .par = (const uint32_t[]){TCG_COND_GEU}, |
| 2848 | .op_flags = XTENSA_OP_NAME_ARRAY, |
| 2849 | }, { |
| 2850 | .name = (const char * const[]) { |
| 2851 | "bgeui", "bgeui.w15", "bgeui.w18", NULL, |
| 2852 | }, |
| 2853 | .translate = translate_bi, |
| 2854 | .par = (const uint32_t[]){TCG_COND_GEU}, |
| 2855 | .op_flags = XTENSA_OP_NAME_ARRAY, |
| 2856 | }, { |
| 2857 | .name = (const char * const[]) { |
| 2858 | "bgez", "bgez.w15", "bgez.w18", NULL, |
| 2859 | }, |
| 2860 | .translate = translate_bz, |
| 2861 | .par = (const uint32_t[]){TCG_COND_GE}, |
| 2862 | .op_flags = XTENSA_OP_NAME_ARRAY, |
| 2863 | }, { |
| 2864 | .name = (const char * const[]) { |
| 2865 | "blt", "blt.w15", "blt.w18", NULL, |
| 2866 | }, |
| 2867 | .translate = translate_b, |
| 2868 | .par = (const uint32_t[]){TCG_COND_LT}, |
| 2869 | .op_flags = XTENSA_OP_NAME_ARRAY, |
| 2870 | }, { |
| 2871 | .name = (const char * const[]) { |
| 2872 | "blti", "blti.w15", "blti.w18", NULL, |
| 2873 | }, |
| 2874 | .translate = translate_bi, |
| 2875 | .par = (const uint32_t[]){TCG_COND_LT}, |
| 2876 | .op_flags = XTENSA_OP_NAME_ARRAY, |
| 2877 | }, { |
| 2878 | .name = (const char * const[]) { |
| 2879 | "bltu", "bltu.w15", "bltu.w18", NULL, |
| 2880 | }, |
| 2881 | .translate = translate_b, |
| 2882 | .par = (const uint32_t[]){TCG_COND_LTU}, |
| 2883 | .op_flags = XTENSA_OP_NAME_ARRAY, |
| 2884 | }, { |
| 2885 | .name = (const char * const[]) { |
| 2886 | "bltui", "bltui.w15", "bltui.w18", NULL, |
| 2887 | }, |
| 2888 | .translate = translate_bi, |
| 2889 | .par = (const uint32_t[]){TCG_COND_LTU}, |
| 2890 | .op_flags = XTENSA_OP_NAME_ARRAY, |
| 2891 | }, { |
| 2892 | .name = (const char * const[]) { |
| 2893 | "bltz", "bltz.w15", "bltz.w18", NULL, |
| 2894 | }, |
| 2895 | .translate = translate_bz, |
| 2896 | .par = (const uint32_t[]){TCG_COND_LT}, |
| 2897 | .op_flags = XTENSA_OP_NAME_ARRAY, |
| 2898 | }, { |
| 2899 | .name = (const char * const[]) { |
| 2900 | "bnall", "bnall.w15", "bnall.w18", NULL, |
| 2901 | }, |
| 2902 | .translate = translate_ball, |
| 2903 | .par = (const uint32_t[]){TCG_COND_NE}, |
| 2904 | .op_flags = XTENSA_OP_NAME_ARRAY, |
| 2905 | }, { |
| 2906 | .name = (const char * const[]) { |
| 2907 | "bne", "bne.w15", "bne.w18", NULL, |
| 2908 | }, |
| 2909 | .translate = translate_b, |
| 2910 | .par = (const uint32_t[]){TCG_COND_NE}, |
| 2911 | .op_flags = XTENSA_OP_NAME_ARRAY, |
| 2912 | }, { |
| 2913 | .name = (const char * const[]) { |
| 2914 | "bnei", "bnei.w15", "bnei.w18", NULL, |
| 2915 | }, |
| 2916 | .translate = translate_bi, |
| 2917 | .par = (const uint32_t[]){TCG_COND_NE}, |
| 2918 | .op_flags = XTENSA_OP_NAME_ARRAY, |
| 2919 | }, { |
| 2920 | .name = (const char * const[]) { |
| 2921 | "bnez", "bnez.n", "bnez.w15", "bnez.w18", NULL, |
| 2922 | }, |
| 2923 | .translate = translate_bz, |
| 2924 | .par = (const uint32_t[]){TCG_COND_NE}, |
| 2925 | .op_flags = XTENSA_OP_NAME_ARRAY, |
| 2926 | }, { |
| 2927 | .name = (const char * const[]) { |
| 2928 | "bnone", "bnone.w15", "bnone.w18", NULL, |
| 2929 | }, |
| 2930 | .translate = translate_bany, |
| 2931 | .par = (const uint32_t[]){TCG_COND_EQ}, |
| 2932 | .op_flags = XTENSA_OP_NAME_ARRAY, |
| 2933 | }, { |
| 2934 | .name = "break", |
| 2935 | .translate = translate_nop, |
| 2936 | .par = (const uint32_t[]){DEBUGCAUSE_BI}, |
| 2937 | .op_flags = XTENSA_OP_DEBUG_BREAK, |
| 2938 | }, { |
| 2939 | .name = "break.n", |
| 2940 | .translate = translate_nop, |
| 2941 | .par = (const uint32_t[]){DEBUGCAUSE_BN}, |
| 2942 | .op_flags = XTENSA_OP_DEBUG_BREAK, |
| 2943 | }, { |
| 2944 | .name = "bt", |
| 2945 | .translate = translate_bp, |
| 2946 | .par = (const uint32_t[]){TCG_COND_NE}, |
| 2947 | }, { |
| 2948 | .name = "call0", |
| 2949 | .translate = translate_call0, |
| 2950 | }, { |
| 2951 | .name = "call12", |
| 2952 | .translate = translate_callw, |
| 2953 | .par = (const uint32_t[]){3}, |
| 2954 | }, { |
| 2955 | .name = "call4", |
| 2956 | .translate = translate_callw, |
| 2957 | .par = (const uint32_t[]){1}, |
| 2958 | }, { |
| 2959 | .name = "call8", |
| 2960 | .translate = translate_callw, |
| 2961 | .par = (const uint32_t[]){2}, |
| 2962 | }, { |
| 2963 | .name = "callx0", |
| 2964 | .translate = translate_callx0, |
| 2965 | }, { |
| 2966 | .name = "callx12", |
| 2967 | .translate = translate_callxw, |
| 2968 | .par = (const uint32_t[]){3}, |
| 2969 | }, { |
| 2970 | .name = "callx4", |
| 2971 | .translate = translate_callxw, |
| 2972 | .par = (const uint32_t[]){1}, |
| 2973 | }, { |
| 2974 | .name = "callx8", |
| 2975 | .translate = translate_callxw, |
| 2976 | .par = (const uint32_t[]){2}, |
| 2977 | }, { |
| 2978 | .name = "clamps", |
| 2979 | .translate = translate_clamps, |
| 2980 | }, { |
| 2981 | .name = "clrb_expstate", |
| 2982 | .translate = translate_clrb_expstate, |
| 2983 | }, { |
| 2984 | .name = "clrex", |
| 2985 | .translate = translate_clrex, |
| 2986 | }, { |
| 2987 | .name = "const16", |
| 2988 | .translate = translate_const16, |
| 2989 | }, { |
| 2990 | .name = "depbits", |
| 2991 | .translate = translate_depbits, |
| 2992 | }, { |
| 2993 | .name = "dhi", |
| 2994 | .translate = translate_dcache, |
| 2995 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 2996 | }, { |
| 2997 | .name = "dhi.b", |
| 2998 | .translate = translate_nop, |
| 2999 | }, { |
| 3000 | .name = "dhu", |
| 3001 | .translate = translate_dcache, |
| 3002 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 3003 | }, { |
| 3004 | .name = "dhwb", |
| 3005 | .translate = translate_dcache, |
| 3006 | }, { |
| 3007 | .name = "dhwb.b", |
| 3008 | .translate = translate_nop, |
| 3009 | }, { |
| 3010 | .name = "dhwbi", |
| 3011 | .translate = translate_dcache, |
| 3012 | }, { |
| 3013 | .name = "dhwbi.b", |
| 3014 | .translate = translate_nop, |
| 3015 | }, { |
| 3016 | .name = "dii", |
| 3017 | .translate = translate_nop, |
| 3018 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 3019 | }, { |
| 3020 | .name = "diu", |
| 3021 | .translate = translate_nop, |
| 3022 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 3023 | }, { |
| 3024 | .name = "diwb", |
| 3025 | .translate = translate_nop, |
| 3026 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 3027 | }, { |
| 3028 | .name = "diwbi", |
| 3029 | .translate = translate_nop, |
| 3030 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 3031 | }, { |
| 3032 | .name = "diwbui.p", |
| 3033 | .translate = translate_diwbuip, |
| 3034 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 3035 | }, { |
| 3036 | .name = "dpfl", |
| 3037 | .translate = translate_dcache, |
| 3038 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 3039 | }, { |
| 3040 | .name = "dpfm.b", |
| 3041 | .translate = translate_nop, |
| 3042 | }, { |
| 3043 | .name = "dpfm.bf", |
| 3044 | .translate = translate_nop, |
| 3045 | }, { |
| 3046 | .name = "dpfr", |
| 3047 | .translate = translate_nop, |
| 3048 | }, { |
| 3049 | .name = "dpfr.b", |
| 3050 | .translate = translate_nop, |
| 3051 | }, { |
| 3052 | .name = "dpfr.bf", |
| 3053 | .translate = translate_nop, |
| 3054 | }, { |
| 3055 | .name = "dpfro", |
| 3056 | .translate = translate_nop, |
| 3057 | }, { |
| 3058 | .name = "dpfw", |
| 3059 | .translate = translate_nop, |
| 3060 | }, { |
| 3061 | .name = "dpfw.b", |
| 3062 | .translate = translate_nop, |
| 3063 | }, { |
| 3064 | .name = "dpfw.bf", |
| 3065 | .translate = translate_nop, |
| 3066 | }, { |
| 3067 | .name = "dpfwo", |
| 3068 | .translate = translate_nop, |
| 3069 | }, { |
| 3070 | .name = "dsync", |
| 3071 | .translate = translate_nop, |
| 3072 | }, { |
| 3073 | .name = "entry", |
| 3074 | .translate = translate_entry, |
| 3075 | .test_exceptions = test_exceptions_entry, |
| 3076 | .test_overflow = test_overflow_entry, |
| 3077 | .op_flags = XTENSA_OP_EXIT_TB_M1 | |
| 3078 | XTENSA_OP_SYNC_REGISTER_WINDOW, |
| 3079 | }, { |
| 3080 | .name = "esync", |
| 3081 | .translate = translate_nop, |
| 3082 | }, { |
| 3083 | .name = "excw", |
| 3084 | .translate = translate_nop, |
| 3085 | }, { |
| 3086 | .name = "extui", |
| 3087 | .translate = translate_extui, |
| 3088 | }, { |
| 3089 | .name = "extw", |
| 3090 | .translate = translate_memw, |
| 3091 | }, { |
| 3092 | .name = "getex", |
| 3093 | .translate = translate_getex, |
| 3094 | }, { |
| 3095 | .name = "hwwdtlba", |
| 3096 | .op_flags = XTENSA_OP_ILL, |
| 3097 | }, { |
| 3098 | .name = "hwwitlba", |
| 3099 | .op_flags = XTENSA_OP_ILL, |
| 3100 | }, { |
| 3101 | .name = "idtlb", |
| 3102 | .translate = translate_itlb, |
| 3103 | .par = (const uint32_t[]){true}, |
| 3104 | .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, |
| 3105 | }, { |
| 3106 | .name = "ihi", |
| 3107 | .translate = translate_icache, |
| 3108 | }, { |
| 3109 | .name = "ihu", |
| 3110 | .translate = translate_icache, |
| 3111 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 3112 | }, { |
| 3113 | .name = "iii", |
| 3114 | .translate = translate_nop, |
| 3115 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 3116 | }, { |
| 3117 | .name = "iitlb", |
| 3118 | .translate = translate_itlb, |
| 3119 | .par = (const uint32_t[]){false}, |
| 3120 | .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, |
| 3121 | }, { |
| 3122 | .name = "iiu", |
| 3123 | .translate = translate_nop, |
| 3124 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 3125 | }, { |
| 3126 | .name = (const char * const[]) { |
| 3127 | "ill", "ill.n", NULL, |
| 3128 | }, |
| 3129 | .op_flags = XTENSA_OP_ILL | XTENSA_OP_NAME_ARRAY, |
| 3130 | }, { |
| 3131 | .name = "ipf", |
| 3132 | .translate = translate_nop, |
| 3133 | }, { |
| 3134 | .name = "ipfl", |
| 3135 | .translate = translate_icache, |
| 3136 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 3137 | }, { |
| 3138 | .name = "isync", |
| 3139 | .translate = translate_nop, |
| 3140 | }, { |
| 3141 | .name = "j", |
| 3142 | .translate = translate_j, |
| 3143 | }, { |
| 3144 | .name = "jx", |
| 3145 | .translate = translate_jx, |
| 3146 | }, { |
| 3147 | .name = "l16si", |
| 3148 | .translate = translate_ldst, |
| 3149 | .par = (const uint32_t[]){MO_TESW, false, false}, |
| 3150 | .op_flags = XTENSA_OP_LOAD, |
| 3151 | }, { |
| 3152 | .name = "l16ui", |
| 3153 | .translate = translate_ldst, |
| 3154 | .par = (const uint32_t[]){MO_TEUW, false, false}, |
| 3155 | .op_flags = XTENSA_OP_LOAD, |
| 3156 | }, { |
| 3157 | .name = "l32ai", |
| 3158 | .translate = translate_ldst, |
| 3159 | .par = (const uint32_t[]){MO_TEUL | MO_ALIGN, true, false}, |
| 3160 | .op_flags = XTENSA_OP_LOAD, |
| 3161 | }, { |
| 3162 | .name = "l32e", |
| 3163 | .translate = translate_l32e, |
| 3164 | .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_LOAD, |
| 3165 | }, { |
| 3166 | .name = "l32ex", |
| 3167 | .translate = translate_l32ex, |
| 3168 | .op_flags = XTENSA_OP_LOAD, |
| 3169 | }, { |
| 3170 | .name = (const char * const[]) { |
| 3171 | "l32i", "l32i.n", NULL, |
| 3172 | }, |
| 3173 | .translate = translate_ldst, |
| 3174 | .par = (const uint32_t[]){MO_TEUL, false, false}, |
| 3175 | .op_flags = XTENSA_OP_NAME_ARRAY | XTENSA_OP_LOAD, |
| 3176 | }, { |
| 3177 | .name = "l32r", |
| 3178 | .translate = translate_l32r, |
| 3179 | .op_flags = XTENSA_OP_LOAD, |
| 3180 | }, { |
| 3181 | .name = "l8ui", |
| 3182 | .translate = translate_ldst, |
| 3183 | .par = (const uint32_t[]){MO_UB, false, false}, |
| 3184 | .op_flags = XTENSA_OP_LOAD, |
| 3185 | }, { |
| 3186 | .name = "ldct", |
| 3187 | .translate = translate_lct, |
| 3188 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 3189 | }, { |
| 3190 | .name = "ldcw", |
| 3191 | .translate = translate_nop, |
| 3192 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 3193 | }, { |
| 3194 | .name = "lddec", |
| 3195 | .translate = translate_mac16, |
| 3196 | .par = (const uint32_t[]){MAC16_NONE, 0, -4}, |
| 3197 | .op_flags = XTENSA_OP_LOAD, |
| 3198 | }, { |
| 3199 | .name = "ldinc", |
| 3200 | .translate = translate_mac16, |
| 3201 | .par = (const uint32_t[]){MAC16_NONE, 0, 4}, |
| 3202 | .op_flags = XTENSA_OP_LOAD, |
| 3203 | }, { |
| 3204 | .name = "ldpte", |
| 3205 | .op_flags = XTENSA_OP_ILL, |
| 3206 | }, { |
| 3207 | .name = "lict", |
| 3208 | .translate = translate_lct, |
| 3209 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 3210 | }, { |
| 3211 | .name = "licw", |
| 3212 | .translate = translate_nop, |
| 3213 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 3214 | }, { |
| 3215 | .name = (const char * const[]) { |
| 3216 | "loop", "loop.w15", NULL, |
| 3217 | }, |
| 3218 | .translate = translate_loop, |
| 3219 | .par = (const uint32_t[]){TCG_COND_NEVER}, |
| 3220 | .op_flags = XTENSA_OP_NAME_ARRAY, |
| 3221 | }, { |
| 3222 | .name = (const char * const[]) { |
| 3223 | "loopgtz", "loopgtz.w15", NULL, |
| 3224 | }, |
| 3225 | .translate = translate_loop, |
| 3226 | .par = (const uint32_t[]){TCG_COND_GT}, |
| 3227 | .op_flags = XTENSA_OP_NAME_ARRAY, |
| 3228 | }, { |
| 3229 | .name = (const char * const[]) { |
| 3230 | "loopnez", "loopnez.w15", NULL, |
| 3231 | }, |
| 3232 | .translate = translate_loop, |
| 3233 | .par = (const uint32_t[]){TCG_COND_NE}, |
| 3234 | .op_flags = XTENSA_OP_NAME_ARRAY, |
| 3235 | }, { |
| 3236 | .name = "max", |
| 3237 | .translate = translate_smax, |
| 3238 | }, { |
| 3239 | .name = "maxu", |
| 3240 | .translate = translate_umax, |
| 3241 | }, { |
| 3242 | .name = "memw", |
| 3243 | .translate = translate_memw, |
| 3244 | }, { |
| 3245 | .name = "min", |
| 3246 | .translate = translate_smin, |
| 3247 | }, { |
| 3248 | .name = "minu", |
| 3249 | .translate = translate_umin, |
| 3250 | }, { |
| 3251 | .name = (const char * const[]) { |
| 3252 | "mov", "mov.n", NULL, |
| 3253 | }, |
| 3254 | .translate = translate_mov, |
| 3255 | .op_flags = XTENSA_OP_NAME_ARRAY, |
| 3256 | }, { |
| 3257 | .name = "moveqz", |
| 3258 | .translate = translate_movcond, |
| 3259 | .par = (const uint32_t[]){TCG_COND_EQ}, |
| 3260 | }, { |
| 3261 | .name = "movf", |
| 3262 | .translate = translate_movp, |
| 3263 | .par = (const uint32_t[]){TCG_COND_EQ}, |
| 3264 | }, { |
| 3265 | .name = "movgez", |
| 3266 | .translate = translate_movcond, |
| 3267 | .par = (const uint32_t[]){TCG_COND_GE}, |
| 3268 | }, { |
| 3269 | .name = "movi", |
| 3270 | .translate = translate_movi, |
| 3271 | }, { |
| 3272 | .name = "movi.n", |
| 3273 | .translate = translate_movi, |
| 3274 | }, { |
| 3275 | .name = "movltz", |
| 3276 | .translate = translate_movcond, |
| 3277 | .par = (const uint32_t[]){TCG_COND_LT}, |
| 3278 | }, { |
| 3279 | .name = "movnez", |
| 3280 | .translate = translate_movcond, |
| 3281 | .par = (const uint32_t[]){TCG_COND_NE}, |
| 3282 | }, { |
| 3283 | .name = "movsp", |
| 3284 | .translate = translate_movsp, |
| 3285 | .op_flags = XTENSA_OP_ALLOCA, |
| 3286 | }, { |
| 3287 | .name = "movt", |
| 3288 | .translate = translate_movp, |
| 3289 | .par = (const uint32_t[]){TCG_COND_NE}, |
| 3290 | }, { |
| 3291 | .name = "mul.aa.hh", |
| 3292 | .translate = translate_mac16, |
| 3293 | .par = (const uint32_t[]){MAC16_MUL, MAC16_HH, 0}, |
| 3294 | }, { |
| 3295 | .name = "mul.aa.hl", |
| 3296 | .translate = translate_mac16, |
| 3297 | .par = (const uint32_t[]){MAC16_MUL, MAC16_HL, 0}, |
| 3298 | }, { |
| 3299 | .name = "mul.aa.lh", |
| 3300 | .translate = translate_mac16, |
| 3301 | .par = (const uint32_t[]){MAC16_MUL, MAC16_LH, 0}, |
| 3302 | }, { |
| 3303 | .name = "mul.aa.ll", |
| 3304 | .translate = translate_mac16, |
| 3305 | .par = (const uint32_t[]){MAC16_MUL, MAC16_LL, 0}, |
| 3306 | }, { |
| 3307 | .name = "mul.ad.hh", |
| 3308 | .translate = translate_mac16, |
| 3309 | .par = (const uint32_t[]){MAC16_MUL, MAC16_HH, 0}, |
| 3310 | }, { |
| 3311 | .name = "mul.ad.hl", |
| 3312 | .translate = translate_mac16, |
| 3313 | .par = (const uint32_t[]){MAC16_MUL, MAC16_HL, 0}, |
| 3314 | }, { |
| 3315 | .name = "mul.ad.lh", |
| 3316 | .translate = translate_mac16, |
| 3317 | .par = (const uint32_t[]){MAC16_MUL, MAC16_LH, 0}, |
| 3318 | }, { |
| 3319 | .name = "mul.ad.ll", |
| 3320 | .translate = translate_mac16, |
| 3321 | .par = (const uint32_t[]){MAC16_MUL, MAC16_LL, 0}, |
| 3322 | }, { |
| 3323 | .name = "mul.da.hh", |
| 3324 | .translate = translate_mac16, |
| 3325 | .par = (const uint32_t[]){MAC16_MUL, MAC16_HH, 0}, |
| 3326 | }, { |
| 3327 | .name = "mul.da.hl", |
| 3328 | .translate = translate_mac16, |
| 3329 | .par = (const uint32_t[]){MAC16_MUL, MAC16_HL, 0}, |
| 3330 | }, { |
| 3331 | .name = "mul.da.lh", |
| 3332 | .translate = translate_mac16, |
| 3333 | .par = (const uint32_t[]){MAC16_MUL, MAC16_LH, 0}, |
| 3334 | }, { |
| 3335 | .name = "mul.da.ll", |
| 3336 | .translate = translate_mac16, |
| 3337 | .par = (const uint32_t[]){MAC16_MUL, MAC16_LL, 0}, |
| 3338 | }, { |
| 3339 | .name = "mul.dd.hh", |
| 3340 | .translate = translate_mac16, |
| 3341 | .par = (const uint32_t[]){MAC16_MUL, MAC16_HH, 0}, |
| 3342 | }, { |
| 3343 | .name = "mul.dd.hl", |
| 3344 | .translate = translate_mac16, |
| 3345 | .par = (const uint32_t[]){MAC16_MUL, MAC16_HL, 0}, |
| 3346 | }, { |
| 3347 | .name = "mul.dd.lh", |
| 3348 | .translate = translate_mac16, |
| 3349 | .par = (const uint32_t[]){MAC16_MUL, MAC16_LH, 0}, |
| 3350 | }, { |
| 3351 | .name = "mul.dd.ll", |
| 3352 | .translate = translate_mac16, |
| 3353 | .par = (const uint32_t[]){MAC16_MUL, MAC16_LL, 0}, |
| 3354 | }, { |
| 3355 | .name = "mul16s", |
| 3356 | .translate = translate_mul16, |
| 3357 | .par = (const uint32_t[]){true}, |
| 3358 | }, { |
| 3359 | .name = "mul16u", |
| 3360 | .translate = translate_mul16, |
| 3361 | .par = (const uint32_t[]){false}, |
| 3362 | }, { |
| 3363 | .name = "mula.aa.hh", |
| 3364 | .translate = translate_mac16, |
| 3365 | .par = (const uint32_t[]){MAC16_MULA, MAC16_HH, 0}, |
| 3366 | }, { |
| 3367 | .name = "mula.aa.hl", |
| 3368 | .translate = translate_mac16, |
| 3369 | .par = (const uint32_t[]){MAC16_MULA, MAC16_HL, 0}, |
| 3370 | }, { |
| 3371 | .name = "mula.aa.lh", |
| 3372 | .translate = translate_mac16, |
| 3373 | .par = (const uint32_t[]){MAC16_MULA, MAC16_LH, 0}, |
| 3374 | }, { |
| 3375 | .name = "mula.aa.ll", |
| 3376 | .translate = translate_mac16, |
| 3377 | .par = (const uint32_t[]){MAC16_MULA, MAC16_LL, 0}, |
| 3378 | }, { |
| 3379 | .name = "mula.ad.hh", |
| 3380 | .translate = translate_mac16, |
| 3381 | .par = (const uint32_t[]){MAC16_MULA, MAC16_HH, 0}, |
| 3382 | }, { |
| 3383 | .name = "mula.ad.hl", |
| 3384 | .translate = translate_mac16, |
| 3385 | .par = (const uint32_t[]){MAC16_MULA, MAC16_HL, 0}, |
| 3386 | }, { |
| 3387 | .name = "mula.ad.lh", |
| 3388 | .translate = translate_mac16, |
| 3389 | .par = (const uint32_t[]){MAC16_MULA, MAC16_LH, 0}, |
| 3390 | }, { |
| 3391 | .name = "mula.ad.ll", |
| 3392 | .translate = translate_mac16, |
| 3393 | .par = (const uint32_t[]){MAC16_MULA, MAC16_LL, 0}, |
| 3394 | }, { |
| 3395 | .name = "mula.da.hh", |
| 3396 | .translate = translate_mac16, |
| 3397 | .par = (const uint32_t[]){MAC16_MULA, MAC16_HH, 0}, |
| 3398 | }, { |
| 3399 | .name = "mula.da.hh.lddec", |
| 3400 | .translate = translate_mac16, |
| 3401 | .par = (const uint32_t[]){MAC16_MULA, MAC16_HH, -4}, |
| 3402 | }, { |
| 3403 | .name = "mula.da.hh.ldinc", |
| 3404 | .translate = translate_mac16, |
| 3405 | .par = (const uint32_t[]){MAC16_MULA, MAC16_HH, 4}, |
| 3406 | }, { |
| 3407 | .name = "mula.da.hl", |
| 3408 | .translate = translate_mac16, |
| 3409 | .par = (const uint32_t[]){MAC16_MULA, MAC16_HL, 0}, |
| 3410 | }, { |
| 3411 | .name = "mula.da.hl.lddec", |
| 3412 | .translate = translate_mac16, |
| 3413 | .par = (const uint32_t[]){MAC16_MULA, MAC16_HL, -4}, |
| 3414 | }, { |
| 3415 | .name = "mula.da.hl.ldinc", |
| 3416 | .translate = translate_mac16, |
| 3417 | .par = (const uint32_t[]){MAC16_MULA, MAC16_HL, 4}, |
| 3418 | }, { |
| 3419 | .name = "mula.da.lh", |
| 3420 | .translate = translate_mac16, |
| 3421 | .par = (const uint32_t[]){MAC16_MULA, MAC16_LH, 0}, |
| 3422 | }, { |
| 3423 | .name = "mula.da.lh.lddec", |
| 3424 | .translate = translate_mac16, |
| 3425 | .par = (const uint32_t[]){MAC16_MULA, MAC16_LH, -4}, |
| 3426 | }, { |
| 3427 | .name = "mula.da.lh.ldinc", |
| 3428 | .translate = translate_mac16, |
| 3429 | .par = (const uint32_t[]){MAC16_MULA, MAC16_LH, 4}, |
| 3430 | }, { |
| 3431 | .name = "mula.da.ll", |
| 3432 | .translate = translate_mac16, |
| 3433 | .par = (const uint32_t[]){MAC16_MULA, MAC16_LL, 0}, |
| 3434 | }, { |
| 3435 | .name = "mula.da.ll.lddec", |
| 3436 | .translate = translate_mac16, |
| 3437 | .par = (const uint32_t[]){MAC16_MULA, MAC16_LL, -4}, |
| 3438 | }, { |
| 3439 | .name = "mula.da.ll.ldinc", |
| 3440 | .translate = translate_mac16, |
| 3441 | .par = (const uint32_t[]){MAC16_MULA, MAC16_LL, 4}, |
| 3442 | }, { |
| 3443 | .name = "mula.dd.hh", |
| 3444 | .translate = translate_mac16, |
| 3445 | .par = (const uint32_t[]){MAC16_MULA, MAC16_HH, 0}, |
| 3446 | }, { |
| 3447 | .name = "mula.dd.hh.lddec", |
| 3448 | .translate = translate_mac16, |
| 3449 | .par = (const uint32_t[]){MAC16_MULA, MAC16_HH, -4}, |
| 3450 | }, { |
| 3451 | .name = "mula.dd.hh.ldinc", |
| 3452 | .translate = translate_mac16, |
| 3453 | .par = (const uint32_t[]){MAC16_MULA, MAC16_HH, 4}, |
| 3454 | }, { |
| 3455 | .name = "mula.dd.hl", |
| 3456 | .translate = translate_mac16, |
| 3457 | .par = (const uint32_t[]){MAC16_MULA, MAC16_HL, 0}, |
| 3458 | }, { |
| 3459 | .name = "mula.dd.hl.lddec", |
| 3460 | .translate = translate_mac16, |
| 3461 | .par = (const uint32_t[]){MAC16_MULA, MAC16_HL, -4}, |
| 3462 | }, { |
| 3463 | .name = "mula.dd.hl.ldinc", |
| 3464 | .translate = translate_mac16, |
| 3465 | .par = (const uint32_t[]){MAC16_MULA, MAC16_HL, 4}, |
| 3466 | }, { |
| 3467 | .name = "mula.dd.lh", |
| 3468 | .translate = translate_mac16, |
| 3469 | .par = (const uint32_t[]){MAC16_MULA, MAC16_LH, 0}, |
| 3470 | }, { |
| 3471 | .name = "mula.dd.lh.lddec", |
| 3472 | .translate = translate_mac16, |
| 3473 | .par = (const uint32_t[]){MAC16_MULA, MAC16_LH, -4}, |
| 3474 | }, { |
| 3475 | .name = "mula.dd.lh.ldinc", |
| 3476 | .translate = translate_mac16, |
| 3477 | .par = (const uint32_t[]){MAC16_MULA, MAC16_LH, 4}, |
| 3478 | }, { |
| 3479 | .name = "mula.dd.ll", |
| 3480 | .translate = translate_mac16, |
| 3481 | .par = (const uint32_t[]){MAC16_MULA, MAC16_LL, 0}, |
| 3482 | }, { |
| 3483 | .name = "mula.dd.ll.lddec", |
| 3484 | .translate = translate_mac16, |
| 3485 | .par = (const uint32_t[]){MAC16_MULA, MAC16_LL, -4}, |
| 3486 | }, { |
| 3487 | .name = "mula.dd.ll.ldinc", |
| 3488 | .translate = translate_mac16, |
| 3489 | .par = (const uint32_t[]){MAC16_MULA, MAC16_LL, 4}, |
| 3490 | }, { |
| 3491 | .name = "mull", |
| 3492 | .translate = translate_mull, |
| 3493 | }, { |
| 3494 | .name = "muls.aa.hh", |
| 3495 | .translate = translate_mac16, |
| 3496 | .par = (const uint32_t[]){MAC16_MULS, MAC16_HH, 0}, |
| 3497 | }, { |
| 3498 | .name = "muls.aa.hl", |
| 3499 | .translate = translate_mac16, |
| 3500 | .par = (const uint32_t[]){MAC16_MULS, MAC16_HL, 0}, |
| 3501 | }, { |
| 3502 | .name = "muls.aa.lh", |
| 3503 | .translate = translate_mac16, |
| 3504 | .par = (const uint32_t[]){MAC16_MULS, MAC16_LH, 0}, |
| 3505 | }, { |
| 3506 | .name = "muls.aa.ll", |
| 3507 | .translate = translate_mac16, |
| 3508 | .par = (const uint32_t[]){MAC16_MULS, MAC16_LL, 0}, |
| 3509 | }, { |
| 3510 | .name = "muls.ad.hh", |
| 3511 | .translate = translate_mac16, |
| 3512 | .par = (const uint32_t[]){MAC16_MULS, MAC16_HH, 0}, |
| 3513 | }, { |
| 3514 | .name = "muls.ad.hl", |
| 3515 | .translate = translate_mac16, |
| 3516 | .par = (const uint32_t[]){MAC16_MULS, MAC16_HL, 0}, |
| 3517 | }, { |
| 3518 | .name = "muls.ad.lh", |
| 3519 | .translate = translate_mac16, |
| 3520 | .par = (const uint32_t[]){MAC16_MULS, MAC16_LH, 0}, |
| 3521 | }, { |
| 3522 | .name = "muls.ad.ll", |
| 3523 | .translate = translate_mac16, |
| 3524 | .par = (const uint32_t[]){MAC16_MULS, MAC16_LL, 0}, |
| 3525 | }, { |
| 3526 | .name = "muls.da.hh", |
| 3527 | .translate = translate_mac16, |
| 3528 | .par = (const uint32_t[]){MAC16_MULS, MAC16_HH, 0}, |
| 3529 | }, { |
| 3530 | .name = "muls.da.hl", |
| 3531 | .translate = translate_mac16, |
| 3532 | .par = (const uint32_t[]){MAC16_MULS, MAC16_HL, 0}, |
| 3533 | }, { |
| 3534 | .name = "muls.da.lh", |
| 3535 | .translate = translate_mac16, |
| 3536 | .par = (const uint32_t[]){MAC16_MULS, MAC16_LH, 0}, |
| 3537 | }, { |
| 3538 | .name = "muls.da.ll", |
| 3539 | .translate = translate_mac16, |
| 3540 | .par = (const uint32_t[]){MAC16_MULS, MAC16_LL, 0}, |
| 3541 | }, { |
| 3542 | .name = "muls.dd.hh", |
| 3543 | .translate = translate_mac16, |
| 3544 | .par = (const uint32_t[]){MAC16_MULS, MAC16_HH, 0}, |
| 3545 | }, { |
| 3546 | .name = "muls.dd.hl", |
| 3547 | .translate = translate_mac16, |
| 3548 | .par = (const uint32_t[]){MAC16_MULS, MAC16_HL, 0}, |
| 3549 | }, { |
| 3550 | .name = "muls.dd.lh", |
| 3551 | .translate = translate_mac16, |
| 3552 | .par = (const uint32_t[]){MAC16_MULS, MAC16_LH, 0}, |
| 3553 | }, { |
| 3554 | .name = "muls.dd.ll", |
| 3555 | .translate = translate_mac16, |
| 3556 | .par = (const uint32_t[]){MAC16_MULS, MAC16_LL, 0}, |
| 3557 | }, { |
| 3558 | .name = "mulsh", |
| 3559 | .translate = translate_mulh, |
| 3560 | .par = (const uint32_t[]){true}, |
| 3561 | }, { |
| 3562 | .name = "muluh", |
| 3563 | .translate = translate_mulh, |
| 3564 | .par = (const uint32_t[]){false}, |
| 3565 | }, { |
| 3566 | .name = "neg", |
| 3567 | .translate = translate_neg, |
| 3568 | }, { |
| 3569 | .name = (const char * const[]) { |
| 3570 | "nop", "nop.n", NULL, |
| 3571 | }, |
| 3572 | .translate = translate_nop, |
| 3573 | .op_flags = XTENSA_OP_NAME_ARRAY, |
| 3574 | }, { |
| 3575 | .name = "nsa", |
| 3576 | .translate = translate_nsa, |
| 3577 | }, { |
| 3578 | .name = "nsau", |
| 3579 | .translate = translate_nsau, |
| 3580 | }, { |
| 3581 | .name = "or", |
| 3582 | .translate = translate_or, |
| 3583 | }, { |
| 3584 | .name = "orb", |
| 3585 | .translate = translate_boolean, |
| 3586 | .par = (const uint32_t[]){BOOLEAN_OR}, |
| 3587 | }, { |
| 3588 | .name = "orbc", |
| 3589 | .translate = translate_boolean, |
| 3590 | .par = (const uint32_t[]){BOOLEAN_ORC}, |
| 3591 | }, { |
| 3592 | .name = "pdtlb", |
| 3593 | .translate = translate_ptlb, |
| 3594 | .par = (const uint32_t[]){true}, |
| 3595 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 3596 | }, { |
| 3597 | .name = "pfend.a", |
| 3598 | .translate = translate_nop, |
| 3599 | }, { |
| 3600 | .name = "pfend.o", |
| 3601 | .translate = translate_nop, |
| 3602 | }, { |
| 3603 | .name = "pfnxt.f", |
| 3604 | .translate = translate_nop, |
| 3605 | }, { |
| 3606 | .name = "pfwait.a", |
| 3607 | .translate = translate_nop, |
| 3608 | }, { |
| 3609 | .name = "pfwait.r", |
| 3610 | .translate = translate_nop, |
| 3611 | }, { |
| 3612 | .name = "pitlb", |
| 3613 | .translate = translate_ptlb, |
| 3614 | .par = (const uint32_t[]){false}, |
| 3615 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 3616 | }, { |
| 3617 | .name = "pptlb", |
| 3618 | .translate = translate_pptlb, |
| 3619 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 3620 | }, { |
| 3621 | .name = "quos", |
| 3622 | .translate = translate_quos, |
| 3623 | .par = (const uint32_t[]){true}, |
| 3624 | .op_flags = XTENSA_OP_DIVIDE_BY_ZERO, |
| 3625 | }, { |
| 3626 | .name = "quou", |
| 3627 | .translate = translate_quou, |
| 3628 | .op_flags = XTENSA_OP_DIVIDE_BY_ZERO, |
| 3629 | }, { |
| 3630 | .name = "rdtlb0", |
| 3631 | .translate = translate_rtlb, |
| 3632 | .par = (const uint32_t[]){true, 0}, |
| 3633 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 3634 | }, { |
| 3635 | .name = "rdtlb1", |
| 3636 | .translate = translate_rtlb, |
| 3637 | .par = (const uint32_t[]){true, 1}, |
| 3638 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 3639 | }, { |
| 3640 | .name = "read_impwire", |
| 3641 | .translate = translate_read_impwire, |
| 3642 | }, { |
| 3643 | .name = "rems", |
| 3644 | .translate = translate_quos, |
| 3645 | .par = (const uint32_t[]){false}, |
| 3646 | .op_flags = XTENSA_OP_DIVIDE_BY_ZERO, |
| 3647 | }, { |
| 3648 | .name = "remu", |
| 3649 | .translate = translate_remu, |
| 3650 | .op_flags = XTENSA_OP_DIVIDE_BY_ZERO, |
| 3651 | }, { |
| 3652 | .name = "rer", |
| 3653 | .translate = translate_rer, |
| 3654 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 3655 | }, { |
| 3656 | .name = (const char * const[]) { |
| 3657 | "ret", "ret.n", NULL, |
| 3658 | }, |
| 3659 | .translate = translate_ret, |
| 3660 | .op_flags = XTENSA_OP_NAME_ARRAY, |
| 3661 | }, { |
| 3662 | .name = (const char * const[]) { |
| 3663 | "retw", "retw.n", NULL, |
| 3664 | }, |
| 3665 | .translate = translate_retw, |
| 3666 | .test_exceptions = test_exceptions_retw, |
| 3667 | .op_flags = XTENSA_OP_UNDERFLOW | XTENSA_OP_NAME_ARRAY, |
| 3668 | }, { |
| 3669 | .name = "rfdd", |
| 3670 | .op_flags = XTENSA_OP_ILL, |
| 3671 | }, { |
| 3672 | .name = "rfde", |
| 3673 | .translate = translate_rfde, |
| 3674 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 3675 | }, { |
| 3676 | .name = "rfdo", |
| 3677 | .op_flags = XTENSA_OP_ILL, |
| 3678 | }, { |
| 3679 | .name = "rfe", |
| 3680 | .translate = translate_rfe, |
| 3681 | .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_CHECK_INTERRUPTS, |
| 3682 | }, { |
| 3683 | .name = "rfi", |
| 3684 | .translate = translate_rfi, |
| 3685 | .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_CHECK_INTERRUPTS, |
| 3686 | }, { |
| 3687 | .name = "rfwo", |
| 3688 | .translate = translate_rfw, |
| 3689 | .par = (const uint32_t[]){true}, |
| 3690 | .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_CHECK_INTERRUPTS, |
| 3691 | }, { |
| 3692 | .name = "rfwu", |
| 3693 | .translate = translate_rfw, |
| 3694 | .par = (const uint32_t[]){false}, |
| 3695 | .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_CHECK_INTERRUPTS, |
| 3696 | }, { |
| 3697 | .name = "ritlb0", |
| 3698 | .translate = translate_rtlb, |
| 3699 | .par = (const uint32_t[]){false, 0}, |
| 3700 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 3701 | }, { |
| 3702 | .name = "ritlb1", |
| 3703 | .translate = translate_rtlb, |
| 3704 | .par = (const uint32_t[]){false, 1}, |
| 3705 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 3706 | }, { |
| 3707 | .name = "rptlb0", |
| 3708 | .translate = translate_rptlb0, |
| 3709 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 3710 | }, { |
| 3711 | .name = "rptlb1", |
| 3712 | .translate = translate_rptlb1, |
| 3713 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 3714 | }, { |
| 3715 | .name = "rotw", |
| 3716 | .translate = translate_rotw, |
| 3717 | .op_flags = XTENSA_OP_PRIVILEGED | |
| 3718 | XTENSA_OP_EXIT_TB_M1 | |
| 3719 | XTENSA_OP_SYNC_REGISTER_WINDOW, |
| 3720 | }, { |
| 3721 | .name = "rsil", |
| 3722 | .translate = translate_rsil, |
| 3723 | .op_flags = |
| 3724 | XTENSA_OP_PRIVILEGED | |
| 3725 | XTENSA_OP_EXIT_TB_0 | |
| 3726 | XTENSA_OP_CHECK_INTERRUPTS, |
| 3727 | }, { |
| 3728 | .name = "rsr.176", |
| 3729 | .translate = translate_rsr, |
| 3730 | .par = (const uint32_t[]){176}, |
| 3731 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 3732 | }, { |
| 3733 | .name = "rsr.208", |
| 3734 | .translate = translate_rsr, |
| 3735 | .par = (const uint32_t[]){208}, |
| 3736 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 3737 | }, { |
| 3738 | .name = "rsr.acchi", |
| 3739 | .translate = translate_rsr, |
| 3740 | .test_exceptions = test_exceptions_sr, |
| 3741 | .par = (const uint32_t[]){ |
| 3742 | ACCHI, |
| 3743 | XTENSA_OPTION_MAC16, |
| 3744 | }, |
| 3745 | }, { |
| 3746 | .name = "rsr.acclo", |
| 3747 | .translate = translate_rsr, |
| 3748 | .test_exceptions = test_exceptions_sr, |
| 3749 | .par = (const uint32_t[]){ |
| 3750 | ACCLO, |
| 3751 | XTENSA_OPTION_MAC16, |
| 3752 | }, |
| 3753 | }, { |
| 3754 | .name = "rsr.atomctl", |
| 3755 | .translate = translate_rsr, |
| 3756 | .test_exceptions = test_exceptions_sr, |
| 3757 | .par = (const uint32_t[]){ |
| 3758 | ATOMCTL, |
| 3759 | XTENSA_OPTION_ATOMCTL, |
| 3760 | }, |
| 3761 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 3762 | }, { |
| 3763 | .name = "rsr.br", |
| 3764 | .translate = translate_rsr, |
| 3765 | .test_exceptions = test_exceptions_sr, |
| 3766 | .par = (const uint32_t[]){ |
| 3767 | BR, |
| 3768 | XTENSA_OPTION_BOOLEAN, |
| 3769 | }, |
| 3770 | }, { |
| 3771 | .name = "rsr.cacheadrdis", |
| 3772 | .translate = translate_rsr, |
| 3773 | .test_exceptions = test_exceptions_sr, |
| 3774 | .par = (const uint32_t[]){ |
| 3775 | CACHEADRDIS, |
| 3776 | XTENSA_OPTION_MPU, |
| 3777 | }, |
| 3778 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 3779 | }, { |
| 3780 | .name = "rsr.cacheattr", |
| 3781 | .translate = translate_rsr, |
| 3782 | .test_exceptions = test_exceptions_sr, |
| 3783 | .par = (const uint32_t[]){ |
| 3784 | CACHEATTR, |
| 3785 | XTENSA_OPTION_CACHEATTR, |
| 3786 | }, |
| 3787 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 3788 | }, { |
| 3789 | .name = "rsr.ccompare0", |
| 3790 | .translate = translate_rsr, |
| 3791 | .test_exceptions = test_exceptions_ccompare, |
| 3792 | .par = (const uint32_t[]){ |
| 3793 | CCOMPARE, |
| 3794 | XTENSA_OPTION_TIMER_INTERRUPT, |
| 3795 | }, |
| 3796 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 3797 | }, { |
| 3798 | .name = "rsr.ccompare1", |
| 3799 | .translate = translate_rsr, |
| 3800 | .test_exceptions = test_exceptions_ccompare, |
| 3801 | .par = (const uint32_t[]){ |
| 3802 | CCOMPARE + 1, |
| 3803 | XTENSA_OPTION_TIMER_INTERRUPT, |
| 3804 | }, |
| 3805 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 3806 | }, { |
| 3807 | .name = "rsr.ccompare2", |
| 3808 | .translate = translate_rsr, |
| 3809 | .test_exceptions = test_exceptions_ccompare, |
| 3810 | .par = (const uint32_t[]){ |
| 3811 | CCOMPARE + 2, |
| 3812 | XTENSA_OPTION_TIMER_INTERRUPT, |
| 3813 | }, |
| 3814 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 3815 | }, { |
| 3816 | .name = "rsr.ccount", |
| 3817 | .translate = translate_rsr_ccount, |
| 3818 | .test_exceptions = test_exceptions_sr, |
| 3819 | .par = (const uint32_t[]){ |
| 3820 | CCOUNT, |
| 3821 | XTENSA_OPTION_TIMER_INTERRUPT, |
| 3822 | }, |
| 3823 | .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, |
| 3824 | }, { |
| 3825 | .name = "rsr.configid0", |
| 3826 | .translate = translate_rsr, |
| 3827 | .par = (const uint32_t[]){CONFIGID0}, |
| 3828 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 3829 | }, { |
| 3830 | .name = "rsr.configid1", |
| 3831 | .translate = translate_rsr, |
| 3832 | .par = (const uint32_t[]){CONFIGID1}, |
| 3833 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 3834 | }, { |
| 3835 | .name = "rsr.cpenable", |
| 3836 | .translate = translate_rsr, |
| 3837 | .test_exceptions = test_exceptions_sr, |
| 3838 | .par = (const uint32_t[]){ |
| 3839 | CPENABLE, |
| 3840 | XTENSA_OPTION_COPROCESSOR, |
| 3841 | }, |
| 3842 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 3843 | }, { |
| 3844 | .name = "rsr.dbreaka0", |
| 3845 | .translate = translate_rsr, |
| 3846 | .test_exceptions = test_exceptions_dbreak, |
| 3847 | .par = (const uint32_t[]){ |
| 3848 | DBREAKA, |
| 3849 | XTENSA_OPTION_DEBUG, |
| 3850 | }, |
| 3851 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 3852 | }, { |
| 3853 | .name = "rsr.dbreaka1", |
| 3854 | .translate = translate_rsr, |
| 3855 | .test_exceptions = test_exceptions_dbreak, |
| 3856 | .par = (const uint32_t[]){ |
| 3857 | DBREAKA + 1, |
| 3858 | XTENSA_OPTION_DEBUG, |
| 3859 | }, |
| 3860 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 3861 | }, { |
| 3862 | .name = "rsr.dbreakc0", |
| 3863 | .translate = translate_rsr, |
| 3864 | .test_exceptions = test_exceptions_dbreak, |
| 3865 | .par = (const uint32_t[]){ |
| 3866 | DBREAKC, |
| 3867 | XTENSA_OPTION_DEBUG, |
| 3868 | }, |
| 3869 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 3870 | }, { |
| 3871 | .name = "rsr.dbreakc1", |
| 3872 | .translate = translate_rsr, |
| 3873 | .test_exceptions = test_exceptions_dbreak, |
| 3874 | .par = (const uint32_t[]){ |
| 3875 | DBREAKC + 1, |
| 3876 | XTENSA_OPTION_DEBUG, |
| 3877 | }, |
| 3878 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 3879 | }, { |
| 3880 | .name = "rsr.ddr", |
| 3881 | .translate = translate_rsr, |
| 3882 | .test_exceptions = test_exceptions_sr, |
| 3883 | .par = (const uint32_t[]){ |
| 3884 | DDR, |
| 3885 | XTENSA_OPTION_DEBUG, |
| 3886 | }, |
| 3887 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 3888 | }, { |
| 3889 | .name = "rsr.debugcause", |
| 3890 | .translate = translate_rsr, |
| 3891 | .test_exceptions = test_exceptions_sr, |
| 3892 | .par = (const uint32_t[]){ |
| 3893 | DEBUGCAUSE, |
| 3894 | XTENSA_OPTION_DEBUG, |
| 3895 | }, |
| 3896 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 3897 | }, { |
| 3898 | .name = "rsr.depc", |
| 3899 | .translate = translate_rsr, |
| 3900 | .test_exceptions = test_exceptions_sr, |
| 3901 | .par = (const uint32_t[]){ |
| 3902 | DEPC, |
| 3903 | XTENSA_OPTION_EXCEPTION, |
| 3904 | }, |
| 3905 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 3906 | }, { |
| 3907 | .name = "rsr.dtlbcfg", |
| 3908 | .translate = translate_rsr, |
| 3909 | .test_exceptions = test_exceptions_sr, |
| 3910 | .par = (const uint32_t[]){ |
| 3911 | DTLBCFG, |
| 3912 | XTENSA_OPTION_MMU, |
| 3913 | }, |
| 3914 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 3915 | }, { |
| 3916 | .name = "rsr.epc1", |
| 3917 | .translate = translate_rsr, |
| 3918 | .test_exceptions = test_exceptions_sr, |
| 3919 | .par = (const uint32_t[]){ |
| 3920 | EPC1, |
| 3921 | XTENSA_OPTION_EXCEPTION, |
| 3922 | }, |
| 3923 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 3924 | }, { |
| 3925 | .name = "rsr.epc2", |
| 3926 | .translate = translate_rsr, |
| 3927 | .test_exceptions = test_exceptions_hpi, |
| 3928 | .par = (const uint32_t[]){ |
| 3929 | EPC1 + 1, |
| 3930 | XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, |
| 3931 | }, |
| 3932 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 3933 | }, { |
| 3934 | .name = "rsr.epc3", |
| 3935 | .translate = translate_rsr, |
| 3936 | .test_exceptions = test_exceptions_hpi, |
| 3937 | .par = (const uint32_t[]){ |
| 3938 | EPC1 + 2, |
| 3939 | XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, |
| 3940 | }, |
| 3941 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 3942 | }, { |
| 3943 | .name = "rsr.epc4", |
| 3944 | .translate = translate_rsr, |
| 3945 | .test_exceptions = test_exceptions_hpi, |
| 3946 | .par = (const uint32_t[]){ |
| 3947 | EPC1 + 3, |
| 3948 | XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, |
| 3949 | }, |
| 3950 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 3951 | }, { |
| 3952 | .name = "rsr.epc5", |
| 3953 | .translate = translate_rsr, |
| 3954 | .test_exceptions = test_exceptions_hpi, |
| 3955 | .par = (const uint32_t[]){ |
| 3956 | EPC1 + 4, |
| 3957 | XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, |
| 3958 | }, |
| 3959 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 3960 | }, { |
| 3961 | .name = "rsr.epc6", |
| 3962 | .translate = translate_rsr, |
| 3963 | .test_exceptions = test_exceptions_hpi, |
| 3964 | .par = (const uint32_t[]){ |
| 3965 | EPC1 + 5, |
| 3966 | XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, |
| 3967 | }, |
| 3968 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 3969 | }, { |
| 3970 | .name = "rsr.epc7", |
| 3971 | .translate = translate_rsr, |
| 3972 | .test_exceptions = test_exceptions_hpi, |
| 3973 | .par = (const uint32_t[]){ |
| 3974 | EPC1 + 6, |
| 3975 | XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, |
| 3976 | }, |
| 3977 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 3978 | }, { |
| 3979 | .name = "rsr.eps2", |
| 3980 | .translate = translate_rsr, |
| 3981 | .test_exceptions = test_exceptions_hpi, |
| 3982 | .par = (const uint32_t[]){ |
| 3983 | EPS2, |
| 3984 | XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, |
| 3985 | }, |
| 3986 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 3987 | }, { |
| 3988 | .name = "rsr.eps3", |
| 3989 | .translate = translate_rsr, |
| 3990 | .test_exceptions = test_exceptions_hpi, |
| 3991 | .par = (const uint32_t[]){ |
| 3992 | EPS2 + 1, |
| 3993 | XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, |
| 3994 | }, |
| 3995 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 3996 | }, { |
| 3997 | .name = "rsr.eps4", |
| 3998 | .translate = translate_rsr, |
| 3999 | .test_exceptions = test_exceptions_hpi, |
| 4000 | .par = (const uint32_t[]){ |
| 4001 | EPS2 + 2, |
| 4002 | XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, |
| 4003 | }, |
| 4004 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 4005 | }, { |
| 4006 | .name = "rsr.eps5", |
| 4007 | .translate = translate_rsr, |
| 4008 | .test_exceptions = test_exceptions_hpi, |
| 4009 | .par = (const uint32_t[]){ |
| 4010 | EPS2 + 3, |
| 4011 | XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, |
| 4012 | }, |
| 4013 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 4014 | }, { |
| 4015 | .name = "rsr.eps6", |
| 4016 | .translate = translate_rsr, |
| 4017 | .test_exceptions = test_exceptions_hpi, |
| 4018 | .par = (const uint32_t[]){ |
| 4019 | EPS2 + 4, |
| 4020 | XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, |
| 4021 | }, |
| 4022 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 4023 | }, { |
| 4024 | .name = "rsr.eps7", |
| 4025 | .translate = translate_rsr, |
| 4026 | .test_exceptions = test_exceptions_hpi, |
| 4027 | .par = (const uint32_t[]){ |
| 4028 | EPS2 + 5, |
| 4029 | XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, |
| 4030 | }, |
| 4031 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 4032 | }, { |
| 4033 | .name = "rsr.eraccess", |
| 4034 | .translate = translate_rsr, |
| 4035 | .par = (const uint32_t[]){ERACCESS}, |
| 4036 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 4037 | }, { |
| 4038 | .name = "rsr.exccause", |
| 4039 | .translate = translate_rsr, |
| 4040 | .test_exceptions = test_exceptions_sr, |
| 4041 | .par = (const uint32_t[]){ |
| 4042 | EXCCAUSE, |
| 4043 | XTENSA_OPTION_EXCEPTION, |
| 4044 | }, |
| 4045 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 4046 | }, { |
| 4047 | .name = "rsr.excsave1", |
| 4048 | .translate = translate_rsr, |
| 4049 | .test_exceptions = test_exceptions_sr, |
| 4050 | .par = (const uint32_t[]){ |
| 4051 | EXCSAVE1, |
| 4052 | XTENSA_OPTION_EXCEPTION, |
| 4053 | }, |
| 4054 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 4055 | }, { |
| 4056 | .name = "rsr.excsave2", |
| 4057 | .translate = translate_rsr, |
| 4058 | .test_exceptions = test_exceptions_hpi, |
| 4059 | .par = (const uint32_t[]){ |
| 4060 | EXCSAVE1 + 1, |
| 4061 | XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, |
| 4062 | }, |
| 4063 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 4064 | }, { |
| 4065 | .name = "rsr.excsave3", |
| 4066 | .translate = translate_rsr, |
| 4067 | .test_exceptions = test_exceptions_hpi, |
| 4068 | .par = (const uint32_t[]){ |
| 4069 | EXCSAVE1 + 2, |
| 4070 | XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, |
| 4071 | }, |
| 4072 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 4073 | }, { |
| 4074 | .name = "rsr.excsave4", |
| 4075 | .translate = translate_rsr, |
| 4076 | .test_exceptions = test_exceptions_hpi, |
| 4077 | .par = (const uint32_t[]){ |
| 4078 | EXCSAVE1 + 3, |
| 4079 | XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, |
| 4080 | }, |
| 4081 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 4082 | }, { |
| 4083 | .name = "rsr.excsave5", |
| 4084 | .translate = translate_rsr, |
| 4085 | .test_exceptions = test_exceptions_hpi, |
| 4086 | .par = (const uint32_t[]){ |
| 4087 | EXCSAVE1 + 4, |
| 4088 | XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, |
| 4089 | }, |
| 4090 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 4091 | }, { |
| 4092 | .name = "rsr.excsave6", |
| 4093 | .translate = translate_rsr, |
| 4094 | .test_exceptions = test_exceptions_hpi, |
| 4095 | .par = (const uint32_t[]){ |
| 4096 | EXCSAVE1 + 5, |
| 4097 | XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, |
| 4098 | }, |
| 4099 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 4100 | }, { |
| 4101 | .name = "rsr.excsave7", |
| 4102 | .translate = translate_rsr, |
| 4103 | .test_exceptions = test_exceptions_hpi, |
| 4104 | .par = (const uint32_t[]){ |
| 4105 | EXCSAVE1 + 6, |
| 4106 | XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, |
| 4107 | }, |
| 4108 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 4109 | }, { |
| 4110 | .name = "rsr.excvaddr", |
| 4111 | .translate = translate_rsr, |
| 4112 | .test_exceptions = test_exceptions_sr, |
| 4113 | .par = (const uint32_t[]){ |
| 4114 | EXCVADDR, |
| 4115 | XTENSA_OPTION_EXCEPTION, |
| 4116 | }, |
| 4117 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 4118 | }, { |
| 4119 | .name = "rsr.ibreaka0", |
| 4120 | .translate = translate_rsr, |
| 4121 | .test_exceptions = test_exceptions_ibreak, |
| 4122 | .par = (const uint32_t[]){ |
| 4123 | IBREAKA, |
| 4124 | XTENSA_OPTION_DEBUG, |
| 4125 | }, |
| 4126 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 4127 | }, { |
| 4128 | .name = "rsr.ibreaka1", |
| 4129 | .translate = translate_rsr, |
| 4130 | .test_exceptions = test_exceptions_ibreak, |
| 4131 | .par = (const uint32_t[]){ |
| 4132 | IBREAKA + 1, |
| 4133 | XTENSA_OPTION_DEBUG, |
| 4134 | }, |
| 4135 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 4136 | }, { |
| 4137 | .name = "rsr.ibreakenable", |
| 4138 | .translate = translate_rsr, |
| 4139 | .test_exceptions = test_exceptions_sr, |
| 4140 | .par = (const uint32_t[]){ |
| 4141 | IBREAKENABLE, |
| 4142 | XTENSA_OPTION_DEBUG, |
| 4143 | }, |
| 4144 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 4145 | }, { |
| 4146 | .name = "rsr.icount", |
| 4147 | .translate = translate_rsr, |
| 4148 | .test_exceptions = test_exceptions_sr, |
| 4149 | .par = (const uint32_t[]){ |
| 4150 | ICOUNT, |
| 4151 | XTENSA_OPTION_DEBUG, |
| 4152 | }, |
| 4153 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 4154 | }, { |
| 4155 | .name = "rsr.icountlevel", |
| 4156 | .translate = translate_rsr, |
| 4157 | .test_exceptions = test_exceptions_sr, |
| 4158 | .par = (const uint32_t[]){ |
| 4159 | ICOUNTLEVEL, |
| 4160 | XTENSA_OPTION_DEBUG, |
| 4161 | }, |
| 4162 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 4163 | }, { |
| 4164 | .name = "rsr.intclear", |
| 4165 | .translate = translate_rsr, |
| 4166 | .test_exceptions = test_exceptions_sr, |
| 4167 | .par = (const uint32_t[]){ |
| 4168 | INTCLEAR, |
| 4169 | XTENSA_OPTION_INTERRUPT, |
| 4170 | }, |
| 4171 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 4172 | }, { |
| 4173 | .name = "rsr.intenable", |
| 4174 | .translate = translate_rsr, |
| 4175 | .test_exceptions = test_exceptions_sr, |
| 4176 | .par = (const uint32_t[]){ |
| 4177 | INTENABLE, |
| 4178 | XTENSA_OPTION_INTERRUPT, |
| 4179 | }, |
| 4180 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 4181 | }, { |
| 4182 | .name = "rsr.interrupt", |
| 4183 | .translate = translate_rsr_ccount, |
| 4184 | .test_exceptions = test_exceptions_sr, |
| 4185 | .par = (const uint32_t[]){ |
| 4186 | INTSET, |
| 4187 | XTENSA_OPTION_INTERRUPT, |
| 4188 | }, |
| 4189 | .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, |
| 4190 | }, { |
| 4191 | .name = "rsr.intset", |
| 4192 | .translate = translate_rsr_ccount, |
| 4193 | .test_exceptions = test_exceptions_sr, |
| 4194 | .par = (const uint32_t[]){ |
| 4195 | INTSET, |
| 4196 | XTENSA_OPTION_INTERRUPT, |
| 4197 | }, |
| 4198 | .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, |
| 4199 | }, { |
| 4200 | .name = "rsr.itlbcfg", |
| 4201 | .translate = translate_rsr, |
| 4202 | .test_exceptions = test_exceptions_sr, |
| 4203 | .par = (const uint32_t[]){ |
| 4204 | ITLBCFG, |
| 4205 | XTENSA_OPTION_MMU, |
| 4206 | }, |
| 4207 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 4208 | }, { |
| 4209 | .name = "rsr.lbeg", |
| 4210 | .translate = translate_rsr, |
| 4211 | .test_exceptions = test_exceptions_sr, |
| 4212 | .par = (const uint32_t[]){ |
| 4213 | LBEG, |
| 4214 | XTENSA_OPTION_LOOP, |
| 4215 | }, |
| 4216 | }, { |
| 4217 | .name = "rsr.lcount", |
| 4218 | .translate = translate_rsr, |
| 4219 | .test_exceptions = test_exceptions_sr, |
| 4220 | .par = (const uint32_t[]){ |
| 4221 | LCOUNT, |
| 4222 | XTENSA_OPTION_LOOP, |
| 4223 | }, |
| 4224 | }, { |
| 4225 | .name = "rsr.lend", |
| 4226 | .translate = translate_rsr, |
| 4227 | .test_exceptions = test_exceptions_sr, |
| 4228 | .par = (const uint32_t[]){ |
| 4229 | LEND, |
| 4230 | XTENSA_OPTION_LOOP, |
| 4231 | }, |
| 4232 | }, { |
| 4233 | .name = "rsr.litbase", |
| 4234 | .translate = translate_rsr, |
| 4235 | .test_exceptions = test_exceptions_sr, |
| 4236 | .par = (const uint32_t[]){ |
| 4237 | LITBASE, |
| 4238 | XTENSA_OPTION_EXTENDED_L32R, |
| 4239 | }, |
| 4240 | }, { |
| 4241 | .name = "rsr.m0", |
| 4242 | .translate = translate_rsr, |
| 4243 | .test_exceptions = test_exceptions_sr, |
| 4244 | .par = (const uint32_t[]){ |
| 4245 | MR, |
| 4246 | XTENSA_OPTION_MAC16, |
| 4247 | }, |
| 4248 | }, { |
| 4249 | .name = "rsr.m1", |
| 4250 | .translate = translate_rsr, |
| 4251 | .test_exceptions = test_exceptions_sr, |
| 4252 | .par = (const uint32_t[]){ |
| 4253 | MR + 1, |
| 4254 | XTENSA_OPTION_MAC16, |
| 4255 | }, |
| 4256 | }, { |
| 4257 | .name = "rsr.m2", |
| 4258 | .translate = translate_rsr, |
| 4259 | .test_exceptions = test_exceptions_sr, |
| 4260 | .par = (const uint32_t[]){ |
| 4261 | MR + 2, |
| 4262 | XTENSA_OPTION_MAC16, |
| 4263 | }, |
| 4264 | }, { |
| 4265 | .name = "rsr.m3", |
| 4266 | .translate = translate_rsr, |
| 4267 | .test_exceptions = test_exceptions_sr, |
| 4268 | .par = (const uint32_t[]){ |
| 4269 | MR + 3, |
| 4270 | XTENSA_OPTION_MAC16, |
| 4271 | }, |
| 4272 | }, { |
| 4273 | .name = "rsr.memctl", |
| 4274 | .translate = translate_rsr, |
| 4275 | .par = (const uint32_t[]){MEMCTL}, |
| 4276 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 4277 | }, { |
| 4278 | .name = "rsr.mecr", |
| 4279 | .translate = translate_rsr, |
| 4280 | .test_exceptions = test_exceptions_sr, |
| 4281 | .par = (const uint32_t[]){ |
| 4282 | MECR, |
| 4283 | XTENSA_OPTION_MEMORY_ECC_PARITY, |
| 4284 | }, |
| 4285 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 4286 | }, { |
| 4287 | .name = "rsr.mepc", |
| 4288 | .translate = translate_rsr, |
| 4289 | .test_exceptions = test_exceptions_sr, |
| 4290 | .par = (const uint32_t[]){ |
| 4291 | MEPC, |
| 4292 | XTENSA_OPTION_MEMORY_ECC_PARITY, |
| 4293 | }, |
| 4294 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 4295 | }, { |
| 4296 | .name = "rsr.meps", |
| 4297 | .translate = translate_rsr, |
| 4298 | .test_exceptions = test_exceptions_sr, |
| 4299 | .par = (const uint32_t[]){ |
| 4300 | MEPS, |
| 4301 | XTENSA_OPTION_MEMORY_ECC_PARITY, |
| 4302 | }, |
| 4303 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 4304 | }, { |
| 4305 | .name = "rsr.mesave", |
| 4306 | .translate = translate_rsr, |
| 4307 | .test_exceptions = test_exceptions_sr, |
| 4308 | .par = (const uint32_t[]){ |
| 4309 | MESAVE, |
| 4310 | XTENSA_OPTION_MEMORY_ECC_PARITY, |
| 4311 | }, |
| 4312 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 4313 | }, { |
| 4314 | .name = "rsr.mesr", |
| 4315 | .translate = translate_rsr, |
| 4316 | .test_exceptions = test_exceptions_sr, |
| 4317 | .par = (const uint32_t[]){ |
| 4318 | MESR, |
| 4319 | XTENSA_OPTION_MEMORY_ECC_PARITY, |
| 4320 | }, |
| 4321 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 4322 | }, { |
| 4323 | .name = "rsr.mevaddr", |
| 4324 | .translate = translate_rsr, |
| 4325 | .test_exceptions = test_exceptions_sr, |
| 4326 | .par = (const uint32_t[]){ |
| 4327 | MESR, |
| 4328 | XTENSA_OPTION_MEMORY_ECC_PARITY, |
| 4329 | }, |
| 4330 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 4331 | }, { |
| 4332 | .name = "rsr.misc0", |
| 4333 | .translate = translate_rsr, |
| 4334 | .test_exceptions = test_exceptions_sr, |
| 4335 | .par = (const uint32_t[]){ |
| 4336 | MISC, |
| 4337 | XTENSA_OPTION_MISC_SR, |
| 4338 | }, |
| 4339 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 4340 | }, { |
| 4341 | .name = "rsr.misc1", |
| 4342 | .translate = translate_rsr, |
| 4343 | .test_exceptions = test_exceptions_sr, |
| 4344 | .par = (const uint32_t[]){ |
| 4345 | MISC + 1, |
| 4346 | XTENSA_OPTION_MISC_SR, |
| 4347 | }, |
| 4348 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 4349 | }, { |
| 4350 | .name = "rsr.misc2", |
| 4351 | .translate = translate_rsr, |
| 4352 | .test_exceptions = test_exceptions_sr, |
| 4353 | .par = (const uint32_t[]){ |
| 4354 | MISC + 2, |
| 4355 | XTENSA_OPTION_MISC_SR, |
| 4356 | }, |
| 4357 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 4358 | }, { |
| 4359 | .name = "rsr.misc3", |
| 4360 | .translate = translate_rsr, |
| 4361 | .test_exceptions = test_exceptions_sr, |
| 4362 | .par = (const uint32_t[]){ |
| 4363 | MISC + 3, |
| 4364 | XTENSA_OPTION_MISC_SR, |
| 4365 | }, |
| 4366 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 4367 | }, { |
| 4368 | .name = "rsr.mpucfg", |
| 4369 | .translate = translate_rsr, |
| 4370 | .test_exceptions = test_exceptions_sr, |
| 4371 | .par = (const uint32_t[]){ |
| 4372 | MPUCFG, |
| 4373 | XTENSA_OPTION_MPU, |
| 4374 | }, |
| 4375 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 4376 | }, { |
| 4377 | .name = "rsr.mpuenb", |
| 4378 | .translate = translate_rsr, |
| 4379 | .test_exceptions = test_exceptions_sr, |
| 4380 | .par = (const uint32_t[]){ |
| 4381 | MPUENB, |
| 4382 | XTENSA_OPTION_MPU, |
| 4383 | }, |
| 4384 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 4385 | }, { |
| 4386 | .name = "rsr.prefctl", |
| 4387 | .translate = translate_rsr, |
| 4388 | .par = (const uint32_t[]){PREFCTL}, |
| 4389 | }, { |
| 4390 | .name = "rsr.prid", |
| 4391 | .translate = translate_rsr, |
| 4392 | .test_exceptions = test_exceptions_sr, |
| 4393 | .par = (const uint32_t[]){ |
| 4394 | PRID, |
| 4395 | XTENSA_OPTION_PROCESSOR_ID, |
| 4396 | }, |
| 4397 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 4398 | }, { |
| 4399 | .name = "rsr.ps", |
| 4400 | .translate = translate_rsr, |
| 4401 | .test_exceptions = test_exceptions_sr, |
| 4402 | .par = (const uint32_t[]){ |
| 4403 | PS, |
| 4404 | XTENSA_OPTION_EXCEPTION, |
| 4405 | }, |
| 4406 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 4407 | }, { |
| 4408 | .name = "rsr.ptevaddr", |
| 4409 | .translate = translate_rsr_ptevaddr, |
| 4410 | .test_exceptions = test_exceptions_sr, |
| 4411 | .par = (const uint32_t[]){ |
| 4412 | PTEVADDR, |
| 4413 | XTENSA_OPTION_MMU, |
| 4414 | }, |
| 4415 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 4416 | }, { |
| 4417 | .name = "rsr.rasid", |
| 4418 | .translate = translate_rsr, |
| 4419 | .test_exceptions = test_exceptions_sr, |
| 4420 | .par = (const uint32_t[]){ |
| 4421 | RASID, |
| 4422 | XTENSA_OPTION_MMU, |
| 4423 | }, |
| 4424 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 4425 | }, { |
| 4426 | .name = "rsr.sar", |
| 4427 | .translate = translate_rsr, |
| 4428 | .par = (const uint32_t[]){SAR}, |
| 4429 | }, { |
| 4430 | .name = "rsr.scompare1", |
| 4431 | .translate = translate_rsr, |
| 4432 | .test_exceptions = test_exceptions_sr, |
| 4433 | .par = (const uint32_t[]){ |
| 4434 | SCOMPARE1, |
| 4435 | XTENSA_OPTION_CONDITIONAL_STORE, |
| 4436 | }, |
| 4437 | }, { |
| 4438 | .name = "rsr.vecbase", |
| 4439 | .translate = translate_rsr, |
| 4440 | .test_exceptions = test_exceptions_sr, |
| 4441 | .par = (const uint32_t[]){ |
| 4442 | VECBASE, |
| 4443 | XTENSA_OPTION_RELOCATABLE_VECTOR, |
| 4444 | }, |
| 4445 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 4446 | }, { |
| 4447 | .name = "rsr.windowbase", |
| 4448 | .translate = translate_rsr, |
| 4449 | .test_exceptions = test_exceptions_sr, |
| 4450 | .par = (const uint32_t[]){ |
| 4451 | WINDOW_BASE, |
| 4452 | XTENSA_OPTION_WINDOWED_REGISTER, |
| 4453 | }, |
| 4454 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 4455 | }, { |
| 4456 | .name = "rsr.windowstart", |
| 4457 | .translate = translate_rsr, |
| 4458 | .test_exceptions = test_exceptions_sr, |
| 4459 | .par = (const uint32_t[]){ |
| 4460 | WINDOW_START, |
| 4461 | XTENSA_OPTION_WINDOWED_REGISTER, |
| 4462 | }, |
| 4463 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 4464 | }, { |
| 4465 | .name = "rsync", |
| 4466 | .translate = translate_nop, |
| 4467 | }, { |
| 4468 | .name = "rur.expstate", |
| 4469 | .translate = translate_rur, |
| 4470 | .par = (const uint32_t[]){EXPSTATE}, |
| 4471 | }, { |
| 4472 | .name = "rur.threadptr", |
| 4473 | .translate = translate_rur, |
| 4474 | .par = (const uint32_t[]){THREADPTR}, |
| 4475 | }, { |
| 4476 | .name = "s16i", |
| 4477 | .translate = translate_ldst, |
| 4478 | .par = (const uint32_t[]){MO_TEUW, false, true}, |
| 4479 | .op_flags = XTENSA_OP_STORE, |
| 4480 | }, { |
| 4481 | .name = "s32c1i", |
| 4482 | .translate = translate_s32c1i, |
| 4483 | .op_flags = XTENSA_OP_LOAD | XTENSA_OP_STORE, |
| 4484 | }, { |
| 4485 | .name = "s32e", |
| 4486 | .translate = translate_s32e, |
| 4487 | .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_STORE, |
| 4488 | }, { |
| 4489 | .name = "s32ex", |
| 4490 | .translate = translate_s32ex, |
| 4491 | .op_flags = XTENSA_OP_LOAD | XTENSA_OP_STORE, |
| 4492 | }, { |
| 4493 | .name = (const char * const[]) { |
| 4494 | "s32i", "s32i.n", "s32nb", NULL, |
| 4495 | }, |
| 4496 | .translate = translate_ldst, |
| 4497 | .par = (const uint32_t[]){MO_TEUL, false, true}, |
| 4498 | .op_flags = XTENSA_OP_NAME_ARRAY | XTENSA_OP_STORE, |
| 4499 | }, { |
| 4500 | .name = "s32ri", |
| 4501 | .translate = translate_ldst, |
| 4502 | .par = (const uint32_t[]){MO_TEUL | MO_ALIGN, true, true}, |
| 4503 | .op_flags = XTENSA_OP_STORE, |
| 4504 | }, { |
| 4505 | .name = "s8i", |
| 4506 | .translate = translate_ldst, |
| 4507 | .par = (const uint32_t[]){MO_UB, false, true}, |
| 4508 | .op_flags = XTENSA_OP_STORE, |
| 4509 | }, { |
| 4510 | .name = "salt", |
| 4511 | .translate = translate_salt, |
| 4512 | .par = (const uint32_t[]){TCG_COND_LT}, |
| 4513 | }, { |
| 4514 | .name = "saltu", |
| 4515 | .translate = translate_salt, |
| 4516 | .par = (const uint32_t[]){TCG_COND_LTU}, |
| 4517 | }, { |
| 4518 | .name = "sdct", |
| 4519 | .translate = translate_nop, |
| 4520 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 4521 | }, { |
| 4522 | .name = "sdcw", |
| 4523 | .translate = translate_nop, |
| 4524 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 4525 | }, { |
| 4526 | .name = "setb_expstate", |
| 4527 | .translate = translate_setb_expstate, |
| 4528 | }, { |
| 4529 | .name = "sext", |
| 4530 | .translate = translate_sext, |
| 4531 | }, { |
| 4532 | .name = "sict", |
| 4533 | .translate = translate_nop, |
| 4534 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 4535 | }, { |
| 4536 | .name = "sicw", |
| 4537 | .translate = translate_nop, |
| 4538 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 4539 | }, { |
| 4540 | .name = "simcall", |
| 4541 | .translate = translate_simcall, |
| 4542 | .test_exceptions = test_exceptions_simcall, |
| 4543 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 4544 | }, { |
| 4545 | .name = "sll", |
| 4546 | .translate = translate_sll, |
| 4547 | }, { |
| 4548 | .name = "slli", |
| 4549 | .translate = translate_slli, |
| 4550 | }, { |
| 4551 | .name = "sra", |
| 4552 | .translate = translate_sra, |
| 4553 | }, { |
| 4554 | .name = "srai", |
| 4555 | .translate = translate_srai, |
| 4556 | }, { |
| 4557 | .name = "src", |
| 4558 | .translate = translate_src, |
| 4559 | }, { |
| 4560 | .name = "srl", |
| 4561 | .translate = translate_srl, |
| 4562 | }, { |
| 4563 | .name = "srli", |
| 4564 | .translate = translate_srli, |
| 4565 | }, { |
| 4566 | .name = "ssa8b", |
| 4567 | .translate = translate_ssa8b, |
| 4568 | }, { |
| 4569 | .name = "ssa8l", |
| 4570 | .translate = translate_ssa8l, |
| 4571 | }, { |
| 4572 | .name = "ssai", |
| 4573 | .translate = translate_ssai, |
| 4574 | }, { |
| 4575 | .name = "ssl", |
| 4576 | .translate = translate_ssl, |
| 4577 | }, { |
| 4578 | .name = "ssr", |
| 4579 | .translate = translate_ssr, |
| 4580 | }, { |
| 4581 | .name = "sub", |
| 4582 | .translate = translate_sub, |
| 4583 | }, { |
| 4584 | .name = "subx2", |
| 4585 | .translate = translate_subx, |
| 4586 | .par = (const uint32_t[]){1}, |
| 4587 | }, { |
| 4588 | .name = "subx4", |
| 4589 | .translate = translate_subx, |
| 4590 | .par = (const uint32_t[]){2}, |
| 4591 | }, { |
| 4592 | .name = "subx8", |
| 4593 | .translate = translate_subx, |
| 4594 | .par = (const uint32_t[]){3}, |
| 4595 | }, { |
| 4596 | .name = "syscall", |
| 4597 | .op_flags = XTENSA_OP_SYSCALL, |
| 4598 | }, { |
| 4599 | .name = "umul.aa.hh", |
| 4600 | .translate = translate_mac16, |
| 4601 | .par = (const uint32_t[]){MAC16_UMUL, MAC16_HH, 0}, |
| 4602 | }, { |
| 4603 | .name = "umul.aa.hl", |
| 4604 | .translate = translate_mac16, |
| 4605 | .par = (const uint32_t[]){MAC16_UMUL, MAC16_HL, 0}, |
| 4606 | }, { |
| 4607 | .name = "umul.aa.lh", |
| 4608 | .translate = translate_mac16, |
| 4609 | .par = (const uint32_t[]){MAC16_UMUL, MAC16_LH, 0}, |
| 4610 | }, { |
| 4611 | .name = "umul.aa.ll", |
| 4612 | .translate = translate_mac16, |
| 4613 | .par = (const uint32_t[]){MAC16_UMUL, MAC16_LL, 0}, |
| 4614 | }, { |
| 4615 | .name = "waiti", |
| 4616 | .translate = translate_waiti, |
| 4617 | .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, |
| 4618 | }, { |
| 4619 | .name = "wdtlb", |
| 4620 | .translate = translate_wtlb, |
| 4621 | .par = (const uint32_t[]){true}, |
| 4622 | .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, |
| 4623 | }, { |
| 4624 | .name = "wer", |
| 4625 | .translate = translate_wer, |
| 4626 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 4627 | }, { |
| 4628 | .name = "witlb", |
| 4629 | .translate = translate_wtlb, |
| 4630 | .par = (const uint32_t[]){false}, |
| 4631 | .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, |
| 4632 | }, { |
| 4633 | .name = "wptlb", |
| 4634 | .translate = translate_wptlb, |
| 4635 | .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, |
| 4636 | }, { |
| 4637 | .name = "wrmsk_expstate", |
| 4638 | .translate = translate_wrmsk_expstate, |
| 4639 | }, { |
| 4640 | .name = "wsr.176", |
| 4641 | .op_flags = XTENSA_OP_ILL, |
| 4642 | }, { |
| 4643 | .name = "wsr.208", |
| 4644 | .op_flags = XTENSA_OP_ILL, |
| 4645 | }, { |
| 4646 | .name = "wsr.acchi", |
| 4647 | .translate = translate_wsr_acchi, |
| 4648 | .test_exceptions = test_exceptions_sr, |
| 4649 | .par = (const uint32_t[]){ |
| 4650 | ACCHI, |
| 4651 | XTENSA_OPTION_MAC16, |
| 4652 | }, |
| 4653 | }, { |
| 4654 | .name = "wsr.acclo", |
| 4655 | .translate = translate_wsr, |
| 4656 | .test_exceptions = test_exceptions_sr, |
| 4657 | .par = (const uint32_t[]){ |
| 4658 | ACCLO, |
| 4659 | XTENSA_OPTION_MAC16, |
| 4660 | }, |
| 4661 | }, { |
| 4662 | .name = "wsr.atomctl", |
| 4663 | .translate = translate_wsr_mask, |
| 4664 | .test_exceptions = test_exceptions_sr, |
| 4665 | .par = (const uint32_t[]){ |
| 4666 | ATOMCTL, |
| 4667 | XTENSA_OPTION_ATOMCTL, |
| 4668 | 0x3f, |
| 4669 | }, |
| 4670 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 4671 | }, { |
| 4672 | .name = "wsr.br", |
| 4673 | .translate = translate_wsr_mask, |
| 4674 | .test_exceptions = test_exceptions_sr, |
| 4675 | .par = (const uint32_t[]){ |
| 4676 | BR, |
| 4677 | XTENSA_OPTION_BOOLEAN, |
| 4678 | 0xffff, |
| 4679 | }, |
| 4680 | }, { |
| 4681 | .name = "wsr.cacheadrdis", |
| 4682 | .translate = translate_wsr_mask, |
| 4683 | .test_exceptions = test_exceptions_sr, |
| 4684 | .par = (const uint32_t[]){ |
| 4685 | CACHEADRDIS, |
| 4686 | XTENSA_OPTION_MPU, |
| 4687 | 0xff, |
| 4688 | }, |
| 4689 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 4690 | }, { |
| 4691 | .name = "wsr.cacheattr", |
| 4692 | .translate = translate_wsr, |
| 4693 | .test_exceptions = test_exceptions_sr, |
| 4694 | .par = (const uint32_t[]){ |
| 4695 | CACHEATTR, |
| 4696 | XTENSA_OPTION_CACHEATTR, |
| 4697 | }, |
| 4698 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 4699 | }, { |
| 4700 | .name = "wsr.ccompare0", |
| 4701 | .translate = translate_wsr_ccompare, |
| 4702 | .test_exceptions = test_exceptions_ccompare, |
| 4703 | .par = (const uint32_t[]){ |
| 4704 | CCOMPARE, |
| 4705 | XTENSA_OPTION_TIMER_INTERRUPT, |
| 4706 | }, |
| 4707 | .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, |
| 4708 | }, { |
| 4709 | .name = "wsr.ccompare1", |
| 4710 | .translate = translate_wsr_ccompare, |
| 4711 | .test_exceptions = test_exceptions_ccompare, |
| 4712 | .par = (const uint32_t[]){ |
| 4713 | CCOMPARE + 1, |
| 4714 | XTENSA_OPTION_TIMER_INTERRUPT, |
| 4715 | }, |
| 4716 | .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, |
| 4717 | }, { |
| 4718 | .name = "wsr.ccompare2", |
| 4719 | .translate = translate_wsr_ccompare, |
| 4720 | .test_exceptions = test_exceptions_ccompare, |
| 4721 | .par = (const uint32_t[]){ |
| 4722 | CCOMPARE + 2, |
| 4723 | XTENSA_OPTION_TIMER_INTERRUPT, |
| 4724 | }, |
| 4725 | .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, |
| 4726 | }, { |
| 4727 | .name = "wsr.ccount", |
| 4728 | .translate = translate_wsr_ccount, |
| 4729 | .test_exceptions = test_exceptions_sr, |
| 4730 | .par = (const uint32_t[]){ |
| 4731 | CCOUNT, |
| 4732 | XTENSA_OPTION_TIMER_INTERRUPT, |
| 4733 | }, |
| 4734 | .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, |
| 4735 | }, { |
| 4736 | .name = "wsr.configid0", |
| 4737 | .op_flags = XTENSA_OP_ILL, |
| 4738 | }, { |
| 4739 | .name = "wsr.configid1", |
| 4740 | .op_flags = XTENSA_OP_ILL, |
| 4741 | }, { |
| 4742 | .name = "wsr.cpenable", |
| 4743 | .translate = translate_wsr_mask, |
| 4744 | .test_exceptions = test_exceptions_sr, |
| 4745 | .par = (const uint32_t[]){ |
| 4746 | CPENABLE, |
| 4747 | XTENSA_OPTION_COPROCESSOR, |
| 4748 | 0xff, |
| 4749 | }, |
| 4750 | .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, |
| 4751 | }, { |
| 4752 | .name = "wsr.dbreaka0", |
| 4753 | .translate = translate_wsr_dbreaka, |
| 4754 | .test_exceptions = test_exceptions_dbreak, |
| 4755 | .par = (const uint32_t[]){ |
| 4756 | DBREAKA, |
| 4757 | XTENSA_OPTION_DEBUG, |
| 4758 | }, |
| 4759 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 4760 | }, { |
| 4761 | .name = "wsr.dbreaka1", |
| 4762 | .translate = translate_wsr_dbreaka, |
| 4763 | .test_exceptions = test_exceptions_dbreak, |
| 4764 | .par = (const uint32_t[]){ |
| 4765 | DBREAKA + 1, |
| 4766 | XTENSA_OPTION_DEBUG, |
| 4767 | }, |
| 4768 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 4769 | }, { |
| 4770 | .name = "wsr.dbreakc0", |
| 4771 | .translate = translate_wsr_dbreakc, |
| 4772 | .test_exceptions = test_exceptions_dbreak, |
| 4773 | .par = (const uint32_t[]){ |
| 4774 | DBREAKC, |
| 4775 | XTENSA_OPTION_DEBUG, |
| 4776 | }, |
| 4777 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 4778 | }, { |
| 4779 | .name = "wsr.dbreakc1", |
| 4780 | .translate = translate_wsr_dbreakc, |
| 4781 | .test_exceptions = test_exceptions_dbreak, |
| 4782 | .par = (const uint32_t[]){ |
| 4783 | DBREAKC + 1, |
| 4784 | XTENSA_OPTION_DEBUG, |
| 4785 | }, |
| 4786 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 4787 | }, { |
| 4788 | .name = "wsr.ddr", |
| 4789 | .translate = translate_wsr, |
| 4790 | .test_exceptions = test_exceptions_sr, |
| 4791 | .par = (const uint32_t[]){ |
| 4792 | DDR, |
| 4793 | XTENSA_OPTION_DEBUG, |
| 4794 | }, |
| 4795 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 4796 | }, { |
| 4797 | .name = "wsr.debugcause", |
| 4798 | .op_flags = XTENSA_OP_ILL, |
| 4799 | }, { |
| 4800 | .name = "wsr.depc", |
| 4801 | .translate = translate_wsr, |
| 4802 | .test_exceptions = test_exceptions_sr, |
| 4803 | .par = (const uint32_t[]){ |
| 4804 | DEPC, |
| 4805 | XTENSA_OPTION_EXCEPTION, |
| 4806 | }, |
| 4807 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 4808 | }, { |
| 4809 | .name = "wsr.dtlbcfg", |
| 4810 | .translate = translate_wsr_mask, |
| 4811 | .test_exceptions = test_exceptions_sr, |
| 4812 | .par = (const uint32_t[]){ |
| 4813 | DTLBCFG, |
| 4814 | XTENSA_OPTION_MMU, |
| 4815 | 0x01130000, |
| 4816 | }, |
| 4817 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 4818 | }, { |
| 4819 | .name = "wsr.epc1", |
| 4820 | .translate = translate_wsr, |
| 4821 | .test_exceptions = test_exceptions_sr, |
| 4822 | .par = (const uint32_t[]){ |
| 4823 | EPC1, |
| 4824 | XTENSA_OPTION_EXCEPTION, |
| 4825 | }, |
| 4826 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 4827 | }, { |
| 4828 | .name = "wsr.epc2", |
| 4829 | .translate = translate_wsr, |
| 4830 | .test_exceptions = test_exceptions_hpi, |
| 4831 | .par = (const uint32_t[]){ |
| 4832 | EPC1 + 1, |
| 4833 | XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, |
| 4834 | }, |
| 4835 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 4836 | }, { |
| 4837 | .name = "wsr.epc3", |
| 4838 | .translate = translate_wsr, |
| 4839 | .test_exceptions = test_exceptions_hpi, |
| 4840 | .par = (const uint32_t[]){ |
| 4841 | EPC1 + 2, |
| 4842 | XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, |
| 4843 | }, |
| 4844 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 4845 | }, { |
| 4846 | .name = "wsr.epc4", |
| 4847 | .translate = translate_wsr, |
| 4848 | .test_exceptions = test_exceptions_hpi, |
| 4849 | .par = (const uint32_t[]){ |
| 4850 | EPC1 + 3, |
| 4851 | XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, |
| 4852 | }, |
| 4853 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 4854 | }, { |
| 4855 | .name = "wsr.epc5", |
| 4856 | .translate = translate_wsr, |
| 4857 | .test_exceptions = test_exceptions_hpi, |
| 4858 | .par = (const uint32_t[]){ |
| 4859 | EPC1 + 4, |
| 4860 | XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, |
| 4861 | }, |
| 4862 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 4863 | }, { |
| 4864 | .name = "wsr.epc6", |
| 4865 | .translate = translate_wsr, |
| 4866 | .test_exceptions = test_exceptions_hpi, |
| 4867 | .par = (const uint32_t[]){ |
| 4868 | EPC1 + 5, |
| 4869 | XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, |
| 4870 | }, |
| 4871 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 4872 | }, { |
| 4873 | .name = "wsr.epc7", |
| 4874 | .translate = translate_wsr, |
| 4875 | .test_exceptions = test_exceptions_hpi, |
| 4876 | .par = (const uint32_t[]){ |
| 4877 | EPC1 + 6, |
| 4878 | XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, |
| 4879 | }, |
| 4880 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 4881 | }, { |
| 4882 | .name = "wsr.eps2", |
| 4883 | .translate = translate_wsr, |
| 4884 | .test_exceptions = test_exceptions_hpi, |
| 4885 | .par = (const uint32_t[]){ |
| 4886 | EPS2, |
| 4887 | XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, |
| 4888 | }, |
| 4889 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 4890 | }, { |
| 4891 | .name = "wsr.eps3", |
| 4892 | .translate = translate_wsr, |
| 4893 | .test_exceptions = test_exceptions_hpi, |
| 4894 | .par = (const uint32_t[]){ |
| 4895 | EPS2 + 1, |
| 4896 | XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, |
| 4897 | }, |
| 4898 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 4899 | }, { |
| 4900 | .name = "wsr.eps4", |
| 4901 | .translate = translate_wsr, |
| 4902 | .test_exceptions = test_exceptions_hpi, |
| 4903 | .par = (const uint32_t[]){ |
| 4904 | EPS2 + 2, |
| 4905 | XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, |
| 4906 | }, |
| 4907 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 4908 | }, { |
| 4909 | .name = "wsr.eps5", |
| 4910 | .translate = translate_wsr, |
| 4911 | .test_exceptions = test_exceptions_hpi, |
| 4912 | .par = (const uint32_t[]){ |
| 4913 | EPS2 + 3, |
| 4914 | XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, |
| 4915 | }, |
| 4916 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 4917 | }, { |
| 4918 | .name = "wsr.eps6", |
| 4919 | .translate = translate_wsr, |
| 4920 | .test_exceptions = test_exceptions_hpi, |
| 4921 | .par = (const uint32_t[]){ |
| 4922 | EPS2 + 4, |
| 4923 | XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, |
| 4924 | }, |
| 4925 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 4926 | }, { |
| 4927 | .name = "wsr.eps7", |
| 4928 | .translate = translate_wsr, |
| 4929 | .test_exceptions = test_exceptions_hpi, |
| 4930 | .par = (const uint32_t[]){ |
| 4931 | EPS2 + 5, |
| 4932 | XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, |
| 4933 | }, |
| 4934 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 4935 | }, { |
| 4936 | .name = "wsr.eraccess", |
| 4937 | .translate = translate_wsr_mask, |
| 4938 | .par = (const uint32_t[]){ |
| 4939 | ERACCESS, |
| 4940 | 0, |
| 4941 | 0xffff, |
| 4942 | }, |
| 4943 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 4944 | }, { |
| 4945 | .name = "wsr.exccause", |
| 4946 | .translate = translate_wsr, |
| 4947 | .test_exceptions = test_exceptions_sr, |
| 4948 | .par = (const uint32_t[]){ |
| 4949 | EXCCAUSE, |
| 4950 | XTENSA_OPTION_EXCEPTION, |
| 4951 | }, |
| 4952 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 4953 | }, { |
| 4954 | .name = "wsr.excsave1", |
| 4955 | .translate = translate_wsr, |
| 4956 | .test_exceptions = test_exceptions_sr, |
| 4957 | .par = (const uint32_t[]){ |
| 4958 | EXCSAVE1, |
| 4959 | XTENSA_OPTION_EXCEPTION, |
| 4960 | }, |
| 4961 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 4962 | }, { |
| 4963 | .name = "wsr.excsave2", |
| 4964 | .translate = translate_wsr, |
| 4965 | .test_exceptions = test_exceptions_hpi, |
| 4966 | .par = (const uint32_t[]){ |
| 4967 | EXCSAVE1 + 1, |
| 4968 | XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, |
| 4969 | }, |
| 4970 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 4971 | }, { |
| 4972 | .name = "wsr.excsave3", |
| 4973 | .translate = translate_wsr, |
| 4974 | .test_exceptions = test_exceptions_hpi, |
| 4975 | .par = (const uint32_t[]){ |
| 4976 | EXCSAVE1 + 2, |
| 4977 | XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, |
| 4978 | }, |
| 4979 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 4980 | }, { |
| 4981 | .name = "wsr.excsave4", |
| 4982 | .translate = translate_wsr, |
| 4983 | .test_exceptions = test_exceptions_hpi, |
| 4984 | .par = (const uint32_t[]){ |
| 4985 | EXCSAVE1 + 3, |
| 4986 | XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, |
| 4987 | }, |
| 4988 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 4989 | }, { |
| 4990 | .name = "wsr.excsave5", |
| 4991 | .translate = translate_wsr, |
| 4992 | .test_exceptions = test_exceptions_hpi, |
| 4993 | .par = (const uint32_t[]){ |
| 4994 | EXCSAVE1 + 4, |
| 4995 | XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, |
| 4996 | }, |
| 4997 | .op_flags = XTENSA_OP_PRIVILEGED, |
| 4998 | }, { |
| 4999 | .name = "wsr.excsave6", |
| 5000 | .translate = translate_wsr, |
Showing first 5,000 of 7,670 lines.
View raw