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1 /* SPDX-License-Identifier: MIT */
2 /*
3 * Define target-specific opcode support
4 * Copyright (c) 2021 WANG Xuerui <git@xen0n.name>
5 */
6
7 #ifndef TCG_TARGET_HAS_H
8 #define TCG_TARGET_HAS_H
9
10 #include "host/cpuinfo.h"
11
12 /* 64-bit operations */
13 #define TCG_TARGET_HAS_extr_i64_i32 1
14
15 #define TCG_TARGET_HAS_qemu_ldst_i128 (cpuinfo & CPUINFO_LSX)
16
17 #define TCG_TARGET_HAS_tst 0
18
19 #define TCG_TARGET_HAS_v64 (cpuinfo & CPUINFO_LSX)
20 #define TCG_TARGET_HAS_v128 (cpuinfo & CPUINFO_LSX)
21 #define TCG_TARGET_HAS_v256 (cpuinfo & CPUINFO_LASX)
22
23 #define TCG_TARGET_HAS_not_vec 1
24 #define TCG_TARGET_HAS_neg_vec 1
25 #define TCG_TARGET_HAS_abs_vec 0
26 #define TCG_TARGET_HAS_andc_vec 1
27 #define TCG_TARGET_HAS_orc_vec 1
28 #define TCG_TARGET_HAS_nand_vec 0
29 #define TCG_TARGET_HAS_nor_vec 1
30 #define TCG_TARGET_HAS_eqv_vec 0
31 #define TCG_TARGET_HAS_mul_vec 1
32 #define TCG_TARGET_HAS_shi_vec 1
33 #define TCG_TARGET_HAS_shs_vec 0
34 #define TCG_TARGET_HAS_shv_vec 1
35 #define TCG_TARGET_HAS_roti_vec 1
36 #define TCG_TARGET_HAS_rots_vec 0
37 #define TCG_TARGET_HAS_rotv_vec 1
38 #define TCG_TARGET_HAS_sat_vec 1
39 #define TCG_TARGET_HAS_minmax_vec 1
40 #define TCG_TARGET_HAS_bitsel_vec 1
41 #define TCG_TARGET_HAS_cmpsel_vec 0
42 #define TCG_TARGET_HAS_tst_vec 0
43
44 #define TCG_TARGET_extract_valid(type, ofs, len) 1
45 #define TCG_TARGET_deposit_valid(type, ofs, len) 1
46
47 static inline bool
48 tcg_target_sextract_valid(TCGType type, unsigned ofs, unsigned len)
49 {
50 if (type == TCG_TYPE_I64 && ofs + len == 32) {
51 return true;
52 }
53 return ofs == 0 && (len == 8 || len == 16);
54 }
55 #define TCG_TARGET_sextract_valid tcg_target_sextract_valid
56
57 #endif