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1 /*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2021 WANG Xuerui <git@xen0n.name>
5 *
6 * Based on tcg/riscv/tcg-target.h
7 *
8 * Copyright (c) 2018 SiFive, Inc
9 *
10 * Permission is hereby granted, free of charge, to any person obtaining a copy
11 * of this software and associated documentation files (the "Software"), to deal
12 * in the Software without restriction, including without limitation the rights
13 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
14 * copies of the Software, and to permit persons to whom the Software is
15 * furnished to do so, subject to the following conditions:
16 *
17 * The above copyright notice and this permission notice shall be included in
18 * all copies or substantial portions of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
24 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 * THE SOFTWARE.
27 */
28
29 #ifndef LOONGARCH_TCG_TARGET_H
30 #define LOONGARCH_TCG_TARGET_H
31
32 #define TCG_TARGET_INSN_UNIT_SIZE 4
33 #define TCG_TARGET_NB_REGS 64
34
35 #define MAX_CODE_GEN_BUFFER_SIZE ((size_t)-1)
36
37 typedef enum {
38 TCG_REG_ZERO,
39 TCG_REG_RA,
40 TCG_REG_TP,
41 TCG_REG_SP,
42 TCG_REG_A0,
43 TCG_REG_A1,
44 TCG_REG_A2,
45 TCG_REG_A3,
46 TCG_REG_A4,
47 TCG_REG_A5,
48 TCG_REG_A6,
49 TCG_REG_A7,
50 TCG_REG_T0,
51 TCG_REG_T1,
52 TCG_REG_T2,
53 TCG_REG_T3,
54 TCG_REG_T4,
55 TCG_REG_T5,
56 TCG_REG_T6,
57 TCG_REG_T7,
58 TCG_REG_T8,
59 TCG_REG_RESERVED,
60 TCG_REG_S9,
61 TCG_REG_S0,
62 TCG_REG_S1,
63 TCG_REG_S2,
64 TCG_REG_S3,
65 TCG_REG_S4,
66 TCG_REG_S5,
67 TCG_REG_S6,
68 TCG_REG_S7,
69 TCG_REG_S8,
70
71 TCG_REG_V0 = 32, TCG_REG_V1, TCG_REG_V2, TCG_REG_V3,
72 TCG_REG_V4, TCG_REG_V5, TCG_REG_V6, TCG_REG_V7,
73 TCG_REG_V8, TCG_REG_V9, TCG_REG_V10, TCG_REG_V11,
74 TCG_REG_V12, TCG_REG_V13, TCG_REG_V14, TCG_REG_V15,
75 TCG_REG_V16, TCG_REG_V17, TCG_REG_V18, TCG_REG_V19,
76 TCG_REG_V20, TCG_REG_V21, TCG_REG_V22, TCG_REG_V23,
77 TCG_REG_V24, TCG_REG_V25, TCG_REG_V26, TCG_REG_V27,
78 TCG_REG_V28, TCG_REG_V29, TCG_REG_V30, TCG_REG_V31,
79
80 /* aliases */
81 TCG_AREG0 = TCG_REG_S0,
82 TCG_REG_TMP0 = TCG_REG_T8,
83 TCG_REG_TMP1 = TCG_REG_T7,
84 TCG_REG_TMP2 = TCG_REG_T6,
85 TCG_VEC_TMP0 = TCG_REG_V23,
86 } TCGReg;
87
88 #define TCG_REG_ZERO TCG_REG_ZERO
89
90 #endif /* LOONGARCH_TCG_TARGET_H */