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1 /*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2009 Ulrich Hecht <uli@suse.de>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #ifndef S390_TCG_TARGET_H
26 #define S390_TCG_TARGET_H
27
28 #define TCG_TARGET_INSN_UNIT_SIZE 2
29
30 /* We have a +- 4GB range on the branches; leave some slop. */
31 #define MAX_CODE_GEN_BUFFER_SIZE (3 * GiB)
32
33 typedef enum TCGReg {
34 TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_R3,
35 TCG_REG_R4, TCG_REG_R5, TCG_REG_R6, TCG_REG_R7,
36 TCG_REG_R8, TCG_REG_R9, TCG_REG_R10, TCG_REG_R11,
37 TCG_REG_R12, TCG_REG_R13, TCG_REG_R14, TCG_REG_R15,
38
39 TCG_REG_V0 = 32, TCG_REG_V1, TCG_REG_V2, TCG_REG_V3,
40 TCG_REG_V4, TCG_REG_V5, TCG_REG_V6, TCG_REG_V7,
41 TCG_REG_V8, TCG_REG_V9, TCG_REG_V10, TCG_REG_V11,
42 TCG_REG_V12, TCG_REG_V13, TCG_REG_V14, TCG_REG_V15,
43 TCG_REG_V16, TCG_REG_V17, TCG_REG_V18, TCG_REG_V19,
44 TCG_REG_V20, TCG_REG_V21, TCG_REG_V22, TCG_REG_V23,
45 TCG_REG_V24, TCG_REG_V25, TCG_REG_V26, TCG_REG_V27,
46 TCG_REG_V28, TCG_REG_V29, TCG_REG_V30, TCG_REG_V31,
47
48 TCG_AREG0 = TCG_REG_R10,
49 TCG_REG_CALL_STACK = TCG_REG_R15
50 } TCGReg;
51
52 #define TCG_TARGET_NB_REGS 64
53
54 #endif