| 1 | /* |
| 2 | * Tiny Code Generator for QEMU |
| 3 | * |
| 4 | * Copyright (c) 2018 Linaro, Inc. |
| 5 | * |
| 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2.1 of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU Lesser General Public |
| 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
| 18 | */ |
| 19 | |
| 20 | #include "qemu/osdep.h" |
| 21 | #include "tcg/tcg.h" |
| 22 | #include "tcg/tcg-temp-internal.h" |
| 23 | #include "tcg/tcg-op-common.h" |
| 24 | #include "tcg/tcg-mo.h" |
| 25 | #include "tcg-internal.h" |
| 26 | #include "tcg-has.h" |
| 27 | |
| 28 | /* |
| 29 | * Vector optional opcode tracking. |
| 30 | * Except for the basic logical operations (and, or, xor), and |
| 31 | * data movement (mov, ld, st, dupi), many vector opcodes are |
| 32 | * optional and may not be supported on the host. Thank Intel |
| 33 | * for the irregularity in their instruction set. |
| 34 | * |
| 35 | * The gvec expanders allow custom vector operations to be composed, |
| 36 | * generally via the .fniv callback in the GVecGen* structures. At |
| 37 | * the same time, in deciding whether to use this hook we need to |
| 38 | * know if the host supports the required operations. This is |
| 39 | * presented as an array of opcodes, terminated by 0. Each opcode |
| 40 | * is assumed to be expanded with the given VECE. |
| 41 | * |
| 42 | * For debugging, we want to validate this array. Therefore, when |
| 43 | * tcg_ctx->vec_opt_opc is non-NULL, the tcg_gen_*_vec expanders |
| 44 | * will validate that their opcode is present in the list. |
| 45 | */ |
| 46 | static void tcg_assert_listed_vecop(TCGOpcode op) |
| 47 | { |
| 48 | #ifdef CONFIG_DEBUG_TCG |
| 49 | const TCGOpcode *p = tcg_ctx->vecop_list; |
| 50 | if (p) { |
| 51 | for (; *p; ++p) { |
| 52 | if (*p == op) { |
| 53 | return; |
| 54 | } |
| 55 | } |
| 56 | g_assert_not_reached(); |
| 57 | } |
| 58 | #endif |
| 59 | } |
| 60 | |
| 61 | bool tcg_can_emit_vecop_list(const TCGOpcode *list, |
| 62 | TCGType type, unsigned vece) |
| 63 | { |
| 64 | if (list == NULL) { |
| 65 | return true; |
| 66 | } |
| 67 | |
| 68 | for (; *list; ++list) { |
| 69 | TCGOpcode opc = *list; |
| 70 | |
| 71 | #ifdef CONFIG_DEBUG_TCG |
| 72 | switch (opc) { |
| 73 | case INDEX_op_and_vec: |
| 74 | case INDEX_op_or_vec: |
| 75 | case INDEX_op_xor_vec: |
| 76 | case INDEX_op_mov_vec: |
| 77 | case INDEX_op_dup_vec: |
| 78 | case INDEX_op_ld_vec: |
| 79 | case INDEX_op_st_vec: |
| 80 | case INDEX_op_bitsel_vec: |
| 81 | /* These opcodes are mandatory and should not be listed. */ |
| 82 | g_assert_not_reached(); |
| 83 | case INDEX_op_not_vec: |
| 84 | /* These opcodes have generic expansions using the above. */ |
| 85 | g_assert_not_reached(); |
| 86 | default: |
| 87 | break; |
| 88 | } |
| 89 | #endif |
| 90 | |
| 91 | if (tcg_can_emit_vec_op(opc, type, vece)) { |
| 92 | continue; |
| 93 | } |
| 94 | |
| 95 | /* |
| 96 | * The opcode list is created by front ends based on what they |
| 97 | * actually invoke. We must mirror the logic in the routines |
| 98 | * below for generic expansions using other opcodes. |
| 99 | */ |
| 100 | switch (opc) { |
| 101 | case INDEX_op_neg_vec: |
| 102 | if (tcg_can_emit_vec_op(INDEX_op_sub_vec, type, vece)) { |
| 103 | continue; |
| 104 | } |
| 105 | break; |
| 106 | case INDEX_op_abs_vec: |
| 107 | if (tcg_can_emit_vec_op(INDEX_op_sub_vec, type, vece) |
| 108 | && (tcg_can_emit_vec_op(INDEX_op_smax_vec, type, vece) > 0 |
| 109 | || tcg_can_emit_vec_op(INDEX_op_sari_vec, type, vece) > 0 |
| 110 | || tcg_can_emit_vec_op(INDEX_op_cmp_vec, type, vece))) { |
| 111 | continue; |
| 112 | } |
| 113 | break; |
| 114 | case INDEX_op_usadd_vec: |
| 115 | if (tcg_can_emit_vec_op(INDEX_op_umin_vec, type, vece) || |
| 116 | tcg_can_emit_vec_op(INDEX_op_cmp_vec, type, vece)) { |
| 117 | continue; |
| 118 | } |
| 119 | break; |
| 120 | case INDEX_op_ussub_vec: |
| 121 | if (tcg_can_emit_vec_op(INDEX_op_umax_vec, type, vece) || |
| 122 | tcg_can_emit_vec_op(INDEX_op_cmp_vec, type, vece)) { |
| 123 | continue; |
| 124 | } |
| 125 | break; |
| 126 | case INDEX_op_cmpsel_vec: |
| 127 | case INDEX_op_smin_vec: |
| 128 | case INDEX_op_smax_vec: |
| 129 | case INDEX_op_umin_vec: |
| 130 | case INDEX_op_umax_vec: |
| 131 | if (tcg_can_emit_vec_op(INDEX_op_cmp_vec, type, vece)) { |
| 132 | continue; |
| 133 | } |
| 134 | break; |
| 135 | default: |
| 136 | break; |
| 137 | } |
| 138 | return false; |
| 139 | } |
| 140 | return true; |
| 141 | } |
| 142 | |
| 143 | void vec_gen_2(TCGOpcode opc, TCGType type, unsigned vece, TCGArg r, TCGArg a) |
| 144 | { |
| 145 | TCGOp *op = tcg_emit_op(opc, 2); |
| 146 | TCGOP_TYPE(op) = type; |
| 147 | TCGOP_VECE(op) = vece; |
| 148 | op->args[0] = r; |
| 149 | op->args[1] = a; |
| 150 | } |
| 151 | |
| 152 | void vec_gen_3(TCGOpcode opc, TCGType type, unsigned vece, |
| 153 | TCGArg r, TCGArg a, TCGArg b) |
| 154 | { |
| 155 | TCGOp *op = tcg_emit_op(opc, 3); |
| 156 | TCGOP_TYPE(op) = type; |
| 157 | TCGOP_VECE(op) = vece; |
| 158 | op->args[0] = r; |
| 159 | op->args[1] = a; |
| 160 | op->args[2] = b; |
| 161 | } |
| 162 | |
| 163 | void vec_gen_4(TCGOpcode opc, TCGType type, unsigned vece, |
| 164 | TCGArg r, TCGArg a, TCGArg b, TCGArg c) |
| 165 | { |
| 166 | TCGOp *op = tcg_emit_op(opc, 4); |
| 167 | TCGOP_TYPE(op) = type; |
| 168 | TCGOP_VECE(op) = vece; |
| 169 | op->args[0] = r; |
| 170 | op->args[1] = a; |
| 171 | op->args[2] = b; |
| 172 | op->args[3] = c; |
| 173 | } |
| 174 | |
| 175 | void vec_gen_6(TCGOpcode opc, TCGType type, unsigned vece, TCGArg r, |
| 176 | TCGArg a, TCGArg b, TCGArg c, TCGArg d, TCGArg e) |
| 177 | { |
| 178 | TCGOp *op = tcg_emit_op(opc, 6); |
| 179 | TCGOP_TYPE(op) = type; |
| 180 | TCGOP_VECE(op) = vece; |
| 181 | op->args[0] = r; |
| 182 | op->args[1] = a; |
| 183 | op->args[2] = b; |
| 184 | op->args[3] = c; |
| 185 | op->args[4] = d; |
| 186 | op->args[5] = e; |
| 187 | } |
| 188 | |
| 189 | static void vec_gen_op2(TCGOpcode opc, unsigned vece, TCGv_vec r, TCGv_vec a) |
| 190 | { |
| 191 | TCGTemp *rt = tcgv_vec_temp(r); |
| 192 | TCGTemp *at = tcgv_vec_temp(a); |
| 193 | TCGType type = rt->base_type; |
| 194 | |
| 195 | /* Must enough inputs for the output. */ |
| 196 | tcg_debug_assert(at->base_type >= type); |
| 197 | vec_gen_2(opc, type, vece, temp_arg(rt), temp_arg(at)); |
| 198 | } |
| 199 | |
| 200 | static void vec_gen_op3(TCGOpcode opc, unsigned vece, |
| 201 | TCGv_vec r, TCGv_vec a, TCGv_vec b) |
| 202 | { |
| 203 | TCGTemp *rt = tcgv_vec_temp(r); |
| 204 | TCGTemp *at = tcgv_vec_temp(a); |
| 205 | TCGTemp *bt = tcgv_vec_temp(b); |
| 206 | TCGType type = rt->base_type; |
| 207 | |
| 208 | /* Must enough inputs for the output. */ |
| 209 | tcg_debug_assert(at->base_type >= type); |
| 210 | tcg_debug_assert(bt->base_type >= type); |
| 211 | vec_gen_3(opc, type, vece, temp_arg(rt), temp_arg(at), temp_arg(bt)); |
| 212 | } |
| 213 | |
| 214 | void tcg_gen_mov_vec(TCGv_vec r, TCGv_vec a) |
| 215 | { |
| 216 | if (r != a) { |
| 217 | vec_gen_op2(INDEX_op_mov_vec, 0, r, a); |
| 218 | } |
| 219 | } |
| 220 | |
| 221 | void tcg_gen_dupi_vec(unsigned vece, TCGv_vec r, uint64_t a) |
| 222 | { |
| 223 | TCGTemp *rt = tcgv_vec_temp(r); |
| 224 | tcg_gen_mov_vec(r, tcg_constant_vec(rt->base_type, vece, a)); |
| 225 | } |
| 226 | |
| 227 | void tcg_gen_dup_i64_vec(unsigned vece, TCGv_vec r, TCGv_i64 a) |
| 228 | { |
| 229 | TCGArg ri = tcgv_vec_arg(r); |
| 230 | TCGArg ai = tcgv_i64_arg(a); |
| 231 | TCGTemp *rt = arg_temp(ri); |
| 232 | TCGType type = rt->base_type; |
| 233 | |
| 234 | vec_gen_2(INDEX_op_dup_vec, type, vece, ri, ai); |
| 235 | } |
| 236 | |
| 237 | void tcg_gen_dup_i32_vec(unsigned vece, TCGv_vec r, TCGv_i32 a) |
| 238 | { |
| 239 | TCGArg ri = tcgv_vec_arg(r); |
| 240 | TCGArg ai = tcgv_i32_arg(a); |
| 241 | TCGTemp *rt = arg_temp(ri); |
| 242 | TCGType type = rt->base_type; |
| 243 | |
| 244 | vec_gen_2(INDEX_op_dup_vec, type, vece, ri, ai); |
| 245 | } |
| 246 | |
| 247 | void tcg_gen_dup_mem_vec(unsigned vece, TCGv_vec r, TCGv_ptr b, |
| 248 | tcg_target_long ofs) |
| 249 | { |
| 250 | TCGArg ri = tcgv_vec_arg(r); |
| 251 | TCGArg bi = tcgv_ptr_arg(b); |
| 252 | TCGTemp *rt = arg_temp(ri); |
| 253 | TCGType type = rt->base_type; |
| 254 | |
| 255 | vec_gen_3(INDEX_op_dupm_vec, type, vece, ri, bi, ofs); |
| 256 | } |
| 257 | |
| 258 | static void vec_gen_ldst(TCGOpcode opc, TCGv_vec r, TCGv_ptr b, TCGArg o) |
| 259 | { |
| 260 | TCGArg ri = tcgv_vec_arg(r); |
| 261 | TCGArg bi = tcgv_ptr_arg(b); |
| 262 | TCGTemp *rt = arg_temp(ri); |
| 263 | TCGType type = rt->base_type; |
| 264 | |
| 265 | vec_gen_3(opc, type, 0, ri, bi, o); |
| 266 | } |
| 267 | |
| 268 | void tcg_gen_ld_vec(TCGv_vec r, TCGv_ptr b, TCGArg o) |
| 269 | { |
| 270 | vec_gen_ldst(INDEX_op_ld_vec, r, b, o); |
| 271 | } |
| 272 | |
| 273 | void tcg_gen_st_vec(TCGv_vec r, TCGv_ptr b, TCGArg o) |
| 274 | { |
| 275 | vec_gen_ldst(INDEX_op_st_vec, r, b, o); |
| 276 | } |
| 277 | |
| 278 | void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr b, TCGArg o, TCGType low_type) |
| 279 | { |
| 280 | TCGArg ri = tcgv_vec_arg(r); |
| 281 | TCGArg bi = tcgv_ptr_arg(b); |
| 282 | TCGTemp *rt = arg_temp(ri); |
| 283 | TCGType type = rt->base_type; |
| 284 | |
| 285 | tcg_debug_assert(low_type >= TCG_TYPE_V64); |
| 286 | tcg_debug_assert(low_type <= type); |
| 287 | vec_gen_3(INDEX_op_st_vec, low_type, 0, ri, bi, o); |
| 288 | } |
| 289 | |
| 290 | void tcg_gen_and_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) |
| 291 | { |
| 292 | vec_gen_op3(INDEX_op_and_vec, 0, r, a, b); |
| 293 | } |
| 294 | |
| 295 | void tcg_gen_or_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) |
| 296 | { |
| 297 | vec_gen_op3(INDEX_op_or_vec, 0, r, a, b); |
| 298 | } |
| 299 | |
| 300 | void tcg_gen_xor_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) |
| 301 | { |
| 302 | vec_gen_op3(INDEX_op_xor_vec, 0, r, a, b); |
| 303 | } |
| 304 | |
| 305 | void tcg_gen_andc_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) |
| 306 | { |
| 307 | if (TCG_TARGET_HAS_andc_vec) { |
| 308 | vec_gen_op3(INDEX_op_andc_vec, 0, r, a, b); |
| 309 | } else { |
| 310 | TCGv_vec t = tcg_temp_new_vec_matching(r); |
| 311 | tcg_gen_not_vec(0, t, b); |
| 312 | tcg_gen_and_vec(0, r, a, t); |
| 313 | tcg_temp_free_vec(t); |
| 314 | } |
| 315 | } |
| 316 | |
| 317 | void tcg_gen_orc_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) |
| 318 | { |
| 319 | if (TCG_TARGET_HAS_orc_vec) { |
| 320 | vec_gen_op3(INDEX_op_orc_vec, 0, r, a, b); |
| 321 | } else { |
| 322 | TCGv_vec t = tcg_temp_new_vec_matching(r); |
| 323 | tcg_gen_not_vec(0, t, b); |
| 324 | tcg_gen_or_vec(0, r, a, t); |
| 325 | tcg_temp_free_vec(t); |
| 326 | } |
| 327 | } |
| 328 | |
| 329 | void tcg_gen_nand_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) |
| 330 | { |
| 331 | if (TCG_TARGET_HAS_nand_vec) { |
| 332 | vec_gen_op3(INDEX_op_nand_vec, 0, r, a, b); |
| 333 | } else { |
| 334 | tcg_gen_and_vec(0, r, a, b); |
| 335 | tcg_gen_not_vec(0, r, r); |
| 336 | } |
| 337 | } |
| 338 | |
| 339 | void tcg_gen_nor_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) |
| 340 | { |
| 341 | if (TCG_TARGET_HAS_nor_vec) { |
| 342 | vec_gen_op3(INDEX_op_nor_vec, 0, r, a, b); |
| 343 | } else { |
| 344 | tcg_gen_or_vec(0, r, a, b); |
| 345 | tcg_gen_not_vec(0, r, r); |
| 346 | } |
| 347 | } |
| 348 | |
| 349 | void tcg_gen_eqv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) |
| 350 | { |
| 351 | if (TCG_TARGET_HAS_eqv_vec) { |
| 352 | vec_gen_op3(INDEX_op_eqv_vec, 0, r, a, b); |
| 353 | } else { |
| 354 | tcg_gen_xor_vec(0, r, a, b); |
| 355 | tcg_gen_not_vec(0, r, r); |
| 356 | } |
| 357 | } |
| 358 | |
| 359 | static bool do_op2(unsigned vece, TCGv_vec r, TCGv_vec a, TCGOpcode opc) |
| 360 | { |
| 361 | TCGTemp *rt = tcgv_vec_temp(r); |
| 362 | TCGTemp *at = tcgv_vec_temp(a); |
| 363 | TCGArg ri = temp_arg(rt); |
| 364 | TCGArg ai = temp_arg(at); |
| 365 | TCGType type = rt->base_type; |
| 366 | int can; |
| 367 | |
| 368 | tcg_debug_assert(at->base_type >= type); |
| 369 | tcg_assert_listed_vecop(opc); |
| 370 | can = tcg_can_emit_vec_op(opc, type, vece); |
| 371 | if (can > 0) { |
| 372 | vec_gen_2(opc, type, vece, ri, ai); |
| 373 | } else if (can < 0) { |
| 374 | const TCGOpcode *hold_list = tcg_swap_vecop_list(NULL); |
| 375 | tcg_expand_vec_op(opc, type, vece, ri, ai); |
| 376 | tcg_swap_vecop_list(hold_list); |
| 377 | } else { |
| 378 | return false; |
| 379 | } |
| 380 | return true; |
| 381 | } |
| 382 | |
| 383 | void tcg_gen_not_vec(unsigned vece, TCGv_vec r, TCGv_vec a) |
| 384 | { |
| 385 | if (TCG_TARGET_HAS_not_vec) { |
| 386 | vec_gen_op2(INDEX_op_not_vec, 0, r, a); |
| 387 | } else { |
| 388 | tcg_gen_xor_vec(0, r, a, tcg_constant_vec_matching(r, 0, -1)); |
| 389 | } |
| 390 | } |
| 391 | |
| 392 | void tcg_gen_neg_vec(unsigned vece, TCGv_vec r, TCGv_vec a) |
| 393 | { |
| 394 | const TCGOpcode *hold_list; |
| 395 | |
| 396 | tcg_assert_listed_vecop(INDEX_op_neg_vec); |
| 397 | hold_list = tcg_swap_vecop_list(NULL); |
| 398 | |
| 399 | if (!TCG_TARGET_HAS_neg_vec || !do_op2(vece, r, a, INDEX_op_neg_vec)) { |
| 400 | tcg_gen_sub_vec(vece, r, tcg_constant_vec_matching(r, vece, 0), a); |
| 401 | } |
| 402 | tcg_swap_vecop_list(hold_list); |
| 403 | } |
| 404 | |
| 405 | void tcg_gen_abs_vec(unsigned vece, TCGv_vec r, TCGv_vec a) |
| 406 | { |
| 407 | const TCGOpcode *hold_list; |
| 408 | |
| 409 | tcg_assert_listed_vecop(INDEX_op_abs_vec); |
| 410 | hold_list = tcg_swap_vecop_list(NULL); |
| 411 | |
| 412 | if (!do_op2(vece, r, a, INDEX_op_abs_vec)) { |
| 413 | TCGType type = tcgv_vec_temp(r)->base_type; |
| 414 | TCGv_vec t = tcg_temp_new_vec(type); |
| 415 | |
| 416 | tcg_debug_assert(tcg_can_emit_vec_op(INDEX_op_sub_vec, type, vece)); |
| 417 | if (tcg_can_emit_vec_op(INDEX_op_smax_vec, type, vece) > 0) { |
| 418 | tcg_gen_neg_vec(vece, t, a); |
| 419 | tcg_gen_smax_vec(vece, r, a, t); |
| 420 | } else { |
| 421 | if (tcg_can_emit_vec_op(INDEX_op_sari_vec, type, vece) > 0) { |
| 422 | tcg_gen_sari_vec(vece, t, a, (8 << vece) - 1); |
| 423 | } else { |
| 424 | tcg_gen_cmp_vec(TCG_COND_LT, vece, t, a, |
| 425 | tcg_constant_vec(type, vece, 0)); |
| 426 | } |
| 427 | tcg_gen_xor_vec(vece, r, a, t); |
| 428 | tcg_gen_sub_vec(vece, r, r, t); |
| 429 | } |
| 430 | |
| 431 | tcg_temp_free_vec(t); |
| 432 | } |
| 433 | tcg_swap_vecop_list(hold_list); |
| 434 | } |
| 435 | |
| 436 | static void do_shifti(TCGOpcode opc, unsigned vece, |
| 437 | TCGv_vec r, TCGv_vec a, int64_t i) |
| 438 | { |
| 439 | TCGTemp *rt = tcgv_vec_temp(r); |
| 440 | TCGTemp *at = tcgv_vec_temp(a); |
| 441 | TCGArg ri = temp_arg(rt); |
| 442 | TCGArg ai = temp_arg(at); |
| 443 | TCGType type = rt->base_type; |
| 444 | int can; |
| 445 | |
| 446 | tcg_debug_assert(at->base_type == type); |
| 447 | tcg_debug_assert(i >= 0 && i < (8 << vece)); |
| 448 | tcg_assert_listed_vecop(opc); |
| 449 | |
| 450 | if (i == 0) { |
| 451 | tcg_gen_mov_vec(r, a); |
| 452 | return; |
| 453 | } |
| 454 | |
| 455 | can = tcg_can_emit_vec_op(opc, type, vece); |
| 456 | if (can > 0) { |
| 457 | vec_gen_3(opc, type, vece, ri, ai, i); |
| 458 | } else { |
| 459 | /* We leave the choice of expansion via scalar or vector shift |
| 460 | to the target. Often, but not always, dupi can feed a vector |
| 461 | shift easier than a scalar. */ |
| 462 | const TCGOpcode *hold_list = tcg_swap_vecop_list(NULL); |
| 463 | tcg_debug_assert(can < 0); |
| 464 | tcg_expand_vec_op(opc, type, vece, ri, ai, i); |
| 465 | tcg_swap_vecop_list(hold_list); |
| 466 | } |
| 467 | } |
| 468 | |
| 469 | void tcg_gen_shli_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i) |
| 470 | { |
| 471 | do_shifti(INDEX_op_shli_vec, vece, r, a, i); |
| 472 | } |
| 473 | |
| 474 | void tcg_gen_shri_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i) |
| 475 | { |
| 476 | do_shifti(INDEX_op_shri_vec, vece, r, a, i); |
| 477 | } |
| 478 | |
| 479 | void tcg_gen_sari_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i) |
| 480 | { |
| 481 | do_shifti(INDEX_op_sari_vec, vece, r, a, i); |
| 482 | } |
| 483 | |
| 484 | void tcg_gen_rotli_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i) |
| 485 | { |
| 486 | do_shifti(INDEX_op_rotli_vec, vece, r, a, i); |
| 487 | } |
| 488 | |
| 489 | void tcg_gen_rotri_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i) |
| 490 | { |
| 491 | int bits = 8 << vece; |
| 492 | tcg_debug_assert(i >= 0 && i < bits); |
| 493 | do_shifti(INDEX_op_rotli_vec, vece, r, a, -i & (bits - 1)); |
| 494 | } |
| 495 | |
| 496 | void tcg_gen_cmp_vec(TCGCond cond, unsigned vece, |
| 497 | TCGv_vec r, TCGv_vec a, TCGv_vec b) |
| 498 | { |
| 499 | TCGTemp *rt = tcgv_vec_temp(r); |
| 500 | TCGTemp *at = tcgv_vec_temp(a); |
| 501 | TCGTemp *bt = tcgv_vec_temp(b); |
| 502 | TCGTemp *tt = NULL; |
| 503 | TCGArg ri = temp_arg(rt); |
| 504 | TCGArg ai = temp_arg(at); |
| 505 | TCGArg bi = temp_arg(bt); |
| 506 | TCGArg ti; |
| 507 | TCGType type = rt->base_type; |
| 508 | int can; |
| 509 | |
| 510 | tcg_debug_assert(at->base_type >= type); |
| 511 | tcg_debug_assert(bt->base_type >= type); |
| 512 | tcg_assert_listed_vecop(INDEX_op_cmp_vec); |
| 513 | can = tcg_can_emit_vec_op(INDEX_op_cmp_vec, type, vece); |
| 514 | |
| 515 | if (!TCG_TARGET_HAS_tst_vec && is_tst_cond(cond)) { |
| 516 | tt = tcg_temp_new_internal(type, TEMP_EBB); |
| 517 | ti = temp_arg(tt); |
| 518 | vec_gen_3(INDEX_op_and_vec, type, 0, ti, ai, bi); |
| 519 | at = tt; |
| 520 | ai = ti; |
| 521 | bt = tcg_constant_internal(type, 0); |
| 522 | bi = temp_arg(bt); |
| 523 | cond = tcg_tst_eqne_cond(cond); |
| 524 | } |
| 525 | |
| 526 | if (can > 0) { |
| 527 | vec_gen_4(INDEX_op_cmp_vec, type, vece, ri, ai, bi, cond); |
| 528 | } else { |
| 529 | const TCGOpcode *hold_list = tcg_swap_vecop_list(NULL); |
| 530 | tcg_debug_assert(can < 0); |
| 531 | tcg_expand_vec_op(INDEX_op_cmp_vec, type, vece, ri, ai, bi, cond); |
| 532 | tcg_swap_vecop_list(hold_list); |
| 533 | } |
| 534 | |
| 535 | if (tt) { |
| 536 | tcg_temp_free_internal(tt); |
| 537 | } |
| 538 | } |
| 539 | |
| 540 | static bool do_op3(unsigned vece, TCGv_vec r, TCGv_vec a, |
| 541 | TCGv_vec b, TCGOpcode opc) |
| 542 | { |
| 543 | TCGTemp *rt = tcgv_vec_temp(r); |
| 544 | TCGTemp *at = tcgv_vec_temp(a); |
| 545 | TCGTemp *bt = tcgv_vec_temp(b); |
| 546 | TCGArg ri = temp_arg(rt); |
| 547 | TCGArg ai = temp_arg(at); |
| 548 | TCGArg bi = temp_arg(bt); |
| 549 | TCGType type = rt->base_type; |
| 550 | int can; |
| 551 | |
| 552 | tcg_debug_assert(at->base_type >= type); |
| 553 | tcg_debug_assert(bt->base_type >= type); |
| 554 | tcg_assert_listed_vecop(opc); |
| 555 | can = tcg_can_emit_vec_op(opc, type, vece); |
| 556 | if (can > 0) { |
| 557 | vec_gen_3(opc, type, vece, ri, ai, bi); |
| 558 | } else if (can < 0) { |
| 559 | const TCGOpcode *hold_list = tcg_swap_vecop_list(NULL); |
| 560 | tcg_expand_vec_op(opc, type, vece, ri, ai, bi); |
| 561 | tcg_swap_vecop_list(hold_list); |
| 562 | } else { |
| 563 | return false; |
| 564 | } |
| 565 | return true; |
| 566 | } |
| 567 | |
| 568 | static void do_op3_nofail(unsigned vece, TCGv_vec r, TCGv_vec a, |
| 569 | TCGv_vec b, TCGOpcode opc) |
| 570 | { |
| 571 | bool ok = do_op3(vece, r, a, b, opc); |
| 572 | tcg_debug_assert(ok); |
| 573 | } |
| 574 | |
| 575 | void tcg_gen_add_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) |
| 576 | { |
| 577 | do_op3_nofail(vece, r, a, b, INDEX_op_add_vec); |
| 578 | } |
| 579 | |
| 580 | void tcg_gen_sub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) |
| 581 | { |
| 582 | do_op3_nofail(vece, r, a, b, INDEX_op_sub_vec); |
| 583 | } |
| 584 | |
| 585 | void tcg_gen_mul_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) |
| 586 | { |
| 587 | do_op3_nofail(vece, r, a, b, INDEX_op_mul_vec); |
| 588 | } |
| 589 | |
| 590 | void tcg_gen_ssadd_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) |
| 591 | { |
| 592 | do_op3_nofail(vece, r, a, b, INDEX_op_ssadd_vec); |
| 593 | } |
| 594 | |
| 595 | void tcg_gen_usadd_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) |
| 596 | { |
| 597 | if (!do_op3(vece, r, a, b, INDEX_op_usadd_vec)) { |
| 598 | const TCGOpcode *hold_list = tcg_swap_vecop_list(NULL); |
| 599 | TCGv_vec t = tcg_temp_new_vec_matching(r); |
| 600 | |
| 601 | /* usadd(a, b) = min(a, ~b) + b */ |
| 602 | tcg_gen_not_vec(vece, t, b); |
| 603 | tcg_gen_umin_vec(vece, t, t, a); |
| 604 | tcg_gen_add_vec(vece, r, t, b); |
| 605 | |
| 606 | tcg_temp_free_vec(t); |
| 607 | tcg_swap_vecop_list(hold_list); |
| 608 | } |
| 609 | } |
| 610 | |
| 611 | void tcg_gen_sssub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) |
| 612 | { |
| 613 | do_op3_nofail(vece, r, a, b, INDEX_op_sssub_vec); |
| 614 | } |
| 615 | |
| 616 | void tcg_gen_ussub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) |
| 617 | { |
| 618 | if (!do_op3(vece, r, a, b, INDEX_op_ussub_vec)) { |
| 619 | const TCGOpcode *hold_list = tcg_swap_vecop_list(NULL); |
| 620 | TCGv_vec t = tcg_temp_new_vec_matching(r); |
| 621 | |
| 622 | /* ussub(a, b) = max(a, b) - b */ |
| 623 | tcg_gen_umax_vec(vece, t, a, b); |
| 624 | tcg_gen_sub_vec(vece, r, t, b); |
| 625 | |
| 626 | tcg_temp_free_vec(t); |
| 627 | tcg_swap_vecop_list(hold_list); |
| 628 | } |
| 629 | } |
| 630 | |
| 631 | static void do_minmax(unsigned vece, TCGv_vec r, TCGv_vec a, |
| 632 | TCGv_vec b, TCGOpcode opc, TCGCond cond) |
| 633 | { |
| 634 | if (!do_op3(vece, r, a, b, opc)) { |
| 635 | const TCGOpcode *hold_list = tcg_swap_vecop_list(NULL); |
| 636 | tcg_gen_cmpsel_vec(cond, vece, r, a, b, a, b); |
| 637 | tcg_swap_vecop_list(hold_list); |
| 638 | } |
| 639 | } |
| 640 | |
| 641 | void tcg_gen_smin_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) |
| 642 | { |
| 643 | do_minmax(vece, r, a, b, INDEX_op_smin_vec, TCG_COND_LT); |
| 644 | } |
| 645 | |
| 646 | void tcg_gen_umin_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) |
| 647 | { |
| 648 | do_minmax(vece, r, a, b, INDEX_op_umin_vec, TCG_COND_LTU); |
| 649 | } |
| 650 | |
| 651 | void tcg_gen_smax_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) |
| 652 | { |
| 653 | do_minmax(vece, r, a, b, INDEX_op_smax_vec, TCG_COND_GT); |
| 654 | } |
| 655 | |
| 656 | void tcg_gen_umax_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) |
| 657 | { |
| 658 | do_minmax(vece, r, a, b, INDEX_op_umax_vec, TCG_COND_GTU); |
| 659 | } |
| 660 | |
| 661 | void tcg_gen_shlv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) |
| 662 | { |
| 663 | do_op3_nofail(vece, r, a, b, INDEX_op_shlv_vec); |
| 664 | } |
| 665 | |
| 666 | void tcg_gen_shrv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) |
| 667 | { |
| 668 | do_op3_nofail(vece, r, a, b, INDEX_op_shrv_vec); |
| 669 | } |
| 670 | |
| 671 | void tcg_gen_sarv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) |
| 672 | { |
| 673 | do_op3_nofail(vece, r, a, b, INDEX_op_sarv_vec); |
| 674 | } |
| 675 | |
| 676 | void tcg_gen_rotlv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) |
| 677 | { |
| 678 | do_op3_nofail(vece, r, a, b, INDEX_op_rotlv_vec); |
| 679 | } |
| 680 | |
| 681 | void tcg_gen_rotrv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) |
| 682 | { |
| 683 | do_op3_nofail(vece, r, a, b, INDEX_op_rotrv_vec); |
| 684 | } |
| 685 | |
| 686 | static void do_shifts(unsigned vece, TCGv_vec r, TCGv_vec a, |
| 687 | TCGv_i32 s, TCGOpcode opc) |
| 688 | { |
| 689 | TCGTemp *rt = tcgv_vec_temp(r); |
| 690 | TCGTemp *at = tcgv_vec_temp(a); |
| 691 | TCGTemp *st = tcgv_i32_temp(s); |
| 692 | TCGArg ri = temp_arg(rt); |
| 693 | TCGArg ai = temp_arg(at); |
| 694 | TCGArg si = temp_arg(st); |
| 695 | TCGType type = rt->base_type; |
| 696 | int can; |
| 697 | |
| 698 | tcg_debug_assert(at->base_type >= type); |
| 699 | tcg_assert_listed_vecop(opc); |
| 700 | can = tcg_can_emit_vec_op(opc, type, vece); |
| 701 | if (can > 0) { |
| 702 | vec_gen_3(opc, type, vece, ri, ai, si); |
| 703 | } else if (can < 0) { |
| 704 | const TCGOpcode *hold_list = tcg_swap_vecop_list(NULL); |
| 705 | tcg_expand_vec_op(opc, type, vece, ri, ai, si); |
| 706 | tcg_swap_vecop_list(hold_list); |
| 707 | } else { |
| 708 | g_assert_not_reached(); |
| 709 | } |
| 710 | } |
| 711 | |
| 712 | void tcg_gen_shls_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 b) |
| 713 | { |
| 714 | do_shifts(vece, r, a, b, INDEX_op_shls_vec); |
| 715 | } |
| 716 | |
| 717 | void tcg_gen_shrs_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 b) |
| 718 | { |
| 719 | do_shifts(vece, r, a, b, INDEX_op_shrs_vec); |
| 720 | } |
| 721 | |
| 722 | void tcg_gen_sars_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 b) |
| 723 | { |
| 724 | do_shifts(vece, r, a, b, INDEX_op_sars_vec); |
| 725 | } |
| 726 | |
| 727 | void tcg_gen_rotls_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s) |
| 728 | { |
| 729 | do_shifts(vece, r, a, s, INDEX_op_rotls_vec); |
| 730 | } |
| 731 | |
| 732 | void tcg_gen_bitsel_vec(unsigned vece, TCGv_vec r, TCGv_vec a, |
| 733 | TCGv_vec b, TCGv_vec c) |
| 734 | { |
| 735 | TCGTemp *rt = tcgv_vec_temp(r); |
| 736 | TCGTemp *at = tcgv_vec_temp(a); |
| 737 | TCGTemp *bt = tcgv_vec_temp(b); |
| 738 | TCGTemp *ct = tcgv_vec_temp(c); |
| 739 | TCGType type = rt->base_type; |
| 740 | |
| 741 | tcg_debug_assert(at->base_type >= type); |
| 742 | tcg_debug_assert(bt->base_type >= type); |
| 743 | tcg_debug_assert(ct->base_type >= type); |
| 744 | |
| 745 | if (TCG_TARGET_HAS_bitsel_vec) { |
| 746 | vec_gen_4(INDEX_op_bitsel_vec, type, MO_8, |
| 747 | temp_arg(rt), temp_arg(at), temp_arg(bt), temp_arg(ct)); |
| 748 | } else { |
| 749 | TCGv_vec t = tcg_temp_new_vec(type); |
| 750 | tcg_gen_and_vec(MO_8, t, a, b); |
| 751 | tcg_gen_andc_vec(MO_8, r, c, a); |
| 752 | tcg_gen_or_vec(MO_8, r, r, t); |
| 753 | tcg_temp_free_vec(t); |
| 754 | } |
| 755 | } |
| 756 | |
| 757 | void tcg_gen_cmpsel_vec(TCGCond cond, unsigned vece, TCGv_vec r, |
| 758 | TCGv_vec a, TCGv_vec b, TCGv_vec c, TCGv_vec d) |
| 759 | { |
| 760 | TCGTemp *rt = tcgv_vec_temp(r); |
| 761 | TCGTemp *at = tcgv_vec_temp(a); |
| 762 | TCGTemp *bt = tcgv_vec_temp(b); |
| 763 | TCGTemp *ct = tcgv_vec_temp(c); |
| 764 | TCGTemp *dt = tcgv_vec_temp(d); |
| 765 | TCGArg ri = temp_arg(rt); |
| 766 | TCGArg ai = temp_arg(at); |
| 767 | TCGArg bi = temp_arg(bt); |
| 768 | TCGArg ci = temp_arg(ct); |
| 769 | TCGArg di = temp_arg(dt); |
| 770 | TCGType type = rt->base_type; |
| 771 | const TCGOpcode *hold_list; |
| 772 | int can; |
| 773 | |
| 774 | tcg_debug_assert(at->base_type >= type); |
| 775 | tcg_debug_assert(bt->base_type >= type); |
| 776 | tcg_debug_assert(ct->base_type >= type); |
| 777 | tcg_debug_assert(dt->base_type >= type); |
| 778 | |
| 779 | tcg_assert_listed_vecop(INDEX_op_cmpsel_vec); |
| 780 | hold_list = tcg_swap_vecop_list(NULL); |
| 781 | can = tcg_can_emit_vec_op(INDEX_op_cmpsel_vec, type, vece); |
| 782 | |
| 783 | if (can > 0) { |
| 784 | vec_gen_6(INDEX_op_cmpsel_vec, type, vece, ri, ai, bi, ci, di, cond); |
| 785 | } else if (can < 0) { |
| 786 | tcg_expand_vec_op(INDEX_op_cmpsel_vec, type, vece, |
| 787 | ri, ai, bi, ci, di, cond); |
| 788 | } else { |
| 789 | TCGv_vec t = tcg_temp_new_vec(type); |
| 790 | tcg_gen_cmp_vec(cond, vece, t, a, b); |
| 791 | tcg_gen_bitsel_vec(vece, r, t, c, d); |
| 792 | tcg_temp_free_vec(t); |
| 793 | } |
| 794 | tcg_swap_vecop_list(hold_list); |
| 795 | } |