| 1 | /* SPDX-License-Identifier: MIT */ |
| 2 | /* |
| 3 | * Define target-specific opcode support |
| 4 | * Copyright (c) 2008 Fabrice Bellard |
| 5 | */ |
| 6 | |
| 7 | #ifndef TCG_TARGET_HAS_H |
| 8 | #define TCG_TARGET_HAS_H |
| 9 | |
| 10 | #include "host/cpuinfo.h" |
| 11 | |
| 12 | #define have_bmi1 (cpuinfo & CPUINFO_BMI1) |
| 13 | #define have_popcnt (cpuinfo & CPUINFO_POPCNT) |
| 14 | #define have_avx1 (cpuinfo & CPUINFO_AVX1) |
| 15 | #define have_avx2 (cpuinfo & CPUINFO_AVX2) |
| 16 | #define have_movbe (cpuinfo & CPUINFO_MOVBE) |
| 17 | |
| 18 | /* |
| 19 | * There are interesting instructions in AVX512, so long as we have AVX512VL, |
| 20 | * which indicates support for EVEX on sizes smaller than 512 bits. |
| 21 | */ |
| 22 | #define have_avx512vl ((cpuinfo & CPUINFO_AVX512VL) && \ |
| 23 | (cpuinfo & CPUINFO_AVX512F)) |
| 24 | #define have_avx512bw ((cpuinfo & CPUINFO_AVX512BW) && have_avx512vl) |
| 25 | #define have_avx512dq ((cpuinfo & CPUINFO_AVX512DQ) && have_avx512vl) |
| 26 | #define have_avx512vbmi2 ((cpuinfo & CPUINFO_AVX512VBMI2) && have_avx512vl) |
| 27 | |
| 28 | /* optional instructions */ |
| 29 | /* Keep 32-bit values zero-extended in a register. */ |
| 30 | #define TCG_TARGET_HAS_extr_i64_i32 1 |
| 31 | |
| 32 | #define TCG_TARGET_HAS_qemu_ldst_i128 (cpuinfo & CPUINFO_ATOMIC_VMOVDQA) |
| 33 | |
| 34 | #define TCG_TARGET_HAS_tst 1 |
| 35 | |
| 36 | /* We do not support older SSE systems, only beginning with AVX1. */ |
| 37 | #define TCG_TARGET_HAS_v64 have_avx1 |
| 38 | #define TCG_TARGET_HAS_v128 have_avx1 |
| 39 | #define TCG_TARGET_HAS_v256 have_avx2 |
| 40 | |
| 41 | #define TCG_TARGET_HAS_andc_vec 1 |
| 42 | #define TCG_TARGET_HAS_orc_vec have_avx512vl |
| 43 | #define TCG_TARGET_HAS_nand_vec have_avx512vl |
| 44 | #define TCG_TARGET_HAS_nor_vec have_avx512vl |
| 45 | #define TCG_TARGET_HAS_eqv_vec have_avx512vl |
| 46 | #define TCG_TARGET_HAS_not_vec have_avx512vl |
| 47 | #define TCG_TARGET_HAS_neg_vec 0 |
| 48 | #define TCG_TARGET_HAS_abs_vec 1 |
| 49 | #define TCG_TARGET_HAS_roti_vec have_avx512vl |
| 50 | #define TCG_TARGET_HAS_rots_vec 0 |
| 51 | #define TCG_TARGET_HAS_rotv_vec have_avx512vl |
| 52 | #define TCG_TARGET_HAS_shi_vec 1 |
| 53 | #define TCG_TARGET_HAS_shs_vec 1 |
| 54 | #define TCG_TARGET_HAS_shv_vec have_avx2 |
| 55 | #define TCG_TARGET_HAS_mul_vec 1 |
| 56 | #define TCG_TARGET_HAS_sat_vec 1 |
| 57 | #define TCG_TARGET_HAS_minmax_vec 1 |
| 58 | #define TCG_TARGET_HAS_bitsel_vec have_avx512vl |
| 59 | #define TCG_TARGET_HAS_cmpsel_vec 1 |
| 60 | #define TCG_TARGET_HAS_tst_vec have_avx512bw |
| 61 | |
| 62 | #define TCG_TARGET_deposit_valid(type, ofs, len) \ |
| 63 | ((ofs) == 0 && ((len) == 8 || (len) == 16)) |
| 64 | |
| 65 | /* |
| 66 | * Check for the possibility of low byte/word extraction, high-byte extraction |
| 67 | * and zero-extending 32-bit right-shift. |
| 68 | * |
| 69 | * We cannot sign-extend from high byte to 64-bits without using the |
| 70 | * REX prefix that explicitly excludes access to the high-byte registers. |
| 71 | */ |
| 72 | static inline bool |
| 73 | tcg_target_sextract_valid(TCGType type, unsigned ofs, unsigned len) |
| 74 | { |
| 75 | switch (ofs) { |
| 76 | case 0: |
| 77 | switch (len) { |
| 78 | case 8: |
| 79 | case 16: |
| 80 | return true; |
| 81 | case 32: |
| 82 | return type == TCG_TYPE_I64; |
| 83 | } |
| 84 | return false; |
| 85 | case 8: |
| 86 | return len == 8 && type == TCG_TYPE_I32; |
| 87 | } |
| 88 | return false; |
| 89 | } |
| 90 | #define TCG_TARGET_sextract_valid tcg_target_sextract_valid |
| 91 | |
| 92 | static inline bool |
| 93 | tcg_target_extract_valid(TCGType type, unsigned ofs, unsigned len) |
| 94 | { |
| 95 | if (type == TCG_TYPE_I64 && ofs + len == 32) { |
| 96 | return true; |
| 97 | } |
| 98 | switch (ofs) { |
| 99 | case 0: |
| 100 | return len == 8 || len == 16; |
| 101 | case 8: |
| 102 | return len == 8; |
| 103 | } |
| 104 | return false; |
| 105 | } |
| 106 | #define TCG_TARGET_extract_valid tcg_target_extract_valid |
| 107 | |
| 108 | #endif |