| 1 | #!/usr/bin/env python3 |
| 2 | # |
| 3 | # Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. |
| 4 | # |
| 5 | # SPDX-License-Identifier: GPL-2.0-or-later |
| 6 | |
| 7 | from qemu_test import QemuSystemTest, Asset |
| 8 | from qemu_test.cmd import wait_for_console_pattern |
| 9 | |
| 10 | |
| 11 | class ArchTestsUart(QemuSystemTest): |
| 12 | """ |
| 13 | Hexagon architecture verification tests |
| 14 | |
| 15 | These are bare-metal tests from hexagon-arch-tests that exercise |
| 16 | system functionality. |
| 17 | |
| 18 | Tests output results via UART. |
| 19 | """ |
| 20 | timeout = 60 |
| 21 | |
| 22 | ASSET_TARBALL = Asset( |
| 23 | "https://github.com/qualcomm/qemu-hexagon-testing/releases/" |
| 24 | "download/v0.2.5/arch_tests_uart.tar.gz", |
| 25 | "edb4f37b877a3a72a0e10920477458a43b40045d34398fee8cb763fefd342f4f", |
| 26 | ) |
| 27 | |
| 28 | def run_uart_test(self, test_name: str, |
| 29 | machine: str = "virt") -> None: |
| 30 | """ |
| 31 | Run an arch test binary and verify PASS via UART console output. |
| 32 | """ |
| 33 | self.set_machine(machine) |
| 34 | self.archive_extract(self.ASSET_TARBALL) |
| 35 | target_bin = self.scratch_file('arch_tests_uart_package', |
| 36 | 'bin', test_name) |
| 37 | self.vm.set_console() |
| 38 | self.set_vm_arg("-display", "none") |
| 39 | self.set_vm_arg("-kernel", target_bin) |
| 40 | self.vm.launch() |
| 41 | wait_for_console_pattern(self, "PASS") |
| 42 | |
| 43 | def test_exceptions(self) -> None: |
| 44 | """Tests exception delivery for trap instructions, privilege |
| 45 | violations, and verifies SSR cause codes and ELR values. |
| 46 | """ |
| 47 | self.run_uart_test("test_exceptions") |
| 48 | |
| 49 | def test_guest_mode(self) -> None: |
| 50 | """Tests guest mode entry/exit via CCR configuration, verifying |
| 51 | GSR fields, GELR, and guest event vector table dispatch. |
| 52 | """ |
| 53 | self.run_uart_test("test_guest_mode") |
| 54 | |
| 55 | def test_int_steering(self) -> None: |
| 56 | """Tests interrupt steering via priority-based routing to |
| 57 | specific threads using STID priority and iassignw. |
| 58 | """ |
| 59 | self.run_uart_test("test_int_steering") |
| 60 | |
| 61 | def test_cache(self) -> None: |
| 62 | """Tests cache operations: dckill/ickill, l2kill, dczeroa, |
| 63 | dccleaninva, cache disable/enable, barriers, and dcinva/dccleana. |
| 64 | """ |
| 65 | self.run_uart_test("test_cache") |
| 66 | |
| 67 | def test_l2vic(self) -> None: |
| 68 | """Tests the L2VIC interrupt controller: enable readback, |
| 69 | interrupt type readback, VID capture, and the fast interface. |
| 70 | """ |
| 71 | self.run_uart_test("test_l2vic") |
| 72 | |
| 73 | def test_threads(self) -> None: |
| 74 | """Tests hardware thread management: start/stop, MODECTL state, |
| 75 | per-thread HTID, shared memory, wait/resume, STID priority, and |
| 76 | SCHEDCFG/BESTWAIT readback. |
| 77 | """ |
| 78 | self.run_uart_test("test_threads") |
| 79 | |
| 80 | def test_tlb_mmu(self) -> None: |
| 81 | """Tests TLB/MMU operations: write/read/probe/invalidate, |
| 82 | global entries, multiple entries, overwrite, ASID matching, |
| 83 | and permission checks. |
| 84 | """ |
| 85 | self.run_uart_test("test_tlb_mmu") |
| 86 | |
| 87 | def test_user_mode(self) -> None: |
| 88 | """Tests user mode / privilege transitions: supervisor mode, |
| 89 | SSR UM/IE/XE/CE/PE bits, and the trap0 user-mode exit handler. |
| 90 | """ |
| 91 | self.run_uart_test("test_user_mode") |
| 92 | |
| 93 | |
| 94 | if __name__ == "__main__": |
| 95 | QemuSystemTest.main() |