| 1 | #!/usr/bin/env python3 |
| 2 | # |
| 3 | # Functional tests for RISC-V big-endian support |
| 4 | # |
| 5 | # Copyright (c) 2026 MIPS |
| 6 | # |
| 7 | # SPDX-License-Identifier: GPL-2.0-or-later |
| 8 | |
| 9 | from qemu_test import QemuSystemTest, Asset |
| 10 | from qemu_test import wait_for_console_pattern |
| 11 | |
| 12 | |
| 13 | class RiscvBigEndian(QemuSystemTest): |
| 14 | """ |
| 15 | Tests for RISC-V runtime big-endian data support. |
| 16 | |
| 17 | Uses a bare-metal RV64 ELF that detects data endianness at runtime |
| 18 | by storing a 32-bit word and reading back byte 0. Prints "ENDIAN: BE" |
| 19 | or "ENDIAN: LE" to the NS16550A UART on the virt machine. |
| 20 | """ |
| 21 | |
| 22 | timeout = 10 |
| 23 | |
| 24 | ASSET_BE_TEST = Asset( |
| 25 | 'https://github.com/MIPS/linux-test-downloads/raw/main/' |
| 26 | 'riscvbe-baremetal/be-test-bare-metal.elf', |
| 27 | '9ad51b675e101de65908fadbac064ed1d0564c17463715d09dd734db86ea0f58') |
| 28 | |
| 29 | def _run_bare_metal(self, big_endian=False): |
| 30 | self.set_machine('virt') |
| 31 | kernel = self.ASSET_BE_TEST.fetch() |
| 32 | self.vm.add_args('-bios', 'none') |
| 33 | self.vm.add_args('-kernel', kernel) |
| 34 | if big_endian: |
| 35 | self.vm.add_args('-cpu', 'rv64,big-endian=on') |
| 36 | self.vm.set_console() |
| 37 | self.vm.launch() |
| 38 | expected = 'ENDIAN: BE' if big_endian else 'ENDIAN: LE' |
| 39 | wait_for_console_pattern(self, expected) |
| 40 | |
| 41 | def test_bare_metal_littleendian(self): |
| 42 | """ |
| 43 | Boot bare-metal ELF on virt with default little-endian CPU. |
| 44 | Expects "ENDIAN: LE" on UART. |
| 45 | """ |
| 46 | self._run_bare_metal(big_endian=False) |
| 47 | |
| 48 | def test_bare_metal_bigendian(self): |
| 49 | """ |
| 50 | Boot bare-metal ELF on virt with big-endian=on CPU property. |
| 51 | Expects "ENDIAN: BE" on UART. |
| 52 | """ |
| 53 | self._run_bare_metal(big_endian=True) |
| 54 | |
| 55 | |
| 56 | if __name__ == '__main__': |
| 57 | QemuSystemTest.main() |