| 1 | #!/usr/bin/env python3 |
| 2 | # |
| 3 | # OpenSBI boot test for RISC-V machines |
| 4 | # |
| 5 | # Copyright (c) 2022, Ventana Micro |
| 6 | # |
| 7 | # This work is licensed under the terms of the GNU GPL, version 2 or |
| 8 | # later. See the COPYING file in the top-level directory. |
| 9 | |
| 10 | from qemu_test import QemuSystemTest |
| 11 | from qemu_test import wait_for_console_pattern |
| 12 | |
| 13 | class RiscvOpenSBI(QemuSystemTest): |
| 14 | |
| 15 | timeout = 5 |
| 16 | |
| 17 | def boot_opensbi(self): |
| 18 | self.vm.set_console() |
| 19 | self.vm.launch() |
| 20 | wait_for_console_pattern(self, 'Platform Name') |
| 21 | wait_for_console_pattern(self, 'Boot HART MEDELEG') |
| 22 | |
| 23 | def test_riscv_spike(self): |
| 24 | self.set_machine('spike') |
| 25 | self.boot_opensbi() |
| 26 | |
| 27 | def test_riscv_sifive_u(self): |
| 28 | self.set_machine('sifive_u') |
| 29 | self.boot_opensbi() |
| 30 | |
| 31 | def test_riscv_tt_atlantis(self): |
| 32 | self.set_machine('tt-atlantis') |
| 33 | self.boot_opensbi() |
| 34 | |
| 35 | def test_riscv_virt(self): |
| 36 | self.set_machine('virt') |
| 37 | self.boot_opensbi() |
| 38 | |
| 39 | if __name__ == '__main__': |
| 40 | QemuSystemTest.main() |