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1 /*
2 * AHCI test cases
3 *
4 * Copyright (c) 2014 John Snow <jsnow@redhat.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include <getopt.h>
27
28 #include "libqtest.h"
29 #include "libqos/libqos-pc.h"
30 #include "libqos/ahci.h"
31 #include "libqos/pci-pc.h"
32
33 #include "qobject/qdict.h"
34 #include "qemu/bswap.h"
35
36 #include "hw/pci/pci_ids.h"
37 #include "hw/pci/pci_regs.h"
38
39 /* Test images sizes in MB */
40 #define TEST_IMAGE_SIZE_MB_LARGE (200 * 1024)
41 #define TEST_IMAGE_SIZE_MB_SMALL 64
42
43 /*** Globals ***/
44 static char *tmp_path;
45 static char *debug_path;
46 static char *mig_socket;
47 static bool ahci_pedantic;
48 static const char *imgfmt;
49 static unsigned test_image_size_mb;
50
51 /*** Function Declarations ***/
52 static void ahci_test_port_spec(AHCIQState *ahci, uint8_t port);
53 static void ahci_test_pci_spec(AHCIQState *ahci);
54 static void ahci_test_pci_caps(AHCIQState *ahci, uint16_t header,
55 uint8_t offset);
56 static void ahci_test_satacap(AHCIQState *ahci, uint8_t offset);
57 static void ahci_test_msicap(AHCIQState *ahci, uint8_t offset);
58 static void ahci_test_pmcap(AHCIQState *ahci, uint8_t offset);
59
60 /*** Utilities ***/
61
62 static uint64_t mb_to_sectors(uint64_t image_size_mb)
63 {
64 return (image_size_mb * 1024 * 1024) / AHCI_SECTOR_SIZE;
65 }
66
67 static void string_bswap16(uint16_t *s, size_t bytes)
68 {
69 g_assert_cmphex((bytes & 1), ==, 0);
70 bytes /= 2;
71
72 while (bytes--) {
73 *s = bswap16(*s);
74 s++;
75 }
76 }
77
78 /**
79 * Verify that the transfer did not corrupt our state at all.
80 */
81 static void verify_state(AHCIQState *ahci, uint64_t hba_old)
82 {
83 int i, j;
84 uint32_t ahci_fingerprint;
85 uint64_t hba_base;
86 AHCICommandHeader cmd;
87
88 ahci_fingerprint = qpci_config_readl(ahci->dev, PCI_VENDOR_ID);
89 g_assert_cmphex(ahci_fingerprint, ==, ahci->fingerprint);
90
91 /* If we haven't initialized, this is as much as can be validated. */
92 if (!ahci->enabled) {
93 return;
94 }
95
96 hba_base = (uint64_t)qpci_config_readl(ahci->dev, PCI_BASE_ADDRESS_5);
97 g_assert_cmphex(hba_base, ==, hba_old);
98
99 g_assert_cmphex(ahci_rreg(ahci, AHCI_CAP), ==, ahci->cap);
100 g_assert_cmphex(ahci_rreg(ahci, AHCI_CAP2), ==, ahci->cap2);
101
102 for (i = 0; i < 32; i++) {
103 g_assert_cmphex(ahci_px_rreg(ahci, i, AHCI_PX_FB), ==,
104 ahci->port[i].fb);
105 g_assert_cmphex(ahci_px_rreg(ahci, i, AHCI_PX_CLB), ==,
106 ahci->port[i].clb);
107 for (j = 0; j < 32; j++) {
108 ahci_get_command_header(ahci, i, j, &cmd);
109 g_assert_cmphex(cmd.prdtl, ==, ahci->port[i].prdtl[j]);
110 g_assert_cmphex(cmd.ctba, ==, ahci->port[i].ctba[j]);
111 }
112 }
113 }
114
115 static void ahci_migrate(AHCIQState *from, AHCIQState *to, const char *uri)
116 {
117 QOSState *tmp = to->parent;
118 QPCIDevice *dev = to->dev;
119 char *uri_local = NULL;
120 uint64_t hba_old;
121
122 if (uri == NULL) {
123 uri_local = g_strdup_printf("%s%s", "unix:", mig_socket);
124 uri = uri_local;
125 }
126
127 hba_old = (uint64_t)qpci_config_readl(from->dev, PCI_BASE_ADDRESS_5);
128
129 /* context will be 'to' after completion. */
130 migrate(from->parent, to->parent, uri);
131
132 /* We'd like for the AHCIState objects to still point
133 * to information specific to its specific parent
134 * instance, but otherwise just inherit the new data. */
135 memcpy(to, from, sizeof(AHCIQState));
136 to->parent = tmp;
137 to->dev = dev;
138
139 tmp = from->parent;
140 dev = from->dev;
141 memset(from, 0x00, sizeof(AHCIQState));
142 from->parent = tmp;
143 from->dev = dev;
144
145 verify_state(to, hba_old);
146 g_free(uri_local);
147 }
148
149 /*** Test Setup & Teardown ***/
150
151 /**
152 * Start a Q35 machine and bookmark a handle to the AHCI device.
153 */
154 G_GNUC_PRINTF(1, 0)
155 static AHCIQState *ahci_vboot(const char *cli, va_list ap)
156 {
157 AHCIQState *s;
158
159 s = g_new0(AHCIQState, 1);
160 s->parent = qtest_pc_vboot(cli, ap);
161 alloc_set_flags(&s->parent->alloc, ALLOC_LEAK_ASSERT);
162
163 /* Verify that we have an AHCI device present. */
164 s->dev = get_ahci_device(s->parent->qts, &s->fingerprint);
165
166 return s;
167 }
168
169 /**
170 * Start a Q35 machine and bookmark a handle to the AHCI device.
171 */
172 G_GNUC_PRINTF(1, 2)
173 static AHCIQState *ahci_boot(const char *cli, ...)
174 {
175 AHCIQState *s;
176 va_list ap;
177
178 if (cli) {
179 va_start(ap, cli);
180 s = ahci_vboot(cli, ap);
181 va_end(ap);
182 } else {
183 cli = "-drive if=none,id=drive0,file=%s,cache=writeback,format=%s"
184 " -M q35 "
185 "-device ide-hd,drive=drive0 "
186 "-global ide-hd.serial=%s "
187 "-global ide-hd.ver=%s";
188 s = ahci_boot(cli, tmp_path, imgfmt, "testdisk", "version");
189 }
190
191 return s;
192 }
193
194 /**
195 * Clean up the PCI device, then terminate the QEMU instance.
196 */
197 static void ahci_shutdown(AHCIQState *ahci)
198 {
199 QOSState *qs = ahci->parent;
200
201 ahci_clean_mem(ahci);
202 free_ahci_device(ahci->dev);
203 g_free(ahci);
204 qtest_shutdown(qs);
205 }
206
207 /**
208 * Boot and fully enable the HBA device.
209 * @see ahci_boot, ahci_pci_enable and ahci_hba_enable.
210 */
211 G_GNUC_PRINTF(1, 2)
212 static AHCIQState *ahci_boot_and_enable(const char *cli, ...)
213 {
214 AHCIQState *ahci;
215 va_list ap;
216 uint16_t buff[256];
217 uint8_t port;
218 uint8_t hello;
219
220 if (cli) {
221 va_start(ap, cli);
222 ahci = ahci_vboot(cli, ap);
223 va_end(ap);
224 } else {
225 ahci = ahci_boot(NULL);
226 }
227
228 ahci_pci_enable(ahci);
229 ahci_hba_enable(ahci);
230 /* Initialize test device */
231 port = ahci_port_select(ahci);
232 ahci_port_clear(ahci, port);
233 if (is_atapi(ahci, port)) {
234 hello = CMD_PACKET_ID;
235 } else {
236 hello = CMD_IDENTIFY;
237 }
238 ahci_io(ahci, port, hello, &buff, sizeof(buff), 0);
239
240 return ahci;
241 }
242
243 /*** Specification Adherence Tests ***/
244
245 /**
246 * Implementation for test_pci_spec. Ensures PCI configuration space is sane.
247 */
248 static void ahci_test_pci_spec(AHCIQState *ahci)
249 {
250 uint8_t datab;
251 uint16_t data;
252 uint32_t datal;
253
254 /* Most of these bits should start cleared until we turn them on. */
255 data = qpci_config_readw(ahci->dev, PCI_COMMAND);
256 ASSERT_BIT_CLEAR(data, PCI_COMMAND_MEMORY);
257 ASSERT_BIT_CLEAR(data, PCI_COMMAND_MASTER);
258 ASSERT_BIT_CLEAR(data, PCI_COMMAND_SPECIAL); /* Reserved */
259 ASSERT_BIT_CLEAR(data, PCI_COMMAND_VGA_PALETTE); /* Reserved */
260 ASSERT_BIT_CLEAR(data, PCI_COMMAND_PARITY);
261 ASSERT_BIT_CLEAR(data, PCI_COMMAND_WAIT); /* Reserved */
262 ASSERT_BIT_CLEAR(data, PCI_COMMAND_SERR);
263 ASSERT_BIT_CLEAR(data, PCI_COMMAND_FAST_BACK);
264 ASSERT_BIT_CLEAR(data, PCI_COMMAND_INTX_DISABLE);
265 ASSERT_BIT_CLEAR(data, 0xF800); /* Reserved */
266
267 data = qpci_config_readw(ahci->dev, PCI_STATUS);
268 ASSERT_BIT_CLEAR(data, 0x01 | 0x02 | 0x04); /* Reserved */
269 ASSERT_BIT_CLEAR(data, PCI_STATUS_INTERRUPT);
270 ASSERT_BIT_SET(data, PCI_STATUS_CAP_LIST); /* must be set */
271 ASSERT_BIT_CLEAR(data, PCI_STATUS_UDF); /* Reserved */
272 ASSERT_BIT_CLEAR(data, PCI_STATUS_PARITY);
273 ASSERT_BIT_CLEAR(data, PCI_STATUS_SIG_TARGET_ABORT);
274 ASSERT_BIT_CLEAR(data, PCI_STATUS_REC_TARGET_ABORT);
275 ASSERT_BIT_CLEAR(data, PCI_STATUS_REC_MASTER_ABORT);
276 ASSERT_BIT_CLEAR(data, PCI_STATUS_SIG_SYSTEM_ERROR);
277 ASSERT_BIT_CLEAR(data, PCI_STATUS_DETECTED_PARITY);
278
279 /* RID occupies the low byte, CCs occupy the high three. */
280 datal = qpci_config_readl(ahci->dev, PCI_CLASS_REVISION);
281 if (ahci_pedantic) {
282 /* AHCI 1.3 specifies that at-boot, the RID should reset to 0x00,
283 * Though in practice this is likely seldom true. */
284 ASSERT_BIT_CLEAR(datal, 0xFF);
285 }
286
287 /* BCC *must* equal 0x01. */
288 g_assert_cmphex(PCI_BCC(datal), ==, 0x01);
289 if (PCI_SCC(datal) == 0x01) {
290 /* IDE */
291 ASSERT_BIT_SET(0x80000000, datal);
292 ASSERT_BIT_CLEAR(0x60000000, datal);
293 } else if (PCI_SCC(datal) == 0x04) {
294 /* RAID */
295 g_assert_cmphex(PCI_PI(datal), ==, 0);
296 } else if (PCI_SCC(datal) == 0x06) {
297 /* AHCI */
298 g_assert_cmphex(PCI_PI(datal), ==, 0x01);
299 } else {
300 g_assert_not_reached();
301 }
302
303 datab = qpci_config_readb(ahci->dev, PCI_CACHE_LINE_SIZE);
304 g_assert_cmphex(datab, ==, 0);
305
306 datab = qpci_config_readb(ahci->dev, PCI_LATENCY_TIMER);
307 g_assert_cmphex(datab, ==, 0);
308
309 /* Only the bottom 7 bits must be off. */
310 datab = qpci_config_readb(ahci->dev, PCI_HEADER_TYPE);
311 ASSERT_BIT_CLEAR(datab, 0x7F);
312
313 /* BIST is optional, but the low 7 bits must always start off regardless. */
314 datab = qpci_config_readb(ahci->dev, PCI_BIST);
315 ASSERT_BIT_CLEAR(datab, 0x7F);
316
317 /* BARS 0-4 do not have a boot spec, but ABAR/BAR5 must be clean. */
318 datal = qpci_config_readl(ahci->dev, PCI_BASE_ADDRESS_5);
319 g_assert_cmphex(datal, ==, 0);
320
321 qpci_config_writel(ahci->dev, PCI_BASE_ADDRESS_5, 0xFFFFFFFF);
322 datal = qpci_config_readl(ahci->dev, PCI_BASE_ADDRESS_5);
323 /* ABAR must be 32-bit, memory mapped, non-prefetchable and
324 * must be >= 512 bytes. To that end, bits 0-8 must be off. */
325 ASSERT_BIT_CLEAR(datal, 0xFF);
326
327 /* Capability list MUST be present, */
328 datal = qpci_config_readl(ahci->dev, PCI_CAPABILITY_LIST);
329 /* But these bits are reserved. */
330 ASSERT_BIT_CLEAR(datal, ~0xFF);
331 g_assert_cmphex(datal, !=, 0);
332
333 /* Check specification adherence for capability extensions. */
334 data = qpci_config_readw(ahci->dev, datal);
335
336 switch (ahci->fingerprint) {
337 case AHCI_INTEL_ICH9:
338 /* Intel ICH9 Family Datasheet 14.1.19 p.550 */
339 g_assert_cmphex((data & 0xFF), ==, PCI_CAP_ID_MSI);
340 break;
341 default:
342 /* AHCI 1.3, Section 2.1.14 -- CAP must point to PMCAP. */
343 g_assert_cmphex((data & 0xFF), ==, PCI_CAP_ID_PM);
344 }
345
346 ahci_test_pci_caps(ahci, data, (uint8_t)datal);
347
348 /* Reserved. */
349 datal = qpci_config_readl(ahci->dev, PCI_CAPABILITY_LIST + 4);
350 g_assert_cmphex(datal, ==, 0);
351
352 /* IPIN might vary, but ILINE must be off. */
353 datab = qpci_config_readb(ahci->dev, PCI_INTERRUPT_LINE);
354 g_assert_cmphex(datab, ==, 0);
355 }
356
357 /**
358 * Test PCI capabilities for AHCI specification adherence.
359 */
360 static void ahci_test_pci_caps(AHCIQState *ahci, uint16_t header,
361 uint8_t offset)
362 {
363 uint8_t cid = header & 0xFF;
364 uint8_t next = header >> 8;
365
366 g_test_message("CID: %02x; next: %02x", cid, next);
367
368 switch (cid) {
369 case PCI_CAP_ID_PM:
370 ahci_test_pmcap(ahci, offset);
371 break;
372 case PCI_CAP_ID_MSI:
373 ahci_test_msicap(ahci, offset);
374 break;
375 case PCI_CAP_ID_SATA:
376 ahci_test_satacap(ahci, offset);
377 break;
378
379 default:
380 g_test_message("Unknown CAP 0x%02x", cid);
381 }
382
383 if (next) {
384 ahci_test_pci_caps(ahci, qpci_config_readw(ahci->dev, next), next);
385 }
386 }
387
388 /**
389 * Test SATA PCI capabilitity for AHCI specification adherence.
390 */
391 static void ahci_test_satacap(AHCIQState *ahci, uint8_t offset)
392 {
393 uint16_t dataw;
394 uint32_t datal;
395
396 g_test_message("Verifying SATACAP");
397
398 /* Assert that the SATACAP version is 1.0, And reserved bits are empty. */
399 dataw = qpci_config_readw(ahci->dev, offset + 2);
400 g_assert_cmphex(dataw, ==, 0x10);
401
402 /* Grab the SATACR1 register. */
403 datal = qpci_config_readw(ahci->dev, offset + 4);
404
405 switch (datal & 0x0F) {
406 case 0x04: /* BAR0 */
407 case 0x05: /* BAR1 */
408 case 0x06:
409 case 0x07:
410 case 0x08:
411 case 0x09: /* BAR5 */
412 case 0x0F: /* Immediately following SATACR1 in PCI config space. */
413 break;
414 default:
415 /* Invalid BARLOC for the Index Data Pair. */
416 g_assert_not_reached();
417 }
418
419 /* Reserved. */
420 g_assert_cmphex((datal >> 24), ==, 0x00);
421 }
422
423 /**
424 * Test MSI PCI capability for AHCI specification adherence.
425 */
426 static void ahci_test_msicap(AHCIQState *ahci, uint8_t offset)
427 {
428 uint16_t dataw;
429 uint32_t datal;
430
431 g_test_message("Verifying MSICAP");
432
433 dataw = qpci_config_readw(ahci->dev, offset + PCI_MSI_FLAGS);
434 ASSERT_BIT_CLEAR(dataw, PCI_MSI_FLAGS_ENABLE);
435 ASSERT_BIT_CLEAR(dataw, PCI_MSI_FLAGS_QSIZE);
436 ASSERT_BIT_CLEAR(dataw, PCI_MSI_FLAGS_RESERVED);
437
438 datal = qpci_config_readl(ahci->dev, offset + PCI_MSI_ADDRESS_LO);
439 g_assert_cmphex(datal, ==, 0);
440
441 if (dataw & PCI_MSI_FLAGS_64BIT) {
442 g_test_message("MSICAP is 64bit");
443 datal = qpci_config_readl(ahci->dev, offset + PCI_MSI_ADDRESS_HI);
444 g_assert_cmphex(datal, ==, 0);
445 dataw = qpci_config_readw(ahci->dev, offset + PCI_MSI_DATA_64);
446 g_assert_cmphex(dataw, ==, 0);
447 } else {
448 g_test_message("MSICAP is 32bit");
449 dataw = qpci_config_readw(ahci->dev, offset + PCI_MSI_DATA_32);
450 g_assert_cmphex(dataw, ==, 0);
451 }
452 }
453
454 /**
455 * Test Power Management PCI capability for AHCI specification adherence.
456 */
457 static void ahci_test_pmcap(AHCIQState *ahci, uint8_t offset)
458 {
459 uint16_t dataw;
460
461 g_test_message("Verifying PMCAP");
462
463 dataw = qpci_config_readw(ahci->dev, offset + PCI_PM_PMC);
464 ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_PME_CLOCK);
465 ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_RESERVED);
466 ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_D1);
467 ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_D2);
468
469 dataw = qpci_config_readw(ahci->dev, offset + PCI_PM_CTRL);
470 ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_STATE_MASK);
471 ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_RESERVED);
472 ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_DATA_SEL_MASK);
473 ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_DATA_SCALE_MASK);
474 }
475
476 static void ahci_test_hba_spec(AHCIQState *ahci)
477 {
478 unsigned i;
479 uint32_t reg;
480 uint32_t ports;
481 uint8_t nports_impl;
482 uint8_t maxports;
483
484 g_assert(ahci != NULL);
485
486 /*
487 * Note that the AHCI spec does expect the BIOS to set up a few things:
488 * CAP.SSS - Support for staggered spin-up (t/f)
489 * CAP.SMPS - Support for mechanical presence switches (t/f)
490 * PI - Ports Implemented (1-32)
491 * PxCMD.HPCP - Hot Plug Capable Port
492 * PxCMD.MPSP - Mechanical Presence Switch Present
493 * PxCMD.CPD - Cold Presence Detection support
494 *
495 * Additional items are touched if CAP.SSS is on, see AHCI 10.1.1 p.97:
496 * Foreach Port Implemented:
497 * -PxCMD.ST, PxCMD.CR, PxCMD.FRE, PxCMD.FR, PxSCTL.DET are 0
498 * -PxCLB/U and PxFB/U are set to valid regions in memory
499 * -PxSUD is set to 1.
500 * -PxSSTS.DET is polled for presence; if detected, we continue:
501 * -PxSERR is cleared with 1's.
502 * -If PxTFD.STS.BSY, PxTFD.STS.DRQ, and PxTFD.STS.ERR are all zero,
503 * the device is ready.
504 */
505
506 /* 1 CAP - Capabilities Register */
507 ahci->cap = ahci_rreg(ahci, AHCI_CAP);
508 ASSERT_BIT_CLEAR(ahci->cap, AHCI_CAP_RESERVED);
509
510 /* 2 GHC - Global Host Control */
511 reg = ahci_rreg(ahci, AHCI_GHC);
512 ASSERT_BIT_CLEAR(reg, AHCI_GHC_HR);
513 ASSERT_BIT_CLEAR(reg, AHCI_GHC_IE);
514 ASSERT_BIT_CLEAR(reg, AHCI_GHC_MRSM);
515 if (BITSET(ahci->cap, AHCI_CAP_SAM)) {
516 g_test_message("Supports AHCI-Only Mode: GHC_AE is Read-Only.");
517 ASSERT_BIT_SET(reg, AHCI_GHC_AE);
518 } else {
519 g_test_message("Supports AHCI/Legacy mix.");
520 ASSERT_BIT_CLEAR(reg, AHCI_GHC_AE);
521 }
522
523 /* 3 IS - Interrupt Status */
524 reg = ahci_rreg(ahci, AHCI_IS);
525 g_assert_cmphex(reg, ==, 0);
526
527 /* 4 PI - Ports Implemented */
528 ports = ahci_rreg(ahci, AHCI_PI);
529 /* Ports Implemented must be non-zero. */
530 g_assert_cmphex(ports, !=, 0);
531 /* Ports Implemented must be <= Number of Ports. */
532 nports_impl = ctpopl(ports);
533 g_assert_cmpuint(((AHCI_CAP_NP & ahci->cap) + 1), >=, nports_impl);
534
535 /* Ports must be within the proper range. Given a mapping of SIZE,
536 * 256 bytes are used for global HBA control, and the rest is used
537 * for ports data, at 0x80 bytes each. */
538 g_assert_cmphex(ahci->barsize, >, 0);
539 maxports = (ahci->barsize - HBA_DATA_REGION_SIZE) / HBA_PORT_DATA_SIZE;
540 /* e.g, 30 ports for 4K of memory. (4096 - 256) / 128 = 30 */
541 g_assert_cmphex((reg >> maxports), ==, 0);
542
543 /* 5 AHCI Version */
544 reg = ahci_rreg(ahci, AHCI_VS);
545 switch (reg) {
546 case AHCI_VERSION_0_95:
547 case AHCI_VERSION_1_0:
548 case AHCI_VERSION_1_1:
549 case AHCI_VERSION_1_2:
550 case AHCI_VERSION_1_3:
551 break;
552 default:
553 g_assert_not_reached();
554 }
555
556 /* 6 Command Completion Coalescing Control: depends on CAP.CCCS. */
557 reg = ahci_rreg(ahci, AHCI_CCCCTL);
558 if (BITSET(ahci->cap, AHCI_CAP_CCCS)) {
559 ASSERT_BIT_CLEAR(reg, AHCI_CCCCTL_EN);
560 ASSERT_BIT_CLEAR(reg, AHCI_CCCCTL_RESERVED);
561 ASSERT_BIT_SET(reg, AHCI_CCCCTL_CC);
562 ASSERT_BIT_SET(reg, AHCI_CCCCTL_TV);
563 } else {
564 g_assert_cmphex(reg, ==, 0);
565 }
566
567 /* 7 CCC_PORTS */
568 reg = ahci_rreg(ahci, AHCI_CCCPORTS);
569 /* Must be zeroes initially regardless of CAP.CCCS */
570 g_assert_cmphex(reg, ==, 0);
571
572 /* 8 EM_LOC */
573 reg = ahci_rreg(ahci, AHCI_EMLOC);
574 if (BITCLR(ahci->cap, AHCI_CAP_EMS)) {
575 g_assert_cmphex(reg, ==, 0);
576 }
577
578 /* 9 EM_CTL */
579 reg = ahci_rreg(ahci, AHCI_EMCTL);
580 if (BITSET(ahci->cap, AHCI_CAP_EMS)) {
581 ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_STSMR);
582 ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_CTLTM);
583 ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_CTLRST);
584 ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_RESERVED);
585 } else {
586 g_assert_cmphex(reg, ==, 0);
587 }
588
589 /* 10 CAP2 -- Capabilities Extended */
590 ahci->cap2 = ahci_rreg(ahci, AHCI_CAP2);
591 ASSERT_BIT_CLEAR(ahci->cap2, AHCI_CAP2_RESERVED);
592
593 /* 11 BOHC -- Bios/OS Handoff Control */
594 reg = ahci_rreg(ahci, AHCI_BOHC);
595 g_assert_cmphex(reg, ==, 0);
596
597 /* 12 -- 23: Reserved */
598 g_test_message("Verifying HBA reserved area is empty.");
599 for (i = AHCI_RESERVED; i < AHCI_NVMHCI; ++i) {
600 reg = ahci_rreg(ahci, i);
601 g_assert_cmphex(reg, ==, 0);
602 }
603
604 /* 24 -- 39: NVMHCI */
605 if (BITCLR(ahci->cap2, AHCI_CAP2_NVMP)) {
606 g_test_message("Verifying HBA/NVMHCI area is empty.");
607 for (i = AHCI_NVMHCI; i < AHCI_VENDOR; ++i) {
608 reg = ahci_rreg(ahci, i);
609 g_assert_cmphex(reg, ==, 0);
610 }
611 }
612
613 /* 40 -- 63: Vendor */
614 g_test_message("Verifying HBA/Vendor area is empty.");
615 for (i = AHCI_VENDOR; i < AHCI_PORTS; ++i) {
616 reg = ahci_rreg(ahci, i);
617 g_assert_cmphex(reg, ==, 0);
618 }
619
620 /* 64 -- XX: Port Space */
621 for (i = 0; ports || (i < maxports); ports >>= 1, ++i) {
622 if (BITSET(ports, 0x1)) {
623 g_test_message("Testing port %u for spec", i);
624 ahci_test_port_spec(ahci, i);
625 } else {
626 uint16_t j;
627 uint16_t low = AHCI_PORTS + (32 * i);
628 uint16_t high = AHCI_PORTS + (32 * (i + 1));
629 g_test_message("Asserting unimplemented port %u "
630 "(reg [%u-%u]) is empty.",
631 i, low, high - 1);
632 for (j = low; j < high; ++j) {
633 reg = ahci_rreg(ahci, j);
634 g_assert_cmphex(reg, ==, 0);
635 }
636 }
637 }
638 }
639
640 /**
641 * Test the memory space for one port for specification adherence.
642 */
643 static void ahci_test_port_spec(AHCIQState *ahci, uint8_t port)
644 {
645 uint32_t reg;
646 unsigned i;
647
648 /* (0) CLB */
649 reg = ahci_px_rreg(ahci, port, AHCI_PX_CLB);
650 ASSERT_BIT_CLEAR(reg, AHCI_PX_CLB_RESERVED);
651
652 /* (1) CLBU */
653 if (BITCLR(ahci->cap, AHCI_CAP_S64A)) {
654 reg = ahci_px_rreg(ahci, port, AHCI_PX_CLBU);
655 g_assert_cmphex(reg, ==, 0);
656 }
657
658 /* (2) FB */
659 reg = ahci_px_rreg(ahci, port, AHCI_PX_FB);
660 ASSERT_BIT_CLEAR(reg, AHCI_PX_FB_RESERVED);
661
662 /* (3) FBU */
663 if (BITCLR(ahci->cap, AHCI_CAP_S64A)) {
664 reg = ahci_px_rreg(ahci, port, AHCI_PX_FBU);
665 g_assert_cmphex(reg, ==, 0);
666 }
667
668 /* (4) IS */
669 reg = ahci_px_rreg(ahci, port, AHCI_PX_IS);
670 g_assert_cmphex(reg, ==, 0);
671
672 /* (5) IE */
673 reg = ahci_px_rreg(ahci, port, AHCI_PX_IE);
674 g_assert_cmphex(reg, ==, 0);
675
676 /* (6) CMD */
677 reg = ahci_px_rreg(ahci, port, AHCI_PX_CMD);
678 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_FRE);
679 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_RESERVED);
680 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_CCS);
681 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_FR);
682 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_CR);
683 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_PMA); /* And RW only if CAP.SPM */
684 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_APSTE); /* RW only if CAP2.APST */
685 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ATAPI);
686 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_DLAE);
687 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ALPE); /* RW only if CAP.SALP */
688 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ASP); /* RW only if CAP.SALP */
689 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ICC);
690 /* If CPDetect support does not exist, CPState must be off. */
691 if (BITCLR(reg, AHCI_PX_CMD_CPD)) {
692 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_CPS);
693 }
694 /* If MPSPresence is not set, MPSState must be off. */
695 if (BITCLR(reg, AHCI_PX_CMD_MPSP)) {
696 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_MPSS);
697 }
698 /* If we do not support MPS, MPSS and MPSP must be off. */
699 if (BITCLR(ahci->cap, AHCI_CAP_SMPS)) {
700 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_MPSS);
701 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_MPSP);
702 }
703 /* If, via CPD or MPSP we detect a drive, HPCP must be on. */
704 if (BITANY(reg, AHCI_PX_CMD_CPD | AHCI_PX_CMD_MPSP)) {
705 ASSERT_BIT_SET(reg, AHCI_PX_CMD_HPCP);
706 }
707 /* HPCP and ESP cannot both be active. */
708 g_assert(!BITSET(reg, AHCI_PX_CMD_HPCP | AHCI_PX_CMD_ESP));
709 /* If CAP.FBSS is not set, FBSCP must not be set. */
710 if (BITCLR(ahci->cap, AHCI_CAP_FBSS)) {
711 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_FBSCP);
712 }
713
714 /* (7) RESERVED */
715 reg = ahci_px_rreg(ahci, port, AHCI_PX_RES1);
716 g_assert_cmphex(reg, ==, 0);
717
718 /* (8) TFD */
719 reg = ahci_px_rreg(ahci, port, AHCI_PX_TFD);
720 /* At boot, prior to an FIS being received, the TFD register should be 0x7F,
721 * which breaks down as follows, as seen in AHCI 1.3 sec 3.3.8, p. 27. */
722 ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_ERR);
723 ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_CS1);
724 ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_DRQ);
725 ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_CS2);
726 ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_STS_BSY);
727 ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_ERR);
728 ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_RESERVED);
729
730 /* (9) SIG */
731 /* Though AHCI specifies the boot value should be 0xFFFFFFFF,
732 * Even when GHC.ST is zero, the AHCI HBA may receive the initial
733 * D2H register FIS and update the signature asynchronously,
734 * so we cannot expect a value here. AHCI 1.3, sec 3.3.9, pp 27-28 */
735
736 /* (10) SSTS / SCR0: SStatus */
737 reg = ahci_px_rreg(ahci, port, AHCI_PX_SSTS);
738 ASSERT_BIT_CLEAR(reg, AHCI_PX_SSTS_RESERVED);
739 /* Even though the register should be 0 at boot, it is asynchronous and
740 * prone to change, so we cannot test any well known value. */
741
742 /* (11) SCTL / SCR2: SControl */
743 reg = ahci_px_rreg(ahci, port, AHCI_PX_SCTL);
744 g_assert_cmphex(reg, ==, 0);
745
746 /* (12) SERR / SCR1: SError */
747 reg = ahci_px_rreg(ahci, port, AHCI_PX_SERR);
748 g_assert_cmphex(reg, ==, 0);
749
750 /* (13) SACT / SCR3: SActive */
751 reg = ahci_px_rreg(ahci, port, AHCI_PX_SACT);
752 g_assert_cmphex(reg, ==, 0);
753
754 /* (14) CI */
755 reg = ahci_px_rreg(ahci, port, AHCI_PX_CI);
756 g_assert_cmphex(reg, ==, 0);
757
758 /* (15) SNTF */
759 reg = ahci_px_rreg(ahci, port, AHCI_PX_SNTF);
760 g_assert_cmphex(reg, ==, 0);
761
762 /* (16) FBS */
763 reg = ahci_px_rreg(ahci, port, AHCI_PX_FBS);
764 ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_EN);
765 ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_DEC);
766 ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_SDE);
767 ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_DEV);
768 ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_DWE);
769 ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_RESERVED);
770 if (BITSET(ahci->cap, AHCI_CAP_FBSS)) {
771 /* if Port-Multiplier FIS-based switching avail, ADO must >= 2 */
772 g_assert((reg & AHCI_PX_FBS_ADO) >> ctzl(AHCI_PX_FBS_ADO) >= 2);
773 }
774
775 /* [17 -- 27] RESERVED */
776 for (i = AHCI_PX_RES2; i < AHCI_PX_VS; ++i) {
777 reg = ahci_px_rreg(ahci, port, i);
778 g_assert_cmphex(reg, ==, 0);
779 }
780
781 /* [28 -- 31] Vendor-Specific */
782 for (i = AHCI_PX_VS; i < 32; ++i) {
783 reg = ahci_px_rreg(ahci, port, i);
784 if (reg) {
785 g_test_message("INFO: Vendor register %u non-empty", i);
786 }
787 }
788 }
789
790 /**
791 * Utilizing an initialized AHCI HBA, issue an IDENTIFY command to the first
792 * device we see, then read and check the response.
793 */
794 static void ahci_test_identify(AHCIQState *ahci)
795 {
796 uint16_t buff[256];
797 unsigned px;
798 int rc;
799 uint16_t sect_size;
800 const size_t buffsize = 512;
801
802 g_assert(ahci != NULL);
803
804 /**
805 * This serves as a bit of a tutorial on AHCI device programming:
806 *
807 * (1) Create a data buffer for the IDENTIFY response to be sent to
808 * (2) Create a Command Table buffer, where we will store the
809 * command and PRDT (Physical Region Descriptor Table)
810 * (3) Construct an FIS host-to-device command structure, and write it to
811 * the top of the Command Table buffer.
812 * (4) Create one or more Physical Region Descriptors (PRDs) that describe
813 * a location in memory where data may be stored/retrieved.
814 * (5) Write these PRDTs to the bottom (offset 0x80) of the Command Table.
815 * (6) Each AHCI port has up to 32 command slots. Each slot contains a
816 * header that points to a Command Table buffer. Pick an unused slot
817 * and update it to point to the Command Table we have built.
818 * (7) Now: Command #n points to our Command Table, and our Command Table
819 * contains the FIS (that describes our command) and the PRDTL, which
820 * describes our buffer.
821 * (8) We inform the HBA via PxCI (Command Issue) that the command in slot
822 * #n is ready for processing.
823 */
824
825 /* Pick the first implemented and running port */
826 px = ahci_port_select(ahci);
827 g_test_message("Selected port %u for test", px);
828
829 /* Clear out the FIS Receive area and any pending interrupts. */
830 ahci_port_clear(ahci, px);
831
832 /* "Read" 512 bytes using CMD_IDENTIFY into the host buffer. */
833 ahci_io(ahci, px, CMD_IDENTIFY, &buff, buffsize, 0);
834
835 /* Check serial number/version in the buffer */
836 /* NB: IDENTIFY strings are packed in 16bit little endian chunks.
837 * Since we copy byte-for-byte in ahci-test, on both LE and BE, we need to
838 * unchunk this data. By contrast, ide-test copies 2 bytes at a time, and
839 * as a consequence, only needs to unchunk the data on LE machines. */
840 string_bswap16(&buff[10], 20);
841 rc = memcmp(&buff[10], "testdisk ", 20);
842 g_assert_cmphex(rc, ==, 0);
843
844 string_bswap16(&buff[23], 8);
845 rc = memcmp(&buff[23], "version ", 8);
846 g_assert_cmphex(rc, ==, 0);
847
848 sect_size = le16_to_cpu(*((uint16_t *)(&buff[5])));
849 g_assert_cmphex(sect_size, ==, AHCI_SECTOR_SIZE);
850 }
851
852 static void ahci_test_io_rw_simple(AHCIQState *ahci, unsigned bufsize,
853 uint64_t sector, uint8_t read_cmd,
854 uint8_t write_cmd)
855 {
856 uint64_t ptr;
857 uint8_t port;
858 unsigned char *tx = g_malloc(bufsize);
859 unsigned char *rx = g_malloc0(bufsize);
860
861 g_assert(ahci != NULL);
862
863 /* Pick the first running port and clear it. */
864 port = ahci_port_select(ahci);
865 ahci_port_clear(ahci, port);
866
867 /*** Create pattern and transfer to guest ***/
868 /* Data buffer in the guest */
869 ptr = ahci_alloc(ahci, bufsize);
870 g_assert(ptr);
871
872 /* Write some indicative pattern to our buffer. */
873 generate_pattern(tx, bufsize, AHCI_SECTOR_SIZE);
874 qtest_bufwrite(ahci->parent->qts, ptr, tx, bufsize);
875
876 /* Write this buffer to disk, then read it back to the DMA buffer. */
877 ahci_guest_io(ahci, port, write_cmd, ptr, bufsize, sector);
878 qtest_memset(ahci->parent->qts, ptr, 0x00, bufsize);
879 ahci_guest_io(ahci, port, read_cmd, ptr, bufsize, sector);
880
881 /*** Read back the Data ***/
882 qtest_bufread(ahci->parent->qts, ptr, rx, bufsize);
883 g_assert_cmphex(memcmp(tx, rx, bufsize), ==, 0);
884
885 ahci_free(ahci, ptr);
886 g_free(tx);
887 g_free(rx);
888 }
889
890 static uint8_t ahci_test_nondata(AHCIQState *ahci, uint8_t ide_cmd)
891 {
892 uint8_t port;
893
894 /* Sanitize */
895 port = ahci_port_select(ahci);
896 ahci_port_clear(ahci, port);
897
898 ahci_io(ahci, port, ide_cmd, NULL, 0, 0);
899
900 return port;
901 }
902
903 static void ahci_test_flush(AHCIQState *ahci)
904 {
905 ahci_test_nondata(ahci, CMD_FLUSH_CACHE);
906 }
907
908 static void ahci_test_specify(AHCIQState *ahci, uint16_t sectors,
909 bool supported)
910 {
911 AHCICommand *cmd;
912 uint8_t port;
913
914 port = ahci_port_select(ahci);
915 ahci_port_clear(ahci, port);
916
917 cmd = ahci_command_create(CMD_INIT_DP);
918 ahci_command_set_count(cmd, sectors);
919 if (!supported) {
920 ahci_command_expect_error(cmd, ATA_ERR_ABRT);
921 }
922 ahci_command_commit(ahci, cmd, port);
923 ahci_command_issue(ahci, cmd);
924 if (!supported) {
925 ASSERT_BIT_SET(ahci_px_rreg(ahci, port, AHCI_PX_TFD),
926 AHCI_PX_TFD_STS_ERR);
927 }
928 ahci_command_verify(ahci, cmd);
929 ahci_command_free(cmd);
930 }
931
932 static void ahci_test_max(AHCIQState *ahci)
933 {
934 RegD2HFIS *d2h = g_malloc0(0x20);
935 uint64_t nsect;
936 uint8_t port;
937 uint8_t cmd;
938 uint64_t config_sect = mb_to_sectors(test_image_size_mb) - 1;
939
940 if (config_sect > 0xFFFFFF) {
941 cmd = CMD_READ_MAX_EXT;
942 } else {
943 cmd = CMD_READ_MAX;
944 }
945
946 port = ahci_test_nondata(ahci, cmd);
947 qtest_memread(ahci->parent->qts, ahci->port[port].fb + 0x40, d2h, 0x20);
948 nsect = (uint64_t)d2h->lba_hi[2] << 40 |
949 (uint64_t)d2h->lba_hi[1] << 32 |
950 (uint64_t)d2h->lba_hi[0] << 24 |
951 (uint64_t)d2h->lba_lo[2] << 16 |
952 (uint64_t)d2h->lba_lo[1] << 8 |
953 (uint64_t)d2h->lba_lo[0];
954
955 g_assert_cmphex(nsect, ==, config_sect);
956 g_free(d2h);
957 }
958
959
960 /******************************************************************************/
961 /* Test Interfaces */
962 /******************************************************************************/
963
964 /**
965 * Basic sanity test to boot a machine, find an AHCI device, and shutdown.
966 */
967 static void test_sanity(void)
968 {
969 AHCIQState *ahci;
970 ahci = ahci_boot(NULL);
971 ahci_shutdown(ahci);
972 }
973
974 /**
975 * Ensure that the PCI configuration space for the AHCI device is in-line with
976 * the AHCI 1.3 specification for initial values.
977 */
978 static void test_pci_spec(void)
979 {
980 AHCIQState *ahci;
981 ahci = ahci_boot(NULL);
982 ahci_test_pci_spec(ahci);
983 ahci_shutdown(ahci);
984 }
985
986 /**
987 * Engage the PCI AHCI device and sanity check the response.
988 * Perform additional PCI config space bringup for the HBA.
989 */
990 static void test_pci_enable(void)
991 {
992 AHCIQState *ahci;
993 ahci = ahci_boot(NULL);
994 ahci_pci_enable(ahci);
995 ahci_shutdown(ahci);
996 }
997
998 /**
999 * Investigate the memory mapped regions of the HBA,
1000 * and test them for AHCI specification adherence.
1001 */
1002 static void test_hba_spec(void)
1003 {
1004 AHCIQState *ahci;
1005
1006 ahci = ahci_boot(NULL);
1007 ahci_pci_enable(ahci);
1008 ahci_test_hba_spec(ahci);
1009 ahci_shutdown(ahci);
1010 }
1011
1012 /**
1013 * Engage the HBA functionality of the AHCI PCI device,
1014 * and bring it into a functional idle state.
1015 */
1016 static void test_hba_enable(void)
1017 {
1018 AHCIQState *ahci;
1019
1020 ahci = ahci_boot(NULL);
1021 ahci_pci_enable(ahci);
1022 ahci_hba_enable(ahci);
1023 ahci_shutdown(ahci);
1024 }
1025
1026 /**
1027 * Bring up the device and issue an IDENTIFY command.
1028 * Inspect the state of the HBA device and the data returned.
1029 */
1030 static void test_identify(void)
1031 {
1032 AHCIQState *ahci;
1033
1034 ahci = ahci_boot_and_enable(NULL);
1035 ahci_test_identify(ahci);
1036 ahci_shutdown(ahci);
1037 }
1038
1039 static void test_specify(void)
1040 {
1041 AHCIQState *ahci;
1042
1043 ahci = ahci_boot_and_enable(NULL);
1044
1045 /* A register FIS carries 16 bits of count, the legacy ports only eight */
1046 ahci_test_specify(ahci, 0, false);
1047 ahci_test_specify(ahci, 256, false);
1048 ahci_test_specify(ahci, 0xffff, false);
1049 ahci_test_specify(ahci, 32, true);
1050
1051 ahci_shutdown(ahci);
1052 }
1053
1054 /**
1055 * Fragmented DMA test: Perform a standard 4K DMA read/write
1056 * test, but make sure the physical regions are fragmented to
1057 * be very small, each just 32 bytes, to see how AHCI performs
1058 * with chunks defined to be much less than a sector.
1059 */
1060 static void test_dma_fragmented(void)
1061 {
1062 AHCIQState *ahci;
1063 AHCICommand *cmd;
1064 uint8_t px;
1065 size_t bufsize = 4096;
1066 unsigned char *tx = g_malloc(bufsize);
1067 unsigned char *rx = g_malloc0(bufsize);
1068 uint64_t ptr;
1069
1070 ahci = ahci_boot_and_enable(NULL);
1071 px = ahci_port_select(ahci);
1072 ahci_port_clear(ahci, px);
1073
1074 /* create pattern */
1075 generate_pattern(tx, bufsize, AHCI_SECTOR_SIZE);
1076
1077 /* Create a DMA buffer in guest memory, and write our pattern to it. */
1078 ptr = guest_alloc(&ahci->parent->alloc, bufsize);
1079 g_assert(ptr);
1080 qtest_bufwrite(ahci->parent->qts, ptr, tx, bufsize);
1081
1082 cmd = ahci_command_create(CMD_WRITE_DMA);
1083 ahci_command_adjust(cmd, 0, ptr, bufsize, 32);
1084 ahci_command_commit(ahci, cmd, px);
1085 ahci_command_issue(ahci, cmd);
1086 ahci_command_verify(ahci, cmd);
1087 ahci_command_free(cmd);
1088
1089 cmd = ahci_command_create(CMD_READ_DMA);
1090 ahci_command_adjust(cmd, 0, ptr, bufsize, 32);
1091 ahci_command_commit(ahci, cmd, px);
1092 ahci_command_issue(ahci, cmd);
1093 ahci_command_verify(ahci, cmd);
1094 ahci_command_free(cmd);
1095
1096 /* Read back the guest's receive buffer into local memory */
1097 qtest_bufread(ahci->parent->qts, ptr, rx, bufsize);
1098 guest_free(&ahci->parent->alloc, ptr);
1099
1100 g_assert_cmphex(memcmp(tx, rx, bufsize), ==, 0);
1101
1102 ahci_shutdown(ahci);
1103
1104 g_free(rx);
1105 g_free(tx);
1106 }
1107
1108 /*
1109 * Write sector 1 with random data to make AHCI storage dirty
1110 * Needed for flush tests so that flushes actually go though the block layer
1111 */
1112 static void make_dirty(AHCIQState* ahci, uint8_t port)
1113 {
1114 uint64_t ptr;
1115 unsigned bufsize = 512;
1116
1117 ptr = ahci_alloc(ahci, bufsize);
1118 g_assert(ptr);
1119
1120 ahci_guest_io(ahci, port, CMD_WRITE_DMA, ptr, bufsize, 1);
1121 ahci_free(ahci, ptr);
1122 }
1123
1124 static void test_flush(void)
1125 {
1126 AHCIQState *ahci;
1127 uint8_t port;
1128
1129 ahci = ahci_boot_and_enable(NULL);
1130
1131 port = ahci_port_select(ahci);
1132 ahci_port_clear(ahci, port);
1133
1134 make_dirty(ahci, port);
1135
1136 ahci_test_flush(ahci);
1137 ahci_shutdown(ahci);
1138 }
1139
1140 static void test_flush_retry(void)
1141 {
1142 AHCIQState *ahci;
1143 AHCICommand *cmd;
1144 uint8_t port;
1145
1146 prepare_blkdebug_script(debug_path, "flush_to_disk");
1147 ahci = ahci_boot_and_enable("-drive file=blkdebug:%s:%s,if=none,id=drive0,"
1148 "format=%s,cache=writeback,"
1149 "rerror=stop,werror=stop "
1150 "-M q35 "
1151 "-device ide-hd,drive=drive0 ",
1152 debug_path,
1153 tmp_path, imgfmt);
1154
1155 port = ahci_port_select(ahci);
1156 ahci_port_clear(ahci, port);
1157
1158 /* Issue write so that flush actually goes to disk */
1159 make_dirty(ahci, port);
1160
1161 /* Issue Flush Command and wait for error */
1162 cmd = ahci_guest_io_halt(ahci, port, CMD_FLUSH_CACHE, 0, 0, 0);
1163 ahci_guest_io_resume(ahci, cmd);
1164
1165 ahci_shutdown(ahci);
1166 }
1167
1168 /**
1169 * Basic sanity test to boot a machine, find an AHCI device, and shutdown.
1170 */
1171 static void test_migrate_sanity(void)
1172 {
1173 AHCIQState *src, *dst;
1174 char *uri = g_strdup_printf("unix:%s", mig_socket);
1175
1176 src = ahci_boot("-m 384 -M q35 "
1177 "-drive if=ide,file=%s,format=%s ", tmp_path, imgfmt);
1178 dst = ahci_boot("-m 384 -M q35 "
1179 "-drive if=ide,file=%s,format=%s "
1180 "-incoming %s", tmp_path, imgfmt, uri);
1181
1182 ahci_migrate(src, dst, uri);
1183
1184 ahci_shutdown(src);
1185 ahci_shutdown(dst);
1186 g_free(uri);
1187 }
1188
1189 /**
1190 * Simple migration test: Write a pattern, migrate, then read.
1191 */
1192 static void ahci_migrate_simple(uint8_t cmd_read, uint8_t cmd_write)
1193 {
1194 AHCIQState *src, *dst;
1195 uint8_t px;
1196 size_t bufsize = 4096;
1197 unsigned char *tx = g_malloc(bufsize);
1198 unsigned char *rx = g_malloc0(bufsize);
1199 char *uri = g_strdup_printf("unix:%s", mig_socket);
1200
1201 src = ahci_boot_and_enable("-m 384 -M q35 "
1202 "-drive if=ide,format=%s,file=%s ",
1203 imgfmt, tmp_path);
1204 dst = ahci_boot("-m 384 -M q35 "
1205 "-drive if=ide,format=%s,file=%s "
1206 "-incoming %s", imgfmt, tmp_path, uri);
1207
1208 /* initialize */
1209 px = ahci_port_select(src);
1210 ahci_port_clear(src, px);
1211
1212 /* create pattern */
1213 generate_pattern(tx, bufsize, AHCI_SECTOR_SIZE);
1214
1215 /* Write, migrate, then read. */
1216 ahci_io(src, px, cmd_write, tx, bufsize, 0);
1217 ahci_migrate(src, dst, uri);
1218 ahci_io(dst, px, cmd_read, rx, bufsize, 0);
1219
1220 /* Verify pattern */
1221 g_assert_cmphex(memcmp(tx, rx, bufsize), ==, 0);
1222
1223 ahci_shutdown(src);
1224 ahci_shutdown(dst);
1225 g_free(rx);
1226 g_free(tx);
1227 g_free(uri);
1228 }
1229
1230 static void test_migrate_dma(void)
1231 {
1232 ahci_migrate_simple(CMD_READ_DMA, CMD_WRITE_DMA);
1233 }
1234
1235 static void test_migrate_ncq(void)
1236 {
1237 ahci_migrate_simple(READ_FPDMA_QUEUED, WRITE_FPDMA_QUEUED);
1238 }
1239
1240 /**
1241 * Halted IO Error Test
1242 *
1243 * Simulate an error on first write, Try to write a pattern,
1244 * Confirm the VM has stopped, resume the VM, verify command
1245 * has completed, then read back the data and verify.
1246 */
1247 static void ahci_halted_io_test(uint8_t cmd_read, uint8_t cmd_write)
1248 {
1249 AHCIQState *ahci;
1250 uint8_t port;
1251 size_t bufsize = 4096;
1252 unsigned char *tx = g_malloc(bufsize);
1253 unsigned char *rx = g_malloc0(bufsize);
1254 uint64_t ptr;
1255 AHCICommand *cmd;
1256
1257 prepare_blkdebug_script(debug_path, "write_aio");
1258
1259 ahci = ahci_boot_and_enable("-drive file=blkdebug:%s:%s,if=none,id=drive0,"
1260 "format=%s,cache=writeback,"
1261 "rerror=stop,werror=stop "
1262 "-M q35 "
1263 "-device ide-hd,drive=drive0 ",
1264 debug_path,
1265 tmp_path, imgfmt);
1266
1267 /* Initialize and prepare */
1268 port = ahci_port_select(ahci);
1269 ahci_port_clear(ahci, port);
1270
1271 /* create DMA source buffer and write pattern */
1272 generate_pattern(tx, bufsize, AHCI_SECTOR_SIZE);
1273 ptr = ahci_alloc(ahci, bufsize);
1274 g_assert(ptr);
1275 qtest_memwrite(ahci->parent->qts, ptr, tx, bufsize);
1276
1277 /* Attempt to write (and fail) */
1278 cmd = ahci_guest_io_halt(ahci, port, cmd_write,
1279 ptr, bufsize, 0);
1280
1281 /* Attempt to resume the command */
1282 ahci_guest_io_resume(ahci, cmd);
1283 ahci_free(ahci, ptr);
1284
1285 /* Read back and verify */
1286 ahci_io(ahci, port, cmd_read, rx, bufsize, 0);
1287 g_assert_cmphex(memcmp(tx, rx, bufsize), ==, 0);
1288
1289 /* Cleanup and go home */
1290 ahci_shutdown(ahci);
1291 g_free(rx);
1292 g_free(tx);
1293 }
1294
1295 static void test_halted_dma(void)
1296 {
1297 ahci_halted_io_test(CMD_READ_DMA, CMD_WRITE_DMA);
1298 }
1299
1300 static void test_halted_ncq(void)
1301 {
1302 ahci_halted_io_test(READ_FPDMA_QUEUED, WRITE_FPDMA_QUEUED);
1303 }
1304
1305 /**
1306 * IO Error Migration Test
1307 *
1308 * Simulate an error on first write, Try to write a pattern,
1309 * Confirm the VM has stopped, migrate, resume the VM,
1310 * verify command has completed, then read back the data and verify.
1311 */
1312 static void ahci_migrate_halted_io(uint8_t cmd_read, uint8_t cmd_write)
1313 {
1314 AHCIQState *src, *dst;
1315 uint8_t port;
1316 size_t bufsize = 4096;
1317 unsigned char *tx = g_malloc(bufsize);
1318 unsigned char *rx = g_malloc0(bufsize);
1319 uint64_t ptr;
1320 AHCICommand *cmd;
1321 char *uri = g_strdup_printf("unix:%s", mig_socket);
1322
1323 prepare_blkdebug_script(debug_path, "write_aio");
1324
1325 src = ahci_boot_and_enable("-drive file=blkdebug:%s:%s,if=none,id=drive0,"
1326 "format=%s,cache=writeback,"
1327 "rerror=stop,werror=stop "
1328 "-M q35 "
1329 "-device ide-hd,drive=drive0 ",
1330 debug_path,
1331 tmp_path, imgfmt);
1332
1333 dst = ahci_boot("-drive file=%s,if=none,id=drive0,"
1334 "format=%s,cache=writeback,"
1335 "rerror=stop,werror=stop "
1336 "-M q35 "
1337 "-device ide-hd,drive=drive0 "
1338 "-incoming %s",
1339 tmp_path, imgfmt, uri);
1340
1341 /* Initialize and prepare */
1342 port = ahci_port_select(src);
1343 ahci_port_clear(src, port);
1344 generate_pattern(tx, bufsize, AHCI_SECTOR_SIZE);
1345
1346 /* create DMA source buffer and write pattern */
1347 ptr = ahci_alloc(src, bufsize);
1348 g_assert(ptr);
1349 qtest_memwrite(src->parent->qts, ptr, tx, bufsize);
1350
1351 /* Write, trigger the VM to stop, migrate, then resume. */
1352 cmd = ahci_guest_io_halt(src, port, cmd_write,
1353 ptr, bufsize, 0);
1354 ahci_migrate(src, dst, uri);
1355 ahci_guest_io_resume(dst, cmd);
1356 ahci_free(dst, ptr);
1357
1358 /* Read back */
1359 ahci_io(dst, port, cmd_read, rx, bufsize, 0);
1360
1361 /* Verify TX and RX are identical */
1362 g_assert_cmphex(memcmp(tx, rx, bufsize), ==, 0);
1363
1364 /* Cleanup and go home. */
1365 ahci_shutdown(src);
1366 ahci_shutdown(dst);
1367 g_free(rx);
1368 g_free(tx);
1369 g_free(uri);
1370 }
1371
1372 static void test_migrate_halted_dma(void)
1373 {
1374 ahci_migrate_halted_io(CMD_READ_DMA, CMD_WRITE_DMA);
1375 }
1376
1377 static void test_migrate_halted_ncq(void)
1378 {
1379 ahci_migrate_halted_io(READ_FPDMA_QUEUED, WRITE_FPDMA_QUEUED);
1380 }
1381
1382 /**
1383 * Migration test: Try to flush, migrate, then resume.
1384 */
1385 static void test_flush_migrate(void)
1386 {
1387 AHCIQState *src, *dst;
1388 AHCICommand *cmd;
1389 uint8_t px;
1390 char *uri = g_strdup_printf("unix:%s", mig_socket);
1391
1392 prepare_blkdebug_script(debug_path, "flush_to_disk");
1393
1394 src = ahci_boot_and_enable("-drive file=blkdebug:%s:%s,if=none,id=drive0,"
1395 "cache=writeback,rerror=stop,werror=stop,"
1396 "format=%s "
1397 "-M q35 "
1398 "-device ide-hd,drive=drive0 ",
1399 debug_path, tmp_path, imgfmt);
1400 dst = ahci_boot("-drive file=%s,if=none,id=drive0,"
1401 "cache=writeback,rerror=stop,werror=stop,"
1402 "format=%s "
1403 "-M q35 "
1404 "-device ide-hd,drive=drive0 "
1405 "-incoming %s", tmp_path, imgfmt, uri);
1406
1407 px = ahci_port_select(src);
1408 ahci_port_clear(src, px);
1409
1410 /* Dirty device so that flush reaches disk */
1411 make_dirty(src, px);
1412
1413 /* Issue Flush Command */
1414 cmd = ahci_command_create(CMD_FLUSH_CACHE);
1415 ahci_command_commit(src, cmd, px);
1416 ahci_command_issue_async(src, cmd);
1417 qtest_qmp_eventwait(src->parent->qts, "STOP");
1418
1419 /* Migrate over */
1420 ahci_migrate(src, dst, uri);
1421
1422 /* Complete the command */
1423 qtest_qmp_send(dst->parent->qts, "{'execute':'cont' }");
1424 qtest_qmp_eventwait(dst->parent->qts, "RESUME");
1425 ahci_command_wait(dst, cmd);
1426 ahci_command_verify(dst, cmd);
1427
1428 ahci_command_free(cmd);
1429 ahci_shutdown(src);
1430 ahci_shutdown(dst);
1431 g_free(uri);
1432 }
1433
1434 static void test_max(void)
1435 {
1436 AHCIQState *ahci;
1437
1438 ahci = ahci_boot_and_enable(NULL);
1439 ahci_test_max(ahci);
1440 ahci_shutdown(ahci);
1441 }
1442
1443 static void test_reset(void)
1444 {
1445 AHCIQState *ahci;
1446 int i;
1447
1448 ahci = ahci_boot(NULL);
1449 ahci_test_pci_spec(ahci);
1450 ahci_pci_enable(ahci);
1451
1452 for (i = 0; i < 2; i++) {
1453 ahci_test_hba_spec(ahci);
1454 ahci_hba_enable(ahci);
1455 ahci_test_identify(ahci);
1456 ahci_test_io_rw_simple(ahci, 4096, 0,
1457 CMD_READ_DMA_EXT,
1458 CMD_WRITE_DMA_EXT);
1459 ahci_set(ahci, AHCI_GHC, AHCI_GHC_HR);
1460 ahci_clean_mem(ahci);
1461 }
1462
1463 ahci_shutdown(ahci);
1464 }
1465
1466 static void test_reset_pending_callback(void)
1467 {
1468 AHCIQState *ahci;
1469 AHCICommand *cmd;
1470 uint8_t port;
1471 uint64_t ptr1;
1472 uint64_t ptr2;
1473
1474 int bufsize = 4 * 1024;
1475 int speed = bufsize + (bufsize / 2);
1476 int offset1 = 0;
1477 int offset2 = bufsize / AHCI_SECTOR_SIZE;
1478
1479 g_autofree unsigned char *tx1 = g_malloc(bufsize);
1480 g_autofree unsigned char *tx2 = g_malloc(bufsize);
1481 g_autofree unsigned char *rx1 = g_malloc0(bufsize);
1482 g_autofree unsigned char *rx2 = g_malloc0(bufsize);
1483
1484 /* Uses throttling to make test independent of specific environment. */
1485 ahci = ahci_boot_and_enable("-drive if=none,id=drive0,file=%s,"
1486 "cache=writeback,format=%s,"
1487 "throttling.bps-write=%d "
1488 "-M q35 "
1489 "-device ide-hd,drive=drive0 ",
1490 tmp_path, imgfmt, speed);
1491
1492 port = ahci_port_select(ahci);
1493 ahci_port_clear(ahci, port);
1494
1495 ptr1 = ahci_alloc(ahci, bufsize);
1496 ptr2 = ahci_alloc(ahci, bufsize);
1497
1498 g_assert(ptr1 && ptr2);
1499
1500 /* Need two different patterns. */
1501 do {
1502 generate_pattern(tx1, bufsize, AHCI_SECTOR_SIZE);
1503 generate_pattern(tx2, bufsize, AHCI_SECTOR_SIZE);
1504 } while (memcmp(tx1, tx2, bufsize) == 0);
1505
1506 qtest_bufwrite(ahci->parent->qts, ptr1, tx1, bufsize);
1507 qtest_bufwrite(ahci->parent->qts, ptr2, tx2, bufsize);
1508
1509 /* Write to beginning of disk to check it wasn't overwritten later. */
1510 ahci_guest_io(ahci, port, CMD_WRITE_DMA_EXT, ptr1, bufsize, offset1);
1511
1512 /* Issue asynchronously to get a pending callback during reset. */
1513 cmd = ahci_command_create(CMD_WRITE_DMA_EXT);
1514 ahci_command_adjust(cmd, offset2, ptr2, bufsize, 0);
1515 ahci_command_commit(ahci, cmd, port);
1516 ahci_command_issue_async(ahci, cmd);
1517
1518 ahci_set(ahci, AHCI_GHC, AHCI_GHC_HR);
1519
1520 ahci_command_free(cmd);
1521
1522 /* Wait for throttled write to finish. */
1523 sleep(1);
1524
1525 /* Start again. */
1526 ahci_clean_mem(ahci);
1527 ahci_pci_enable(ahci);
1528 ahci_hba_enable(ahci);
1529 port = ahci_port_select(ahci);
1530 ahci_port_clear(ahci, port);
1531
1532 /* Read and verify. */
1533 ahci_guest_io(ahci, port, CMD_READ_DMA_EXT, ptr1, bufsize, offset1);
1534 qtest_bufread(ahci->parent->qts, ptr1, rx1, bufsize);
1535 g_assert_cmphex(memcmp(tx1, rx1, bufsize), ==, 0);
1536
1537 ahci_guest_io(ahci, port, CMD_READ_DMA_EXT, ptr2, bufsize, offset2);
1538 qtest_bufread(ahci->parent->qts, ptr2, rx2, bufsize);
1539 g_assert_cmphex(memcmp(tx2, rx2, bufsize), ==, 0);
1540
1541 ahci_free(ahci, ptr1);
1542 ahci_free(ahci, ptr2);
1543
1544 ahci_clean_mem(ahci);
1545
1546 ahci_shutdown(ahci);
1547 }
1548
1549 static void test_ncq_simple(void)
1550 {
1551 AHCIQState *ahci;
1552
1553 ahci = ahci_boot_and_enable(NULL);
1554 ahci_test_io_rw_simple(ahci, 4096, 0,
1555 READ_FPDMA_QUEUED,
1556 WRITE_FPDMA_QUEUED);
1557 ahci_shutdown(ahci);
1558 }
1559
1560 static int prepare_iso(size_t size, unsigned char **buf, char **name)
1561 {
1562 g_autofree char *cdrom_path = NULL;
1563 unsigned char *patt;
1564 ssize_t ret;
1565 int fd = g_file_open_tmp("qtest.iso.XXXXXX", &cdrom_path, NULL);
1566
1567 g_assert(fd != -1);
1568 g_assert(buf);
1569 g_assert(name);
1570 patt = g_malloc(size);
1571
1572 /* Generate a pattern and build a CDROM image to read from */
1573 generate_pattern(patt, size, ATAPI_SECTOR_SIZE);
1574 ret = write(fd, patt, size);
1575 g_assert(ret == size);
1576
1577 *name = g_strdup(cdrom_path);
1578 *buf = patt;
1579 return fd;
1580 }
1581
1582 static void remove_iso(int fd, char *name)
1583 {
1584 unlink(name);
1585 g_free(name);
1586 close(fd);
1587 }
1588
1589 static int ahci_cb_cmp_buff(AHCIQState *ahci, AHCICommand *cmd,
1590 const AHCIOpts *opts)
1591 {
1592 unsigned char *tx = opts->opaque;
1593 unsigned char *rx;
1594
1595 if (!opts->size) {
1596 return 0;
1597 }
1598
1599 rx = g_malloc0(opts->size);
1600 qtest_bufread(ahci->parent->qts, opts->buffer, rx, opts->size);
1601 g_assert_cmphex(memcmp(tx, rx, opts->size), ==, 0);
1602 g_free(rx);
1603
1604 return 0;
1605 }
1606
1607 static int ahci_cb_cmp_raw(AHCIQState *ahci, AHCICommand *cmd,
1608 const AHCIOpts *opts)
1609 {
1610 unsigned char *tx = opts->opaque;
1611 unsigned char *rx;
1612 unsigned i, nsectors;
1613
1614 if (!opts->size) {
1615 return 0;
1616 }
1617
1618 nsectors = opts->size / ATAPI_RAW_SECTOR_SIZE;
1619 rx = g_malloc0(opts->size);
1620 qtest_bufread(ahci->parent->qts, opts->buffer, rx, opts->size);
1621 /* Each raw sector carries its 2048-byte payload past a 16-byte header. */
1622 for (i = 0; i < nsectors; i++) {
1623 g_assert_cmphex(memcmp(rx + i * ATAPI_RAW_SECTOR_SIZE + 16,
1624 tx + i * ATAPI_SECTOR_SIZE,
1625 ATAPI_SECTOR_SIZE), ==, 0);
1626 }
1627 g_free(rx);
1628
1629 return 0;
1630 }
1631
1632 static void ahci_test_cdrom(int nsectors, bool dma, uint8_t cmd,
1633 bool override_bcl, uint16_t bcl)
1634 {
1635 AHCIQState *ahci;
1636 unsigned char *tx;
1637 char *iso;
1638 int fd;
1639 AHCIOpts opts = {
1640 .size = ((uint64_t)ATAPI_SECTOR_SIZE * nsectors),
1641 .atapi = true,
1642 .atapi_dma = dma,
1643 .post_cb = ahci_cb_cmp_buff,
1644 .set_bcl = override_bcl,
1645 .bcl = bcl,
1646 };
1647 uint64_t iso_size = (uint64_t)ATAPI_SECTOR_SIZE * (nsectors + 1);
1648
1649 /* Prepare ISO and fill 'tx' buffer */
1650 fd = prepare_iso(iso_size, &tx, &iso);
1651 opts.opaque = tx;
1652
1653 /* Standard startup wonkery, but use ide-cd and our special iso file */
1654 ahci = ahci_boot_and_enable("-drive if=none,id=drive0,file=%s,format=raw "
1655 "-M q35 "
1656 "-device ide-cd,drive=drive0 ", iso);
1657
1658 /* Build & Send AHCI command */
1659 ahci_exec(ahci, ahci_port_select(ahci), cmd, &opts);
1660
1661 /* Cleanup */
1662 g_free(tx);
1663 ahci_shutdown(ahci);
1664 remove_iso(fd, iso);
1665 }
1666
1667 static void ahci_test_cdrom_read10(int nsectors, bool dma)
1668 {
1669 ahci_test_cdrom(nsectors, dma, CMD_ATAPI_READ_10, false, 0);
1670 }
1671
1672 static void test_cdrom_dma(void)
1673 {
1674 ahci_test_cdrom_read10(1, true);
1675 }
1676
1677 static void test_cdrom_dma_multi(void)
1678 {
1679 ahci_test_cdrom_read10(3, true);
1680 }
1681
1682 static void test_cdrom_pio(void)
1683 {
1684 ahci_test_cdrom_read10(1, false);
1685 }
1686
1687 static void test_cdrom_pio_multi(void)
1688 {
1689 ahci_test_cdrom_read10(3, false);
1690 }
1691
1692 static void ahci_test_cdrom_raw(int nsectors, bool dma)
1693 {
1694 AHCIQState *ahci;
1695 unsigned char *tx;
1696 char *iso;
1697 int fd;
1698 AHCIOpts opts = {
1699 .size = (uint64_t)ATAPI_RAW_SECTOR_SIZE * nsectors,
1700 .atapi = true,
1701 .atapi_dma = dma,
1702 .atapi_raw = true,
1703 .set_bcl = true,
1704 .bcl = ATAPI_RAW_SECTOR_SIZE, /* one raw sector per DRQ burst */
1705 .post_cb = ahci_cb_cmp_raw,
1706 };
1707 uint64_t iso_size = (uint64_t)ATAPI_SECTOR_SIZE * (nsectors + 1);
1708
1709 fd = prepare_iso(iso_size, &tx, &iso);
1710 opts.opaque = tx;
1711
1712 ahci = ahci_boot_and_enable("-drive if=none,id=drive0,file=%s,format=raw "
1713 "-M q35 "
1714 "-device ide-cd,drive=drive0 ", iso);
1715
1716 ahci_exec(ahci, ahci_port_select(ahci), CMD_ATAPI_READ_CD, &opts);
1717
1718 g_free(tx);
1719 ahci_shutdown(ahci);
1720 remove_iso(fd, iso);
1721 }
1722
1723 static void test_cdrom_dma_raw(void)
1724 {
1725 ahci_test_cdrom_raw(3, true);
1726 }
1727
1728 static void test_cdrom_pio_raw(void)
1729 {
1730 ahci_test_cdrom_raw(3, false);
1731 }
1732
1733 /*
1734 * Regression test: a buffered ATAPI read completing after a command
1735 * engine restart must not dereference the cleared cur_cmd. Cover both
1736 * PIO and DMA; the DMA variant is the reliable guard.
1737 */
1738 static void test_atapi_engine_restart_in_flight(bool dma)
1739 {
1740 AHCIQState *ahci;
1741 AHCICommand *cmd;
1742 unsigned char *tx;
1743 char *iso;
1744 int fd;
1745 uint8_t port;
1746 uint64_t buffer;
1747 uint64_t iso_size = (uint64_t)ATAPI_SECTOR_SIZE * 2;
1748
1749 fd = prepare_iso(iso_size, &tx, &iso);
1750
1751 ahci = ahci_boot_and_enable("-drive if=none,id=drive0,"
1752 "file=blkdebug::%s,format=raw,readonly=on "
1753 "-M q35 "
1754 "-device ide-cd,drive=drive0 ", iso);
1755 port = ahci_port_select(ahci);
1756
1757 buffer = ahci_alloc(ahci, ATAPI_SECTOR_SIZE);
1758 qtest_memset(ahci->parent->qts, buffer, 0x00, ATAPI_SECTOR_SIZE);
1759
1760 /* Suspend the next backend read so the ATAPI read stays in flight. */
1761 qtest_qemu_io(ahci->parent->qts, "drive0", "break read_aio rd");
1762
1763 cmd = ahci_atapi_command_create(CMD_ATAPI_READ_10, ATAPI_SECTOR_SIZE,
1764 dma);
1765 ahci_command_adjust(cmd, 0, buffer, ATAPI_SECTOR_SIZE, 0);
1766 ahci_command_commit(ahci, cmd, port);
1767 ahci_command_issue_async(ahci, cmd);
1768
1769 /* Stop and restart the command engine to re-map the command list. */
1770 ahci_px_clr(ahci, port, AHCI_PX_CMD, AHCI_PX_CMD_ST);
1771 ahci_px_set(ahci, port, AHCI_PX_CMD, AHCI_PX_CMD_ST);
1772
1773 qtest_qemu_io(ahci->parent->qts, "drive0", "resume rd");
1774
1775 /* Round-trip through the device to confirm qemu is still alive. */
1776 ahci_px_rreg(ahci, port, AHCI_PX_TFD);
1777
1778 ahci_command_free(cmd);
1779 ahci_free(ahci, buffer);
1780 g_free(tx);
1781 ahci_shutdown(ahci);
1782 remove_iso(fd, iso);
1783 }
1784
1785 static void test_atapi_engine_restart_pio(void)
1786 {
1787 test_atapi_engine_restart_in_flight(false);
1788 }
1789
1790 static void test_atapi_engine_restart_dma(void)
1791 {
1792 test_atapi_engine_restart_in_flight(true);
1793 }
1794
1795 /*
1796 * Regression test: an unplug runs no device reset, so it is the last chance to
1797 * detach an outstanding request. Its completion would otherwise walk the
1798 * AHCIDevice array that ahci_uninit() has freed, which each of the NCQ, DMA
1799 * and PIO completions reaches by a different route.
1800 *
1801 * The ACPI ejection register is what a guest writes to finish a PCI unplug.
1802 * -M pc is what puts it in reach: q35 has no ACPI hotplug on pcie.0, so the
1803 * unplug never happens there. Unlike the pciehp attention button this reaches
1804 * the unplug with no secondary bus reset, which is the ordering that leaves a
1805 * request outstanding.
1806 */
1807 static void test_unplug_in_flight(uint8_t ide_cmd)
1808 {
1809 AHCIQState *ahci;
1810 AHCICommand *cmd;
1811 uint64_t ptr;
1812 uint8_t port;
1813 QTestState *qts;
1814
1815 /*
1816 * The latency keeps the backend read in flight across the unplug. A
1817 * blkdebug breakpoint cannot stand in for it: cancelling a suspended
1818 * request waits for it, so the unplug would never return.
1819 */
1820 ahci = ahci_boot_and_enable(
1821 "-M pc "
1822 "-blockdev driver=null-co,node-name=drive0,read-zeroes=on,"
1823 "latency-ns=100000000 "
1824 "-device ich9-ahci,addr=1f.2,id=ahci0 "
1825 "-device ide-hd,drive=drive0,bus=ahci0.0 ");
1826 qts = ahci->parent->qts;
1827 port = ahci_port_select(ahci);
1828 ahci_port_clear(ahci, port);
1829
1830 ptr = ahci_alloc(ahci, AHCI_SECTOR_SIZE);
1831 g_assert(ptr);
1832
1833 cmd = ahci_command_create(ide_cmd);
1834 ahci_command_adjust(cmd, 0, ptr, AHCI_SECTOR_SIZE, 0);
1835 ahci_command_commit(ahci, cmd, port);
1836 ahci_command_issue_async(ahci, cmd);
1837
1838 /* Eject slot 0x1f of the root bus, which frees the AHCIDevice array. */
1839 qtest_outl(qts, 0xae10, 0);
1840 qtest_outl(qts, 0xae08, 1u << 0x1f);
1841 qtest_qmp_eventwait(qts, "DEVICE_DELETED");
1842
1843 /* Four times the backend latency, so the completion has surely run. */
1844 g_usleep(400 * 1000);
1845 qtest_qmp_assert_success(qts, "{ 'execute': 'query-status' }");
1846
1847 ahci_command_free(cmd);
1848 ahci_free(ahci, ptr);
1849 ahci_shutdown(ahci);
1850 }
1851
1852 static void test_unplug_ncq(void)
1853 {
1854 test_unplug_in_flight(READ_FPDMA_QUEUED);
1855 }
1856
1857 static void test_unplug_dma(void)
1858 {
1859 test_unplug_in_flight(CMD_READ_DMA);
1860 }
1861
1862 static void test_unplug_pio(void)
1863 {
1864 test_unplug_in_flight(CMD_READ_PIO);
1865 }
1866
1867 /*
1868 * Regression test: a PIO write outlives the command list it was issued from.
1869 * ide_cancel_dma_sync() does not reach s->pio_aiocb, so the second DRQ phase
1870 * runs from the write completion after PxCLB has been unmapped and must not
1871 * touch the command header any more.
1872 */
1873 static void test_write_engine_stop_in_flight(void)
1874 {
1875 AHCIQState *ahci;
1876 AHCICommand *cmd;
1877 unsigned char *tx;
1878 unsigned char *rx;
1879 uint64_t ptr;
1880 uint8_t port;
1881 size_t bufsize = AHCI_SECTOR_SIZE * 2;
1882 size_t i;
1883
1884 ahci = ahci_boot_and_enable("-drive file=blkdebug::%s,if=none,id=drive0,"
1885 "format=%s,cache=writeback "
1886 "-M q35 "
1887 "-device ide-hd,drive=drive0 ",
1888 tmp_path, imgfmt);
1889 port = ahci_port_select(ahci);
1890 ahci_port_clear(ahci, port);
1891
1892 tx = g_malloc(bufsize);
1893 generate_pattern(tx, bufsize, AHCI_SECTOR_SIZE);
1894 ptr = ahci_alloc(ahci, bufsize);
1895 g_assert(ptr);
1896 qtest_memwrite(ahci->parent->qts, ptr, tx, bufsize);
1897
1898 /* Zero the second sector, which the abandoned command must not reach. */
1899 rx = g_malloc0(AHCI_SECTOR_SIZE);
1900 ahci_io(ahci, port, CMD_WRITE_DMA, rx, AHCI_SECTOR_SIZE, 1);
1901
1902 /* Suspend the backend write so the first sector stays in flight. */
1903 g_free(qtest_hmp(ahci->parent->qts,
1904 "qemu-io drive0 \"break write_aio wr\""));
1905
1906 cmd = ahci_command_create(CMD_WRITE_PIO);
1907 ahci_command_adjust(cmd, 0, ptr, bufsize, 0);
1908 ahci_command_commit(ahci, cmd, port);
1909 ahci_command_issue_async(ahci, cmd);
1910
1911 /* Drop the command list while the write is still outstanding. */
1912 ahci_px_clr(ahci, port, AHCI_PX_CMD, AHCI_PX_CMD_ST);
1913
1914 g_free(qtest_hmp(ahci->parent->qts, "qemu-io drive0 \"resume wr\""));
1915
1916 /* Round-trip through the device to confirm qemu is still alive. */
1917 ahci_px_rreg(ahci, port, AHCI_PX_TFD);
1918
1919 /*
1920 * The second DRQ phase never fetched its data, so the sector it would
1921 * have carried has to be untouched rather than hold a copy of the first.
1922 */
1923 ahci_px_set(ahci, port, AHCI_PX_CMD, AHCI_PX_CMD_ST);
1924 memset(rx, 0xff, AHCI_SECTOR_SIZE);
1925 ahci_io(ahci, port, CMD_READ_DMA, rx, AHCI_SECTOR_SIZE, 1);
1926 for (i = 0; i < AHCI_SECTOR_SIZE; i++) {
1927 g_assert_cmpint(rx[i], ==, 0);
1928 }
1929
1930 ahci_command_free(cmd);
1931 ahci_free(ahci, ptr);
1932 g_free(rx);
1933 g_free(tx);
1934 ahci_shutdown(ahci);
1935 }
1936
1937 /*
1938 * Regression test: a multi-sector ATAPI read fetches its later sectors from
1939 * inside the first read's completion; a concurrent drain (as a guest reset
1940 * triggers via bdrv_drain_all_begin) must not wedge on that nested read.
1941 * blkdebug keeps the read in flight across x-blockdev-set-iothread.
1942 */
1943 static void test_atapi_drain_in_flight(bool dma)
1944 {
1945 AHCIQState *ahci;
1946 AHCICommand *cmd;
1947 unsigned char *tx;
1948 char *iso;
1949 int fd;
1950 uint8_t port;
1951 uint64_t buffer;
1952 uint16_t bcl = ATAPI_SECTOR_SIZE * 2;
1953 uint64_t iso_size = (uint64_t)ATAPI_SECTOR_SIZE * 3;
1954
1955 fd = prepare_iso(iso_size, &tx, &iso);
1956
1957 /* 1s read delay: a wide margin so the drain starts before it completes */
1958 ahci = ahci_boot_and_enable(
1959 "-blockdev driver=file,node-name=file0,filename=%s,read-only=on "
1960 "-blockdev driver=blkdebug,node-name=cd0,image=file0,read-only=on,"
1961 "inject-error.0.event=none,inject-error.0.iotype=read,"
1962 "inject-error.0.errno=0,inject-error.0.delay-ns=1000000000 "
1963 "-M q35 "
1964 "-device ide-cd,drive=cd0 ", iso);
1965 port = ahci_port_select(ahci);
1966
1967 buffer = ahci_alloc(ahci, bcl);
1968 qtest_memset(ahci->parent->qts, buffer, 0x00, bcl);
1969
1970 cmd = ahci_atapi_command_create(CMD_ATAPI_READ_10, bcl, dma);
1971 ahci_command_adjust(cmd, 0, buffer, bcl, 0);
1972 ahci_command_commit(ahci, cmd, port);
1973 ahci_command_issue_async(ahci, cmd);
1974
1975 /* Drain (all nodes) while the delayed read is still in flight. */
1976 qtest_qmp_assert_success(ahci->parent->qts,
1977 "{ 'execute': 'x-blockdev-set-iothread',"
1978 " 'arguments': { 'node-name': 'cd0', 'iothread': null,"
1979 " 'force': true } }");
1980
1981 /* Round-trip through the device to confirm qemu is still alive. */
1982 ahci_px_rreg(ahci, port, AHCI_PX_TFD);
1983
1984 ahci_command_free(cmd);
1985 ahci_free(ahci, buffer);
1986 g_free(tx);
1987 ahci_shutdown(ahci);
1988 remove_iso(fd, iso);
1989 }
1990
1991 static void test_atapi_drain_pio(void)
1992 {
1993 test_atapi_drain_in_flight(false);
1994 }
1995
1996 static void test_atapi_drain_dma(void)
1997 {
1998 test_atapi_drain_in_flight(true);
1999 }
2000
2001 /* Regression test: Test that a READ_CD command with a BCL of 0 but a size of 0
2002 * completes as a NOP instead of erroring out. */
2003 static void test_atapi_bcl(void)
2004 {
2005 ahci_test_cdrom(0, false, CMD_ATAPI_READ_CD, true, 0);
2006 }
2007
2008
2009 static void atapi_wait_tray(AHCIQState *ahci, bool open)
2010 {
2011 QDict *rsp = qtest_qmp_eventwait_ref(ahci->parent->qts,
2012 "DEVICE_TRAY_MOVED");
2013 QDict *data = qdict_get_qdict(rsp, "data");
2014 if (open) {
2015 g_assert(qdict_get_bool(data, "tray-open"));
2016 } else {
2017 g_assert(!qdict_get_bool(data, "tray-open"));
2018 }
2019 qobject_unref(rsp);
2020 }
2021
2022 static void test_atapi_tray(void)
2023 {
2024 AHCIQState *ahci;
2025 unsigned char *tx;
2026 char *iso;
2027 int fd;
2028 uint8_t port, sense, asc;
2029 uint64_t iso_size = ATAPI_SECTOR_SIZE;
2030 QDict *rsp;
2031
2032 fd = prepare_iso(iso_size, &tx, &iso);
2033 ahci = ahci_boot_and_enable("-blockdev node-name=drive0,driver=file,filename=%s "
2034 "-M q35 "
2035 "-device ide-cd,id=cd0,drive=drive0 ", iso);
2036 port = ahci_port_select(ahci);
2037
2038 ahci_atapi_eject(ahci, port);
2039 atapi_wait_tray(ahci, true);
2040
2041 ahci_atapi_load(ahci, port);
2042 atapi_wait_tray(ahci, false);
2043
2044 /* Remove media */
2045 qtest_qmp_send(ahci->parent->qts, "{'execute': 'blockdev-open-tray', "
2046 "'arguments': {'id': 'cd0'}}");
2047 atapi_wait_tray(ahci, true);
2048 rsp = qtest_qmp_receive(ahci->parent->qts);
2049 qobject_unref(rsp);
2050
2051 qtest_qmp_assert_success(ahci->parent->qts,
2052 "{'execute': 'blockdev-remove-medium', "
2053 "'arguments': {'id': 'cd0'}}");
2054
2055 /* Test the tray without a medium */
2056 ahci_atapi_load(ahci, port);
2057 atapi_wait_tray(ahci, false);
2058
2059 ahci_atapi_eject(ahci, port);
2060 atapi_wait_tray(ahci, true);
2061
2062 /* Re-insert media */
2063 qtest_qmp_assert_success(
2064 ahci->parent->qts,
2065 "{'execute': 'blockdev-add', "
2066 "'arguments': {'node-name': 'node0', "
2067 "'driver': 'raw', "
2068 "'file': { 'driver': 'file', "
2069 "'filename': %s }}}", iso);
2070 qtest_qmp_assert_success(
2071 ahci->parent->qts,
2072 "{'execute': 'blockdev-insert-medium',"
2073 "'arguments': { 'id': 'cd0', "
2074 "'node-name': 'node0' }}");
2075
2076 /* Again, the event shows up first */
2077 qtest_qmp_send(ahci->parent->qts, "{'execute': 'blockdev-close-tray', "
2078 "'arguments': {'id': 'cd0'}}");
2079 atapi_wait_tray(ahci, false);
2080 rsp = qtest_qmp_receive(ahci->parent->qts);
2081 qobject_unref(rsp);
2082
2083 /* Now, to convince ATAPI we understand the media has changed... */
2084 ahci_atapi_test_ready(ahci, port, false, SENSE_NOT_READY);
2085 ahci_atapi_get_sense(ahci, port, &sense, &asc);
2086 g_assert_cmpuint(sense, ==, SENSE_NOT_READY);
2087 g_assert_cmpuint(asc, ==, ASC_MEDIUM_NOT_PRESENT);
2088
2089 ahci_atapi_test_ready(ahci, port, false, SENSE_UNIT_ATTENTION);
2090 ahci_atapi_get_sense(ahci, port, &sense, &asc);
2091 g_assert_cmpuint(sense, ==, SENSE_UNIT_ATTENTION);
2092 g_assert_cmpuint(asc, ==, ASC_MEDIUM_MAY_HAVE_CHANGED);
2093
2094 ahci_atapi_test_ready(ahci, port, true, SENSE_NO_SENSE);
2095 ahci_atapi_get_sense(ahci, port, &sense, &asc);
2096 g_assert_cmpuint(sense, ==, SENSE_NO_SENSE);
2097
2098 /* Final tray test. */
2099 ahci_atapi_eject(ahci, port);
2100 atapi_wait_tray(ahci, true);
2101
2102 ahci_atapi_load(ahci, port);
2103 atapi_wait_tray(ahci, false);
2104
2105 /* Cleanup */
2106 g_free(tx);
2107 ahci_shutdown(ahci);
2108 remove_iso(fd, iso);
2109 }
2110
2111 /******************************************************************************/
2112 /* AHCI I/O Test Matrix Definitions */
2113
2114 enum BuffLen {
2115 LEN_BEGIN = 0,
2116 LEN_SIMPLE = LEN_BEGIN,
2117 LEN_DOUBLE,
2118 LEN_LONG,
2119 LEN_SHORT,
2120 NUM_LENGTHS
2121 };
2122
2123 static const char *buff_len_str[NUM_LENGTHS] = { "simple", "double",
2124 "long", "short" };
2125
2126 enum AddrMode {
2127 ADDR_MODE_BEGIN = 0,
2128 ADDR_MODE_LBA28 = ADDR_MODE_BEGIN,
2129 ADDR_MODE_LBA48,
2130 NUM_ADDR_MODES
2131 };
2132
2133 static const char *addr_mode_str[NUM_ADDR_MODES] = { "lba28", "lba48" };
2134
2135 enum IOMode {
2136 MODE_BEGIN = 0,
2137 MODE_PIO = MODE_BEGIN,
2138 MODE_DMA,
2139 NUM_MODES
2140 };
2141
2142 static const char *io_mode_str[NUM_MODES] = { "pio", "dma" };
2143
2144 enum IOOps {
2145 IO_BEGIN = 0,
2146 IO_READ = IO_BEGIN,
2147 IO_WRITE,
2148 NUM_IO_OPS
2149 };
2150
2151 enum OffsetType {
2152 OFFSET_BEGIN = 0,
2153 OFFSET_ZERO = OFFSET_BEGIN,
2154 OFFSET_LOW,
2155 OFFSET_HIGH,
2156 NUM_OFFSETS
2157 };
2158
2159 static const char *offset_str[NUM_OFFSETS] = { "zero", "low", "high" };
2160
2161 typedef struct AHCIIOTestOptions {
2162 enum BuffLen length;
2163 enum AddrMode address_type;
2164 enum IOMode io_type;
2165 enum OffsetType offset;
2166 } AHCIIOTestOptions;
2167
2168 static uint64_t offset_sector(enum OffsetType ofst,
2169 enum AddrMode addr_type,
2170 uint64_t buffsize)
2171 {
2172 uint64_t ceil;
2173 uint64_t nsectors;
2174
2175 switch (ofst) {
2176 case OFFSET_ZERO:
2177 return 0;
2178 case OFFSET_LOW:
2179 return 1;
2180 case OFFSET_HIGH:
2181 ceil = (addr_type == ADDR_MODE_LBA28) ? 0xfffffff : 0xffffffffffff;
2182 ceil = MIN(ceil, mb_to_sectors(test_image_size_mb) - 1);
2183 nsectors = buffsize / AHCI_SECTOR_SIZE;
2184 return ceil - nsectors + 1;
2185 default:
2186 g_assert_not_reached();
2187 }
2188 }
2189
2190 /**
2191 * Table of possible I/O ATA commands given a set of enumerations.
2192 */
2193 static const uint8_t io_cmds[NUM_MODES][NUM_ADDR_MODES][NUM_IO_OPS] = {
2194 [MODE_PIO] = {
2195 [ADDR_MODE_LBA28] = {
2196 [IO_READ] = CMD_READ_PIO,
2197 [IO_WRITE] = CMD_WRITE_PIO },
2198 [ADDR_MODE_LBA48] = {
2199 [IO_READ] = CMD_READ_PIO_EXT,
2200 [IO_WRITE] = CMD_WRITE_PIO_EXT }
2201 },
2202 [MODE_DMA] = {
2203 [ADDR_MODE_LBA28] = {
2204 [IO_READ] = CMD_READ_DMA,
2205 [IO_WRITE] = CMD_WRITE_DMA },
2206 [ADDR_MODE_LBA48] = {
2207 [IO_READ] = CMD_READ_DMA_EXT,
2208 [IO_WRITE] = CMD_WRITE_DMA_EXT }
2209 }
2210 };
2211
2212 /**
2213 * Test a Read/Write pattern using various commands, addressing modes,
2214 * transfer modes, and buffer sizes.
2215 */
2216 static void test_io_rw_interface(enum AddrMode lba48, enum IOMode dma,
2217 unsigned bufsize, uint64_t sector)
2218 {
2219 AHCIQState *ahci;
2220
2221 ahci = ahci_boot_and_enable(NULL);
2222 ahci_test_io_rw_simple(ahci, bufsize, sector,
2223 io_cmds[dma][lba48][IO_READ],
2224 io_cmds[dma][lba48][IO_WRITE]);
2225 ahci_shutdown(ahci);
2226 }
2227
2228 /**
2229 * Demultiplex the test data and invoke the actual test routine.
2230 */
2231 static void test_io_interface(gconstpointer opaque)
2232 {
2233 AHCIIOTestOptions *opts = (AHCIIOTestOptions *)opaque;
2234 unsigned bufsize;
2235 uint64_t sector;
2236
2237 switch (opts->length) {
2238 case LEN_SIMPLE:
2239 bufsize = 4096;
2240 break;
2241 case LEN_DOUBLE:
2242 bufsize = 8192;
2243 break;
2244 case LEN_LONG:
2245 bufsize = 4096 * 64;
2246 break;
2247 case LEN_SHORT:
2248 bufsize = 512;
2249 break;
2250 default:
2251 g_assert_not_reached();
2252 }
2253
2254 sector = offset_sector(opts->offset, opts->address_type, bufsize);
2255 test_io_rw_interface(opts->address_type, opts->io_type, bufsize, sector);
2256 g_free(opts);
2257 }
2258
2259 static void create_ahci_io_test(enum IOMode type, enum AddrMode addr,
2260 enum BuffLen len, enum OffsetType offset)
2261 {
2262 char *name;
2263 AHCIIOTestOptions *opts;
2264
2265 opts = g_new(AHCIIOTestOptions, 1);
2266 opts->length = len;
2267 opts->address_type = addr;
2268 opts->io_type = type;
2269 opts->offset = offset;
2270
2271 name = g_strdup_printf("ahci/io/%s/%s/%s/%s",
2272 io_mode_str[type],
2273 addr_mode_str[addr],
2274 buff_len_str[len],
2275 offset_str[offset]);
2276
2277 if ((addr == ADDR_MODE_LBA48) && (offset == OFFSET_HIGH) &&
2278 (mb_to_sectors(test_image_size_mb) <= 0xFFFFFFF)) {
2279 g_test_message("%s: skipped; test image too small", name);
2280 g_free(opts);
2281 g_free(name);
2282 return;
2283 }
2284
2285 qtest_add_data_func(name, opts, test_io_interface);
2286 g_free(name);
2287 }
2288
2289 /******************************************************************************/
2290
2291 int main(int argc, char **argv)
2292 {
2293 const char *arch, *base;
2294 int ret;
2295 int fd;
2296 int c;
2297 int i, j, k, m;
2298
2299 static struct option long_options[] = {
2300 {"pedantic", no_argument, 0, 'p' },
2301 {0, 0, 0, 0},
2302 };
2303
2304 /* Should be first to utilize g_test functionality, So we can see errors. */
2305 g_test_init(&argc, &argv, NULL);
2306
2307 while (1) {
2308 c = getopt_long(argc, argv, "", long_options, NULL);
2309 if (c == -1) {
2310 break;
2311 }
2312 switch (c) {
2313 case -1:
2314 break;
2315 case 'p':
2316 ahci_pedantic = 1;
2317 break;
2318 default:
2319 fprintf(stderr, "Unrecognized ahci_test option.\n");
2320 g_assert_not_reached();
2321 }
2322 }
2323
2324 /* Check architecture */
2325 arch = qtest_get_arch();
2326 if (strcmp(arch, "i386") && strcmp(arch, "x86_64")) {
2327 g_test_message("Skipping test for non-x86");
2328 return 0;
2329 }
2330
2331 /*
2332 * "base" stores the starting point where we create temporary files.
2333 *
2334 * On Windows, this is set to the relative path of current working
2335 * directory, because the absolute path causes the blkdebug filename
2336 * parser fail to parse "blkdebug:path/to/config:path/to/image".
2337 */
2338 #ifndef _WIN32
2339 base = g_get_tmp_dir();
2340 #else
2341 base = ".";
2342 #endif
2343
2344 /* Create a temporary image */
2345 tmp_path = g_strdup_printf("%s/qtest.XXXXXX", base);
2346 fd = g_mkstemp(tmp_path);
2347 g_assert(fd >= 0);
2348 if (have_qemu_img()) {
2349 imgfmt = "qcow2";
2350 test_image_size_mb = TEST_IMAGE_SIZE_MB_LARGE;
2351 mkqcow2(tmp_path, TEST_IMAGE_SIZE_MB_LARGE);
2352 } else {
2353 g_test_message("QTEST_QEMU_IMG not set or qemu-img missing; "
2354 "skipping LBA48 high-sector tests");
2355 imgfmt = "raw";
2356 test_image_size_mb = TEST_IMAGE_SIZE_MB_SMALL;
2357 ret = ftruncate(fd, test_image_size_mb * 1024 * 1024);
2358 g_assert(ret == 0);
2359 }
2360 close(fd);
2361
2362 /* Create temporary blkdebug instructions */
2363 debug_path = g_strdup_printf("%s/qtest-blkdebug.XXXXXX", base);
2364 fd = g_mkstemp(debug_path);
2365 g_assert(fd >= 0);
2366 close(fd);
2367
2368 /* Reserve a hollow file to use as a socket for migration tests */
2369 fd = g_file_open_tmp("qtest-migration.XXXXXX", &mig_socket, NULL);
2370 g_assert(fd >= 0);
2371 close(fd);
2372
2373 /* Run the tests */
2374 qtest_add_func("/ahci/sanity", test_sanity);
2375 qtest_add_func("/ahci/pci_spec", test_pci_spec);
2376 qtest_add_func("/ahci/pci_enable", test_pci_enable);
2377 qtest_add_func("/ahci/hba_spec", test_hba_spec);
2378 qtest_add_func("/ahci/hba_enable", test_hba_enable);
2379 qtest_add_func("/ahci/identify", test_identify);
2380
2381 for (i = MODE_BEGIN; i < NUM_MODES; i++) {
2382 for (j = ADDR_MODE_BEGIN; j < NUM_ADDR_MODES; j++) {
2383 for (k = LEN_BEGIN; k < NUM_LENGTHS; k++) {
2384 for (m = OFFSET_BEGIN; m < NUM_OFFSETS; m++) {
2385 create_ahci_io_test(i, j, k, m);
2386 }
2387 }
2388 }
2389 }
2390
2391 qtest_add_func("/ahci/io/dma/lba28/fragmented", test_dma_fragmented);
2392
2393 qtest_add_func("/ahci/flush/simple", test_flush);
2394 qtest_add_func("/ahci/flush/retry", test_flush_retry);
2395 qtest_add_func("/ahci/flush/migrate", test_flush_migrate);
2396
2397 qtest_add_func("/ahci/migrate/sanity", test_migrate_sanity);
2398 qtest_add_func("/ahci/migrate/dma/simple", test_migrate_dma);
2399 qtest_add_func("/ahci/io/dma/lba28/retry", test_halted_dma);
2400 qtest_add_func("/ahci/migrate/dma/halted", test_migrate_halted_dma);
2401
2402 qtest_add_func("/ahci/max", test_max);
2403 qtest_add_func("/ahci/specify", test_specify);
2404 qtest_add_func("/ahci/reset/simple", test_reset);
2405 qtest_add_func("/ahci/reset/pending_callback", test_reset_pending_callback);
2406
2407 qtest_add_func("/ahci/io/ncq/simple", test_ncq_simple);
2408 qtest_add_func("/ahci/migrate/ncq/simple", test_migrate_ncq);
2409 qtest_add_func("/ahci/io/ncq/retry", test_halted_ncq);
2410 qtest_add_func("/ahci/migrate/ncq/halted", test_migrate_halted_ncq);
2411
2412 qtest_add_func("/ahci/cdrom/dma/single", test_cdrom_dma);
2413 qtest_add_func("/ahci/cdrom/dma/multi", test_cdrom_dma_multi);
2414 qtest_add_func("/ahci/cdrom/dma/raw", test_cdrom_dma_raw);
2415 qtest_add_func("/ahci/cdrom/pio/single", test_cdrom_pio);
2416 qtest_add_func("/ahci/cdrom/pio/multi", test_cdrom_pio_multi);
2417 qtest_add_func("/ahci/cdrom/pio/raw", test_cdrom_pio_raw);
2418
2419 qtest_add_func("/ahci/cdrom/pio/bcl", test_atapi_bcl);
2420 qtest_add_func("/ahci/cdrom/eject", test_atapi_tray);
2421 qtest_add_func("/ahci/cdrom/engine_restart/pio",
2422 test_atapi_engine_restart_pio);
2423 qtest_add_func("/ahci/cdrom/engine_restart/dma",
2424 test_atapi_engine_restart_dma);
2425 qtest_add_func("/ahci/io/ncq/unplug", test_unplug_ncq);
2426 qtest_add_func("/ahci/io/dma/unplug", test_unplug_dma);
2427 qtest_add_func("/ahci/io/pio/unplug", test_unplug_pio);
2428 qtest_add_func("/ahci/io/pio/engine_stop",
2429 test_write_engine_stop_in_flight);
2430 qtest_add_func("/ahci/cdrom/drain/pio", test_atapi_drain_pio);
2431 qtest_add_func("/ahci/cdrom/drain/dma", test_atapi_drain_dma);
2432
2433 ret = g_test_run();
2434
2435 /* Cleanup */
2436 unlink(tmp_path);
2437 g_free(tmp_path);
2438 unlink(debug_path);
2439 g_free(debug_path);
2440 unlink(mig_socket);
2441 g_free(mig_socket);
2442
2443 return ret;
2444 }