| 1 | /* |
| 2 | * QTest testcase for the ASPEED Hash and Crypto Engine |
| 3 | * |
| 4 | * SPDX-License-Identifier: GPL-2.0-or-later |
| 5 | * Copyright 2021 IBM Corp. |
| 6 | */ |
| 7 | |
| 8 | #include "qemu/osdep.h" |
| 9 | #include "libqtest.h" |
| 10 | #include "qemu/bitops.h" |
| 11 | #include "qemu/bswap.h" |
| 12 | #include "crypto/cipher.h" |
| 13 | #include "aspeed-hace-utils.h" |
| 14 | |
| 15 | /* |
| 16 | * Test vector is the ascii "abc" |
| 17 | * |
| 18 | * Expected results were generated using command line utitiles: |
| 19 | * |
| 20 | * echo -n -e 'abc' | dd of=/tmp/test |
| 21 | * for hash in sha512sum sha384sum sha256sum md5sum; do $hash /tmp/test; done |
| 22 | * |
| 23 | */ |
| 24 | static const uint8_t test_vector[3] = {0x61, 0x62, 0x63}; |
| 25 | |
| 26 | static const uint8_t test_result_sha512[64] = { |
| 27 | 0xdd, 0xaf, 0x35, 0xa1, 0x93, 0x61, 0x7a, 0xba, 0xcc, 0x41, 0x73, 0x49, |
| 28 | 0xae, 0x20, 0x41, 0x31, 0x12, 0xe6, 0xfa, 0x4e, 0x89, 0xa9, 0x7e, 0xa2, |
| 29 | 0x0a, 0x9e, 0xee, 0xe6, 0x4b, 0x55, 0xd3, 0x9a, 0x21, 0x92, 0x99, 0x2a, |
| 30 | 0x27, 0x4f, 0xc1, 0xa8, 0x36, 0xba, 0x3c, 0x23, 0xa3, 0xfe, 0xeb, 0xbd, |
| 31 | 0x45, 0x4d, 0x44, 0x23, 0x64, 0x3c, 0xe8, 0x0e, 0x2a, 0x9a, 0xc9, 0x4f, |
| 32 | 0xa5, 0x4c, 0xa4, 0x9f}; |
| 33 | |
| 34 | static const uint8_t test_result_sha384[48] = { |
| 35 | 0xcb, 0x00, 0x75, 0x3f, 0x45, 0xa3, 0x5e, 0x8b, 0xb5, 0xa0, 0x3d, 0x69, |
| 36 | 0x9a, 0xc6, 0x50, 0x07, 0x27, 0x2c, 0x32, 0xab, 0x0e, 0xde, 0xd1, 0x63, |
| 37 | 0x1a, 0x8b, 0x60, 0x5a, 0x43, 0xff, 0x5b, 0xed, 0x80, 0x86, 0x07, 0x2b, |
| 38 | 0xa1, 0xe7, 0xcc, 0x23, 0x58, 0xba, 0xec, 0xa1, 0x34, 0xc8, 0x25, 0xa7}; |
| 39 | |
| 40 | static const uint8_t test_result_sha256[32] = { |
| 41 | 0xba, 0x78, 0x16, 0xbf, 0x8f, 0x01, 0xcf, 0xea, 0x41, 0x41, 0x40, 0xde, |
| 42 | 0x5d, 0xae, 0x22, 0x23, 0xb0, 0x03, 0x61, 0xa3, 0x96, 0x17, 0x7a, 0x9c, |
| 43 | 0xb4, 0x10, 0xff, 0x61, 0xf2, 0x00, 0x15, 0xad}; |
| 44 | |
| 45 | static const uint8_t test_result_md5[16] = { |
| 46 | 0x90, 0x01, 0x50, 0x98, 0x3c, 0xd2, 0x4f, 0xb0, 0xd6, 0x96, 0x3f, 0x7d, |
| 47 | 0x28, 0xe1, 0x7f, 0x72}; |
| 48 | |
| 49 | /* |
| 50 | * The Scatter-Gather Test vector is the ascii "abc" "def" "ghi", broken |
| 51 | * into blocks of 3 characters as shown |
| 52 | * |
| 53 | * Expected results were generated using command line utitiles: |
| 54 | * |
| 55 | * echo -n -e 'abcdefghijkl' | dd of=/tmp/test |
| 56 | * for hash in sha512sum sha384sum sha256sum; do $hash /tmp/test; done |
| 57 | * |
| 58 | */ |
| 59 | static const uint8_t test_vector_sg1[6] = {0x61, 0x62, 0x63, 0x64, 0x65, 0x66}; |
| 60 | static const uint8_t test_vector_sg2[3] = {0x67, 0x68, 0x69}; |
| 61 | static const uint8_t test_vector_sg3[3] = {0x6a, 0x6b, 0x6c}; |
| 62 | |
| 63 | static const uint8_t test_result_sg_sha512[64] = { |
| 64 | 0x17, 0x80, 0x7c, 0x72, 0x8e, 0xe3, 0xba, 0x35, 0xe7, 0xcf, 0x7a, 0xf8, |
| 65 | 0x23, 0x11, 0x6d, 0x26, 0xe4, 0x1e, 0x5d, 0x4d, 0x6c, 0x2f, 0xf1, 0xf3, |
| 66 | 0x72, 0x0d, 0x3d, 0x96, 0xaa, 0xcb, 0x6f, 0x69, 0xde, 0x64, 0x2e, 0x63, |
| 67 | 0xd5, 0xb7, 0x3f, 0xc3, 0x96, 0xc1, 0x2b, 0xe3, 0x8b, 0x2b, 0xd5, 0xd8, |
| 68 | 0x84, 0x25, 0x7c, 0x32, 0xc8, 0xf6, 0xd0, 0x85, 0x4a, 0xe6, 0xb5, 0x40, |
| 69 | 0xf8, 0x6d, 0xda, 0x2e}; |
| 70 | |
| 71 | static const uint8_t test_result_sg_sha384[48] = { |
| 72 | 0x10, 0x3c, 0xa9, 0x6c, 0x06, 0xa1, 0xce, 0x79, 0x8f, 0x08, 0xf8, 0xef, |
| 73 | 0xf0, 0xdf, 0xb0, 0xcc, 0xdb, 0x56, 0x7d, 0x48, 0xb2, 0x85, 0xb2, 0x3d, |
| 74 | 0x0c, 0xd7, 0x73, 0x45, 0x46, 0x67, 0xa3, 0xc2, 0xfa, 0x5f, 0x1b, 0x58, |
| 75 | 0xd9, 0xcd, 0xf2, 0x32, 0x9b, 0xd9, 0x97, 0x97, 0x30, 0xbf, 0xaa, 0xff}; |
| 76 | |
| 77 | static const uint8_t test_result_sg_sha256[32] = { |
| 78 | 0xd6, 0x82, 0xed, 0x4c, 0xa4, 0xd9, 0x89, 0xc1, 0x34, 0xec, 0x94, 0xf1, |
| 79 | 0x55, 0x1e, 0x1e, 0xc5, 0x80, 0xdd, 0x6d, 0x5a, 0x6e, 0xcd, 0xe9, 0xf3, |
| 80 | 0xd3, 0x5e, 0x6e, 0x4a, 0x71, 0x7f, 0xbd, 0xe4}; |
| 81 | |
| 82 | /* |
| 83 | * The accumulative mode requires firmware to provide internal initial state |
| 84 | * and message padding (including length L at the end of padding). |
| 85 | * |
| 86 | * This test vector is a ascii text "abc" with padding message. |
| 87 | * |
| 88 | * Expected results were generated using command line utitiles: |
| 89 | * |
| 90 | * echo -n -e 'abc' | dd of=/tmp/test |
| 91 | * for hash in sha512sum sha384sum sha256sum; do $hash /tmp/test; done |
| 92 | */ |
| 93 | static const uint8_t test_vector_accum_512[128] = { |
| 94 | 0x61, 0x62, 0x63, 0x80, 0x00, 0x00, 0x00, 0x00, |
| 95 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 96 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 97 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 98 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 99 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 100 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 101 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 102 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 103 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 104 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 105 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 106 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 107 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 108 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 109 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18}; |
| 110 | |
| 111 | static const uint8_t test_vector_accum_384[128] = { |
| 112 | 0x61, 0x62, 0x63, 0x80, 0x00, 0x00, 0x00, 0x00, |
| 113 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 114 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 115 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 116 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 117 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 118 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 119 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 120 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 121 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 122 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 123 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 124 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 125 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 126 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 127 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18}; |
| 128 | |
| 129 | static const uint8_t test_vector_accum_256[64] = { |
| 130 | 0x61, 0x62, 0x63, 0x80, 0x00, 0x00, 0x00, 0x00, |
| 131 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 132 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 133 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 134 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 135 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 136 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 137 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18}; |
| 138 | |
| 139 | static const uint8_t test_result_accum_sha512[64] = { |
| 140 | 0xdd, 0xaf, 0x35, 0xa1, 0x93, 0x61, 0x7a, 0xba, 0xcc, 0x41, 0x73, 0x49, |
| 141 | 0xae, 0x20, 0x41, 0x31, 0x12, 0xe6, 0xfa, 0x4e, 0x89, 0xa9, 0x7e, 0xa2, |
| 142 | 0x0a, 0x9e, 0xee, 0xe6, 0x4b, 0x55, 0xd3, 0x9a, 0x21, 0x92, 0x99, 0x2a, |
| 143 | 0x27, 0x4f, 0xc1, 0xa8, 0x36, 0xba, 0x3c, 0x23, 0xa3, 0xfe, 0xeb, 0xbd, |
| 144 | 0x45, 0x4d, 0x44, 0x23, 0x64, 0x3c, 0xe8, 0x0e, 0x2a, 0x9a, 0xc9, 0x4f, |
| 145 | 0xa5, 0x4c, 0xa4, 0x9f}; |
| 146 | |
| 147 | static const uint8_t test_result_accum_sha384[48] = { |
| 148 | 0xcb, 0x00, 0x75, 0x3f, 0x45, 0xa3, 0x5e, 0x8b, 0xb5, 0xa0, 0x3d, 0x69, |
| 149 | 0x9a, 0xc6, 0x50, 0x07, 0x27, 0x2c, 0x32, 0xab, 0x0e, 0xde, 0xd1, 0x63, |
| 150 | 0x1a, 0x8b, 0x60, 0x5a, 0x43, 0xff, 0x5b, 0xed, 0x80, 0x86, 0x07, 0x2b, |
| 151 | 0xa1, 0xe7, 0xcc, 0x23, 0x58, 0xba, 0xec, 0xa1, 0x34, 0xc8, 0x25, 0xa7}; |
| 152 | |
| 153 | static const uint8_t test_result_accum_sha256[32] = { |
| 154 | 0xba, 0x78, 0x16, 0xbf, 0x8f, 0x01, 0xcf, 0xea, 0x41, 0x41, 0x40, 0xde, |
| 155 | 0x5d, 0xae, 0x22, 0x23, 0xb0, 0x03, 0x61, 0xa3, 0x96, 0x17, 0x7a, 0x9c, |
| 156 | 0xb4, 0x10, 0xff, 0x61, 0xf2, 0x00, 0x15, 0xad}; |
| 157 | |
| 158 | static void write_regs(QTestState *s, uint32_t base, uint64_t src, |
| 159 | uint32_t length, uint64_t out, uint32_t method) |
| 160 | { |
| 161 | qtest_writel(s, base + HACE_HASH_SRC, extract64(src, 0, 32)); |
| 162 | qtest_writel(s, base + HACE_HASH_SRC_HI, extract64(src, 32, 32)); |
| 163 | qtest_writel(s, base + HACE_HASH_DIGEST, extract64(out, 0, 32)); |
| 164 | qtest_writel(s, base + HACE_HASH_DIGEST_HI, extract64(out, 32, 32)); |
| 165 | qtest_writel(s, base + HACE_HASH_DATA_LEN, length); |
| 166 | qtest_writel(s, base + HACE_HASH_CMD, HACE_SHA_BE_EN | method); |
| 167 | } |
| 168 | |
| 169 | void aspeed_test_md5(const char *machine, const uint32_t base, |
| 170 | const uint64_t src_addr) |
| 171 | |
| 172 | { |
| 173 | QTestState *s = qtest_init(machine); |
| 174 | |
| 175 | uint64_t digest_addr = src_addr + 0x010000; |
| 176 | uint8_t digest[16] = {0}; |
| 177 | |
| 178 | /* Check engine is idle, no busy or irq bits set */ |
| 179 | g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); |
| 180 | |
| 181 | /* Write test vector into memory */ |
| 182 | qtest_memwrite(s, src_addr, test_vector, sizeof(test_vector)); |
| 183 | |
| 184 | write_regs(s, base, src_addr, sizeof(test_vector), |
| 185 | digest_addr, HACE_ALGO_MD5); |
| 186 | |
| 187 | /* Check hash IRQ status is asserted */ |
| 188 | g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0x00000200); |
| 189 | |
| 190 | /* Clear IRQ status and check status is deasserted */ |
| 191 | qtest_writel(s, base + HACE_STS, 0x00000200); |
| 192 | g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); |
| 193 | |
| 194 | /* Read computed digest from memory */ |
| 195 | qtest_memread(s, digest_addr, digest, sizeof(digest)); |
| 196 | |
| 197 | /* Check result of computation */ |
| 198 | g_assert_cmpmem(digest, sizeof(digest), |
| 199 | test_result_md5, sizeof(digest)); |
| 200 | |
| 201 | qtest_quit(s); |
| 202 | } |
| 203 | |
| 204 | void aspeed_test_sha256(const char *machine, const uint32_t base, |
| 205 | const uint64_t src_addr) |
| 206 | { |
| 207 | QTestState *s = qtest_init(machine); |
| 208 | |
| 209 | const uint64_t digest_addr = src_addr + 0x10000; |
| 210 | uint8_t digest[32] = {0}; |
| 211 | |
| 212 | /* Check engine is idle, no busy or irq bits set */ |
| 213 | g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); |
| 214 | |
| 215 | /* Write test vector into memory */ |
| 216 | qtest_memwrite(s, src_addr, test_vector, sizeof(test_vector)); |
| 217 | |
| 218 | write_regs(s, base, src_addr, sizeof(test_vector), digest_addr, |
| 219 | HACE_ALGO_SHA256); |
| 220 | |
| 221 | /* Check hash IRQ status is asserted */ |
| 222 | g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0x00000200); |
| 223 | |
| 224 | /* Clear IRQ status and check status is deasserted */ |
| 225 | qtest_writel(s, base + HACE_STS, 0x00000200); |
| 226 | g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); |
| 227 | |
| 228 | /* Read computed digest from memory */ |
| 229 | qtest_memread(s, digest_addr, digest, sizeof(digest)); |
| 230 | |
| 231 | /* Check result of computation */ |
| 232 | g_assert_cmpmem(digest, sizeof(digest), |
| 233 | test_result_sha256, sizeof(digest)); |
| 234 | |
| 235 | qtest_quit(s); |
| 236 | } |
| 237 | |
| 238 | void aspeed_test_sha384(const char *machine, const uint32_t base, |
| 239 | const uint64_t src_addr) |
| 240 | { |
| 241 | QTestState *s = qtest_init(machine); |
| 242 | |
| 243 | const uint64_t digest_addr = src_addr + 0x10000; |
| 244 | uint8_t digest[48] = {0}; |
| 245 | |
| 246 | /* Check engine is idle, no busy or irq bits set */ |
| 247 | g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); |
| 248 | |
| 249 | /* Write test vector into memory */ |
| 250 | qtest_memwrite(s, src_addr, test_vector, sizeof(test_vector)); |
| 251 | |
| 252 | write_regs(s, base, src_addr, sizeof(test_vector), digest_addr, |
| 253 | HACE_ALGO_SHA384); |
| 254 | |
| 255 | /* Check hash IRQ status is asserted */ |
| 256 | g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0x00000200); |
| 257 | |
| 258 | /* Clear IRQ status and check status is deasserted */ |
| 259 | qtest_writel(s, base + HACE_STS, 0x00000200); |
| 260 | g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); |
| 261 | |
| 262 | /* Read computed digest from memory */ |
| 263 | qtest_memread(s, digest_addr, digest, sizeof(digest)); |
| 264 | |
| 265 | /* Check result of computation */ |
| 266 | g_assert_cmpmem(digest, sizeof(digest), |
| 267 | test_result_sha384, sizeof(digest)); |
| 268 | |
| 269 | qtest_quit(s); |
| 270 | } |
| 271 | |
| 272 | void aspeed_test_sha512(const char *machine, const uint32_t base, |
| 273 | const uint64_t src_addr) |
| 274 | { |
| 275 | QTestState *s = qtest_init(machine); |
| 276 | |
| 277 | const uint64_t digest_addr = src_addr + 0x10000; |
| 278 | uint8_t digest[64] = {0}; |
| 279 | |
| 280 | /* Check engine is idle, no busy or irq bits set */ |
| 281 | g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); |
| 282 | |
| 283 | /* Write test vector into memory */ |
| 284 | qtest_memwrite(s, src_addr, test_vector, sizeof(test_vector)); |
| 285 | |
| 286 | write_regs(s, base, src_addr, sizeof(test_vector), digest_addr, |
| 287 | HACE_ALGO_SHA512); |
| 288 | |
| 289 | /* Check hash IRQ status is asserted */ |
| 290 | g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0x00000200); |
| 291 | |
| 292 | /* Clear IRQ status and check status is deasserted */ |
| 293 | qtest_writel(s, base + HACE_STS, 0x00000200); |
| 294 | g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); |
| 295 | |
| 296 | /* Read computed digest from memory */ |
| 297 | qtest_memread(s, digest_addr, digest, sizeof(digest)); |
| 298 | |
| 299 | /* Check result of computation */ |
| 300 | g_assert_cmpmem(digest, sizeof(digest), |
| 301 | test_result_sha512, sizeof(digest)); |
| 302 | |
| 303 | qtest_quit(s); |
| 304 | } |
| 305 | |
| 306 | void aspeed_test_sha256_sg(const char *machine, const uint32_t base, |
| 307 | const uint64_t src_addr) |
| 308 | { |
| 309 | QTestState *s = qtest_init(machine); |
| 310 | |
| 311 | const uint64_t src_addr_1 = src_addr + 0x10000; |
| 312 | const uint64_t src_addr_2 = src_addr + 0x20000; |
| 313 | const uint64_t src_addr_3 = src_addr + 0x30000; |
| 314 | const uint64_t digest_addr = src_addr + 0x40000; |
| 315 | uint8_t digest[32] = {0}; |
| 316 | struct AspeedSgList array[] = { |
| 317 | { cpu_to_le32(sizeof(test_vector_sg1)), |
| 318 | cpu_to_le32(src_addr_1) }, |
| 319 | { cpu_to_le32(sizeof(test_vector_sg2)), |
| 320 | cpu_to_le32(src_addr_2) }, |
| 321 | { cpu_to_le32(sizeof(test_vector_sg3) | SG_LIST_LEN_LAST), |
| 322 | cpu_to_le32(src_addr_3) }, |
| 323 | }; |
| 324 | |
| 325 | /* Check engine is idle, no busy or irq bits set */ |
| 326 | g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); |
| 327 | |
| 328 | /* Write test vector into memory */ |
| 329 | qtest_memwrite(s, src_addr_1, test_vector_sg1, sizeof(test_vector_sg1)); |
| 330 | qtest_memwrite(s, src_addr_2, test_vector_sg2, sizeof(test_vector_sg2)); |
| 331 | qtest_memwrite(s, src_addr_3, test_vector_sg3, sizeof(test_vector_sg3)); |
| 332 | qtest_memwrite(s, src_addr, array, sizeof(array)); |
| 333 | |
| 334 | write_regs(s, base, src_addr, |
| 335 | (sizeof(test_vector_sg1) |
| 336 | + sizeof(test_vector_sg2) |
| 337 | + sizeof(test_vector_sg3)), |
| 338 | digest_addr, HACE_ALGO_SHA256 | HACE_SG_EN); |
| 339 | |
| 340 | /* Check hash IRQ status is asserted */ |
| 341 | g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0x00000200); |
| 342 | |
| 343 | /* Clear IRQ status and check status is deasserted */ |
| 344 | qtest_writel(s, base + HACE_STS, 0x00000200); |
| 345 | g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); |
| 346 | |
| 347 | /* Read computed digest from memory */ |
| 348 | qtest_memread(s, digest_addr, digest, sizeof(digest)); |
| 349 | |
| 350 | /* Check result of computation */ |
| 351 | g_assert_cmpmem(digest, sizeof(digest), |
| 352 | test_result_sg_sha256, sizeof(digest)); |
| 353 | |
| 354 | qtest_quit(s); |
| 355 | } |
| 356 | |
| 357 | void aspeed_test_sha384_sg(const char *machine, const uint32_t base, |
| 358 | const uint64_t src_addr) |
| 359 | { |
| 360 | QTestState *s = qtest_init(machine); |
| 361 | |
| 362 | const uint64_t src_addr_1 = src_addr + 0x10000; |
| 363 | const uint64_t src_addr_2 = src_addr + 0x20000; |
| 364 | const uint64_t src_addr_3 = src_addr + 0x30000; |
| 365 | const uint64_t digest_addr = src_addr + 0x40000; |
| 366 | uint8_t digest[48] = {0}; |
| 367 | struct AspeedSgList array[] = { |
| 368 | { cpu_to_le32(sizeof(test_vector_sg1)), |
| 369 | cpu_to_le32(src_addr_1) }, |
| 370 | { cpu_to_le32(sizeof(test_vector_sg2)), |
| 371 | cpu_to_le32(src_addr_2) }, |
| 372 | { cpu_to_le32(sizeof(test_vector_sg3) | SG_LIST_LEN_LAST), |
| 373 | cpu_to_le32(src_addr_3) }, |
| 374 | }; |
| 375 | |
| 376 | /* Check engine is idle, no busy or irq bits set */ |
| 377 | g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); |
| 378 | |
| 379 | /* Write test vector into memory */ |
| 380 | qtest_memwrite(s, src_addr_1, test_vector_sg1, sizeof(test_vector_sg1)); |
| 381 | qtest_memwrite(s, src_addr_2, test_vector_sg2, sizeof(test_vector_sg2)); |
| 382 | qtest_memwrite(s, src_addr_3, test_vector_sg3, sizeof(test_vector_sg3)); |
| 383 | qtest_memwrite(s, src_addr, array, sizeof(array)); |
| 384 | |
| 385 | write_regs(s, base, src_addr, |
| 386 | (sizeof(test_vector_sg1) |
| 387 | + sizeof(test_vector_sg2) |
| 388 | + sizeof(test_vector_sg3)), |
| 389 | digest_addr, HACE_ALGO_SHA384 | HACE_SG_EN); |
| 390 | |
| 391 | /* Check hash IRQ status is asserted */ |
| 392 | g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0x00000200); |
| 393 | |
| 394 | /* Clear IRQ status and check status is deasserted */ |
| 395 | qtest_writel(s, base + HACE_STS, 0x00000200); |
| 396 | g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); |
| 397 | |
| 398 | /* Read computed digest from memory */ |
| 399 | qtest_memread(s, digest_addr, digest, sizeof(digest)); |
| 400 | |
| 401 | /* Check result of computation */ |
| 402 | g_assert_cmpmem(digest, sizeof(digest), |
| 403 | test_result_sg_sha384, sizeof(digest)); |
| 404 | |
| 405 | qtest_quit(s); |
| 406 | } |
| 407 | |
| 408 | void aspeed_test_sha512_sg(const char *machine, const uint32_t base, |
| 409 | const uint64_t src_addr) |
| 410 | { |
| 411 | QTestState *s = qtest_init(machine); |
| 412 | |
| 413 | const uint64_t src_addr_1 = src_addr + 0x10000; |
| 414 | const uint64_t src_addr_2 = src_addr + 0x20000; |
| 415 | const uint64_t src_addr_3 = src_addr + 0x30000; |
| 416 | const uint64_t digest_addr = src_addr + 0x40000; |
| 417 | uint8_t digest[64] = {0}; |
| 418 | struct AspeedSgList array[] = { |
| 419 | { cpu_to_le32(sizeof(test_vector_sg1)), |
| 420 | cpu_to_le32(src_addr_1) }, |
| 421 | { cpu_to_le32(sizeof(test_vector_sg2)), |
| 422 | cpu_to_le32(src_addr_2) }, |
| 423 | { cpu_to_le32(sizeof(test_vector_sg3) | SG_LIST_LEN_LAST), |
| 424 | cpu_to_le32(src_addr_3) }, |
| 425 | }; |
| 426 | |
| 427 | /* Check engine is idle, no busy or irq bits set */ |
| 428 | g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); |
| 429 | |
| 430 | /* Write test vector into memory */ |
| 431 | qtest_memwrite(s, src_addr_1, test_vector_sg1, sizeof(test_vector_sg1)); |
| 432 | qtest_memwrite(s, src_addr_2, test_vector_sg2, sizeof(test_vector_sg2)); |
| 433 | qtest_memwrite(s, src_addr_3, test_vector_sg3, sizeof(test_vector_sg3)); |
| 434 | qtest_memwrite(s, src_addr, array, sizeof(array)); |
| 435 | |
| 436 | write_regs(s, base, src_addr, |
| 437 | (sizeof(test_vector_sg1) |
| 438 | + sizeof(test_vector_sg2) |
| 439 | + sizeof(test_vector_sg3)), |
| 440 | digest_addr, HACE_ALGO_SHA512 | HACE_SG_EN); |
| 441 | |
| 442 | /* Check hash IRQ status is asserted */ |
| 443 | g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0x00000200); |
| 444 | |
| 445 | /* Clear IRQ status and check status is deasserted */ |
| 446 | qtest_writel(s, base + HACE_STS, 0x00000200); |
| 447 | g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); |
| 448 | |
| 449 | /* Read computed digest from memory */ |
| 450 | qtest_memread(s, digest_addr, digest, sizeof(digest)); |
| 451 | |
| 452 | /* Check result of computation */ |
| 453 | g_assert_cmpmem(digest, sizeof(digest), |
| 454 | test_result_sg_sha512, sizeof(digest)); |
| 455 | |
| 456 | qtest_quit(s); |
| 457 | } |
| 458 | |
| 459 | void aspeed_test_sha256_accum(const char *machine, const uint32_t base, |
| 460 | const uint64_t src_addr) |
| 461 | { |
| 462 | QTestState *s = qtest_init(machine); |
| 463 | |
| 464 | const uint64_t buffer_addr = src_addr + 0x10000; |
| 465 | const uint64_t digest_addr = src_addr + 0x40000; |
| 466 | uint8_t digest[32] = {0}; |
| 467 | struct AspeedSgList array[] = { |
| 468 | { cpu_to_le32(sizeof(test_vector_accum_256) | SG_LIST_LEN_LAST), |
| 469 | cpu_to_le32(buffer_addr) }, |
| 470 | }; |
| 471 | |
| 472 | /* Check engine is idle, no busy or irq bits set */ |
| 473 | g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); |
| 474 | |
| 475 | /* Write test vector into memory */ |
| 476 | qtest_memwrite(s, buffer_addr, test_vector_accum_256, |
| 477 | sizeof(test_vector_accum_256)); |
| 478 | qtest_memwrite(s, src_addr, array, sizeof(array)); |
| 479 | |
| 480 | write_regs(s, base, src_addr, sizeof(test_vector_accum_256), |
| 481 | digest_addr, HACE_ALGO_SHA256 | HACE_SG_EN | HACE_ACCUM_EN); |
| 482 | |
| 483 | /* Check hash IRQ status is asserted */ |
| 484 | g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0x00000200); |
| 485 | |
| 486 | /* Clear IRQ status and check status is deasserted */ |
| 487 | qtest_writel(s, base + HACE_STS, 0x00000200); |
| 488 | g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); |
| 489 | |
| 490 | /* Read computed digest from memory */ |
| 491 | qtest_memread(s, digest_addr, digest, sizeof(digest)); |
| 492 | |
| 493 | /* Check result of computation */ |
| 494 | g_assert_cmpmem(digest, sizeof(digest), |
| 495 | test_result_accum_sha256, sizeof(digest)); |
| 496 | |
| 497 | qtest_quit(s); |
| 498 | } |
| 499 | |
| 500 | void aspeed_test_sha384_accum(const char *machine, const uint32_t base, |
| 501 | const uint64_t src_addr) |
| 502 | { |
| 503 | QTestState *s = qtest_init(machine); |
| 504 | |
| 505 | const uint64_t buffer_addr = src_addr + 0x10000; |
| 506 | const uint64_t digest_addr = src_addr + 0x40000; |
| 507 | uint8_t digest[48] = {0}; |
| 508 | struct AspeedSgList array[] = { |
| 509 | { cpu_to_le32(sizeof(test_vector_accum_384) | SG_LIST_LEN_LAST), |
| 510 | cpu_to_le32(buffer_addr) }, |
| 511 | }; |
| 512 | |
| 513 | /* Check engine is idle, no busy or irq bits set */ |
| 514 | g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); |
| 515 | |
| 516 | /* Write test vector into memory */ |
| 517 | qtest_memwrite(s, buffer_addr, test_vector_accum_384, |
| 518 | sizeof(test_vector_accum_384)); |
| 519 | qtest_memwrite(s, src_addr, array, sizeof(array)); |
| 520 | |
| 521 | write_regs(s, base, src_addr, sizeof(test_vector_accum_384), |
| 522 | digest_addr, HACE_ALGO_SHA384 | HACE_SG_EN | HACE_ACCUM_EN); |
| 523 | |
| 524 | /* Check hash IRQ status is asserted */ |
| 525 | g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0x00000200); |
| 526 | |
| 527 | /* Clear IRQ status and check status is deasserted */ |
| 528 | qtest_writel(s, base + HACE_STS, 0x00000200); |
| 529 | g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); |
| 530 | |
| 531 | /* Read computed digest from memory */ |
| 532 | qtest_memread(s, digest_addr, digest, sizeof(digest)); |
| 533 | |
| 534 | /* Check result of computation */ |
| 535 | g_assert_cmpmem(digest, sizeof(digest), |
| 536 | test_result_accum_sha384, sizeof(digest)); |
| 537 | |
| 538 | qtest_quit(s); |
| 539 | } |
| 540 | |
| 541 | void aspeed_test_sha512_accum(const char *machine, const uint32_t base, |
| 542 | const uint64_t src_addr) |
| 543 | { |
| 544 | QTestState *s = qtest_init(machine); |
| 545 | |
| 546 | const uint64_t buffer_addr = src_addr + 0x10000; |
| 547 | const uint64_t digest_addr = src_addr + 0x40000; |
| 548 | uint8_t digest[64] = {0}; |
| 549 | struct AspeedSgList array[] = { |
| 550 | { cpu_to_le32(sizeof(test_vector_accum_512) | SG_LIST_LEN_LAST), |
| 551 | cpu_to_le32(buffer_addr) }, |
| 552 | }; |
| 553 | |
| 554 | /* Check engine is idle, no busy or irq bits set */ |
| 555 | g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); |
| 556 | |
| 557 | /* Write test vector into memory */ |
| 558 | qtest_memwrite(s, buffer_addr, test_vector_accum_512, |
| 559 | sizeof(test_vector_accum_512)); |
| 560 | qtest_memwrite(s, src_addr, array, sizeof(array)); |
| 561 | |
| 562 | write_regs(s, base, src_addr, sizeof(test_vector_accum_512), |
| 563 | digest_addr, HACE_ALGO_SHA512 | HACE_SG_EN | HACE_ACCUM_EN); |
| 564 | |
| 565 | /* Check hash IRQ status is asserted */ |
| 566 | g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0x00000200); |
| 567 | |
| 568 | /* Clear IRQ status and check status is deasserted */ |
| 569 | qtest_writel(s, base + HACE_STS, 0x00000200); |
| 570 | g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); |
| 571 | |
| 572 | /* Read computed digest from memory */ |
| 573 | qtest_memread(s, digest_addr, digest, sizeof(digest)); |
| 574 | |
| 575 | /* Check result of computation */ |
| 576 | g_assert_cmpmem(digest, sizeof(digest), |
| 577 | test_result_accum_sha512, sizeof(digest)); |
| 578 | |
| 579 | qtest_quit(s); |
| 580 | } |
| 581 | |
| 582 | void aspeed_test_addresses(const char *machine, const uint32_t base, |
| 583 | const struct AspeedMasks *expected) |
| 584 | { |
| 585 | QTestState *s = qtest_init(machine); |
| 586 | |
| 587 | /* |
| 588 | * Check command mode is zero, meaning engine is in direct access mode, |
| 589 | * as this affects the masking behavior of the HASH_SRC register. |
| 590 | */ |
| 591 | g_assert_cmphex(qtest_readl(s, base + HACE_CMD), ==, 0); |
| 592 | g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC), ==, 0); |
| 593 | g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC_HI), ==, 0); |
| 594 | g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST), ==, 0); |
| 595 | g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST_HI), ==, 0); |
| 596 | g_assert_cmphex(qtest_readl(s, base + HACE_HASH_KEY_BUFF), ==, 0); |
| 597 | g_assert_cmphex(qtest_readl(s, base + HACE_HASH_KEY_BUFF_HI), ==, 0); |
| 598 | g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DATA_LEN), ==, 0); |
| 599 | |
| 600 | /* Check that the address masking is correct */ |
| 601 | qtest_writel(s, base + HACE_HASH_SRC, 0xffffffff); |
| 602 | g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC), ==, expected->src); |
| 603 | |
| 604 | qtest_writel(s, base + HACE_HASH_SRC_HI, 0xffffffff); |
| 605 | g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC_HI), |
| 606 | ==, expected->src_hi); |
| 607 | |
| 608 | qtest_writel(s, base + HACE_HASH_DIGEST, 0xffffffff); |
| 609 | g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST), ==, |
| 610 | expected->dest); |
| 611 | |
| 612 | qtest_writel(s, base + HACE_HASH_DIGEST_HI, 0xffffffff); |
| 613 | g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST_HI), ==, |
| 614 | expected->dest_hi); |
| 615 | |
| 616 | qtest_writel(s, base + HACE_HASH_KEY_BUFF, 0xffffffff); |
| 617 | g_assert_cmphex(qtest_readl(s, base + HACE_HASH_KEY_BUFF), ==, |
| 618 | expected->key); |
| 619 | |
| 620 | qtest_writel(s, base + HACE_HASH_KEY_BUFF_HI, 0xffffffff); |
| 621 | g_assert_cmphex(qtest_readl(s, base + HACE_HASH_KEY_BUFF_HI), ==, |
| 622 | expected->key_hi); |
| 623 | |
| 624 | qtest_writel(s, base + HACE_HASH_DATA_LEN, 0xffffffff); |
| 625 | g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DATA_LEN), ==, |
| 626 | expected->len); |
| 627 | |
| 628 | /* Reset to zero */ |
| 629 | qtest_writel(s, base + HACE_HASH_SRC, 0); |
| 630 | qtest_writel(s, base + HACE_HASH_SRC_HI, 0); |
| 631 | qtest_writel(s, base + HACE_HASH_DIGEST, 0); |
| 632 | qtest_writel(s, base + HACE_HASH_DIGEST_HI, 0); |
| 633 | qtest_writel(s, base + HACE_HASH_KEY_BUFF, 0); |
| 634 | qtest_writel(s, base + HACE_HASH_KEY_BUFF_HI, 0); |
| 635 | qtest_writel(s, base + HACE_HASH_DATA_LEN, 0); |
| 636 | |
| 637 | /* Check that all bits are now zero */ |
| 638 | g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC), ==, 0); |
| 639 | g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC_HI), ==, 0); |
| 640 | g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST), ==, 0); |
| 641 | g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST_HI), ==, 0); |
| 642 | g_assert_cmphex(qtest_readl(s, base + HACE_HASH_KEY_BUFF), ==, 0); |
| 643 | g_assert_cmphex(qtest_readl(s, base + HACE_HASH_KEY_BUFF_HI), ==, 0); |
| 644 | g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DATA_LEN), ==, 0); |
| 645 | |
| 646 | qtest_quit(s); |
| 647 | } |
| 648 | |
| 649 | /* |
| 650 | * Crypto engine register layout (offsets from the HACE base). |
| 651 | */ |
| 652 | #define HACE_CRYPTO_SRC 0x00 |
| 653 | #define HACE_CRYPTO_DEST 0x04 |
| 654 | #define HACE_CRYPTO_CONTEXT 0x08 |
| 655 | #define HACE_CRYPTO_DATA_LEN 0x0c |
| 656 | #define HACE_CRYPTO_CMD 0x10 |
| 657 | #define HACE_CRYPTO_GCM_ADD_LEN 0x14 |
| 658 | #define HACE_CRYPTO_GCM_TAG 0x18 |
| 659 | |
| 660 | /* Crypto command bits */ |
| 661 | #define HACE_CMD_ENCRYPT BIT(7) |
| 662 | #define HACE_CMD_ISR_EN BIT(12) |
| 663 | #define HACE_CMD_DES_SELECT BIT(16) |
| 664 | #define HACE_CMD_TRIPLE_DES BIT(17) |
| 665 | #define HACE_CMD_SRC_SG_CTRL BIT(18) |
| 666 | #define HACE_CMD_DST_SG_CTRL BIT(19) |
| 667 | #define HACE_CMD_OP_MODE_MASK (0x7 << 4) |
| 668 | #define HACE_CMD_ECB (0x0 << 4) |
| 669 | #define HACE_CMD_CBC (0x1 << 4) |
| 670 | #define HACE_CMD_CTR (0x4 << 4) |
| 671 | #define HACE_CMD_GCM (0x5 << 4) |
| 672 | #define HACE_CMD_AES128 (0x0 << 2) |
| 673 | #define HACE_CMD_AES256 (0x2 << 2) |
| 674 | |
| 675 | /* Context buffer layout: IV (DES at +8), key at +0x10 */ |
| 676 | #define HACE_CTX_KEY_OFFSET 0x10 |
| 677 | #define HACE_CTX_SIZE 0x30 |
| 678 | |
| 679 | /* |
| 680 | * Crypto known-answer test vectors, taken verbatim from the Linux kernel |
| 681 | * crypto self-test templates in crypto/testmgr.h: |
| 682 | * |
| 683 | * https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/crypto/testmgr.h?h=v6.18 |
| 684 | * |
| 685 | * The originating template is noted above each block. CTR and the longer CBC |
| 686 | * vectors are truncated to a single block (still a valid known-answer test as |
| 687 | * the first block only depends on the IV). |
| 688 | */ |
| 689 | |
| 690 | /* aes_tv_template[0] (FIPS-197) */ |
| 691 | static const uint8_t aes128_ecb_key[16] = { |
| 692 | 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, |
| 693 | 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f }; |
| 694 | static const uint8_t aes128_ecb_ptext[16] = { |
| 695 | 0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, |
| 696 | 0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff }; |
| 697 | static const uint8_t aes128_ecb_ctext[16] = { |
| 698 | 0x69, 0xc4, 0xe0, 0xd8, 0x6a, 0x7b, 0x04, 0x30, |
| 699 | 0xd8, 0xcd, 0xb7, 0x80, 0x70, 0xb4, 0xc5, 0x5a }; |
| 700 | |
| 701 | /* aes_cbc_tv_template[0] (RFC 3602) */ |
| 702 | static const uint8_t aes128_cbc_key[16] = { |
| 703 | 0x06, 0xa9, 0x21, 0x40, 0x36, 0xb8, 0xa1, 0x5b, |
| 704 | 0x51, 0x2e, 0x03, 0xd5, 0x34, 0x12, 0x00, 0x06 }; |
| 705 | static const uint8_t aes128_cbc_iv[16] = { |
| 706 | 0x3d, 0xaf, 0xba, 0x42, 0x9d, 0x9e, 0xb4, 0x30, |
| 707 | 0xb4, 0x22, 0xda, 0x80, 0x2c, 0x9f, 0xac, 0x41 }; |
| 708 | static const uint8_t aes128_cbc_ptext[16] = { |
| 709 | 0x53, 0x69, 0x6e, 0x67, 0x6c, 0x65, 0x20, 0x62, |
| 710 | 0x6c, 0x6f, 0x63, 0x6b, 0x20, 0x6d, 0x73, 0x67 }; |
| 711 | static const uint8_t aes128_cbc_ctext[16] = { |
| 712 | 0xe3, 0x53, 0x77, 0x9c, 0x10, 0x79, 0xae, 0xb8, |
| 713 | 0x27, 0x08, 0x94, 0x2d, 0xbe, 0x77, 0x18, 0x1a }; |
| 714 | static const uint8_t aes128_cbc_ivout[16] = { |
| 715 | 0xe3, 0x53, 0x77, 0x9c, 0x10, 0x79, 0xae, 0xb8, |
| 716 | 0x27, 0x08, 0x94, 0x2d, 0xbe, 0x77, 0x18, 0x1a }; |
| 717 | |
| 718 | /* des_tv_template[0] (Applied Cryptography) */ |
| 719 | static const uint8_t des_ecb_key[8] = { |
| 720 | 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef }; |
| 721 | static const uint8_t des_ecb_ptext[8] = { |
| 722 | 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xe7 }; |
| 723 | static const uint8_t des_ecb_ctext[8] = { |
| 724 | 0xc9, 0x57, 0x44, 0x25, 0x6a, 0x5e, 0xd3, 0x1d }; |
| 725 | |
| 726 | /* des_cbc_tv_template[0] (OpenSSL), first block */ |
| 727 | static const uint8_t des_cbc_key[8] = { |
| 728 | 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef }; |
| 729 | static const uint8_t des_cbc_iv[8] = { |
| 730 | 0xfe, 0xdc, 0xba, 0x98, 0x76, 0x54, 0x32, 0x10 }; |
| 731 | static const uint8_t des_cbc_ptext[8] = { |
| 732 | 0x37, 0x36, 0x35, 0x34, 0x33, 0x32, 0x31, 0x20 }; |
| 733 | static const uint8_t des_cbc_ctext[8] = { |
| 734 | 0xcc, 0xd1, 0x73, 0xff, 0xab, 0x20, 0x39, 0xf4 }; |
| 735 | |
| 736 | /* des3_ede_tv_template[0] (OpenSSL) */ |
| 737 | static const uint8_t tdes_ecb_key[24] = { |
| 738 | 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef, |
| 739 | 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, |
| 740 | 0xfe, 0xdc, 0xba, 0x98, 0x76, 0x54, 0x32, 0x10 }; |
| 741 | static const uint8_t tdes_ecb_ptext[8] = { |
| 742 | 0x73, 0x6f, 0x6d, 0x65, 0x64, 0x61, 0x74, 0x61 }; |
| 743 | static const uint8_t tdes_ecb_ctext[8] = { |
| 744 | 0x18, 0xd7, 0x48, 0xe5, 0x63, 0x62, 0x05, 0x72 }; |
| 745 | |
| 746 | /* des3_ede_cbc_tv_template[0] (OpenSSL), first block */ |
| 747 | static const uint8_t tdes_cbc_key[24] = { |
| 748 | 0xe9, 0xc0, 0xff, 0x2e, 0x76, 0x0b, 0x64, 0x24, |
| 749 | 0x44, 0x4d, 0x99, 0x5a, 0x12, 0xd6, 0x40, 0xc0, |
| 750 | 0xea, 0xc2, 0x84, 0xe8, 0x14, 0x95, 0xdb, 0xe8 }; |
| 751 | static const uint8_t tdes_cbc_iv[8] = { |
| 752 | 0x7d, 0x33, 0x88, 0x93, 0x0f, 0x93, 0xb2, 0x42 }; |
| 753 | static const uint8_t tdes_cbc_ptext[8] = { |
| 754 | 0x6f, 0x54, 0x20, 0x6f, 0x61, 0x4d, 0x79, 0x6e }; |
| 755 | static const uint8_t tdes_cbc_ctext[8] = { |
| 756 | 0x0e, 0x2d, 0xb6, 0x97, 0x3c, 0x56, 0x33, 0xf4 }; |
| 757 | |
| 758 | /* aes_ctr_tv_template[0] (NIST SP800-38A F.5.1), first block */ |
| 759 | static const uint8_t aes128_ctr_key[16] = { |
| 760 | 0x2b, 0x7e, 0x15, 0x16, 0x28, 0xae, 0xd2, 0xa6, |
| 761 | 0xab, 0xf7, 0x15, 0x88, 0x09, 0xcf, 0x4f, 0x3c }; |
| 762 | static const uint8_t aes128_ctr_iv[16] = { |
| 763 | 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, |
| 764 | 0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff }; |
| 765 | static const uint8_t aes128_ctr_ptext[16] = { |
| 766 | 0x6b, 0xc1, 0xbe, 0xe2, 0x2e, 0x40, 0x9f, 0x96, |
| 767 | 0xe9, 0x3d, 0x7e, 0x11, 0x73, 0x93, 0x17, 0x2a }; |
| 768 | static const uint8_t aes128_ctr_ctext[16] = { |
| 769 | 0x87, 0x4d, 0x61, 0x91, 0xb6, 0x20, 0xe3, 0x26, |
| 770 | 0x1b, 0xef, 0x68, 0x64, 0x99, 0x0d, 0xb6, 0xce }; |
| 771 | static const uint8_t aes128_ctr_ivout[16] = { |
| 772 | 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, |
| 773 | 0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xff, 0x00 }; |
| 774 | |
| 775 | /* des_ctr_tv_template[0] (Crypto++), first block */ |
| 776 | static const uint8_t des_ctr_key[8] = { |
| 777 | 0xc9, 0x83, 0xa6, 0xc9, 0xec, 0x0f, 0x32, 0x55 }; |
| 778 | static const uint8_t des_ctr_iv[8] = { |
| 779 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd }; |
| 780 | static const uint8_t des_ctr_ptext[8] = { |
| 781 | 0x50, 0xb9, 0x22, 0xae, 0x17, 0x80, 0x0c, 0x75 }; |
| 782 | static const uint8_t des_ctr_ctext[8] = { |
| 783 | 0x2f, 0x96, 0x06, 0x0f, 0x50, 0xc9, 0x68, 0x03 }; |
| 784 | static const uint8_t des_ctr_ivout[8] = { |
| 785 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe }; |
| 786 | |
| 787 | /* des3_ede_ctr_tv_template[0] (Crypto++), first block */ |
| 788 | static const uint8_t tdes_ctr_key[24] = { |
| 789 | 0x9c, 0xd6, 0xf3, 0x9c, 0xb9, 0x5a, 0x67, 0x00, |
| 790 | 0x5a, 0x67, 0x00, 0x2d, 0xce, 0xeb, 0x2d, 0xce, |
| 791 | 0xeb, 0xb4, 0x51, 0x72, 0xb4, 0x51, 0x72, 0x1f }; |
| 792 | static const uint8_t tdes_ctr_iv[8] = { |
| 793 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; |
| 794 | static const uint8_t tdes_ctr_ptext[8] = { |
| 795 | 0x05, 0xec, 0x77, 0xfb, 0x42, 0xd5, 0x59, 0x20 }; |
| 796 | static const uint8_t tdes_ctr_ctext[8] = { |
| 797 | 0x07, 0xc2, 0x08, 0x20, 0x72, 0x1f, 0x49, 0xef }; |
| 798 | static const uint8_t tdes_ctr_ivout[8] = { |
| 799 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; |
| 800 | |
| 801 | /* |
| 802 | * aes_gcm_tv_template[2] (AES-128) and [9] (AES-256), from the McGrew & Viega |
| 803 | * GCM spec (also NIST SP 800-38D), no AAD. Both cases share this plaintext/IV. |
| 804 | */ |
| 805 | static const uint8_t aes_gcm_ptext[64] = { |
| 806 | 0xd9, 0x31, 0x32, 0x25, 0xf8, 0x84, 0x06, 0xe5, |
| 807 | 0xa5, 0x59, 0x09, 0xc5, 0xaf, 0xf5, 0x26, 0x9a, |
| 808 | 0x86, 0xa7, 0xa9, 0x53, 0x15, 0x34, 0xf7, 0xda, |
| 809 | 0x2e, 0x4c, 0x30, 0x3d, 0x8a, 0x31, 0x8a, 0x72, |
| 810 | 0x1c, 0x3c, 0x0c, 0x95, 0x95, 0x68, 0x09, 0x53, |
| 811 | 0x2f, 0xcf, 0x0e, 0x24, 0x49, 0xa6, 0xb5, 0x25, |
| 812 | 0xb1, 0x6a, 0xed, 0xf5, 0xaa, 0x0d, 0xe6, 0x57, |
| 813 | 0xba, 0x63, 0x7b, 0x39, 0x1a, 0xaf, 0xd2, 0x55 }; |
| 814 | static const uint8_t aes_gcm_iv[12] = { |
| 815 | 0xca, 0xfe, 0xba, 0xbe, 0xfa, 0xce, 0xdb, 0xad, |
| 816 | 0xde, 0xca, 0xf8, 0x88 }; |
| 817 | |
| 818 | /* aes_gcm_tv_template[2] (AES-128) */ |
| 819 | static const uint8_t aes128_gcm_key[16] = { |
| 820 | 0xfe, 0xff, 0xe9, 0x92, 0x86, 0x65, 0x73, 0x1c, |
| 821 | 0x6d, 0x6a, 0x8f, 0x94, 0x67, 0x30, 0x83, 0x08 }; |
| 822 | static const uint8_t aes128_gcm_ctext[64] = { |
| 823 | 0x42, 0x83, 0x1e, 0xc2, 0x21, 0x77, 0x74, 0x24, |
| 824 | 0x4b, 0x72, 0x21, 0xb7, 0x84, 0xd0, 0xd4, 0x9c, |
| 825 | 0xe3, 0xaa, 0x21, 0x2f, 0x2c, 0x02, 0xa4, 0xe0, |
| 826 | 0x35, 0xc1, 0x7e, 0x23, 0x29, 0xac, 0xa1, 0x2e, |
| 827 | 0x21, 0xd5, 0x14, 0xb2, 0x54, 0x66, 0x93, 0x1c, |
| 828 | 0x7d, 0x8f, 0x6a, 0x5a, 0xac, 0x84, 0xaa, 0x05, |
| 829 | 0x1b, 0xa3, 0x0b, 0x39, 0x6a, 0x0a, 0xac, 0x97, |
| 830 | 0x3d, 0x58, 0xe0, 0x91, 0x47, 0x3f, 0x59, 0x85 }; |
| 831 | static const uint8_t aes128_gcm_tag[16] = { |
| 832 | 0x4d, 0x5c, 0x2a, 0xf3, 0x27, 0xcd, 0x64, 0xa6, |
| 833 | 0x2c, 0xf3, 0x5a, 0xbd, 0x2b, 0xa6, 0xfa, 0xb4 }; |
| 834 | |
| 835 | /* aes_gcm_tv_template[9] (AES-256) */ |
| 836 | static const uint8_t aes256_gcm_key[32] = { |
| 837 | 0xfe, 0xff, 0xe9, 0x92, 0x86, 0x65, 0x73, 0x1c, |
| 838 | 0x6d, 0x6a, 0x8f, 0x94, 0x67, 0x30, 0x83, 0x08, |
| 839 | 0xfe, 0xff, 0xe9, 0x92, 0x86, 0x65, 0x73, 0x1c, |
| 840 | 0x6d, 0x6a, 0x8f, 0x94, 0x67, 0x30, 0x83, 0x08 }; |
| 841 | static const uint8_t aes256_gcm_ctext[64] = { |
| 842 | 0x52, 0x2d, 0xc1, 0xf0, 0x99, 0x56, 0x7d, 0x07, |
| 843 | 0xf4, 0x7f, 0x37, 0xa3, 0x2a, 0x84, 0x42, 0x7d, |
| 844 | 0x64, 0x3a, 0x8c, 0xdc, 0xbf, 0xe5, 0xc0, 0xc9, |
| 845 | 0x75, 0x98, 0xa2, 0xbd, 0x25, 0x55, 0xd1, 0xaa, |
| 846 | 0x8c, 0xb0, 0x8e, 0x48, 0x59, 0x0d, 0xbb, 0x3d, |
| 847 | 0xa7, 0xb0, 0x8b, 0x10, 0x56, 0x82, 0x88, 0x38, |
| 848 | 0xc5, 0xf6, 0x1e, 0x63, 0x93, 0xba, 0x7a, 0x0a, |
| 849 | 0xbc, 0xc9, 0xf6, 0x62, 0x89, 0x80, 0x15, 0xad }; |
| 850 | static const uint8_t aes256_gcm_tag[16] = { |
| 851 | 0xb0, 0x94, 0xda, 0xc5, 0xd9, 0x34, 0x71, 0xbd, |
| 852 | 0xec, 0x1a, 0x50, 0x22, 0x70, 0xe3, 0xcc, 0x6c }; |
| 853 | |
| 854 | typedef struct CryptTest { |
| 855 | QCryptoCipherMode mode; |
| 856 | QCryptoCipherAlgo alg; |
| 857 | /* expected context IV after encrypt, or NULL */ |
| 858 | const uint8_t *iv_out; |
| 859 | const uint8_t *ptext; |
| 860 | const uint8_t *ctext; |
| 861 | /* expected GCM authentication tag, or NULL for non-AEAD modes */ |
| 862 | const uint8_t *tag; |
| 863 | const uint8_t *key; |
| 864 | const uint8_t *iv; |
| 865 | const char *name; |
| 866 | size_t keylen; |
| 867 | size_t taglen; |
| 868 | /* algorithm | mode | key size selection */ |
| 869 | uint32_t cmd; |
| 870 | size_t ivlen; |
| 871 | size_t len; |
| 872 | } CryptTest; |
| 873 | |
| 874 | static const CryptTest crypt_tests[] = { |
| 875 | { |
| 876 | .name = "aes128-ecb", |
| 877 | .cmd = HACE_CMD_AES128 | HACE_CMD_ECB, |
| 878 | .alg = QCRYPTO_CIPHER_ALGO_AES_128, |
| 879 | .mode = QCRYPTO_CIPHER_MODE_ECB, |
| 880 | .key = aes128_ecb_key, |
| 881 | .keylen = sizeof(aes128_ecb_key), |
| 882 | .ptext = aes128_ecb_ptext, |
| 883 | .ctext = aes128_ecb_ctext, |
| 884 | .len = sizeof(aes128_ecb_ptext), |
| 885 | }, |
| 886 | { |
| 887 | .name = "aes128-cbc", |
| 888 | .cmd = HACE_CMD_AES128 | HACE_CMD_CBC, |
| 889 | .alg = QCRYPTO_CIPHER_ALGO_AES_128, |
| 890 | .mode = QCRYPTO_CIPHER_MODE_CBC, |
| 891 | .key = aes128_cbc_key, |
| 892 | .keylen = sizeof(aes128_cbc_key), |
| 893 | .iv = aes128_cbc_iv, |
| 894 | .ivlen = sizeof(aes128_cbc_iv), |
| 895 | .ptext = aes128_cbc_ptext, |
| 896 | .ctext = aes128_cbc_ctext, |
| 897 | .iv_out = aes128_cbc_ivout, |
| 898 | .len = sizeof(aes128_cbc_ptext), |
| 899 | }, |
| 900 | { |
| 901 | .name = "des-ecb", |
| 902 | .cmd = HACE_CMD_DES_SELECT | HACE_CMD_ECB, |
| 903 | .alg = QCRYPTO_CIPHER_ALGO_DES, |
| 904 | .mode = QCRYPTO_CIPHER_MODE_ECB, |
| 905 | .key = des_ecb_key, |
| 906 | .keylen = sizeof(des_ecb_key), |
| 907 | .ptext = des_ecb_ptext, |
| 908 | .ctext = des_ecb_ctext, |
| 909 | .len = sizeof(des_ecb_ptext), |
| 910 | }, |
| 911 | { |
| 912 | .name = "des-cbc", |
| 913 | .cmd = HACE_CMD_DES_SELECT | HACE_CMD_CBC, |
| 914 | .alg = QCRYPTO_CIPHER_ALGO_DES, |
| 915 | .mode = QCRYPTO_CIPHER_MODE_CBC, |
| 916 | .key = des_cbc_key, |
| 917 | .keylen = sizeof(des_cbc_key), |
| 918 | .iv = des_cbc_iv, |
| 919 | .ivlen = sizeof(des_cbc_iv), |
| 920 | .ptext = des_cbc_ptext, |
| 921 | .ctext = des_cbc_ctext, |
| 922 | .len = sizeof(des_cbc_ptext), |
| 923 | }, |
| 924 | { |
| 925 | .name = "des3_ede-ecb", |
| 926 | .cmd = HACE_CMD_DES_SELECT | HACE_CMD_TRIPLE_DES | HACE_CMD_ECB, |
| 927 | .alg = QCRYPTO_CIPHER_ALGO_3DES, |
| 928 | .mode = QCRYPTO_CIPHER_MODE_ECB, |
| 929 | .key = tdes_ecb_key, |
| 930 | .keylen = sizeof(tdes_ecb_key), |
| 931 | .ptext = tdes_ecb_ptext, |
| 932 | .ctext = tdes_ecb_ctext, |
| 933 | .len = sizeof(tdes_ecb_ptext), |
| 934 | }, |
| 935 | { |
| 936 | .name = "des3_ede-cbc", |
| 937 | .cmd = HACE_CMD_DES_SELECT | HACE_CMD_TRIPLE_DES | HACE_CMD_CBC, |
| 938 | .alg = QCRYPTO_CIPHER_ALGO_3DES, |
| 939 | .mode = QCRYPTO_CIPHER_MODE_CBC, |
| 940 | .key = tdes_cbc_key, |
| 941 | .keylen = sizeof(tdes_cbc_key), |
| 942 | .iv = tdes_cbc_iv, |
| 943 | .ivlen = sizeof(tdes_cbc_iv), |
| 944 | .ptext = tdes_cbc_ptext, |
| 945 | .ctext = tdes_cbc_ctext, |
| 946 | .len = sizeof(tdes_cbc_ptext), |
| 947 | }, |
| 948 | { |
| 949 | .name = "aes128-ctr", |
| 950 | .cmd = HACE_CMD_AES128 | HACE_CMD_CTR, |
| 951 | .alg = QCRYPTO_CIPHER_ALGO_AES_128, |
| 952 | .mode = QCRYPTO_CIPHER_MODE_CTR, |
| 953 | .key = aes128_ctr_key, |
| 954 | .keylen = sizeof(aes128_ctr_key), |
| 955 | .iv = aes128_ctr_iv, |
| 956 | .ivlen = sizeof(aes128_ctr_iv), |
| 957 | .ptext = aes128_ctr_ptext, |
| 958 | .ctext = aes128_ctr_ctext, |
| 959 | .iv_out = aes128_ctr_ivout, |
| 960 | .len = sizeof(aes128_ctr_ptext), |
| 961 | }, |
| 962 | { |
| 963 | .name = "des-ctr", |
| 964 | .cmd = HACE_CMD_DES_SELECT | HACE_CMD_CTR, |
| 965 | .alg = QCRYPTO_CIPHER_ALGO_DES, |
| 966 | .mode = QCRYPTO_CIPHER_MODE_CTR, |
| 967 | .key = des_ctr_key, |
| 968 | .keylen = sizeof(des_ctr_key), |
| 969 | .iv = des_ctr_iv, |
| 970 | .ivlen = sizeof(des_ctr_iv), |
| 971 | .ptext = des_ctr_ptext, |
| 972 | .ctext = des_ctr_ctext, |
| 973 | .iv_out = des_ctr_ivout, |
| 974 | .len = sizeof(des_ctr_ptext), |
| 975 | }, |
| 976 | { |
| 977 | .name = "des3_ede-ctr", |
| 978 | .cmd = HACE_CMD_DES_SELECT | HACE_CMD_TRIPLE_DES | HACE_CMD_CTR, |
| 979 | .alg = QCRYPTO_CIPHER_ALGO_3DES, |
| 980 | .mode = QCRYPTO_CIPHER_MODE_CTR, |
| 981 | .key = tdes_ctr_key, |
| 982 | .keylen = sizeof(tdes_ctr_key), |
| 983 | .iv = tdes_ctr_iv, |
| 984 | .ivlen = sizeof(tdes_ctr_iv), |
| 985 | .ptext = tdes_ctr_ptext, |
| 986 | .ctext = tdes_ctr_ctext, |
| 987 | .iv_out = tdes_ctr_ivout, |
| 988 | .len = sizeof(tdes_ctr_ptext), |
| 989 | }, |
| 990 | { |
| 991 | .name = "aes128-gcm", |
| 992 | .cmd = HACE_CMD_AES128 | HACE_CMD_GCM, |
| 993 | .alg = QCRYPTO_CIPHER_ALGO_AES_128, |
| 994 | .mode = QCRYPTO_CIPHER_MODE_GCM, |
| 995 | .key = aes128_gcm_key, |
| 996 | .keylen = sizeof(aes128_gcm_key), |
| 997 | .iv = aes_gcm_iv, |
| 998 | .ivlen = sizeof(aes_gcm_iv), |
| 999 | .ptext = aes_gcm_ptext, |
| 1000 | .ctext = aes128_gcm_ctext, |
| 1001 | .tag = aes128_gcm_tag, |
| 1002 | .taglen = sizeof(aes128_gcm_tag), |
| 1003 | .len = sizeof(aes_gcm_ptext), |
| 1004 | }, |
| 1005 | { |
| 1006 | .name = "aes256-gcm", |
| 1007 | .cmd = HACE_CMD_AES256 | HACE_CMD_GCM, |
| 1008 | .alg = QCRYPTO_CIPHER_ALGO_AES_256, |
| 1009 | .mode = QCRYPTO_CIPHER_MODE_GCM, |
| 1010 | .key = aes256_gcm_key, |
| 1011 | .keylen = sizeof(aes256_gcm_key), |
| 1012 | .iv = aes_gcm_iv, |
| 1013 | .ivlen = sizeof(aes_gcm_iv), |
| 1014 | .ptext = aes_gcm_ptext, |
| 1015 | .ctext = aes256_gcm_ctext, |
| 1016 | .tag = aes256_gcm_tag, |
| 1017 | .taglen = sizeof(aes256_gcm_tag), |
| 1018 | .len = sizeof(aes_gcm_ptext), |
| 1019 | }, |
| 1020 | }; |
| 1021 | |
| 1022 | /* DRAM offsets for the crypto test source, destination and context buffers. */ |
| 1023 | #define CRYPT_OFF_SRC 0x10000 |
| 1024 | #define CRYPT_OFF_DST 0x20000 |
| 1025 | #define CRYPT_OFF_CTX 0x30000 |
| 1026 | /* Scatter-gather list offsets (each list has CRYPT_SG_FRAGS entries). */ |
| 1027 | #define CRYPT_OFF_SRC_SG 0x40000 |
| 1028 | #define CRYPT_OFF_DST_SG 0x50000 |
| 1029 | /* |
| 1030 | * The scatter-gather tests split each buffer into CRYPT_SG_FRAGS fragments, |
| 1031 | * each placed CRYPT_SG_FRAG_STRIDE apart so the fragments never abut. The gaps |
| 1032 | * make the test fail if the engine ignores the list and reads one contiguous |
| 1033 | * block. |
| 1034 | */ |
| 1035 | #define CRYPT_SG_FRAGS 3 |
| 1036 | #define CRYPT_SG_FRAG_STRIDE 0x1000 |
| 1037 | /* DRAM offset for the AES-GCM authentication tag write buffer. */ |
| 1038 | #define CRYPT_OFF_TAG 0x60000 |
| 1039 | |
| 1040 | /* Describes one registered crypto test (qtest_add_data_func() data pointer). */ |
| 1041 | typedef struct AspeedCryptoTest { |
| 1042 | const char *machine; |
| 1043 | uint64_t dram; |
| 1044 | uint32_t base; |
| 1045 | int index; |
| 1046 | bool sg; |
| 1047 | } AspeedCryptoTest; |
| 1048 | |
| 1049 | /* Map a command's operation mode (HACE10[6:4]) to a CRYPT_MODE_* flag. */ |
| 1050 | static uint32_t crypt_mode_flag(uint32_t cmd) |
| 1051 | { |
| 1052 | switch (cmd & HACE_CMD_OP_MODE_MASK) { |
| 1053 | case HACE_CMD_ECB: |
| 1054 | return CRYPT_MODE_ECB; |
| 1055 | case HACE_CMD_CBC: |
| 1056 | return CRYPT_MODE_CBC; |
| 1057 | case HACE_CMD_CTR: |
| 1058 | return CRYPT_MODE_CTR; |
| 1059 | case HACE_CMD_GCM: |
| 1060 | return CRYPT_MODE_GCM; |
| 1061 | default: |
| 1062 | return 0; |
| 1063 | } |
| 1064 | } |
| 1065 | |
| 1066 | static void crypt_write_ctx(QTestState *s, uint64_t ctx_addr, |
| 1067 | const CryptTest *t) |
| 1068 | { |
| 1069 | size_t iv_off = (t->cmd & HACE_CMD_DES_SELECT) ? 8 : 0; |
| 1070 | uint8_t ctx[HACE_CTX_SIZE] = { 0 }; |
| 1071 | |
| 1072 | if (t->iv) { |
| 1073 | memcpy(ctx + iv_off, t->iv, t->ivlen); |
| 1074 | } |
| 1075 | memcpy(ctx + HACE_CTX_KEY_OFFSET, t->key, t->keylen); |
| 1076 | qtest_memwrite(s, ctx_addr, ctx, sizeof(ctx)); |
| 1077 | } |
| 1078 | |
| 1079 | /* Run one crypto operation in direct access mode and read back the result. */ |
| 1080 | static void crypt_run_direct(QTestState *s, uint32_t base, uint64_t dram, |
| 1081 | const CryptTest *t, bool encrypt, uint8_t *out) |
| 1082 | { |
| 1083 | const uint8_t *in = encrypt ? t->ptext : t->ctext; |
| 1084 | uint32_t cmd = t->cmd | HACE_CMD_ISR_EN; |
| 1085 | uint64_t src = dram + CRYPT_OFF_SRC; |
| 1086 | uint64_t dst = dram + CRYPT_OFF_DST; |
| 1087 | uint64_t ctx = dram + CRYPT_OFF_CTX; |
| 1088 | |
| 1089 | if (encrypt) { |
| 1090 | cmd |= HACE_CMD_ENCRYPT; |
| 1091 | } |
| 1092 | |
| 1093 | crypt_write_ctx(s, ctx, t); |
| 1094 | qtest_memwrite(s, src, in, t->len); |
| 1095 | |
| 1096 | qtest_writel(s, base + HACE_CRYPTO_SRC, (uint32_t)src); |
| 1097 | qtest_writel(s, base + HACE_CRYPTO_DEST, (uint32_t)dst); |
| 1098 | qtest_writel(s, base + HACE_CRYPTO_CONTEXT, (uint32_t)ctx); |
| 1099 | qtest_writel(s, base + HACE_CRYPTO_DATA_LEN, t->len); |
| 1100 | qtest_writel(s, base + HACE_CRYPTO_CMD, cmd); |
| 1101 | |
| 1102 | g_assert_cmphex(qtest_readl(s, base + HACE_STS) & HACE_CRYPTO_ISR, ==, |
| 1103 | HACE_CRYPTO_ISR); |
| 1104 | qtest_writel(s, base + HACE_STS, HACE_CRYPTO_ISR); |
| 1105 | |
| 1106 | qtest_memread(s, dst, out, t->len); |
| 1107 | } |
| 1108 | |
| 1109 | /* |
| 1110 | * Byte range [*frag_off, *frag_off + *frag_len) of fragment @index when an |
| 1111 | * @len-byte buffer is split into CRYPT_SG_FRAGS pieces; the last piece takes |
| 1112 | * the remainder of an uneven split. |
| 1113 | */ |
| 1114 | static void crypt_frag_range(uint32_t len, int index, |
| 1115 | uint32_t *frag_off, uint32_t *frag_len) |
| 1116 | { |
| 1117 | uint32_t base = len / CRYPT_SG_FRAGS; |
| 1118 | |
| 1119 | *frag_off = base * index; |
| 1120 | *frag_len = (index == CRYPT_SG_FRAGS - 1) ? len - *frag_off : base; |
| 1121 | } |
| 1122 | |
| 1123 | /* |
| 1124 | * Scatter [in, len) across CRYPT_SG_FRAGS buffers based at @base_off and spaced |
| 1125 | * CRYPT_SG_FRAG_STRIDE apart, then build the SG list describing them at @list. |
| 1126 | * When @in is NULL only the list is built (used for the destination, which the |
| 1127 | * engine fills in). |
| 1128 | */ |
| 1129 | static void crypt_make_sg(QTestState *s, uint64_t dram, uint32_t base_off, |
| 1130 | uint64_t list, const uint8_t *in, uint32_t len) |
| 1131 | { |
| 1132 | struct AspeedSgList sg[CRYPT_SG_FRAGS]; |
| 1133 | uint32_t frag_off; |
| 1134 | uint32_t frag_len; |
| 1135 | uint64_t buf; |
| 1136 | int i; |
| 1137 | |
| 1138 | for (i = 0; i < CRYPT_SG_FRAGS; i++) { |
| 1139 | crypt_frag_range(len, i, &frag_off, &frag_len); |
| 1140 | buf = dram + base_off + i * CRYPT_SG_FRAG_STRIDE; |
| 1141 | |
| 1142 | if (in) { |
| 1143 | qtest_memwrite(s, buf, in + frag_off, frag_len); |
| 1144 | } |
| 1145 | sg[i].len = cpu_to_le32(frag_len | (i == CRYPT_SG_FRAGS - 1 ? |
| 1146 | SG_LIST_LEN_LAST : 0)); |
| 1147 | sg[i].addr = cpu_to_le32((uint32_t)buf); |
| 1148 | } |
| 1149 | |
| 1150 | qtest_memwrite(s, list, sg, sizeof(sg)); |
| 1151 | } |
| 1152 | |
| 1153 | /* Gather a scatter-gathered result back from the CRYPT_SG_FRAGS buffers. */ |
| 1154 | static void crypt_gather_sg(QTestState *s, uint64_t dram, uint32_t base_off, |
| 1155 | uint8_t *out, uint32_t len) |
| 1156 | { |
| 1157 | uint32_t frag_off; |
| 1158 | uint32_t frag_len; |
| 1159 | int i; |
| 1160 | |
| 1161 | for (i = 0; i < CRYPT_SG_FRAGS; i++) { |
| 1162 | crypt_frag_range(len, i, &frag_off, &frag_len); |
| 1163 | qtest_memread(s, dram + base_off + i * CRYPT_SG_FRAG_STRIDE, |
| 1164 | out + frag_off, frag_len); |
| 1165 | } |
| 1166 | } |
| 1167 | |
| 1168 | /* |
| 1169 | * Run one block-cipher (ECB/CBC/CTR) operation in scatter-gather mode and read |
| 1170 | * back the result. The source and destination are each split across |
| 1171 | * CRYPT_SG_FRAGS non-adjacent DRAM buffers described by an SG list; the gaps |
| 1172 | * ensure the test fails if the engine ignores the list and reads one |
| 1173 | * contiguous block. |
| 1174 | */ |
| 1175 | static void crypt_run_sg(QTestState *s, uint32_t base, uint64_t dram, |
| 1176 | const CryptTest *t, bool encrypt, uint8_t *out) |
| 1177 | { |
| 1178 | const uint8_t *in = encrypt ? t->ptext : t->ctext; |
| 1179 | uint64_t src_sg = dram + CRYPT_OFF_SRC_SG; |
| 1180 | uint64_t dst_sg = dram + CRYPT_OFF_DST_SG; |
| 1181 | uint64_t ctx = dram + CRYPT_OFF_CTX; |
| 1182 | uint32_t cmd = t->cmd | HACE_CMD_ISR_EN | HACE_CMD_SRC_SG_CTRL | |
| 1183 | HACE_CMD_DST_SG_CTRL; |
| 1184 | |
| 1185 | if (encrypt) { |
| 1186 | cmd |= HACE_CMD_ENCRYPT; |
| 1187 | } |
| 1188 | |
| 1189 | crypt_write_ctx(s, ctx, t); |
| 1190 | crypt_make_sg(s, dram, CRYPT_OFF_SRC, src_sg, in, t->len); |
| 1191 | crypt_make_sg(s, dram, CRYPT_OFF_DST, dst_sg, NULL, t->len); |
| 1192 | |
| 1193 | qtest_writel(s, base + HACE_CRYPTO_SRC, (uint32_t)src_sg); |
| 1194 | qtest_writel(s, base + HACE_CRYPTO_DEST, (uint32_t)dst_sg); |
| 1195 | qtest_writel(s, base + HACE_CRYPTO_CONTEXT, (uint32_t)ctx); |
| 1196 | qtest_writel(s, base + HACE_CRYPTO_DATA_LEN, t->len); |
| 1197 | qtest_writel(s, base + HACE_CRYPTO_CMD, cmd); |
| 1198 | |
| 1199 | g_assert_cmphex(qtest_readl(s, base + HACE_STS) & HACE_CRYPTO_ISR, ==, |
| 1200 | HACE_CRYPTO_ISR); |
| 1201 | qtest_writel(s, base + HACE_STS, HACE_CRYPTO_ISR); |
| 1202 | |
| 1203 | crypt_gather_sg(s, dram, CRYPT_OFF_DST, out, t->len); |
| 1204 | } |
| 1205 | |
| 1206 | /* |
| 1207 | * Run one AES-GCM operation in scatter-gather mode: like crypt_run_sg() but |
| 1208 | * also program the tag write buffer (HACE18) with no associated data, and read |
| 1209 | * the authentication tag back into @out_tag. |
| 1210 | */ |
| 1211 | static void crypt_run_gcm(QTestState *s, uint32_t base, uint64_t dram, |
| 1212 | const CryptTest *t, bool encrypt, uint8_t *out, |
| 1213 | uint8_t *out_tag) |
| 1214 | { |
| 1215 | const uint8_t *in = encrypt ? t->ptext : t->ctext; |
| 1216 | uint64_t src_sg = dram + CRYPT_OFF_SRC_SG; |
| 1217 | uint64_t dst_sg = dram + CRYPT_OFF_DST_SG; |
| 1218 | uint64_t ctx = dram + CRYPT_OFF_CTX; |
| 1219 | uint32_t cmd = t->cmd | HACE_CMD_ISR_EN | HACE_CMD_SRC_SG_CTRL | |
| 1220 | HACE_CMD_DST_SG_CTRL; |
| 1221 | |
| 1222 | if (encrypt) { |
| 1223 | cmd |= HACE_CMD_ENCRYPT; |
| 1224 | } |
| 1225 | |
| 1226 | crypt_write_ctx(s, ctx, t); |
| 1227 | crypt_make_sg(s, dram, CRYPT_OFF_SRC, src_sg, in, t->len); |
| 1228 | crypt_make_sg(s, dram, CRYPT_OFF_DST, dst_sg, NULL, t->len); |
| 1229 | |
| 1230 | qtest_writel(s, base + HACE_CRYPTO_SRC, (uint32_t)src_sg); |
| 1231 | qtest_writel(s, base + HACE_CRYPTO_DEST, (uint32_t)dst_sg); |
| 1232 | qtest_writel(s, base + HACE_CRYPTO_CONTEXT, (uint32_t)ctx); |
| 1233 | qtest_writel(s, base + HACE_CRYPTO_DATA_LEN, t->len); |
| 1234 | qtest_writel(s, base + HACE_CRYPTO_GCM_ADD_LEN, 0); |
| 1235 | qtest_writel(s, base + HACE_CRYPTO_GCM_TAG, |
| 1236 | (uint32_t)(dram + CRYPT_OFF_TAG)); |
| 1237 | qtest_writel(s, base + HACE_CRYPTO_CMD, cmd); |
| 1238 | |
| 1239 | g_assert_cmphex(qtest_readl(s, base + HACE_STS) & HACE_CRYPTO_ISR, ==, |
| 1240 | HACE_CRYPTO_ISR); |
| 1241 | qtest_writel(s, base + HACE_STS, HACE_CRYPTO_ISR); |
| 1242 | |
| 1243 | crypt_gather_sg(s, dram, CRYPT_OFF_DST, out, t->len); |
| 1244 | qtest_memread(s, dram + CRYPT_OFF_TAG, out_tag, t->taglen); |
| 1245 | } |
| 1246 | |
| 1247 | static void aspeed_test_crypto(const void *data) |
| 1248 | { |
| 1249 | const AspeedCryptoTest *c = data; |
| 1250 | const CryptTest *t = &crypt_tests[c->index]; |
| 1251 | QTestState *s = qtest_init(c->machine); |
| 1252 | uint8_t out[64]; |
| 1253 | uint8_t iv[16]; |
| 1254 | size_t iv_off; |
| 1255 | |
| 1256 | g_assert_cmpuint(t->len, <=, sizeof(out)); |
| 1257 | |
| 1258 | /* Encrypt: ptext -> ctext */ |
| 1259 | if (c->sg) { |
| 1260 | crypt_run_sg(s, c->base, c->dram, t, true, out); |
| 1261 | } else { |
| 1262 | crypt_run_direct(s, c->base, c->dram, t, true, out); |
| 1263 | } |
| 1264 | g_assert_cmpmem(out, t->len, t->ctext, t->len); |
| 1265 | |
| 1266 | if (t->iv_out) { |
| 1267 | iv_off = (t->cmd & HACE_CMD_DES_SELECT) ? 8 : 0; |
| 1268 | qtest_memread(s, c->dram + CRYPT_OFF_CTX + iv_off, iv, t->ivlen); |
| 1269 | g_assert_cmpmem(iv, t->ivlen, t->iv_out, t->ivlen); |
| 1270 | } |
| 1271 | |
| 1272 | /* Decrypt: ctext -> ptext */ |
| 1273 | if (c->sg) { |
| 1274 | crypt_run_sg(s, c->base, c->dram, t, false, out); |
| 1275 | } else { |
| 1276 | crypt_run_direct(s, c->base, c->dram, t, false, out); |
| 1277 | } |
| 1278 | g_assert_cmpmem(out, t->len, t->ptext, t->len); |
| 1279 | |
| 1280 | qtest_quit(s); |
| 1281 | } |
| 1282 | |
| 1283 | static void aspeed_test_crypto_gcm(const void *data) |
| 1284 | { |
| 1285 | const AspeedCryptoTest *c = data; |
| 1286 | const CryptTest *t = &crypt_tests[c->index]; |
| 1287 | QTestState *s = qtest_init(c->machine); |
| 1288 | uint8_t out[64]; |
| 1289 | uint8_t tag[16]; |
| 1290 | |
| 1291 | g_assert_cmpuint(t->len, <=, sizeof(out)); |
| 1292 | |
| 1293 | /* Encrypt: ptext -> ctext, then check the authentication tag. */ |
| 1294 | crypt_run_gcm(s, c->base, c->dram, t, true, out, tag); |
| 1295 | g_assert_cmpmem(out, t->len, t->ctext, t->len); |
| 1296 | g_assert_cmpmem(tag, t->taglen, t->tag, t->taglen); |
| 1297 | |
| 1298 | /* Decrypt: ctext -> ptext, the recomputed tag must match. */ |
| 1299 | crypt_run_gcm(s, c->base, c->dram, t, false, out, tag); |
| 1300 | g_assert_cmpmem(out, t->len, t->ptext, t->len); |
| 1301 | g_assert_cmpmem(tag, t->taglen, t->tag, t->taglen); |
| 1302 | |
| 1303 | qtest_quit(s); |
| 1304 | } |
| 1305 | |
| 1306 | void aspeed_add_crypto_tests(const char *prefix, const char *machine, |
| 1307 | uint32_t base, uint64_t dram, uint32_t modes, |
| 1308 | bool sg) |
| 1309 | { |
| 1310 | int i; |
| 1311 | |
| 1312 | for (i = 0; i < ARRAY_SIZE(crypt_tests); i++) { |
| 1313 | bool is_gcm = crypt_tests[i].mode == QCRYPTO_CIPHER_MODE_GCM; |
| 1314 | g_autofree char *path = NULL; |
| 1315 | AspeedCryptoTest *t; |
| 1316 | |
| 1317 | if (!(modes & crypt_mode_flag(crypt_tests[i].cmd))) { |
| 1318 | continue; |
| 1319 | } |
| 1320 | |
| 1321 | if (!qcrypto_cipher_supports(crypt_tests[i].alg, |
| 1322 | crypt_tests[i].mode)) { |
| 1323 | g_printerr("# skip unsupported %s\n", crypt_tests[i].name); |
| 1324 | continue; |
| 1325 | } |
| 1326 | |
| 1327 | path = g_strdup_printf("%s/hace/crypto/%s", prefix, |
| 1328 | crypt_tests[i].name); |
| 1329 | t = g_new0(AspeedCryptoTest, 1); |
| 1330 | t->machine = machine; |
| 1331 | t->base = base; |
| 1332 | t->dram = dram; |
| 1333 | t->index = i; |
| 1334 | t->sg = sg; |
| 1335 | qtest_add_data_func_full(path, t, |
| 1336 | is_gcm ? aspeed_test_crypto_gcm : |
| 1337 | aspeed_test_crypto, g_free); |
| 1338 | } |
| 1339 | } |
| 1340 |