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1 /*
2 * QTest testcase for the ASPEED Hash and Crypto Engine
3 *
4 * SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2021 IBM Corp.
6 */
7
8 #ifndef TESTS_ASPEED_HACE_UTILS_H
9 #define TESTS_ASPEED_HACE_UTILS_H
10
11 #include "libqtest.h"
12 #include "qemu/bitops.h"
13
14 #define HACE_CMD 0x10
15 #define HACE_SHA_BE_EN BIT(3)
16 #define HACE_MD5_LE_EN BIT(2)
17 #define HACE_ALGO_MD5 0
18 #define HACE_ALGO_SHA1 BIT(5)
19 #define HACE_ALGO_SHA224 BIT(6)
20 #define HACE_ALGO_SHA256 (BIT(4) | BIT(6))
21 #define HACE_ALGO_SHA512 (BIT(5) | BIT(6))
22 #define HACE_ALGO_SHA384 (BIT(5) | BIT(6) | BIT(10))
23 #define HACE_SG_EN BIT(18)
24 #define HACE_ACCUM_EN BIT(8)
25
26 #define HACE_STS 0x1c
27 #define HACE_RSA_ISR BIT(13)
28 #define HACE_CRYPTO_ISR BIT(12)
29 #define HACE_HASH_ISR BIT(9)
30 #define HACE_RSA_BUSY BIT(2)
31 #define HACE_CRYPTO_BUSY BIT(1)
32 #define HACE_HASH_BUSY BIT(0)
33 #define HACE_HASH_SRC 0x20
34 #define HACE_HASH_DIGEST 0x24
35 #define HACE_HASH_KEY_BUFF 0x28
36 #define HACE_HASH_DATA_LEN 0x2c
37 #define HACE_HASH_CMD 0x30
38 #define HACE_HASH_SRC_HI 0x90
39 #define HACE_HASH_DIGEST_HI 0x94
40 #define HACE_HASH_KEY_BUFF_HI 0x98
41
42 /* Scatter-Gather Hash */
43 #define SG_LIST_LEN_LAST BIT(31)
44 struct AspeedSgList {
45 uint32_t len;
46 uint32_t addr;
47 } __attribute__ ((__packed__));
48
49 struct AspeedMasks {
50 uint32_t src;
51 uint32_t dest;
52 uint32_t key;
53 uint32_t len;
54 uint32_t src_hi;
55 uint32_t dest_hi;
56 uint32_t key_hi;
57 };
58
59 void aspeed_test_md5(const char *machine, const uint32_t base,
60 const uint64_t src_addr);
61 void aspeed_test_sha256(const char *machine, const uint32_t base,
62 const uint64_t src_addr);
63 void aspeed_test_sha384(const char *machine, const uint32_t base,
64 const uint64_t src_addr);
65 void aspeed_test_sha512(const char *machine, const uint32_t base,
66 const uint64_t src_addr);
67 void aspeed_test_sha256_sg(const char *machine, const uint32_t base,
68 const uint64_t src_addr);
69 void aspeed_test_sha384_sg(const char *machine, const uint32_t base,
70 const uint64_t src_addr);
71 void aspeed_test_sha512_sg(const char *machine, const uint32_t base,
72 const uint64_t src_addr);
73 void aspeed_test_sha256_accum(const char *machine, const uint32_t base,
74 const uint64_t src_addr);
75 void aspeed_test_sha384_accum(const char *machine, const uint32_t base,
76 const uint64_t src_addr);
77 void aspeed_test_sha512_accum(const char *machine, const uint32_t base,
78 const uint64_t src_addr);
79 void aspeed_test_addresses(const char *machine, const uint32_t base,
80 const struct AspeedMasks *expected);
81
82 /*
83 * Cipher modes a SoC's crypto engine supports, for aspeed_add_crypto_tests().
84 */
85 enum {
86 CRYPT_MODE_ECB = 1 << 0,
87 CRYPT_MODE_CBC = 1 << 1,
88 CRYPT_MODE_CTR = 1 << 2,
89 CRYPT_MODE_GCM = 1 << 3,
90 };
91
92 /*
93 * Register the crypto known-answer tests that @modes selects (a mask of
94 * CRYPT_MODE_*) for the given machine. Each test is named
95 * "<prefix>/hace/crypto/<mode>". @sg selects scatter-gather mode (used by the
96 * AST2600 and later) instead of the AST2500 direct access mode.
97 */
98 void aspeed_add_crypto_tests(const char *prefix, const char *machine,
99 uint32_t base, uint64_t dram, uint32_t modes,
100 bool sg);
101
102 #endif /* TESTS_ASPEED_HACE_UTILS_H */
103