| 1 | /* |
| 2 | * IDE test cases |
| 3 | * |
| 4 | * Copyright (c) 2013 Kevin Wolf <kwolf@redhat.com> |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 7 | * of this software and associated documentation files (the "Software"), to deal |
| 8 | * in the Software without restriction, including without limitation the rights |
| 9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 10 | * copies of the Software, and to permit persons to whom the Software is |
| 11 | * furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 22 | * THE SOFTWARE. |
| 23 | */ |
| 24 | |
| 25 | #include "qemu/osdep.h" |
| 26 | |
| 27 | |
| 28 | #include "libqtest.h" |
| 29 | #include "libqos/libqos.h" |
| 30 | #include "libqos/pci-pc.h" |
| 31 | #include "libqos/malloc-pc.h" |
| 32 | #include "qobject/qdict.h" |
| 33 | #include "qemu/bswap.h" |
| 34 | #include "hw/pci/pci_ids.h" |
| 35 | #include "hw/pci/pci_regs.h" |
| 36 | |
| 37 | /* Specified by ATA (physical) CHS geometry for ~64 MiB device. */ |
| 38 | #define TEST_IMAGE_SIZE ((130 * 16 * 63) * 512) |
| 39 | |
| 40 | #define IDE_PCI_DEV 1 |
| 41 | #define IDE_PCI_FUNC 1 |
| 42 | |
| 43 | #define IDE_BASE 0x1f0 |
| 44 | #define IDE_BASE2 0x3f6 |
| 45 | #define IDE_PRIMARY_IRQ 14 |
| 46 | |
| 47 | #define IDE_CTRL_RESET 0x04 |
| 48 | |
| 49 | #define ATAPI_BLOCK_SIZE 2048 |
| 50 | |
| 51 | /* Raw READ CD sector: 12 sync + 4 header + 2048 data + 288 EDC/ECC. */ |
| 52 | #define ATAPI_RAW_SIZE 2352 |
| 53 | #define ATAPI_RAW_DATA 16 |
| 54 | |
| 55 | /* How many bytes to receive via ATAPI PIO at one time. |
| 56 | * Must be less than 0xFFFF. */ |
| 57 | #define BYTE_COUNT_LIMIT 5120 |
| 58 | |
| 59 | enum { |
| 60 | reg_data = 0x0, |
| 61 | reg_feature = 0x1, |
| 62 | reg_error = 0x1, |
| 63 | reg_nsectors = 0x2, |
| 64 | reg_lba_low = 0x3, |
| 65 | reg_lba_middle = 0x4, |
| 66 | reg_lba_high = 0x5, |
| 67 | reg_device = 0x6, |
| 68 | reg_status = 0x7, |
| 69 | reg_command = 0x7, |
| 70 | }; |
| 71 | |
| 72 | enum { |
| 73 | BSY = 0x80, |
| 74 | DRDY = 0x40, |
| 75 | DF = 0x20, |
| 76 | DRQ = 0x08, |
| 77 | ERR = 0x01, |
| 78 | }; |
| 79 | |
| 80 | /* Error field */ |
| 81 | enum { |
| 82 | ABRT = 0x04, |
| 83 | }; |
| 84 | |
| 85 | enum { |
| 86 | DEV = 0x10, |
| 87 | LBA = 0x40, |
| 88 | }; |
| 89 | |
| 90 | enum { |
| 91 | bmreg_cmd = 0x0, |
| 92 | bmreg_status = 0x2, |
| 93 | bmreg_prdt = 0x4, |
| 94 | }; |
| 95 | |
| 96 | enum { |
| 97 | CMD_DSM = 0x06, |
| 98 | CMD_READ = 0x20, /* READ SECTOR(S) */ |
| 99 | CMD_WRITE = 0x30, /* WRITE SECTOR(S) */ |
| 100 | CMD_DIAGNOSE = 0x90, |
| 101 | CMD_INIT_DP = 0x91, /* INITIALIZE DEVICE PARAMETERS */ |
| 102 | CMD_READ_DMA = 0xc8, |
| 103 | CMD_WRITE_DMA = 0xca, |
| 104 | CMD_FLUSH_CACHE = 0xe7, |
| 105 | CMD_IDENTIFY = 0xec, |
| 106 | CMD_PACKET = 0xa0, |
| 107 | CMD_IDENTIFY_PACKET = 0xa1, |
| 108 | CMD_READ_NATIVE = 0xf8, /* READ NATIVE MAX ADDRESS */ |
| 109 | |
| 110 | CMDF_ABORT = 0x100, |
| 111 | CMDF_NO_BM = 0x200, |
| 112 | CMDF_NO_WAIT = 0x400, |
| 113 | }; |
| 114 | |
| 115 | enum { |
| 116 | BM_CMD_START = 0x1, |
| 117 | BM_CMD_WRITE = 0x8, /* write = from device to memory */ |
| 118 | }; |
| 119 | |
| 120 | enum { |
| 121 | BM_STS_ACTIVE = 0x1, |
| 122 | BM_STS_ERROR = 0x2, |
| 123 | BM_STS_INTR = 0x4, |
| 124 | }; |
| 125 | |
| 126 | enum { |
| 127 | PRDT_EOT = 0x80000000, |
| 128 | }; |
| 129 | |
| 130 | #define assert_bit_set(data, mask) g_assert_cmphex((data) & (mask), ==, (mask)) |
| 131 | #define assert_bit_clear(data, mask) g_assert_cmphex((data) & (mask), ==, 0) |
| 132 | |
| 133 | static QPCIBus *pcibus = NULL; |
| 134 | static QGuestAllocator guest_malloc; |
| 135 | |
| 136 | static char *tmp_path[2]; |
| 137 | static char *debug_path; |
| 138 | |
| 139 | G_GNUC_PRINTF(1, 2) |
| 140 | static QTestState *ide_test_start(const char *cmdline_fmt, ...) |
| 141 | { |
| 142 | QTestState *qts; |
| 143 | g_autofree char *full_fmt = g_strdup_printf("-machine pc %s", cmdline_fmt); |
| 144 | va_list ap; |
| 145 | |
| 146 | va_start(ap, cmdline_fmt); |
| 147 | qts = qtest_vinitf(full_fmt, ap); |
| 148 | va_end(ap); |
| 149 | |
| 150 | pc_alloc_init(&guest_malloc, qts, 0); |
| 151 | |
| 152 | return qts; |
| 153 | } |
| 154 | |
| 155 | static void ide_test_quit(QTestState *qts) |
| 156 | { |
| 157 | if (pcibus) { |
| 158 | qpci_free_pc(pcibus); |
| 159 | pcibus = NULL; |
| 160 | } |
| 161 | alloc_destroy(&guest_malloc); |
| 162 | qtest_quit(qts); |
| 163 | } |
| 164 | |
| 165 | static QPCIDevice *get_pci_device(QTestState *qts, QPCIBar *bmdma_bar, |
| 166 | QPCIBar *ide_bar) |
| 167 | { |
| 168 | QPCIDevice *dev; |
| 169 | uint16_t vendor_id, device_id; |
| 170 | |
| 171 | if (!pcibus) { |
| 172 | pcibus = qpci_new_pc(qts, NULL); |
| 173 | } |
| 174 | |
| 175 | /* Find PCI device and verify it's the right one */ |
| 176 | dev = qpci_device_find(pcibus, QPCI_DEVFN(IDE_PCI_DEV, IDE_PCI_FUNC)); |
| 177 | g_assert(dev != NULL); |
| 178 | |
| 179 | vendor_id = qpci_config_readw(dev, PCI_VENDOR_ID); |
| 180 | device_id = qpci_config_readw(dev, PCI_DEVICE_ID); |
| 181 | g_assert(vendor_id == PCI_VENDOR_ID_INTEL); |
| 182 | g_assert(device_id == PCI_DEVICE_ID_INTEL_82371SB_1); |
| 183 | |
| 184 | /* Map bmdma BAR */ |
| 185 | *bmdma_bar = qpci_iomap(dev, 4, NULL); |
| 186 | |
| 187 | *ide_bar = qpci_legacy_iomap(dev, IDE_BASE); |
| 188 | |
| 189 | qpci_device_enable(dev); |
| 190 | |
| 191 | return dev; |
| 192 | } |
| 193 | |
| 194 | static void free_pci_device(QPCIDevice *dev) |
| 195 | { |
| 196 | /* libqos doesn't have a function for this, so free it manually */ |
| 197 | g_free(dev); |
| 198 | } |
| 199 | |
| 200 | typedef struct PrdtEntry { |
| 201 | uint32_t addr; |
| 202 | uint32_t size; |
| 203 | } QEMU_PACKED PrdtEntry; |
| 204 | |
| 205 | #define assert_bit_set(data, mask) g_assert_cmphex((data) & (mask), ==, (mask)) |
| 206 | #define assert_bit_clear(data, mask) g_assert_cmphex((data) & (mask), ==, 0) |
| 207 | |
| 208 | static uint64_t trim_range_le(uint64_t sector, uint16_t count) |
| 209 | { |
| 210 | /* 2-byte range, 6-byte LBA */ |
| 211 | return cpu_to_le64(((uint64_t)count << 48) + sector); |
| 212 | } |
| 213 | |
| 214 | static uint8_t wait_dma_completion(QTestState *qts, QPCIDevice *dev, |
| 215 | QPCIBar bmdma_bar, QPCIBar ide_bar) |
| 216 | { |
| 217 | uint8_t status; |
| 218 | |
| 219 | /* Wait for the DMA transfer to complete */ |
| 220 | do { |
| 221 | status = qpci_io_readb(dev, bmdma_bar, bmreg_status); |
| 222 | } while ((status & (BM_STS_ACTIVE | BM_STS_INTR)) == BM_STS_ACTIVE); |
| 223 | |
| 224 | g_assert_cmpint(qtest_get_irq(qts, IDE_PRIMARY_IRQ), ==, |
| 225 | !!(status & BM_STS_INTR)); |
| 226 | |
| 227 | /* Check IDE status code */ |
| 228 | assert_bit_set(qpci_io_readb(dev, ide_bar, reg_status), DRDY); |
| 229 | assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), BSY | DRQ); |
| 230 | |
| 231 | /* Reading the status register clears the IRQ */ |
| 232 | g_assert(!qtest_get_irq(qts, IDE_PRIMARY_IRQ)); |
| 233 | |
| 234 | /* Stop DMA transfer if still active */ |
| 235 | if (status & BM_STS_ACTIVE) { |
| 236 | qpci_io_writeb(dev, bmdma_bar, bmreg_cmd, 0); |
| 237 | } |
| 238 | |
| 239 | return status; |
| 240 | } |
| 241 | |
| 242 | static int send_dma_request_dev(QTestState *qts, QPCIDevice *dev, |
| 243 | QPCIBar bmdma_bar, QPCIBar ide_bar, int cmd, |
| 244 | uint64_t sector, int nb_sectors, |
| 245 | PrdtEntry *prdt, int prdt_entries, |
| 246 | void(*post_exec)(QPCIDevice *dev, |
| 247 | QPCIBar ide_bar, |
| 248 | uint64_t sector, |
| 249 | int nb_sectors)) |
| 250 | { |
| 251 | uintptr_t guest_prdt; |
| 252 | size_t len; |
| 253 | bool from_dev; |
| 254 | uint8_t status; |
| 255 | int flags; |
| 256 | |
| 257 | flags = cmd & ~0xff; |
| 258 | cmd &= 0xff; |
| 259 | |
| 260 | switch (cmd) { |
| 261 | case CMD_READ_DMA: |
| 262 | case CMD_PACKET: |
| 263 | /* Assuming we only test data reads w/ ATAPI, otherwise we need to know |
| 264 | * the SCSI command being sent in the packet, too. */ |
| 265 | from_dev = true; |
| 266 | break; |
| 267 | case CMD_DSM: |
| 268 | case CMD_WRITE_DMA: |
| 269 | from_dev = false; |
| 270 | break; |
| 271 | default: |
| 272 | g_assert_not_reached(); |
| 273 | } |
| 274 | |
| 275 | if (flags & CMDF_NO_BM) { |
| 276 | qpci_config_writew(dev, PCI_COMMAND, |
| 277 | PCI_COMMAND_IO | PCI_COMMAND_MEMORY); |
| 278 | } |
| 279 | |
| 280 | /* Select device 0 */ |
| 281 | qpci_io_writeb(dev, ide_bar, reg_device, 0 | LBA); |
| 282 | |
| 283 | /* Stop any running transfer, clear any pending interrupt */ |
| 284 | qpci_io_writeb(dev, bmdma_bar, bmreg_cmd, 0); |
| 285 | qpci_io_writeb(dev, bmdma_bar, bmreg_status, BM_STS_INTR); |
| 286 | |
| 287 | /* Setup PRDT */ |
| 288 | len = sizeof(*prdt) * prdt_entries; |
| 289 | guest_prdt = guest_alloc(&guest_malloc, len); |
| 290 | qtest_memwrite(qts, guest_prdt, prdt, len); |
| 291 | qpci_io_writel(dev, bmdma_bar, bmreg_prdt, guest_prdt); |
| 292 | |
| 293 | /* ATA DMA command */ |
| 294 | if (cmd == CMD_PACKET) { |
| 295 | /* Enables ATAPI DMA; otherwise PIO is attempted */ |
| 296 | qpci_io_writeb(dev, ide_bar, reg_feature, 0x01); |
| 297 | } else { |
| 298 | if (cmd == CMD_DSM) { |
| 299 | /* trim bit */ |
| 300 | qpci_io_writeb(dev, ide_bar, reg_feature, 0x01); |
| 301 | } |
| 302 | qpci_io_writeb(dev, ide_bar, reg_nsectors, nb_sectors); |
| 303 | qpci_io_writeb(dev, ide_bar, reg_lba_low, sector & 0xff); |
| 304 | qpci_io_writeb(dev, ide_bar, reg_lba_middle, (sector >> 8) & 0xff); |
| 305 | qpci_io_writeb(dev, ide_bar, reg_lba_high, (sector >> 16) & 0xff); |
| 306 | } |
| 307 | |
| 308 | qpci_io_writeb(dev, ide_bar, reg_command, cmd); |
| 309 | |
| 310 | if (post_exec) { |
| 311 | post_exec(dev, ide_bar, sector, nb_sectors); |
| 312 | } |
| 313 | |
| 314 | /* Start DMA transfer */ |
| 315 | qpci_io_writeb(dev, bmdma_bar, bmreg_cmd, |
| 316 | BM_CMD_START | (from_dev ? BM_CMD_WRITE : 0)); |
| 317 | |
| 318 | if (flags & CMDF_ABORT) { |
| 319 | qpci_io_writeb(dev, bmdma_bar, bmreg_cmd, 0); |
| 320 | } |
| 321 | |
| 322 | if (flags & CMDF_NO_WAIT) { |
| 323 | return 0; |
| 324 | } |
| 325 | |
| 326 | status = wait_dma_completion(qts, dev, bmdma_bar, ide_bar); |
| 327 | |
| 328 | return status; |
| 329 | } |
| 330 | |
| 331 | static int send_dma_request(QTestState *qts, int cmd, uint64_t sector, |
| 332 | int nb_sectors, PrdtEntry *prdt, int prdt_entries, |
| 333 | void(*post_exec)(QPCIDevice *dev, QPCIBar ide_bar, |
| 334 | uint64_t sector, int nb_sectors)) |
| 335 | { |
| 336 | QPCIDevice *dev; |
| 337 | QPCIBar bmdma_bar, ide_bar; |
| 338 | uint8_t status; |
| 339 | |
| 340 | dev = get_pci_device(qts, &bmdma_bar, &ide_bar); |
| 341 | status = send_dma_request_dev(qts, dev, bmdma_bar, ide_bar, |
| 342 | cmd, sector, nb_sectors, prdt, prdt_entries, |
| 343 | post_exec); |
| 344 | free_pci_device(dev); |
| 345 | |
| 346 | return status; |
| 347 | } |
| 348 | |
| 349 | static QTestState *test_bmdma_setup(void) |
| 350 | { |
| 351 | QTestState *qts; |
| 352 | |
| 353 | qts = ide_test_start( |
| 354 | "-drive file=%s,if=ide,cache=writeback,format=raw " |
| 355 | "-global ide-hd.serial=%s -global ide-hd.ver=%s", |
| 356 | tmp_path[0], "testdisk", "version"); |
| 357 | qtest_irq_intercept_in(qts, "ioapic"); |
| 358 | |
| 359 | return qts; |
| 360 | } |
| 361 | |
| 362 | static void test_bmdma_teardown(QTestState *qts) |
| 363 | { |
| 364 | ide_test_quit(qts); |
| 365 | } |
| 366 | |
| 367 | static void test_bmdma_simple_rw(void) |
| 368 | { |
| 369 | QTestState *qts; |
| 370 | QPCIDevice *dev; |
| 371 | QPCIBar bmdma_bar, ide_bar; |
| 372 | uint8_t status; |
| 373 | uint8_t *buf; |
| 374 | uint8_t *cmpbuf; |
| 375 | size_t len = 512; |
| 376 | uintptr_t guest_buf; |
| 377 | PrdtEntry prdt[1]; |
| 378 | |
| 379 | qts = test_bmdma_setup(); |
| 380 | |
| 381 | guest_buf = guest_alloc(&guest_malloc, len); |
| 382 | prdt[0].addr = cpu_to_le32(guest_buf); |
| 383 | prdt[0].size = cpu_to_le32(len | PRDT_EOT); |
| 384 | |
| 385 | dev = get_pci_device(qts, &bmdma_bar, &ide_bar); |
| 386 | |
| 387 | buf = g_malloc(len); |
| 388 | cmpbuf = g_malloc(len); |
| 389 | |
| 390 | /* Write 0x55 pattern to sector 0 */ |
| 391 | memset(buf, 0x55, len); |
| 392 | qtest_memwrite(qts, guest_buf, buf, len); |
| 393 | |
| 394 | status = send_dma_request(qts, CMD_WRITE_DMA, 0, 1, prdt, |
| 395 | ARRAY_SIZE(prdt), NULL); |
| 396 | g_assert_cmphex(status, ==, BM_STS_INTR); |
| 397 | assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR); |
| 398 | |
| 399 | /* Write 0xaa pattern to sector 1 */ |
| 400 | memset(buf, 0xaa, len); |
| 401 | qtest_memwrite(qts, guest_buf, buf, len); |
| 402 | |
| 403 | status = send_dma_request(qts, CMD_WRITE_DMA, 1, 1, prdt, |
| 404 | ARRAY_SIZE(prdt), NULL); |
| 405 | g_assert_cmphex(status, ==, BM_STS_INTR); |
| 406 | assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR); |
| 407 | |
| 408 | /* Read and verify 0x55 pattern in sector 0 */ |
| 409 | memset(cmpbuf, 0x55, len); |
| 410 | |
| 411 | status = send_dma_request(qts, CMD_READ_DMA, 0, 1, prdt, ARRAY_SIZE(prdt), |
| 412 | NULL); |
| 413 | g_assert_cmphex(status, ==, BM_STS_INTR); |
| 414 | assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR); |
| 415 | |
| 416 | qtest_memread(qts, guest_buf, buf, len); |
| 417 | g_assert(memcmp(buf, cmpbuf, len) == 0); |
| 418 | |
| 419 | /* Read and verify 0xaa pattern in sector 1 */ |
| 420 | memset(cmpbuf, 0xaa, len); |
| 421 | |
| 422 | status = send_dma_request(qts, CMD_READ_DMA, 1, 1, prdt, ARRAY_SIZE(prdt), |
| 423 | NULL); |
| 424 | g_assert_cmphex(status, ==, BM_STS_INTR); |
| 425 | assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR); |
| 426 | |
| 427 | qtest_memread(qts, guest_buf, buf, len); |
| 428 | g_assert(memcmp(buf, cmpbuf, len) == 0); |
| 429 | |
| 430 | free_pci_device(dev); |
| 431 | g_free(buf); |
| 432 | g_free(cmpbuf); |
| 433 | |
| 434 | test_bmdma_teardown(qts); |
| 435 | } |
| 436 | |
| 437 | static void test_bmdma_trim(void) |
| 438 | { |
| 439 | QTestState *qts; |
| 440 | QPCIDevice *dev; |
| 441 | QPCIBar bmdma_bar, ide_bar; |
| 442 | uint8_t status; |
| 443 | const uint64_t trim_range[] = { trim_range_le(0, 2), |
| 444 | trim_range_le(6, 8), |
| 445 | trim_range_le(10, 1), |
| 446 | }; |
| 447 | const uint64_t bad_range = trim_range_le(TEST_IMAGE_SIZE / 512 - 1, 2); |
| 448 | size_t len = 512; |
| 449 | uint8_t *buf; |
| 450 | uintptr_t guest_buf; |
| 451 | PrdtEntry prdt[1]; |
| 452 | |
| 453 | qts = test_bmdma_setup(); |
| 454 | |
| 455 | guest_buf = guest_alloc(&guest_malloc, len); |
| 456 | prdt[0].addr = cpu_to_le32(guest_buf), |
| 457 | prdt[0].size = cpu_to_le32(len | PRDT_EOT), |
| 458 | |
| 459 | dev = get_pci_device(qts, &bmdma_bar, &ide_bar); |
| 460 | |
| 461 | buf = g_malloc(len); |
| 462 | |
| 463 | /* Normal request */ |
| 464 | *((uint64_t *)buf) = trim_range[0]; |
| 465 | *((uint64_t *)buf + 1) = trim_range[1]; |
| 466 | |
| 467 | qtest_memwrite(qts, guest_buf, buf, 2 * sizeof(uint64_t)); |
| 468 | |
| 469 | status = send_dma_request(qts, CMD_DSM, 0, 1, prdt, |
| 470 | ARRAY_SIZE(prdt), NULL); |
| 471 | g_assert_cmphex(status, ==, BM_STS_INTR); |
| 472 | assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR); |
| 473 | |
| 474 | /* Request contains invalid range */ |
| 475 | *((uint64_t *)buf) = trim_range[2]; |
| 476 | *((uint64_t *)buf + 1) = bad_range; |
| 477 | |
| 478 | qtest_memwrite(qts, guest_buf, buf, 2 * sizeof(uint64_t)); |
| 479 | |
| 480 | status = send_dma_request(qts, CMD_DSM, 0, 1, prdt, |
| 481 | ARRAY_SIZE(prdt), NULL); |
| 482 | g_assert_cmphex(status, ==, BM_STS_INTR); |
| 483 | assert_bit_set(qpci_io_readb(dev, ide_bar, reg_status), ERR); |
| 484 | assert_bit_set(qpci_io_readb(dev, ide_bar, reg_error), ABRT); |
| 485 | |
| 486 | free_pci_device(dev); |
| 487 | g_free(buf); |
| 488 | test_bmdma_teardown(qts); |
| 489 | } |
| 490 | |
| 491 | static void test_bmdma_trim_reset(void) |
| 492 | { |
| 493 | QTestState *qts; |
| 494 | QPCIDevice *dev; |
| 495 | QPCIBar bmdma_bar, ide_bar, ide_bar2; |
| 496 | uint8_t status; |
| 497 | const uint64_t trim_range[] = { |
| 498 | trim_range_le(0, 2), |
| 499 | trim_range_le(6, 8), |
| 500 | }; |
| 501 | size_t len = 512; |
| 502 | uint8_t *buf; |
| 503 | uintptr_t guest_buf; |
| 504 | PrdtEntry prdt[1]; |
| 505 | |
| 506 | qts = ide_test_start( |
| 507 | "-blockdev file,filename=%s,node-name=img " |
| 508 | "-blockdev blkdebug,image=img,node-name=dbg,discard=unmap," |
| 509 | "inject-error.0.event=none,inject-error.0.iotype=discard," |
| 510 | "inject-error.0.errno=0,inject-error.0.delay-ns=1000000 " |
| 511 | "-device ide-hd,drive=dbg,bus=ide.0", |
| 512 | tmp_path[0]); |
| 513 | qtest_irq_intercept_in(qts, "ioapic"); |
| 514 | |
| 515 | guest_buf = guest_alloc(&guest_malloc, len); |
| 516 | prdt[0].addr = cpu_to_le32(guest_buf), |
| 517 | prdt[0].size = cpu_to_le32(len | PRDT_EOT), |
| 518 | |
| 519 | dev = get_pci_device(qts, &bmdma_bar, &ide_bar); |
| 520 | ide_bar2 = qpci_legacy_iomap(dev, IDE_BASE2); |
| 521 | |
| 522 | buf = g_malloc(len); |
| 523 | |
| 524 | /* TRIM request with two segments */ |
| 525 | *((uint64_t *)buf) = trim_range[0]; |
| 526 | *((uint64_t *)buf + 1) = trim_range[1]; |
| 527 | |
| 528 | qtest_memwrite(qts, guest_buf, buf, 2 * sizeof(uint64_t)); |
| 529 | |
| 530 | send_dma_request_dev(qts, dev, bmdma_bar, ide_bar, CMD_DSM | CMDF_NO_WAIT, 0, 1, prdt, |
| 531 | ARRAY_SIZE(prdt), NULL); |
| 532 | |
| 533 | /* Reset the device while the first segment is in flight */ |
| 534 | qpci_io_writeb(dev, ide_bar2, 0, IDE_CTRL_RESET); |
| 535 | |
| 536 | status = wait_dma_completion(qts, dev, bmdma_bar, ide_bar); |
| 537 | g_assert_cmphex(status, ==, BM_STS_INTR); |
| 538 | assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR); |
| 539 | |
| 540 | free_pci_device(dev); |
| 541 | g_free(buf); |
| 542 | test_bmdma_teardown(qts); |
| 543 | } |
| 544 | |
| 545 | /* |
| 546 | * This test is developed according to the Programming Interface for |
| 547 | * Bus Master IDE Controller (Revision 1.0 5/16/94) |
| 548 | */ |
| 549 | static void test_bmdma_various_prdts(void) |
| 550 | { |
| 551 | int sectors = 0; |
| 552 | uint32_t size = 0; |
| 553 | |
| 554 | for (sectors = 1; sectors <= 256; sectors *= 2) { |
| 555 | QTestState *qts = NULL; |
| 556 | QPCIDevice *dev = NULL; |
| 557 | QPCIBar bmdma_bar, ide_bar; |
| 558 | |
| 559 | qts = test_bmdma_setup(); |
| 560 | dev = get_pci_device(qts, &bmdma_bar, &ide_bar); |
| 561 | |
| 562 | for (size = 0; size < 65536; size += 256) { |
| 563 | uint32_t req_size = sectors * 512; |
| 564 | uint32_t prd_size = size & 0xfffe; /* bit 0 is always set to 0 */ |
| 565 | uint8_t ret = 0; |
| 566 | uint8_t req_status = 0; |
| 567 | uint8_t abort_req_status = 0; |
| 568 | PrdtEntry prdt[] = { |
| 569 | { |
| 570 | .addr = 0, |
| 571 | .size = cpu_to_le32(size | PRDT_EOT), |
| 572 | }, |
| 573 | }; |
| 574 | |
| 575 | /* A value of zero in PRD size indicates 64K */ |
| 576 | if (prd_size == 0) { |
| 577 | prd_size = 65536; |
| 578 | } |
| 579 | |
| 580 | /* |
| 581 | * 1. If PRDs specified a smaller size than the IDE transfer |
| 582 | * size, then the Interrupt and Active bits in the Controller |
| 583 | * status register are not set (Error Condition). |
| 584 | * |
| 585 | * 2. If the size of the physical memory regions was equal to |
| 586 | * the IDE device transfer size, the Interrupt bit in the |
| 587 | * Controller status register is set to 1, Active bit is set to 0. |
| 588 | * |
| 589 | * 3. If PRDs specified a larger size than the IDE transfer size, |
| 590 | * the Interrupt and Active bits in the Controller status register |
| 591 | * are both set to 1. |
| 592 | */ |
| 593 | if (prd_size < req_size) { |
| 594 | req_status = 0; |
| 595 | abort_req_status = 0; |
| 596 | } else if (prd_size == req_size) { |
| 597 | req_status = BM_STS_INTR; |
| 598 | abort_req_status = BM_STS_INTR; |
| 599 | } else { |
| 600 | req_status = BM_STS_ACTIVE | BM_STS_INTR; |
| 601 | abort_req_status = BM_STS_INTR; |
| 602 | } |
| 603 | |
| 604 | /* Test the request */ |
| 605 | ret = send_dma_request(qts, CMD_READ_DMA, 0, sectors, |
| 606 | prdt, ARRAY_SIZE(prdt), NULL); |
| 607 | g_assert_cmphex(ret, ==, req_status); |
| 608 | assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR); |
| 609 | |
| 610 | /* Now test aborting the same request */ |
| 611 | ret = send_dma_request(qts, CMD_READ_DMA | CMDF_ABORT, 0, |
| 612 | sectors, prdt, ARRAY_SIZE(prdt), NULL); |
| 613 | g_assert_cmphex(ret, ==, abort_req_status); |
| 614 | assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR); |
| 615 | } |
| 616 | |
| 617 | free_pci_device(dev); |
| 618 | test_bmdma_teardown(qts); |
| 619 | } |
| 620 | } |
| 621 | |
| 622 | static void test_bmdma_no_busmaster(void) |
| 623 | { |
| 624 | QTestState *qts; |
| 625 | QPCIDevice *dev; |
| 626 | QPCIBar bmdma_bar, ide_bar; |
| 627 | uint8_t status; |
| 628 | |
| 629 | qts = test_bmdma_setup(); |
| 630 | |
| 631 | dev = get_pci_device(qts, &bmdma_bar, &ide_bar); |
| 632 | |
| 633 | /* No PRDT_EOT, each entry addr 0/size 64k, and in theory qemu shouldn't be |
| 634 | * able to access it anyway because the Bus Master bit in the PCI command |
| 635 | * register isn't set. This is complete nonsense, but it used to be pretty |
| 636 | * good at confusing and occasionally crashing qemu. */ |
| 637 | PrdtEntry prdt[4096] = { }; |
| 638 | |
| 639 | status = send_dma_request(qts, CMD_READ_DMA | CMDF_NO_BM, 0, 512, |
| 640 | prdt, ARRAY_SIZE(prdt), NULL); |
| 641 | |
| 642 | /* Not entirely clear what the expected result is, but this is what we get |
| 643 | * in practice. At least we want to be aware of any changes. */ |
| 644 | g_assert_cmphex(status, ==, BM_STS_ACTIVE | BM_STS_INTR); |
| 645 | assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR); |
| 646 | free_pci_device(dev); |
| 647 | test_bmdma_teardown(qts); |
| 648 | } |
| 649 | |
| 650 | static void string_cpu_to_be16(uint16_t *s, size_t bytes) |
| 651 | { |
| 652 | g_assert((bytes & 1) == 0); |
| 653 | bytes /= 2; |
| 654 | |
| 655 | while (bytes--) { |
| 656 | *s = cpu_to_be16(*s); |
| 657 | s++; |
| 658 | } |
| 659 | } |
| 660 | |
| 661 | static void test_specify(void) |
| 662 | { |
| 663 | QTestState *qts; |
| 664 | QPCIDevice *dev; |
| 665 | QPCIBar bmdma_bar, ide_bar; |
| 666 | uint16_t cyls; |
| 667 | uint8_t heads, spt; |
| 668 | |
| 669 | qts = ide_test_start( |
| 670 | "-blockdev driver=file,node-name=hda,filename=%s " |
| 671 | "-device ide-hd,drive=hda,bus=ide.0,unit=0 ", |
| 672 | tmp_path[0]); |
| 673 | |
| 674 | dev = get_pci_device(qts, &bmdma_bar, &ide_bar); |
| 675 | |
| 676 | /* Initialize drive with zero sectors per track and one head. */ |
| 677 | qpci_io_writeb(dev, ide_bar, reg_nsectors, 0); |
| 678 | qpci_io_writeb(dev, ide_bar, reg_device, 0); |
| 679 | qpci_io_writeb(dev, ide_bar, reg_command, CMD_INIT_DP); |
| 680 | |
| 681 | /* READ NATIVE MAX ADDRESS (CHS mode). */ |
| 682 | qpci_io_writeb(dev, ide_bar, reg_device, 0xa0); |
| 683 | qpci_io_writeb(dev, ide_bar, reg_command, CMD_READ_NATIVE); |
| 684 | |
| 685 | heads = qpci_io_readb(dev, ide_bar, reg_device) & 0xf; |
| 686 | ++heads; |
| 687 | g_assert_cmpint(heads, ==, 16); |
| 688 | |
| 689 | cyls = qpci_io_readb(dev, ide_bar, reg_lba_high) << 8; |
| 690 | cyls |= qpci_io_readb(dev, ide_bar, reg_lba_middle); |
| 691 | ++cyls; |
| 692 | g_assert_cmpint(cyls, ==, 130); |
| 693 | |
| 694 | spt = qpci_io_readb(dev, ide_bar, reg_lba_low); |
| 695 | g_assert_cmpint(spt, ==, 63); |
| 696 | |
| 697 | ide_test_quit(qts); |
| 698 | free_pci_device(dev); |
| 699 | } |
| 700 | |
| 701 | static void test_identify(void) |
| 702 | { |
| 703 | QTestState *qts; |
| 704 | QPCIDevice *dev; |
| 705 | QPCIBar bmdma_bar, ide_bar; |
| 706 | uint8_t data; |
| 707 | uint16_t buf[256]; |
| 708 | int i; |
| 709 | int ret; |
| 710 | |
| 711 | qts = ide_test_start( |
| 712 | "-drive file=%s,if=ide,cache=writeback,format=raw " |
| 713 | "-global ide-hd.serial=%s -global ide-hd.ver=%s", |
| 714 | tmp_path[0], "testdisk", "version"); |
| 715 | |
| 716 | dev = get_pci_device(qts, &bmdma_bar, &ide_bar); |
| 717 | |
| 718 | /* IDENTIFY command on device 0*/ |
| 719 | qpci_io_writeb(dev, ide_bar, reg_device, 0); |
| 720 | qpci_io_writeb(dev, ide_bar, reg_command, CMD_IDENTIFY); |
| 721 | |
| 722 | /* Read in the IDENTIFY buffer and check registers */ |
| 723 | data = qpci_io_readb(dev, ide_bar, reg_device); |
| 724 | g_assert_cmpint(data & DEV, ==, 0); |
| 725 | |
| 726 | for (i = 0; i < 256; i++) { |
| 727 | data = qpci_io_readb(dev, ide_bar, reg_status); |
| 728 | assert_bit_set(data, DRDY | DRQ); |
| 729 | assert_bit_clear(data, BSY | DF | ERR); |
| 730 | |
| 731 | buf[i] = qpci_io_readw(dev, ide_bar, reg_data); |
| 732 | } |
| 733 | |
| 734 | data = qpci_io_readb(dev, ide_bar, reg_status); |
| 735 | assert_bit_set(data, DRDY); |
| 736 | assert_bit_clear(data, BSY | DF | ERR | DRQ); |
| 737 | |
| 738 | /* Check serial number/version in the buffer */ |
| 739 | string_cpu_to_be16(&buf[10], 20); |
| 740 | ret = memcmp(&buf[10], "testdisk ", 20); |
| 741 | g_assert(ret == 0); |
| 742 | |
| 743 | string_cpu_to_be16(&buf[23], 8); |
| 744 | ret = memcmp(&buf[23], "version ", 8); |
| 745 | g_assert(ret == 0); |
| 746 | |
| 747 | /* Write cache enabled bit */ |
| 748 | assert_bit_set(buf[85], 0x20); |
| 749 | |
| 750 | ide_test_quit(qts); |
| 751 | free_pci_device(dev); |
| 752 | } |
| 753 | |
| 754 | static void test_diagnostic(void) |
| 755 | { |
| 756 | QTestState *qts; |
| 757 | QPCIDevice *dev; |
| 758 | QPCIBar bmdma_bar, ide_bar; |
| 759 | uint8_t data; |
| 760 | |
| 761 | qts = ide_test_start( |
| 762 | "-blockdev driver=file,node-name=hda,filename=%s " |
| 763 | "-blockdev driver=file,node-name=hdb,filename=%s " |
| 764 | "-device ide-hd,drive=hda,bus=ide.0,unit=0 " |
| 765 | "-device ide-hd,drive=hdb,bus=ide.0,unit=1 ", |
| 766 | tmp_path[0], tmp_path[1]); |
| 767 | |
| 768 | dev = get_pci_device(qts, &bmdma_bar, &ide_bar); |
| 769 | |
| 770 | /* DIAGNOSE command on device 1 */ |
| 771 | qpci_io_writeb(dev, ide_bar, reg_device, DEV); |
| 772 | data = qpci_io_readb(dev, ide_bar, reg_device); |
| 773 | g_assert_cmphex(data & DEV, ==, DEV); |
| 774 | qpci_io_writeb(dev, ide_bar, reg_command, CMD_DIAGNOSE); |
| 775 | |
| 776 | /* Verify that DEVICE is now 0 */ |
| 777 | data = qpci_io_readb(dev, ide_bar, reg_device); |
| 778 | g_assert_cmphex(data & DEV, ==, 0); |
| 779 | |
| 780 | ide_test_quit(qts); |
| 781 | free_pci_device(dev); |
| 782 | } |
| 783 | |
| 784 | /* |
| 785 | * Write sector 1 with random data to make IDE storage dirty |
| 786 | * Needed for flush tests so that flushes actually go though the block layer |
| 787 | */ |
| 788 | static void make_dirty(QTestState *qts, uint8_t device) |
| 789 | { |
| 790 | QPCIDevice *dev; |
| 791 | QPCIBar bmdma_bar, ide_bar; |
| 792 | uint8_t status; |
| 793 | size_t len = 512; |
| 794 | uintptr_t guest_buf; |
| 795 | void* buf; |
| 796 | |
| 797 | dev = get_pci_device(qts, &bmdma_bar, &ide_bar); |
| 798 | |
| 799 | guest_buf = guest_alloc(&guest_malloc, len); |
| 800 | buf = g_malloc(len); |
| 801 | memset(buf, rand() % 255 + 1, len); |
| 802 | g_assert(guest_buf); |
| 803 | g_assert(buf); |
| 804 | |
| 805 | qtest_memwrite(qts, guest_buf, buf, len); |
| 806 | |
| 807 | PrdtEntry prdt[] = { |
| 808 | { |
| 809 | .addr = cpu_to_le32(guest_buf), |
| 810 | .size = cpu_to_le32(len | PRDT_EOT), |
| 811 | }, |
| 812 | }; |
| 813 | |
| 814 | status = send_dma_request(qts, CMD_WRITE_DMA, 1, 1, prdt, |
| 815 | ARRAY_SIZE(prdt), NULL); |
| 816 | g_assert_cmphex(status, ==, BM_STS_INTR); |
| 817 | assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR); |
| 818 | |
| 819 | g_free(buf); |
| 820 | free_pci_device(dev); |
| 821 | } |
| 822 | |
| 823 | static void test_flush(void) |
| 824 | { |
| 825 | QTestState *qts; |
| 826 | QPCIDevice *dev; |
| 827 | QPCIBar bmdma_bar, ide_bar; |
| 828 | uint8_t data; |
| 829 | |
| 830 | qts = ide_test_start( |
| 831 | "-drive file=blkdebug::%s,if=ide,cache=writeback,format=raw", |
| 832 | tmp_path[0]); |
| 833 | |
| 834 | dev = get_pci_device(qts, &bmdma_bar, &ide_bar); |
| 835 | |
| 836 | qtest_irq_intercept_in(qts, "ioapic"); |
| 837 | |
| 838 | /* Dirty media so that CMD_FLUSH_CACHE will actually go to disk */ |
| 839 | make_dirty(qts, 0); |
| 840 | |
| 841 | /* Delay the completion of the flush request until we explicitly do it */ |
| 842 | qtest_qemu_io(qts, "ide0-hd0", "break flush_to_os A"); |
| 843 | |
| 844 | /* FLUSH CACHE command on device 0*/ |
| 845 | qpci_io_writeb(dev, ide_bar, reg_device, 0); |
| 846 | qpci_io_writeb(dev, ide_bar, reg_command, CMD_FLUSH_CACHE); |
| 847 | |
| 848 | /* Check status while request is in flight*/ |
| 849 | data = qpci_io_readb(dev, ide_bar, reg_status); |
| 850 | assert_bit_set(data, BSY | DRDY); |
| 851 | assert_bit_clear(data, DF | ERR | DRQ); |
| 852 | |
| 853 | /* Complete the command */ |
| 854 | qtest_qemu_io(qts, "ide0-hd0", "resume A"); |
| 855 | |
| 856 | /* Check registers */ |
| 857 | data = qpci_io_readb(dev, ide_bar, reg_device); |
| 858 | g_assert_cmpint(data & DEV, ==, 0); |
| 859 | |
| 860 | do { |
| 861 | data = qpci_io_readb(dev, ide_bar, reg_status); |
| 862 | } while (data & BSY); |
| 863 | |
| 864 | assert_bit_set(data, DRDY); |
| 865 | assert_bit_clear(data, BSY | DF | ERR | DRQ); |
| 866 | |
| 867 | ide_test_quit(qts); |
| 868 | free_pci_device(dev); |
| 869 | } |
| 870 | |
| 871 | static void test_pci_retry_flush(void) |
| 872 | { |
| 873 | QTestState *qts; |
| 874 | QPCIDevice *dev; |
| 875 | QPCIBar bmdma_bar, ide_bar; |
| 876 | uint8_t data; |
| 877 | |
| 878 | prepare_blkdebug_script(debug_path, "flush_to_disk"); |
| 879 | |
| 880 | qts = ide_test_start( |
| 881 | "-drive file=blkdebug:%s:%s,if=ide,cache=writeback,format=raw," |
| 882 | "rerror=stop,werror=stop", |
| 883 | debug_path, tmp_path[0]); |
| 884 | |
| 885 | dev = get_pci_device(qts, &bmdma_bar, &ide_bar); |
| 886 | |
| 887 | qtest_irq_intercept_in(qts, "ioapic"); |
| 888 | |
| 889 | /* Dirty media so that CMD_FLUSH_CACHE will actually go to disk */ |
| 890 | make_dirty(qts, 0); |
| 891 | |
| 892 | /* FLUSH CACHE command on device 0*/ |
| 893 | qpci_io_writeb(dev, ide_bar, reg_device, 0); |
| 894 | qpci_io_writeb(dev, ide_bar, reg_command, CMD_FLUSH_CACHE); |
| 895 | |
| 896 | /* Check status while request is in flight*/ |
| 897 | data = qpci_io_readb(dev, ide_bar, reg_status); |
| 898 | assert_bit_set(data, BSY | DRDY); |
| 899 | assert_bit_clear(data, DF | ERR | DRQ); |
| 900 | |
| 901 | qtest_qmp_eventwait(qts, "STOP"); |
| 902 | |
| 903 | /* Complete the command */ |
| 904 | qtest_qmp_assert_success(qts, "{'execute':'cont' }"); |
| 905 | |
| 906 | /* Check registers */ |
| 907 | data = qpci_io_readb(dev, ide_bar, reg_device); |
| 908 | g_assert_cmpint(data & DEV, ==, 0); |
| 909 | |
| 910 | do { |
| 911 | data = qpci_io_readb(dev, ide_bar, reg_status); |
| 912 | } while (data & BSY); |
| 913 | |
| 914 | assert_bit_set(data, DRDY); |
| 915 | assert_bit_clear(data, BSY | DF | ERR | DRQ); |
| 916 | |
| 917 | ide_test_quit(qts); |
| 918 | free_pci_device(dev); |
| 919 | } |
| 920 | |
| 921 | static void test_flush_nodev(void) |
| 922 | { |
| 923 | QTestState *qts; |
| 924 | QPCIDevice *dev; |
| 925 | QPCIBar bmdma_bar, ide_bar; |
| 926 | |
| 927 | qts = ide_test_start("%s", ""); |
| 928 | |
| 929 | dev = get_pci_device(qts, &bmdma_bar, &ide_bar); |
| 930 | |
| 931 | /* FLUSH CACHE command on device 0*/ |
| 932 | qpci_io_writeb(dev, ide_bar, reg_device, 0); |
| 933 | qpci_io_writeb(dev, ide_bar, reg_command, CMD_FLUSH_CACHE); |
| 934 | |
| 935 | /* Just testing that qemu doesn't crash... */ |
| 936 | |
| 937 | free_pci_device(dev); |
| 938 | ide_test_quit(qts); |
| 939 | } |
| 940 | |
| 941 | static void test_flush_empty_drive(void) |
| 942 | { |
| 943 | QTestState *qts; |
| 944 | QPCIDevice *dev; |
| 945 | QPCIBar bmdma_bar, ide_bar; |
| 946 | |
| 947 | qts = ide_test_start("-device ide-cd,bus=ide.0"); |
| 948 | dev = get_pci_device(qts, &bmdma_bar, &ide_bar); |
| 949 | |
| 950 | /* FLUSH CACHE command on device 0 */ |
| 951 | qpci_io_writeb(dev, ide_bar, reg_device, 0); |
| 952 | qpci_io_writeb(dev, ide_bar, reg_command, CMD_FLUSH_CACHE); |
| 953 | |
| 954 | /* Just testing that qemu doesn't crash... */ |
| 955 | |
| 956 | free_pci_device(dev); |
| 957 | ide_test_quit(qts); |
| 958 | } |
| 959 | |
| 960 | typedef struct Read10CDB { |
| 961 | uint8_t opcode; |
| 962 | uint8_t flags; |
| 963 | uint32_t lba; |
| 964 | uint8_t reserved; |
| 965 | uint16_t nblocks; |
| 966 | uint8_t control; |
| 967 | uint16_t padding; |
| 968 | } __attribute__((__packed__)) Read10CDB; |
| 969 | |
| 970 | static void send_scsi_cdb_read10(QPCIDevice *dev, QPCIBar ide_bar, |
| 971 | uint64_t lba, int nblocks) |
| 972 | { |
| 973 | Read10CDB pkt = { .padding = 0 }; |
| 974 | int i; |
| 975 | |
| 976 | g_assert_cmpint(lba, <=, UINT32_MAX); |
| 977 | g_assert_cmpint(nblocks, <=, UINT16_MAX); |
| 978 | g_assert_cmpint(nblocks, >=, 0); |
| 979 | |
| 980 | /* Construct SCSI CDB packet */ |
| 981 | pkt.opcode = 0x28; |
| 982 | pkt.lba = cpu_to_be32(lba); |
| 983 | pkt.nblocks = cpu_to_be16(nblocks); |
| 984 | |
| 985 | /* Send Packet */ |
| 986 | for (i = 0; i < sizeof(Read10CDB)/2; i++) { |
| 987 | qpci_io_writew(dev, ide_bar, reg_data, |
| 988 | le16_to_cpu(((uint16_t *)&pkt)[i])); |
| 989 | } |
| 990 | } |
| 991 | |
| 992 | typedef struct ReadCDCDB { |
| 993 | uint8_t opcode; |
| 994 | uint8_t sector_type; |
| 995 | uint32_t lba; |
| 996 | uint8_t length[3]; |
| 997 | uint8_t main_channel; |
| 998 | uint8_t sub_channel; |
| 999 | uint8_t control; |
| 1000 | } __attribute__((__packed__)) ReadCDCDB; |
| 1001 | |
| 1002 | static void send_scsi_cdb_read_cd(QPCIDevice *dev, QPCIBar ide_bar, |
| 1003 | uint64_t lba, int nblocks) |
| 1004 | { |
| 1005 | ReadCDCDB pkt = { }; |
| 1006 | int i; |
| 1007 | |
| 1008 | g_assert_cmpint(lba, <=, UINT32_MAX); |
| 1009 | g_assert_cmpint(nblocks, >=, 0); |
| 1010 | g_assert_cmpint(nblocks, <=, 0xffffff); |
| 1011 | |
| 1012 | /* Construct SCSI CDB packet */ |
| 1013 | pkt.opcode = 0xbe; |
| 1014 | pkt.lba = cpu_to_be32(lba); |
| 1015 | pkt.length[0] = (nblocks >> 16) & 0xff; |
| 1016 | pkt.length[1] = (nblocks >> 8) & 0xff; |
| 1017 | pkt.length[2] = nblocks & 0xff; |
| 1018 | pkt.main_channel = 0xf8; /* sync + headers + user data + EDC/ECC: 2352 */ |
| 1019 | |
| 1020 | /* Send Packet */ |
| 1021 | for (i = 0; i < sizeof(ReadCDCDB) / 2; i++) { |
| 1022 | qpci_io_writew(dev, ide_bar, reg_data, |
| 1023 | le16_to_cpu(((uint16_t *)&pkt)[i])); |
| 1024 | } |
| 1025 | } |
| 1026 | |
| 1027 | static void nsleep(QTestState *qts, int64_t nsecs) |
| 1028 | { |
| 1029 | const struct timespec val = { .tv_nsec = nsecs }; |
| 1030 | nanosleep(&val, NULL); |
| 1031 | qtest_clock_set(qts, nsecs); |
| 1032 | } |
| 1033 | |
| 1034 | static uint8_t ide_wait_clear(QTestState *qts, uint8_t flag) |
| 1035 | { |
| 1036 | QPCIDevice *dev; |
| 1037 | QPCIBar bmdma_bar, ide_bar; |
| 1038 | uint8_t data; |
| 1039 | time_t st; |
| 1040 | |
| 1041 | dev = get_pci_device(qts, &bmdma_bar, &ide_bar); |
| 1042 | |
| 1043 | /* Wait with a 5 second timeout */ |
| 1044 | time(&st); |
| 1045 | while (true) { |
| 1046 | data = qpci_io_readb(dev, ide_bar, reg_status); |
| 1047 | if (!(data & flag)) { |
| 1048 | free_pci_device(dev); |
| 1049 | return data; |
| 1050 | } |
| 1051 | if (difftime(time(NULL), st) > 5.0) { |
| 1052 | break; |
| 1053 | } |
| 1054 | nsleep(qts, 400); |
| 1055 | } |
| 1056 | g_assert_not_reached(); |
| 1057 | } |
| 1058 | |
| 1059 | static void ide_wait_intr(QTestState *qts, int irq) |
| 1060 | { |
| 1061 | time_t st; |
| 1062 | bool intr; |
| 1063 | |
| 1064 | time(&st); |
| 1065 | while (true) { |
| 1066 | intr = qtest_get_irq(qts, irq); |
| 1067 | if (intr) { |
| 1068 | return; |
| 1069 | } |
| 1070 | if (difftime(time(NULL), st) > 5.0) { |
| 1071 | break; |
| 1072 | } |
| 1073 | nsleep(qts, 400); |
| 1074 | } |
| 1075 | |
| 1076 | g_assert_not_reached(); |
| 1077 | } |
| 1078 | |
| 1079 | #define CDROM_PIO 0 |
| 1080 | #define CDROM_DMA (1 << 0) |
| 1081 | #define CDROM_RAW (1 << 1) |
| 1082 | |
| 1083 | static void cdrom_read_impl(int nblocks, unsigned flags) |
| 1084 | { |
| 1085 | bool dma = flags & CDROM_DMA; |
| 1086 | bool raw = flags & CDROM_RAW; |
| 1087 | QTestState *qts; |
| 1088 | QPCIDevice *dev; |
| 1089 | QPCIBar bmdma_bar, ide_bar; |
| 1090 | FILE *fh; |
| 1091 | int patt_blocks = MAX(16, nblocks); |
| 1092 | size_t patt_len = ATAPI_BLOCK_SIZE * patt_blocks; |
| 1093 | char *pattern = g_malloc(patt_len); |
| 1094 | unsigned xfer = raw ? ATAPI_RAW_SIZE : ATAPI_BLOCK_SIZE; |
| 1095 | size_t rxsize = xfer * nblocks; |
| 1096 | uint16_t *rx = g_malloc0(rxsize); |
| 1097 | void (*send_cdb)(QPCIDevice *, QPCIBar, uint64_t, int) = |
| 1098 | raw ? send_scsi_cdb_read_cd : send_scsi_cdb_read10; |
| 1099 | int i, j; |
| 1100 | uint8_t data; |
| 1101 | uint16_t limit; |
| 1102 | size_t ret; |
| 1103 | |
| 1104 | /* Prepopulate the CDROM with an interesting pattern */ |
| 1105 | generate_pattern(pattern, patt_len, ATAPI_BLOCK_SIZE); |
| 1106 | fh = fopen(tmp_path[0], "wb+"); |
| 1107 | ret = fwrite(pattern, ATAPI_BLOCK_SIZE, patt_blocks, fh); |
| 1108 | g_assert_cmpint(ret, ==, patt_blocks); |
| 1109 | fclose(fh); |
| 1110 | |
| 1111 | qts = ide_test_start( |
| 1112 | "-drive if=none,file=%s,media=cdrom,format=raw,id=sr0,index=0 " |
| 1113 | "-device ide-cd,drive=sr0,bus=ide.0", tmp_path[0]); |
| 1114 | dev = get_pci_device(qts, &bmdma_bar, &ide_bar); |
| 1115 | qtest_irq_intercept_in(qts, "ioapic"); |
| 1116 | |
| 1117 | if (dma) { |
| 1118 | uintptr_t guest_buf = guest_alloc(&guest_malloc, rxsize); |
| 1119 | PrdtEntry prdt[1]; |
| 1120 | |
| 1121 | prdt[0].addr = cpu_to_le32(guest_buf); |
| 1122 | prdt[0].size = cpu_to_le32(rxsize | PRDT_EOT); |
| 1123 | |
| 1124 | send_dma_request_dev(qts, dev, bmdma_bar, ide_bar, CMD_PACKET, 0, |
| 1125 | nblocks, prdt, ARRAY_SIZE(prdt), send_cdb); |
| 1126 | |
| 1127 | qtest_memread(qts, guest_buf, rx, rxsize); |
| 1128 | } else { |
| 1129 | /* PACKET command on device 0 */ |
| 1130 | qpci_io_writeb(dev, ide_bar, reg_device, 0); |
| 1131 | qpci_io_writeb(dev, ide_bar, reg_lba_middle, BYTE_COUNT_LIMIT & 0xFF); |
| 1132 | qpci_io_writeb(dev, ide_bar, reg_lba_high, |
| 1133 | (BYTE_COUNT_LIMIT >> 8 & 0xFF)); |
| 1134 | qpci_io_writeb(dev, ide_bar, reg_command, CMD_PACKET); |
| 1135 | /* HP0: Check_Status_A State */ |
| 1136 | nsleep(qts, 400); |
| 1137 | data = ide_wait_clear(qts, BSY); |
| 1138 | /* HP1: Send_Packet State */ |
| 1139 | assert_bit_set(data, DRQ | DRDY); |
| 1140 | assert_bit_clear(data, ERR | DF | BSY); |
| 1141 | |
| 1142 | send_cdb(dev, ide_bar, 0, nblocks); |
| 1143 | |
| 1144 | /* |
| 1145 | * Read data back: occurs in bursts of 'BYTE_COUNT_LIMIT' bytes. |
| 1146 | * If BYTE_COUNT_LIMIT is odd, we transfer BYTE_COUNT_LIMIT - 1 bytes. |
| 1147 | * We allow an odd limit only when the remaining transfer size is |
| 1148 | * less than BYTE_COUNT_LIMIT. However, SCSI's read10 command can only |
| 1149 | * request n blocks, so our request size is always even. |
| 1150 | * For this reason, we assume there is never a hanging byte to fetch. |
| 1151 | */ |
| 1152 | g_assert(!(rxsize & 1)); |
| 1153 | limit = BYTE_COUNT_LIMIT & ~1; |
| 1154 | for (i = 0; i < DIV_ROUND_UP(rxsize, limit); i++) { |
| 1155 | size_t offset = i * (limit / 2); |
| 1156 | size_t rem = (rxsize / 2) - offset; |
| 1157 | |
| 1158 | /* HP3: INTRQ_Wait */ |
| 1159 | ide_wait_intr(qts, IDE_PRIMARY_IRQ); |
| 1160 | |
| 1161 | /* HP2: Check_Status_B (and clear IRQ) */ |
| 1162 | data = ide_wait_clear(qts, BSY); |
| 1163 | assert_bit_set(data, DRQ | DRDY); |
| 1164 | assert_bit_clear(data, ERR | DF | BSY); |
| 1165 | |
| 1166 | /* HP4: Transfer_Data */ |
| 1167 | for (j = 0; j < MIN((limit / 2), rem); j++) { |
| 1168 | rx[offset + j] = cpu_to_le16(qpci_io_readw(dev, ide_bar, |
| 1169 | reg_data)); |
| 1170 | } |
| 1171 | } |
| 1172 | |
| 1173 | /* Check for final completion IRQ */ |
| 1174 | ide_wait_intr(qts, IDE_PRIMARY_IRQ); |
| 1175 | |
| 1176 | /* Sanity check final state */ |
| 1177 | data = ide_wait_clear(qts, DRQ); |
| 1178 | assert_bit_set(data, DRDY); |
| 1179 | assert_bit_clear(data, DRQ | ERR | DF | BSY); |
| 1180 | } |
| 1181 | |
| 1182 | if (raw) { |
| 1183 | /* The 2048-byte payload of each raw sector sits past its header. */ |
| 1184 | for (i = 0; i < nblocks; i++) { |
| 1185 | uint8_t *sec = (uint8_t *)rx + i * ATAPI_RAW_SIZE + ATAPI_RAW_DATA; |
| 1186 | |
| 1187 | g_assert_cmpint(memcmp(sec, pattern + i * ATAPI_BLOCK_SIZE, |
| 1188 | ATAPI_BLOCK_SIZE), ==, 0); |
| 1189 | } |
| 1190 | } else { |
| 1191 | g_assert_cmpint(memcmp(pattern, rx, rxsize), ==, 0); |
| 1192 | } |
| 1193 | |
| 1194 | g_free(pattern); |
| 1195 | g_free(rx); |
| 1196 | test_bmdma_teardown(qts); |
| 1197 | free_pci_device(dev); |
| 1198 | } |
| 1199 | |
| 1200 | static void ide_identify_words(QPCIDevice *dev, QPCIBar ide_bar, |
| 1201 | uint16_t buf[256]) |
| 1202 | { |
| 1203 | int i; |
| 1204 | |
| 1205 | qpci_io_writeb(dev, ide_bar, reg_device, 0); |
| 1206 | qpci_io_writeb(dev, ide_bar, reg_command, CMD_IDENTIFY); |
| 1207 | for (i = 0; i < 256; i++) { |
| 1208 | buf[i] = qpci_io_readw(dev, ide_bar, reg_data); |
| 1209 | } |
| 1210 | } |
| 1211 | |
| 1212 | /* Zero sectors per track has to abort (ATA-5 8.16.6), not divide by zero */ |
| 1213 | static void test_specify_zero_sectors(void) |
| 1214 | { |
| 1215 | QTestState *qts; |
| 1216 | QPCIDevice *dev; |
| 1217 | QPCIBar bmdma_bar, ide_bar; |
| 1218 | uint16_t buf[256]; |
| 1219 | uint8_t data; |
| 1220 | int i; |
| 1221 | |
| 1222 | qts = ide_test_start( |
| 1223 | "-blockdev driver=file,node-name=hda,filename=%s " |
| 1224 | "-device ide-hd,drive=hda,bus=ide.0,unit=0 ", |
| 1225 | tmp_path[0]); |
| 1226 | |
| 1227 | dev = get_pci_device(qts, &bmdma_bar, &ide_bar); |
| 1228 | |
| 1229 | qpci_io_writeb(dev, ide_bar, reg_nsectors, 0); |
| 1230 | qpci_io_writeb(dev, ide_bar, reg_device, 0); |
| 1231 | qpci_io_writeb(dev, ide_bar, reg_command, CMD_INIT_DP); |
| 1232 | |
| 1233 | assert_bit_set(qpci_io_readb(dev, ide_bar, reg_status), ERR); |
| 1234 | assert_bit_set(qpci_io_readb(dev, ide_bar, reg_error), ABRT); |
| 1235 | |
| 1236 | /* The refused request has to leave the default translation in effect */ |
| 1237 | ide_identify_words(dev, ide_bar, buf); |
| 1238 | g_assert_cmpint(buf[55], ==, 16); |
| 1239 | g_assert_cmpint(buf[56], ==, 63); |
| 1240 | |
| 1241 | /* READ SECTOR(S) of CHS 0/0/1, which used to crash QEMU */ |
| 1242 | qpci_io_writeb(dev, ide_bar, reg_nsectors, 1); |
| 1243 | qpci_io_writeb(dev, ide_bar, reg_lba_low, 1); |
| 1244 | qpci_io_writeb(dev, ide_bar, reg_lba_middle, 0); |
| 1245 | qpci_io_writeb(dev, ide_bar, reg_lba_high, 0); |
| 1246 | qpci_io_writeb(dev, ide_bar, reg_device, 0); |
| 1247 | qpci_io_writeb(dev, ide_bar, reg_command, CMD_READ); |
| 1248 | |
| 1249 | data = ide_wait_clear(qts, BSY); |
| 1250 | assert_bit_set(data, DRQ); |
| 1251 | assert_bit_clear(data, ERR | DF); |
| 1252 | for (i = 0; i < 256; i++) { |
| 1253 | buf[i] = qpci_io_readw(dev, ide_bar, reg_data); |
| 1254 | } |
| 1255 | assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), ERR | DF | DRQ); |
| 1256 | |
| 1257 | /* A supported translation is still accepted */ |
| 1258 | qpci_io_writeb(dev, ide_bar, reg_nsectors, 32); |
| 1259 | qpci_io_writeb(dev, ide_bar, reg_device, 7); |
| 1260 | qpci_io_writeb(dev, ide_bar, reg_command, CMD_INIT_DP); |
| 1261 | |
| 1262 | assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), ERR); |
| 1263 | |
| 1264 | ide_test_quit(qts); |
| 1265 | free_pci_device(dev); |
| 1266 | } |
| 1267 | |
| 1268 | /* Addressed by LBA, so no translation can influence where it lands */ |
| 1269 | static void ide_write_marker(QTestState *qts, QPCIDevice *dev, QPCIBar ide_bar, |
| 1270 | uint32_t lba, const char *marker) |
| 1271 | { |
| 1272 | uint16_t buf[256]; |
| 1273 | uint8_t data; |
| 1274 | int i; |
| 1275 | |
| 1276 | memset(buf, 0, sizeof(buf)); |
| 1277 | memcpy(buf, marker, strlen(marker)); |
| 1278 | |
| 1279 | qpci_io_writeb(dev, ide_bar, reg_nsectors, 1); |
| 1280 | qpci_io_writeb(dev, ide_bar, reg_lba_low, lba & 0xff); |
| 1281 | qpci_io_writeb(dev, ide_bar, reg_lba_middle, (lba >> 8) & 0xff); |
| 1282 | qpci_io_writeb(dev, ide_bar, reg_lba_high, (lba >> 16) & 0xff); |
| 1283 | qpci_io_writeb(dev, ide_bar, reg_device, LBA | ((lba >> 24) & 0xf)); |
| 1284 | qpci_io_writeb(dev, ide_bar, reg_command, CMD_WRITE); |
| 1285 | |
| 1286 | data = ide_wait_clear(qts, BSY); |
| 1287 | assert_bit_set(data, DRQ); |
| 1288 | for (i = 0; i < 256; i++) { |
| 1289 | qpci_io_writew(dev, ide_bar, reg_data, buf[i]); |
| 1290 | } |
| 1291 | data = ide_wait_clear(qts, BSY); |
| 1292 | assert_bit_clear(data, ERR | DF | DRQ); |
| 1293 | |
| 1294 | qpci_io_writeb(dev, ide_bar, reg_command, CMD_FLUSH_CACHE); |
| 1295 | data = ide_wait_clear(qts, BSY); |
| 1296 | assert_bit_clear(data, ERR | DF); |
| 1297 | } |
| 1298 | |
| 1299 | /* The marker read back names the sector the translation selected */ |
| 1300 | static void ide_read_chs_marker(QTestState *qts, QPCIDevice *dev, |
| 1301 | QPCIBar ide_bar, uint8_t cyl_lo, uint8_t head, |
| 1302 | uint8_t sector, char out[9]) |
| 1303 | { |
| 1304 | uint16_t buf[256]; |
| 1305 | uint8_t data; |
| 1306 | int i; |
| 1307 | |
| 1308 | qpci_io_writeb(dev, ide_bar, reg_nsectors, 1); |
| 1309 | qpci_io_writeb(dev, ide_bar, reg_lba_low, sector); |
| 1310 | qpci_io_writeb(dev, ide_bar, reg_lba_middle, cyl_lo); |
| 1311 | qpci_io_writeb(dev, ide_bar, reg_lba_high, 0); |
| 1312 | qpci_io_writeb(dev, ide_bar, reg_device, head & 0xf); |
| 1313 | qpci_io_writeb(dev, ide_bar, reg_command, CMD_READ); |
| 1314 | |
| 1315 | data = ide_wait_clear(qts, BSY); |
| 1316 | assert_bit_set(data, DRQ); |
| 1317 | assert_bit_clear(data, ERR | DF); |
| 1318 | for (i = 0; i < 256; i++) { |
| 1319 | buf[i] = qpci_io_readw(dev, ide_bar, reg_data); |
| 1320 | } |
| 1321 | data = ide_wait_clear(qts, BSY); |
| 1322 | assert_bit_clear(data, ERR | DF | DRQ); |
| 1323 | |
| 1324 | memcpy(out, buf, 8); |
| 1325 | out[8] = '\0'; |
| 1326 | } |
| 1327 | |
| 1328 | static void ide_set_translation(QPCIDevice *dev, QPCIBar ide_bar, |
| 1329 | uint8_t heads, uint8_t sectors) |
| 1330 | { |
| 1331 | qpci_io_writeb(dev, ide_bar, reg_nsectors, sectors); |
| 1332 | qpci_io_writeb(dev, ide_bar, reg_device, heads - 1); |
| 1333 | qpci_io_writeb(dev, ide_bar, reg_command, CMD_INIT_DP); |
| 1334 | assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), ERR); |
| 1335 | } |
| 1336 | |
| 1337 | /* CHS 0/1/1 is LBA 32 under 8/32, and LBA 63 under the drive's own 16/63 */ |
| 1338 | #define CHS_MARKER_CUSTOM "CUSTOM__" |
| 1339 | #define CHS_MARKER_DEFAULT "DEFAULT_" |
| 1340 | |
| 1341 | static void ide_prepare_markers(QTestState *qts, QPCIDevice *dev, |
| 1342 | QPCIBar ide_bar) |
| 1343 | { |
| 1344 | ide_write_marker(qts, dev, ide_bar, 32, CHS_MARKER_CUSTOM); |
| 1345 | ide_write_marker(qts, dev, ide_bar, 63, CHS_MARKER_DEFAULT); |
| 1346 | } |
| 1347 | |
| 1348 | static void ide_hmp_quiet(QTestState *qts, const char *command) |
| 1349 | { |
| 1350 | g_autofree char *out = qtest_hmp(qts, "%s", command); |
| 1351 | |
| 1352 | g_assert_cmpstr(out, ==, ""); |
| 1353 | } |
| 1354 | |
| 1355 | static char *ide_migration_status(QTestState *qts) |
| 1356 | { |
| 1357 | QDict *ret; |
| 1358 | char *status; |
| 1359 | |
| 1360 | ret = qtest_qmp_assert_success_ref(qts, "{ 'execute': 'query-migrate' }"); |
| 1361 | g_assert(qdict_haskey(ret, "status")); |
| 1362 | status = g_strdup(qdict_get_str(ret, "status")); |
| 1363 | qobject_unref(ret); |
| 1364 | |
| 1365 | return status; |
| 1366 | } |
| 1367 | |
| 1368 | /* Waiting for the other side's event would hang if it refuses the stream */ |
| 1369 | static void ide_migration_wait(QTestState *qts, const char *expected) |
| 1370 | { |
| 1371 | while (true) { |
| 1372 | g_autofree char *status = ide_migration_status(qts); |
| 1373 | |
| 1374 | if (g_str_equal(status, expected)) { |
| 1375 | return; |
| 1376 | } |
| 1377 | if (!g_str_equal(status, "setup") && !g_str_equal(status, "active") && |
| 1378 | !g_str_equal(status, "device")) { |
| 1379 | fprintf(stderr, "Migration status is %s, expected %s\n", |
| 1380 | status, expected); |
| 1381 | g_assert_not_reached(); |
| 1382 | } |
| 1383 | g_usleep(5000); |
| 1384 | } |
| 1385 | } |
| 1386 | |
| 1387 | static void ide_migrate(QTestState *src, QTestState *dst, const char *uri) |
| 1388 | { |
| 1389 | qtest_qmp_assert_success(src, "{ 'execute': 'migrate'," |
| 1390 | " 'arguments': { 'uri': %s } }", uri); |
| 1391 | qtest_qmp_eventwait(src, "STOP"); |
| 1392 | ide_migration_wait(src, "completed"); |
| 1393 | qtest_qmp_eventwait(dst, "RESUME"); |
| 1394 | } |
| 1395 | |
| 1396 | /* A translation the guest selected has to survive migration */ |
| 1397 | static void test_migrate_chs_translation(void) |
| 1398 | { |
| 1399 | QTestState *src, *dst; |
| 1400 | QPCIDevice *dev; |
| 1401 | QPCIBar bmdma_bar, ide_bar; |
| 1402 | g_autofree char *mig_path = NULL; |
| 1403 | g_autofree char *uri = NULL; |
| 1404 | g_autofree char *dst_args = NULL; |
| 1405 | char marker[9]; |
| 1406 | int fd; |
| 1407 | |
| 1408 | fd = g_file_open_tmp("qtest-ide-migration.XXXXXX", &mig_path, NULL); |
| 1409 | g_assert(fd >= 0); |
| 1410 | close(fd); |
| 1411 | uri = g_strdup_printf("unix:%s", mig_path); |
| 1412 | |
| 1413 | src = ide_test_start( |
| 1414 | "-blockdev driver=file,node-name=hda,filename=%s,locking=off " |
| 1415 | "-device ide-hd,drive=hda,bus=ide.0,unit=0 ", |
| 1416 | tmp_path[0]); |
| 1417 | dev = get_pci_device(src, &bmdma_bar, &ide_bar); |
| 1418 | |
| 1419 | ide_prepare_markers(src, dev, ide_bar); |
| 1420 | ide_set_translation(dev, ide_bar, 8, 32); |
| 1421 | ide_read_chs_marker(src, dev, ide_bar, 0, 1, 1, marker); |
| 1422 | g_assert_cmpstr(marker, ==, CHS_MARKER_CUSTOM); |
| 1423 | |
| 1424 | dst_args = g_strdup_printf( |
| 1425 | "-machine pc " |
| 1426 | "-blockdev driver=file,node-name=hda,filename=%s,locking=off " |
| 1427 | "-device ide-hd,drive=hda,bus=ide.0,unit=0 -incoming %s", |
| 1428 | tmp_path[0], uri); |
| 1429 | dst = qtest_init(dst_args); |
| 1430 | |
| 1431 | ide_migrate(src, dst, uri); |
| 1432 | |
| 1433 | /* Talk to the destination instead of the source */ |
| 1434 | qpci_free_pc(pcibus); |
| 1435 | pcibus = NULL; |
| 1436 | free_pci_device(dev); |
| 1437 | dev = get_pci_device(dst, &bmdma_bar, &ide_bar); |
| 1438 | |
| 1439 | ide_read_chs_marker(dst, dev, ide_bar, 0, 1, 1, marker); |
| 1440 | g_assert_cmpstr(marker, ==, CHS_MARKER_CUSTOM); |
| 1441 | |
| 1442 | free_pci_device(dev); |
| 1443 | qtest_quit(dst); |
| 1444 | ide_test_quit(src); |
| 1445 | unlink(mig_path); |
| 1446 | } |
| 1447 | |
| 1448 | /* A translation selected after the snapshot must not outlive loading it */ |
| 1449 | static void test_migrate_chs_snapshot(void) |
| 1450 | { |
| 1451 | QTestState *qts; |
| 1452 | QPCIDevice *dev; |
| 1453 | QPCIBar bmdma_bar, ide_bar; |
| 1454 | g_autofree char *img = NULL; |
| 1455 | char marker[9]; |
| 1456 | int fd; |
| 1457 | |
| 1458 | #ifndef CONFIG_HMP |
| 1459 | g_test_skip("HMP not enabled"); |
| 1460 | return; |
| 1461 | #endif |
| 1462 | if (!have_qemu_img()) { |
| 1463 | g_test_skip("QTEST_QEMU_IMG not set, snapshots need a qcow2 image"); |
| 1464 | return; |
| 1465 | } |
| 1466 | |
| 1467 | fd = g_file_open_tmp("qtest-ide-snapshot.XXXXXX", &img, NULL); |
| 1468 | g_assert(fd >= 0); |
| 1469 | close(fd); |
| 1470 | g_assert(mkimg(img, "qcow2", TEST_IMAGE_SIZE / (1024 * 1024))); |
| 1471 | |
| 1472 | qts = ide_test_start( |
| 1473 | "-blockdev driver=qcow2,node-name=hda,file.driver=file," |
| 1474 | "file.filename=%s " |
| 1475 | "-device ide-hd,drive=hda,bus=ide.0,unit=0 ", img); |
| 1476 | dev = get_pci_device(qts, &bmdma_bar, &ide_bar); |
| 1477 | |
| 1478 | ide_prepare_markers(qts, dev, ide_bar); |
| 1479 | |
| 1480 | /* Snapshot taken while the default translation is in effect */ |
| 1481 | ide_read_chs_marker(qts, dev, ide_bar, 0, 1, 1, marker); |
| 1482 | g_assert_cmpstr(marker, ==, CHS_MARKER_DEFAULT); |
| 1483 | ide_hmp_quiet(qts, "savevm s0"); |
| 1484 | |
| 1485 | ide_set_translation(dev, ide_bar, 8, 32); |
| 1486 | ide_read_chs_marker(qts, dev, ide_bar, 0, 1, 1, marker); |
| 1487 | g_assert_cmpstr(marker, ==, CHS_MARKER_CUSTOM); |
| 1488 | |
| 1489 | ide_hmp_quiet(qts, "loadvm s0"); |
| 1490 | |
| 1491 | ide_read_chs_marker(qts, dev, ide_bar, 0, 1, 1, marker); |
| 1492 | g_assert_cmpstr(marker, ==, CHS_MARKER_DEFAULT); |
| 1493 | |
| 1494 | free_pci_device(dev); |
| 1495 | ide_test_quit(qts); |
| 1496 | unlink(img); |
| 1497 | } |
| 1498 | |
| 1499 | /* A migration stream holds NUL bytes, so this cannot be a string search */ |
| 1500 | static char *ide_stream_find(char *stream, gsize len, const char *name) |
| 1501 | { |
| 1502 | gsize name_len = strlen(name); |
| 1503 | gsize i; |
| 1504 | |
| 1505 | if (len < name_len) { |
| 1506 | return NULL; |
| 1507 | } |
| 1508 | for (i = 0; i <= len - name_len; i++) { |
| 1509 | if (memcmp(stream + i, name, name_len) == 0) { |
| 1510 | return stream + i; |
| 1511 | } |
| 1512 | } |
| 1513 | |
| 1514 | return NULL; |
| 1515 | } |
| 1516 | |
| 1517 | /* A translation no command could have selected has to be refused on load */ |
| 1518 | static void test_migrate_chs_rejected(void) |
| 1519 | { |
| 1520 | const char *name = "ide_drive/chs_translation"; |
| 1521 | QTestState *src, *dst; |
| 1522 | QPCIDevice *dev; |
| 1523 | QPCIBar bmdma_bar, ide_bar; |
| 1524 | g_autofree char *path = NULL; |
| 1525 | g_autofree char *uri = NULL; |
| 1526 | g_autofree char *dst_args = NULL; |
| 1527 | g_autofree char *stream = NULL; |
| 1528 | char *subsection; |
| 1529 | gsize len; |
| 1530 | int fd; |
| 1531 | |
| 1532 | fd = g_file_open_tmp("qtest-ide-stream.XXXXXX", &path, NULL); |
| 1533 | g_assert(fd >= 0); |
| 1534 | close(fd); |
| 1535 | uri = g_strdup_printf("file:%s", path); |
| 1536 | |
| 1537 | src = ide_test_start( |
| 1538 | "-blockdev driver=file,node-name=hda,filename=%s " |
| 1539 | "-device ide-hd,drive=hda,bus=ide.0,unit=0 ", |
| 1540 | tmp_path[0]); |
| 1541 | dev = get_pci_device(src, &bmdma_bar, &ide_bar); |
| 1542 | |
| 1543 | ide_set_translation(dev, ide_bar, 8, 32); |
| 1544 | qtest_qmp_assert_success(src, "{ 'execute': 'migrate'," |
| 1545 | " 'arguments': { 'uri': %s } }", uri); |
| 1546 | qtest_qmp_eventwait(src, "STOP"); |
| 1547 | ide_migration_wait(src, "completed"); |
| 1548 | free_pci_device(dev); |
| 1549 | ide_test_quit(src); |
| 1550 | |
| 1551 | /* |
| 1552 | * Behind the name come version, heads and sectors, each big endian 32 bit. |
| 1553 | * The name recurs in the description at the end of the stream, so the |
| 1554 | * first match is the one carrying data. |
| 1555 | */ |
| 1556 | g_assert(g_file_get_contents(path, &stream, &len, NULL)); |
| 1557 | subsection = ide_stream_find(stream, len, name); |
| 1558 | g_assert(subsection); |
| 1559 | g_assert_cmpint(subsection - stream + strlen(name) + 12, <=, len); |
| 1560 | memset(subsection + strlen(name) + 8, 0, 4); |
| 1561 | g_assert(g_file_set_contents(path, stream, len, NULL)); |
| 1562 | |
| 1563 | dst_args = g_strdup_printf( |
| 1564 | "-machine pc " |
| 1565 | "-blockdev driver=file,node-name=hda,filename=%s " |
| 1566 | "-device ide-hd,drive=hda,bus=ide.0,unit=0 -incoming defer", |
| 1567 | tmp_path[0]); |
| 1568 | dst = qtest_init(dst_args); |
| 1569 | |
| 1570 | qtest_qmp_assert_success(dst, "{ 'execute': 'migrate-incoming'," |
| 1571 | " 'arguments': { 'uri': %s," |
| 1572 | " 'exit-on-error': false } }", uri); |
| 1573 | ide_migration_wait(dst, "failed"); |
| 1574 | |
| 1575 | qtest_quit(dst); |
| 1576 | unlink(path); |
| 1577 | } |
| 1578 | |
| 1579 | /* |
| 1580 | * A device advertising UDMA5 has to claim a standard that defines it, and a |
| 1581 | * parallel attachment has to report the cable word (ACS-3 7.12.7.47). |
| 1582 | */ |
| 1583 | static void test_identify_udma(bool packet) |
| 1584 | { |
| 1585 | QTestState *qts; |
| 1586 | QPCIDevice *dev; |
| 1587 | QPCIBar bmdma_bar, ide_bar; |
| 1588 | uint16_t buf[256]; |
| 1589 | int i; |
| 1590 | |
| 1591 | if (packet) { |
| 1592 | qts = ide_test_start("-device ide-cd,bus=ide.0"); |
| 1593 | } else { |
| 1594 | qts = ide_test_start( |
| 1595 | "-blockdev driver=file,node-name=hda,filename=%s " |
| 1596 | "-device ide-hd,drive=hda,bus=ide.0,unit=0 ", |
| 1597 | tmp_path[0]); |
| 1598 | } |
| 1599 | dev = get_pci_device(qts, &bmdma_bar, &ide_bar); |
| 1600 | |
| 1601 | qpci_io_writeb(dev, ide_bar, reg_device, 0); |
| 1602 | qpci_io_writeb(dev, ide_bar, reg_command, |
| 1603 | packet ? CMD_IDENTIFY_PACKET : CMD_IDENTIFY); |
| 1604 | for (i = 0; i < 256; i++) { |
| 1605 | buf[i] = qpci_io_readw(dev, ide_bar, reg_data); |
| 1606 | } |
| 1607 | |
| 1608 | /* UDMA5 supported and selected */ |
| 1609 | assert_bit_set(buf[88], 1 << 5); |
| 1610 | assert_bit_set(buf[88], 1 << 13); |
| 1611 | |
| 1612 | /* UDMA5 arrived in ATA/ATAPI-6, so word 80 has to reach bit 6 */ |
| 1613 | assert_bit_set(buf[80], 1 << 6); |
| 1614 | if (packet) { |
| 1615 | /* Bits 3:1 are obsolete in IDENTIFY PACKET DEVICE data */ |
| 1616 | assert_bit_clear(buf[80], 0x0e); |
| 1617 | } |
| 1618 | |
| 1619 | /* Word 93: reserved bit clear, fixed bit set, 80-conductor cable */ |
| 1620 | assert_bit_clear(buf[93], 1 << 15); |
| 1621 | assert_bit_set(buf[93], 1 << 14); |
| 1622 | assert_bit_set(buf[93], 1 << 13); |
| 1623 | assert_bit_set(buf[93], 1 << 0); |
| 1624 | /* Device 0 clears the device 1 result */ |
| 1625 | assert_bit_clear(buf[93], 0x1f00); |
| 1626 | if (packet) { |
| 1627 | /* the disk path has yet to gain this */ |
| 1628 | assert_bit_set(buf[93], 1 << 3); |
| 1629 | } |
| 1630 | |
| 1631 | free_pci_device(dev); |
| 1632 | ide_test_quit(qts); |
| 1633 | } |
| 1634 | |
| 1635 | static void test_identify_udma_ata(void) |
| 1636 | { |
| 1637 | test_identify_udma(false); |
| 1638 | } |
| 1639 | |
| 1640 | static void test_identify_udma_atapi(void) |
| 1641 | { |
| 1642 | test_identify_udma(true); |
| 1643 | } |
| 1644 | |
| 1645 | /* A PIO transfer window reaching past the io_buffer has to be refused */ |
| 1646 | static void test_migrate_pio_state_rejected(void) |
| 1647 | { |
| 1648 | const char *name = "ide_drive/pio_state"; |
| 1649 | /* IDE_DMA_BUF_SECTORS * 512 + 4, the length of the streamed io_buffer */ |
| 1650 | const gsize io_buffer_len = 256 * 512 + 4; |
| 1651 | /* cur_io_buffer_offset and cur_io_buffer_len, big endian */ |
| 1652 | const uint8_t in_bounds[8] = { 0, 0, 0, 0, 0, 0, 0x02, 0 }; |
| 1653 | const uint8_t past_the_end[8] = { 0, 0x02, 0, 0x04, 0, 0, 0x10, 0 }; |
| 1654 | QTestState *src, *dst; |
| 1655 | QPCIDevice *dev; |
| 1656 | QPCIBar bmdma_bar, ide_bar; |
| 1657 | g_autofree char *path = NULL; |
| 1658 | g_autofree char *uri = NULL; |
| 1659 | g_autofree char *dst_args = NULL; |
| 1660 | g_autofree char *stream = NULL; |
| 1661 | char *window; |
| 1662 | gsize len; |
| 1663 | int fd; |
| 1664 | |
| 1665 | fd = g_file_open_tmp("qtest-ide-stream.XXXXXX", &path, NULL); |
| 1666 | g_assert(fd >= 0); |
| 1667 | close(fd); |
| 1668 | uri = g_strdup_printf("file:%s", path); |
| 1669 | |
| 1670 | src = ide_test_start( |
| 1671 | "-blockdev driver=file,node-name=hda,filename=%s " |
| 1672 | "-device ide-hd,drive=hda,bus=ide.0,unit=0 ", |
| 1673 | tmp_path[0]); |
| 1674 | dev = get_pci_device(src, &bmdma_bar, &ide_bar); |
| 1675 | |
| 1676 | /* WRITE SECTOR(S) waits in DRQ for the data, so pio_state is streamed */ |
| 1677 | qpci_io_writeb(dev, ide_bar, reg_nsectors, 1); |
| 1678 | qpci_io_writeb(dev, ide_bar, reg_lba_low, 0); |
| 1679 | qpci_io_writeb(dev, ide_bar, reg_lba_middle, 0); |
| 1680 | qpci_io_writeb(dev, ide_bar, reg_lba_high, 0); |
| 1681 | qpci_io_writeb(dev, ide_bar, reg_device, LBA); |
| 1682 | qpci_io_writeb(dev, ide_bar, reg_command, CMD_WRITE); |
| 1683 | assert_bit_set(qpci_io_readb(dev, ide_bar, reg_status), DRQ); |
| 1684 | |
| 1685 | qtest_qmp_assert_success(src, "{ 'execute': 'migrate'," |
| 1686 | " 'arguments': { 'uri': %s } }", uri); |
| 1687 | qtest_qmp_eventwait(src, "STOP"); |
| 1688 | ide_migration_wait(src, "completed"); |
| 1689 | free_pci_device(dev); |
| 1690 | ide_test_quit(src); |
| 1691 | |
| 1692 | /* |
| 1693 | * Behind the name come the version and req_nb_sectors as big endian 32 |
| 1694 | * bit, then the io_buffer array, then the transfer window this rewrites. |
| 1695 | * Asserting the window the source streamed keeps that arithmetic honest. |
| 1696 | */ |
| 1697 | g_assert(g_file_get_contents(path, &stream, &len, NULL)); |
| 1698 | window = ide_stream_find(stream, len, name); |
| 1699 | g_assert(window); |
| 1700 | window += strlen(name) + 8 + io_buffer_len; |
| 1701 | g_assert_cmpint(window - stream + sizeof(past_the_end), <=, len); |
| 1702 | g_assert_cmpint(memcmp(window, in_bounds, sizeof(in_bounds)), ==, 0); |
| 1703 | memcpy(window, past_the_end, sizeof(past_the_end)); |
| 1704 | g_assert(g_file_set_contents(path, stream, len, NULL)); |
| 1705 | |
| 1706 | dst_args = g_strdup_printf( |
| 1707 | "-machine pc " |
| 1708 | "-blockdev driver=file,node-name=hda,filename=%s " |
| 1709 | "-device ide-hd,drive=hda,bus=ide.0,unit=0 -incoming defer", |
| 1710 | tmp_path[0]); |
| 1711 | dst = qtest_init(dst_args); |
| 1712 | |
| 1713 | qtest_qmp_assert_success(dst, "{ 'execute': 'migrate-incoming'," |
| 1714 | " 'arguments': { 'uri': %s," |
| 1715 | " 'exit-on-error': false } }", uri); |
| 1716 | ide_migration_wait(dst, "failed"); |
| 1717 | |
| 1718 | qtest_quit(dst); |
| 1719 | unlink(path); |
| 1720 | } |
| 1721 | |
| 1722 | /* Words 54 to 58 follow the translation even when the data was cached first */ |
| 1723 | static void test_specify_identify(void) |
| 1724 | { |
| 1725 | QTestState *qts; |
| 1726 | QPCIDevice *dev; |
| 1727 | QPCIBar bmdma_bar, ide_bar; |
| 1728 | uint16_t buf[256]; |
| 1729 | unsigned int cyls; |
| 1730 | |
| 1731 | qts = ide_test_start( |
| 1732 | "-blockdev driver=file,node-name=hda,filename=%s " |
| 1733 | "-device ide-hd,drive=hda,bus=ide.0,unit=0 ", |
| 1734 | tmp_path[0]); |
| 1735 | dev = get_pci_device(qts, &bmdma_bar, &ide_bar); |
| 1736 | |
| 1737 | /* Have the data built while the default translation is still in effect */ |
| 1738 | ide_identify_words(dev, ide_bar, buf); |
| 1739 | cyls = buf[1]; |
| 1740 | g_assert_cmpint(buf[3], ==, 16); |
| 1741 | g_assert_cmpint(buf[6], ==, 63); |
| 1742 | g_assert_cmpint(buf[53] & 1, ==, 1); |
| 1743 | g_assert_cmpint(buf[55], ==, 16); |
| 1744 | g_assert_cmpint(buf[56], ==, 63); |
| 1745 | g_assert_cmpint(buf[57] | (buf[58] << 16), ==, cyls * 16 * 63); |
| 1746 | |
| 1747 | ide_set_translation(dev, ide_bar, 8, 32); |
| 1748 | |
| 1749 | ide_identify_words(dev, ide_bar, buf); |
| 1750 | g_assert_cmpint(buf[1], ==, cyls); |
| 1751 | g_assert_cmpint(buf[3], ==, 16); |
| 1752 | g_assert_cmpint(buf[4], ==, 512 * 63); |
| 1753 | g_assert_cmpint(buf[6], ==, 63); |
| 1754 | g_assert_cmpint(buf[55], ==, 8); |
| 1755 | g_assert_cmpint(buf[56], ==, 32); |
| 1756 | g_assert_cmpint(buf[57] | (buf[58] << 16), ==, cyls * 8 * 32); |
| 1757 | |
| 1758 | free_pci_device(dev); |
| 1759 | ide_test_quit(qts); |
| 1760 | } |
| 1761 | |
| 1762 | /* Words 3 and 6 keep the drive's own geometry even if built after a change */ |
| 1763 | static void test_specify_identify_default(void) |
| 1764 | { |
| 1765 | QTestState *qts; |
| 1766 | QPCIDevice *dev; |
| 1767 | QPCIBar bmdma_bar, ide_bar; |
| 1768 | uint16_t buf[256]; |
| 1769 | |
| 1770 | qts = ide_test_start( |
| 1771 | "-blockdev driver=file,node-name=hda,filename=%s " |
| 1772 | "-device ide-hd,drive=hda,bus=ide.0,unit=0 ", |
| 1773 | tmp_path[0]); |
| 1774 | dev = get_pci_device(qts, &bmdma_bar, &ide_bar); |
| 1775 | |
| 1776 | /* No IDENTIFY DEVICE before this one, so nothing was cached yet */ |
| 1777 | ide_set_translation(dev, ide_bar, 8, 32); |
| 1778 | ide_identify_words(dev, ide_bar, buf); |
| 1779 | g_assert_cmpint(buf[3], ==, 16); |
| 1780 | g_assert_cmpint(buf[4], ==, 512 * 63); |
| 1781 | g_assert_cmpint(buf[6], ==, 63); |
| 1782 | g_assert_cmpint(buf[55], ==, 8); |
| 1783 | g_assert_cmpint(buf[56], ==, 32); |
| 1784 | g_assert_cmpint(buf[57] | (buf[58] << 16), ==, buf[1] * 8 * 32); |
| 1785 | |
| 1786 | free_pci_device(dev); |
| 1787 | ide_test_quit(qts); |
| 1788 | } |
| 1789 | |
| 1790 | /* A hardware reset reverts the translation (ATA-5 9.1), SRST does not (9.2) */ |
| 1791 | static void test_specify_reset(void) |
| 1792 | { |
| 1793 | QTestState *qts; |
| 1794 | QPCIDevice *dev; |
| 1795 | QPCIBar bmdma_bar, ide_bar, ide_bar2; |
| 1796 | uint16_t buf[256]; |
| 1797 | char marker[9]; |
| 1798 | |
| 1799 | qts = ide_test_start( |
| 1800 | "-blockdev driver=file,node-name=hda,filename=%s " |
| 1801 | "-device ide-hd,drive=hda,bus=ide.0,unit=0 ", |
| 1802 | tmp_path[0]); |
| 1803 | dev = get_pci_device(qts, &bmdma_bar, &ide_bar); |
| 1804 | ide_bar2 = qpci_legacy_iomap(dev, IDE_BASE2); |
| 1805 | |
| 1806 | ide_prepare_markers(qts, dev, ide_bar); |
| 1807 | ide_set_translation(dev, ide_bar, 8, 32); |
| 1808 | ide_read_chs_marker(qts, dev, ide_bar, 0, 1, 1, marker); |
| 1809 | g_assert_cmpstr(marker, ==, CHS_MARKER_CUSTOM); |
| 1810 | |
| 1811 | qpci_io_writeb(dev, ide_bar2, 0, IDE_CTRL_RESET); |
| 1812 | qpci_io_writeb(dev, ide_bar2, 0, 0); |
| 1813 | ide_wait_clear(qts, BSY); |
| 1814 | |
| 1815 | ide_identify_words(dev, ide_bar, buf); |
| 1816 | g_assert_cmpint(buf[55], ==, 8); |
| 1817 | g_assert_cmpint(buf[56], ==, 32); |
| 1818 | ide_read_chs_marker(qts, dev, ide_bar, 0, 1, 1, marker); |
| 1819 | g_assert_cmpstr(marker, ==, CHS_MARKER_CUSTOM); |
| 1820 | |
| 1821 | qtest_qmp_assert_success(qts, "{ 'execute': 'system_reset' }"); |
| 1822 | qtest_qmp_eventwait(qts, "RESET"); |
| 1823 | qpci_device_enable(dev); |
| 1824 | |
| 1825 | ide_identify_words(dev, ide_bar, buf); |
| 1826 | g_assert_cmpint(buf[55], ==, 16); |
| 1827 | g_assert_cmpint(buf[56], ==, 63); |
| 1828 | ide_read_chs_marker(qts, dev, ide_bar, 0, 1, 1, marker); |
| 1829 | g_assert_cmpstr(marker, ==, CHS_MARKER_DEFAULT); |
| 1830 | |
| 1831 | free_pci_device(dev); |
| 1832 | ide_test_quit(qts); |
| 1833 | } |
| 1834 | |
| 1835 | static void test_cdrom_pio(void) |
| 1836 | { |
| 1837 | cdrom_read_impl(1, CDROM_PIO); |
| 1838 | } |
| 1839 | |
| 1840 | static void test_cdrom_pio_large(void) |
| 1841 | { |
| 1842 | /* Test a few loops of the PIO DRQ mechanism. */ |
| 1843 | cdrom_read_impl(BYTE_COUNT_LIMIT * 4 / ATAPI_BLOCK_SIZE, CDROM_PIO); |
| 1844 | } |
| 1845 | |
| 1846 | static void test_cdrom_dma(void) |
| 1847 | { |
| 1848 | cdrom_read_impl(1, CDROM_DMA); |
| 1849 | } |
| 1850 | |
| 1851 | static void test_cdrom_dma_large(void) |
| 1852 | { |
| 1853 | cdrom_read_impl(BYTE_COUNT_LIMIT * 4 / ATAPI_BLOCK_SIZE, CDROM_DMA); |
| 1854 | } |
| 1855 | |
| 1856 | static void test_cdrom_pio_raw(void) |
| 1857 | { |
| 1858 | cdrom_read_impl(4, CDROM_RAW); |
| 1859 | } |
| 1860 | |
| 1861 | static void test_cdrom_dma_raw(void) |
| 1862 | { |
| 1863 | cdrom_read_impl(4, CDROM_DMA | CDROM_RAW); |
| 1864 | } |
| 1865 | |
| 1866 | int main(int argc, char **argv) |
| 1867 | { |
| 1868 | const char *base; |
| 1869 | int i; |
| 1870 | int fd; |
| 1871 | int ret; |
| 1872 | |
| 1873 | /* |
| 1874 | * "base" stores the starting point where we create temporary files. |
| 1875 | * |
| 1876 | * On Windows, this is set to the relative path of current working |
| 1877 | * directory, because the absolute path causes the blkdebug filename |
| 1878 | * parser fail to parse "blkdebug:path/to/config:path/to/image". |
| 1879 | */ |
| 1880 | #ifndef _WIN32 |
| 1881 | base = g_get_tmp_dir(); |
| 1882 | #else |
| 1883 | base = "."; |
| 1884 | #endif |
| 1885 | |
| 1886 | /* Create temporary blkdebug instructions */ |
| 1887 | debug_path = g_strdup_printf("%s/qtest-blkdebug.XXXXXX", base); |
| 1888 | fd = g_mkstemp(debug_path); |
| 1889 | g_assert(fd >= 0); |
| 1890 | close(fd); |
| 1891 | |
| 1892 | /* Create a temporary raw image */ |
| 1893 | for (i = 0; i < 2; ++i) { |
| 1894 | tmp_path[i] = g_strdup_printf("%s/qtest.XXXXXX", base); |
| 1895 | fd = g_mkstemp(tmp_path[i]); |
| 1896 | g_assert(fd >= 0); |
| 1897 | ret = ftruncate(fd, TEST_IMAGE_SIZE); |
| 1898 | g_assert(ret == 0); |
| 1899 | close(fd); |
| 1900 | } |
| 1901 | |
| 1902 | /* Run the tests */ |
| 1903 | g_test_init(&argc, &argv, NULL); |
| 1904 | |
| 1905 | qtest_add_func("/ide/read_native", test_specify); |
| 1906 | qtest_add_func("/ide/specify/zero_sectors", test_specify_zero_sectors); |
| 1907 | qtest_add_func("/ide/specify/identify", test_specify_identify); |
| 1908 | qtest_add_func("/ide/specify/identify_default", |
| 1909 | test_specify_identify_default); |
| 1910 | qtest_add_func("/ide/specify/reset", test_specify_reset); |
| 1911 | qtest_add_func("/ide/migration/chs_translation", |
| 1912 | test_migrate_chs_translation); |
| 1913 | qtest_add_func("/ide/migration/chs_snapshot", test_migrate_chs_snapshot); |
| 1914 | qtest_add_func("/ide/migration/chs_rejected", test_migrate_chs_rejected); |
| 1915 | qtest_add_func("/ide/migration/pio_state_rejected", |
| 1916 | test_migrate_pio_state_rejected); |
| 1917 | qtest_add_func("/ide/identify/udma", test_identify_udma_ata); |
| 1918 | qtest_add_func("/ide/identify/udma_atapi", test_identify_udma_atapi); |
| 1919 | |
| 1920 | qtest_add_func("/ide/identify", test_identify); |
| 1921 | |
| 1922 | qtest_add_func("/ide/diagnostic", test_diagnostic); |
| 1923 | |
| 1924 | qtest_add_func("/ide/bmdma/simple_rw", test_bmdma_simple_rw); |
| 1925 | qtest_add_func("/ide/bmdma/trim", test_bmdma_trim); |
| 1926 | qtest_add_func("/ide/bmdma/trim_reset", test_bmdma_trim_reset); |
| 1927 | qtest_add_func("/ide/bmdma/various_prdts", test_bmdma_various_prdts); |
| 1928 | qtest_add_func("/ide/bmdma/no_busmaster", test_bmdma_no_busmaster); |
| 1929 | |
| 1930 | qtest_add_func("/ide/flush", test_flush); |
| 1931 | qtest_add_func("/ide/flush/nodev", test_flush_nodev); |
| 1932 | qtest_add_func("/ide/flush/empty_drive", test_flush_empty_drive); |
| 1933 | qtest_add_func("/ide/flush/retry_pci", test_pci_retry_flush); |
| 1934 | |
| 1935 | qtest_add_func("/ide/cdrom/pio", test_cdrom_pio); |
| 1936 | qtest_add_func("/ide/cdrom/pio_large", test_cdrom_pio_large); |
| 1937 | qtest_add_func("/ide/cdrom/dma", test_cdrom_dma); |
| 1938 | qtest_add_func("/ide/cdrom/dma_large", test_cdrom_dma_large); |
| 1939 | qtest_add_func("/ide/cdrom/pio_raw", test_cdrom_pio_raw); |
| 1940 | qtest_add_func("/ide/cdrom/dma_raw", test_cdrom_dma_raw); |
| 1941 | |
| 1942 | ret = g_test_run(); |
| 1943 | |
| 1944 | /* Cleanup */ |
| 1945 | for (i = 0; i < 2; ++i) { |
| 1946 | unlink(tmp_path[i]); |
| 1947 | g_free(tmp_path[i]); |
| 1948 | } |
| 1949 | unlink(debug_path); |
| 1950 | g_free(debug_path); |
| 1951 | |
| 1952 | return ret; |
| 1953 | } |