| 1 | /* |
| 2 | * QTest testcase for RISC-V IOMMU with iommu-testdev |
| 3 | * |
| 4 | * This QTest file is used to test the RISC-V IOMMU with iommu-testdev so that |
| 5 | * we can test RISC-V IOMMU without any guest kernel or firmware. |
| 6 | * |
| 7 | * Copyright (c) 2026 Chao Liu <chao.liu.zevorn@gmail.com> |
| 8 | * |
| 9 | * SPDX-License-Identifier: GPL-2.0-or-later |
| 10 | */ |
| 11 | |
| 12 | #include "qemu/osdep.h" |
| 13 | #include "libqos/generic-pcihost.h" |
| 14 | #include "hw/pci/pci_regs.h" |
| 15 | #include "hw/misc/iommu-testdev.h" |
| 16 | #include "hw/riscv/riscv-iommu-bits.h" |
| 17 | #include "libqos/qos-riscv-iommu.h" |
| 18 | #include "libqos/riscv-iommu.h" |
| 19 | |
| 20 | #define DMA_LEN 4 |
| 21 | |
| 22 | /* RISC-V virt machine PCI configuration */ |
| 23 | #define RISCV_GPEX_PIO_BASE 0x3000000 |
| 24 | #define RISCV_BUS_PIO_LIMIT 0x10000 |
| 25 | #define RISCV_BUS_MMIO_ALLOC_PTR 0x40000000 |
| 26 | #define RISCV_BUS_MMIO_LIMIT 0x80000000 |
| 27 | #define RISCV_ECAM_ALLOC_PTR 0x30000000 |
| 28 | |
| 29 | typedef struct RiscvIommuTestState { |
| 30 | QTestState *qts; |
| 31 | QGenericPCIBus gbus; |
| 32 | QPCIDevice *iommu_dev; |
| 33 | QPCIDevice *testdev; |
| 34 | QPCIBar testdev_bar; |
| 35 | uint64_t iommu_base; |
| 36 | } RiscvIommuTestState; |
| 37 | |
| 38 | static void riscv_config_qpci_bus(QGenericPCIBus *qpci) |
| 39 | { |
| 40 | qpci->gpex_pio_base = RISCV_GPEX_PIO_BASE; |
| 41 | qpci->bus.pio_limit = RISCV_BUS_PIO_LIMIT; |
| 42 | qpci->bus.mmio_alloc_ptr = RISCV_BUS_MMIO_ALLOC_PTR; |
| 43 | qpci->bus.mmio_limit = RISCV_BUS_MMIO_LIMIT; |
| 44 | qpci->ecam_alloc_ptr = RISCV_ECAM_ALLOC_PTR; |
| 45 | } |
| 46 | |
| 47 | static uint64_t riscv_iommu_expected_gpa(uint64_t iova) |
| 48 | { |
| 49 | return QRIOMMU_SPACE_OFFS + QRIOMMU_L2_PTE_VAL + (iova & 0xfff); |
| 50 | } |
| 51 | |
| 52 | static void save_fn(QPCIDevice *dev, int devfn, void *data) |
| 53 | { |
| 54 | QPCIDevice **pdev = (QPCIDevice **) data; |
| 55 | uint16_t vendor = qpci_config_readw(dev, 0); |
| 56 | uint16_t device = qpci_config_readw(dev, 2); |
| 57 | |
| 58 | g_test_message("Found PCI device: vendor=0x%04x device=0x%04x devfn=0x%02x", |
| 59 | vendor, device, devfn); |
| 60 | |
| 61 | if (!*pdev) { |
| 62 | *pdev = dev; |
| 63 | } |
| 64 | } |
| 65 | |
| 66 | static QPCIDevice *find_riscv_iommu_pci(QGenericPCIBus *gbus, |
| 67 | uint64_t *iommu_base) |
| 68 | { |
| 69 | QPCIDevice *iommu_dev = NULL; |
| 70 | QPCIBar iommu_bar; |
| 71 | |
| 72 | g_test_message("Searching for riscv-iommu-pci " |
| 73 | "(vendor=0x%04x, device=0x%04x)", |
| 74 | RISCV_IOMMU_PCI_VENDOR_ID, RISCV_IOMMU_PCI_DEVICE_ID); |
| 75 | |
| 76 | qpci_device_foreach(&gbus->bus, RISCV_IOMMU_PCI_VENDOR_ID, |
| 77 | RISCV_IOMMU_PCI_DEVICE_ID, save_fn, &iommu_dev); |
| 78 | |
| 79 | if (!iommu_dev) { |
| 80 | g_test_message("riscv-iommu-pci device not found!"); |
| 81 | return NULL; |
| 82 | } |
| 83 | |
| 84 | g_test_message("Found riscv-iommu-pci at devfn=0x%02x", iommu_dev->devfn); |
| 85 | |
| 86 | qpci_device_enable(iommu_dev); |
| 87 | iommu_bar = qpci_iomap(iommu_dev, 0, NULL); |
| 88 | g_assert_false(iommu_bar.is_io); |
| 89 | |
| 90 | *iommu_base = iommu_bar.addr; |
| 91 | g_test_message("RISC-V IOMMU MMIO base address: 0x%" PRIx64, *iommu_base); |
| 92 | |
| 93 | return iommu_dev; |
| 94 | } |
| 95 | |
| 96 | static QPCIDevice *find_iommu_testdev(QGenericPCIBus *gbus, QPCIBar *bar) |
| 97 | { |
| 98 | QPCIDevice *dev = NULL; |
| 99 | |
| 100 | g_test_message("Searching for iommu-testdev (vendor=0x%04x, device=0x%04x)", |
| 101 | IOMMU_TESTDEV_VENDOR_ID, IOMMU_TESTDEV_DEVICE_ID); |
| 102 | |
| 103 | qpci_device_foreach(&gbus->bus, IOMMU_TESTDEV_VENDOR_ID, |
| 104 | IOMMU_TESTDEV_DEVICE_ID, save_fn, &dev); |
| 105 | g_assert(dev); |
| 106 | |
| 107 | qpci_device_enable(dev); |
| 108 | *bar = qpci_iomap(dev, 0, NULL); |
| 109 | g_assert_false(bar->is_io); |
| 110 | |
| 111 | return dev; |
| 112 | } |
| 113 | |
| 114 | static bool riscv_iommu_test_setup(RiscvIommuTestState *state) |
| 115 | { |
| 116 | if (!qtest_has_machine("virt")) { |
| 117 | g_test_skip("virt machine not available"); |
| 118 | return false; |
| 119 | } |
| 120 | |
| 121 | state->qts = qtest_init("-machine virt,acpi=off " |
| 122 | "-cpu max -smp 1 -m 512 -net none " |
| 123 | "-device riscv-iommu-pci " |
| 124 | "-device iommu-testdev"); |
| 125 | |
| 126 | qpci_init_generic(&state->gbus, state->qts, NULL, false); |
| 127 | riscv_config_qpci_bus(&state->gbus); |
| 128 | |
| 129 | state->iommu_dev = find_riscv_iommu_pci(&state->gbus, &state->iommu_base); |
| 130 | g_assert(state->iommu_dev); |
| 131 | |
| 132 | state->testdev = find_iommu_testdev(&state->gbus, &state->testdev_bar); |
| 133 | g_assert(state->testdev); |
| 134 | |
| 135 | return true; |
| 136 | } |
| 137 | |
| 138 | static void riscv_iommu_test_teardown(RiscvIommuTestState *state) |
| 139 | { |
| 140 | g_free(state->iommu_dev); |
| 141 | g_free(state->testdev); |
| 142 | qtest_quit(state->qts); |
| 143 | } |
| 144 | |
| 145 | static uint64_t riscv_iommu_check(QTestState *qts, uint64_t iommu_base, |
| 146 | QRIOMMUTransMode mode) |
| 147 | { |
| 148 | uint64_t cap; |
| 149 | uint64_t ddtp; |
| 150 | uint32_t cqcsr; |
| 151 | uint32_t fqcsr; |
| 152 | uint32_t pqcsr; |
| 153 | uint32_t fctl; |
| 154 | uint32_t fctl_mask; |
| 155 | uint32_t fctl_desired; |
| 156 | uint32_t igs; |
| 157 | |
| 158 | cap = qtest_readq(qts, iommu_base + RISCV_IOMMU_REG_CAP); |
| 159 | g_assert_cmpuint((uint32_t)(cap & RISCV_IOMMU_CAP_VERSION), ==, |
| 160 | RISCV_IOMMU_SPEC_DOT_VER); |
| 161 | |
| 162 | fctl = qtest_readl(qts, iommu_base + RISCV_IOMMU_REG_FCTL); |
| 163 | igs = (cap & RISCV_IOMMU_CAP_IGS) >> 28; |
| 164 | g_assert_cmpuint(igs, <=, RISCV_IOMMU_CAP_IGS_BOTH); |
| 165 | |
| 166 | fctl_mask = RISCV_IOMMU_FCTL_BE | RISCV_IOMMU_FCTL_WSI | |
| 167 | RISCV_IOMMU_FCTL_GXL; |
| 168 | fctl_desired = fctl & ~fctl_mask; |
| 169 | if (igs == RISCV_IOMMU_CAP_IGS_WSI) { |
| 170 | fctl_desired |= RISCV_IOMMU_FCTL_WSI; |
| 171 | } |
| 172 | |
| 173 | if ((fctl & fctl_mask) != (fctl_desired & fctl_mask)) { |
| 174 | ddtp = qtest_readq(qts, iommu_base + RISCV_IOMMU_REG_DDTP); |
| 175 | cqcsr = qtest_readl(qts, iommu_base + RISCV_IOMMU_REG_CQCSR); |
| 176 | fqcsr = qtest_readl(qts, iommu_base + RISCV_IOMMU_REG_FQCSR); |
| 177 | pqcsr = qtest_readl(qts, iommu_base + RISCV_IOMMU_REG_PQCSR); |
| 178 | |
| 179 | g_assert_cmpuint((uint32_t)(ddtp & RISCV_IOMMU_DDTP_MODE), ==, |
| 180 | RISCV_IOMMU_DDTP_MODE_OFF); |
| 181 | g_assert_cmpuint(cqcsr & RISCV_IOMMU_CQCSR_CQON, ==, 0); |
| 182 | g_assert_cmpuint(fqcsr & RISCV_IOMMU_FQCSR_FQON, ==, 0); |
| 183 | g_assert_cmpuint(pqcsr & RISCV_IOMMU_PQCSR_PQON, ==, 0); |
| 184 | |
| 185 | qtest_writel(qts, iommu_base + RISCV_IOMMU_REG_FCTL, fctl_desired); |
| 186 | fctl = qtest_readl(qts, iommu_base + RISCV_IOMMU_REG_FCTL); |
| 187 | } |
| 188 | |
| 189 | g_assert_cmpuint(fctl & fctl_mask, ==, fctl_desired & fctl_mask); |
| 190 | |
| 191 | if (mode == QRIOMMU_TM_S_STAGE_ONLY || mode == QRIOMMU_TM_NESTED) { |
| 192 | g_assert((cap & RISCV_IOMMU_CAP_SV39) != 0); |
| 193 | } |
| 194 | if (mode == QRIOMMU_TM_G_STAGE_ONLY || mode == QRIOMMU_TM_NESTED) { |
| 195 | g_assert((cap & RISCV_IOMMU_CAP_SV39X4) != 0); |
| 196 | g_assert_cmpuint(fctl & RISCV_IOMMU_FCTL_GXL, ==, 0); |
| 197 | } |
| 198 | |
| 199 | return cap; |
| 200 | } |
| 201 | |
| 202 | static void run_riscv_iommu_translation(const QRIOMMUTestConfig *cfg) |
| 203 | { |
| 204 | RiscvIommuTestState state = { 0 }; |
| 205 | |
| 206 | if (!riscv_iommu_test_setup(&state)) { |
| 207 | return; |
| 208 | } |
| 209 | |
| 210 | riscv_iommu_check(state.qts, state.iommu_base, cfg->trans_mode); |
| 211 | |
| 212 | g_test_message("### RISC-V IOMMU translation mode=%d ###", |
| 213 | cfg->trans_mode); |
| 214 | qriommu_run_translation_case(state.qts, state.testdev, state.testdev_bar, |
| 215 | state.iommu_base, cfg); |
| 216 | riscv_iommu_test_teardown(&state); |
| 217 | } |
| 218 | |
| 219 | static void test_riscv_iommu_bare(void) |
| 220 | { |
| 221 | QRIOMMUTestConfig cfg = { |
| 222 | .trans_mode = QRIOMMU_TM_BARE, |
| 223 | .dma_gpa = QRIOMMU_IOVA, |
| 224 | .dma_len = DMA_LEN, |
| 225 | .expected_result = 0, |
| 226 | }; |
| 227 | |
| 228 | run_riscv_iommu_translation(&cfg); |
| 229 | } |
| 230 | |
| 231 | static void test_riscv_iommu_s_stage_only(void) |
| 232 | { |
| 233 | QRIOMMUTestConfig cfg = { |
| 234 | .trans_mode = QRIOMMU_TM_S_STAGE_ONLY, |
| 235 | .dma_gpa = riscv_iommu_expected_gpa(QRIOMMU_IOVA), |
| 236 | .dma_len = DMA_LEN, |
| 237 | .expected_result = 0, |
| 238 | }; |
| 239 | |
| 240 | run_riscv_iommu_translation(&cfg); |
| 241 | } |
| 242 | |
| 243 | static void test_riscv_iommu_g_stage_only(void) |
| 244 | { |
| 245 | QRIOMMUTestConfig cfg = { |
| 246 | .trans_mode = QRIOMMU_TM_G_STAGE_ONLY, |
| 247 | .dma_gpa = riscv_iommu_expected_gpa(QRIOMMU_IOVA), |
| 248 | .dma_len = DMA_LEN, |
| 249 | .expected_result = 0, |
| 250 | }; |
| 251 | |
| 252 | run_riscv_iommu_translation(&cfg); |
| 253 | } |
| 254 | |
| 255 | static void test_riscv_iommu_nested(void) |
| 256 | { |
| 257 | QRIOMMUTestConfig cfg = { |
| 258 | .trans_mode = QRIOMMU_TM_NESTED, |
| 259 | .dma_gpa = riscv_iommu_expected_gpa(QRIOMMU_IOVA), |
| 260 | .dma_len = DMA_LEN, |
| 261 | .expected_result = 0, |
| 262 | }; |
| 263 | |
| 264 | run_riscv_iommu_translation(&cfg); |
| 265 | } |
| 266 | |
| 267 | int main(int argc, char **argv) |
| 268 | { |
| 269 | g_test_init(&argc, &argv, NULL); |
| 270 | qtest_add_func("/iommu-testdev/translation/bare", |
| 271 | test_riscv_iommu_bare); |
| 272 | qtest_add_func("/iommu-testdev/translation/s-stage-only", |
| 273 | test_riscv_iommu_s_stage_only); |
| 274 | qtest_add_func("/iommu-testdev/translation/g-stage-only", |
| 275 | test_riscv_iommu_g_stage_only); |
| 276 | qtest_add_func("/iommu-testdev/translation/ns-nested", |
| 277 | test_riscv_iommu_nested); |
| 278 | return g_test_run(); |
| 279 | } |