| 1 | /* |
| 2 | * libqos AHCI functions |
| 3 | * |
| 4 | * Copyright (c) 2014 John Snow <jsnow@redhat.com> |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 7 | * of this software and associated documentation files (the "Software"), to deal |
| 8 | * in the Software without restriction, including without limitation the rights |
| 9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 10 | * copies of the Software, and to permit persons to whom the Software is |
| 11 | * furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 22 | * THE SOFTWARE. |
| 23 | */ |
| 24 | |
| 25 | #include "qemu/osdep.h" |
| 26 | |
| 27 | #include "../libqtest.h" |
| 28 | #include "ahci.h" |
| 29 | #include "pci-pc.h" |
| 30 | |
| 31 | #include "qemu/bswap.h" |
| 32 | |
| 33 | #include "hw/pci/pci_ids.h" |
| 34 | #include "hw/pci/pci_regs.h" |
| 35 | |
| 36 | typedef struct AHCICommandProp { |
| 37 | uint8_t cmd; /* Command Code */ |
| 38 | bool data; /* Data transfer command? */ |
| 39 | bool pio; |
| 40 | bool dma; |
| 41 | bool lba28; |
| 42 | bool lba48; |
| 43 | bool read; |
| 44 | bool write; |
| 45 | bool atapi; |
| 46 | bool ncq; |
| 47 | uint64_t size; /* Static transfer size, for commands like IDENTIFY. */ |
| 48 | uint32_t interrupts; /* Expected interrupts for this command. */ |
| 49 | } AHCICommandProp; |
| 50 | |
| 51 | AHCICommandProp ahci_command_properties[] = { |
| 52 | { .cmd = CMD_READ_PIO, .data = true, .pio = true, |
| 53 | .lba28 = true, .read = true }, |
| 54 | { .cmd = CMD_WRITE_PIO, .data = true, .pio = true, |
| 55 | .lba28 = true, .write = true }, |
| 56 | { .cmd = CMD_READ_PIO_EXT, .data = true, .pio = true, |
| 57 | .lba48 = true, .read = true }, |
| 58 | { .cmd = CMD_WRITE_PIO_EXT, .data = true, .pio = true, |
| 59 | .lba48 = true, .write = true }, |
| 60 | { .cmd = CMD_READ_DMA, .data = true, .dma = true, |
| 61 | .lba28 = true, .read = true }, |
| 62 | { .cmd = CMD_WRITE_DMA, .data = true, .dma = true, |
| 63 | .lba28 = true, .write = true }, |
| 64 | { .cmd = CMD_READ_DMA_EXT, .data = true, .dma = true, |
| 65 | .lba48 = true, .read = true }, |
| 66 | { .cmd = CMD_WRITE_DMA_EXT, .data = true, .dma = true, |
| 67 | .lba48 = true, .write = true }, |
| 68 | { .cmd = CMD_IDENTIFY, .data = true, .pio = true, |
| 69 | .size = 512, .read = true }, |
| 70 | { .cmd = READ_FPDMA_QUEUED, .data = true, .dma = true, |
| 71 | .lba48 = true, .read = true, .ncq = true }, |
| 72 | { .cmd = WRITE_FPDMA_QUEUED, .data = true, .dma = true, |
| 73 | .lba48 = true, .write = true, .ncq = true }, |
| 74 | { .cmd = CMD_READ_MAX, .lba28 = true }, |
| 75 | { .cmd = CMD_READ_MAX_EXT, .lba48 = true }, |
| 76 | { .cmd = CMD_FLUSH_CACHE, .data = false }, |
| 77 | { .cmd = CMD_INIT_DP, .data = false }, |
| 78 | { .cmd = CMD_PACKET, .data = true, .size = 16, |
| 79 | .atapi = true, .pio = true }, |
| 80 | { .cmd = CMD_PACKET_ID, .data = true, .pio = true, |
| 81 | .size = 512, .read = true } |
| 82 | }; |
| 83 | |
| 84 | struct AHCICommand { |
| 85 | /* Test Management Data */ |
| 86 | uint8_t name; |
| 87 | uint8_t port; |
| 88 | uint8_t slot; |
| 89 | uint8_t errors; |
| 90 | uint32_t interrupts; |
| 91 | uint64_t xbytes; |
| 92 | uint32_t prd_size; |
| 93 | uint32_t sector_size; |
| 94 | uint64_t buffer; |
| 95 | AHCICommandProp *props; |
| 96 | /* Data to be transferred to the guest */ |
| 97 | AHCICommandHeader header; |
| 98 | RegH2DFIS fis; |
| 99 | unsigned char *atapi_cmd; |
| 100 | }; |
| 101 | |
| 102 | /** |
| 103 | * Allocate space in the guest using information in the AHCIQState object. |
| 104 | */ |
| 105 | uint64_t ahci_alloc(AHCIQState *ahci, size_t bytes) |
| 106 | { |
| 107 | g_assert(ahci); |
| 108 | g_assert(ahci->parent); |
| 109 | return qmalloc(ahci->parent, bytes); |
| 110 | } |
| 111 | |
| 112 | void ahci_free(AHCIQState *ahci, uint64_t addr) |
| 113 | { |
| 114 | g_assert(ahci); |
| 115 | g_assert(ahci->parent); |
| 116 | qfree(ahci->parent, addr); |
| 117 | } |
| 118 | |
| 119 | bool is_atapi(AHCIQState *ahci, uint8_t port) |
| 120 | { |
| 121 | return ahci_px_rreg(ahci, port, AHCI_PX_SIG) == AHCI_SIGNATURE_CDROM; |
| 122 | } |
| 123 | |
| 124 | /** |
| 125 | * Locate, verify, and return a handle to the AHCI device. |
| 126 | */ |
| 127 | QPCIDevice *get_ahci_device(QTestState *qts, uint32_t *fingerprint) |
| 128 | { |
| 129 | QPCIDevice *ahci; |
| 130 | uint32_t ahci_fingerprint; |
| 131 | QPCIBus *pcibus; |
| 132 | |
| 133 | pcibus = qpci_new_pc(qts, NULL); |
| 134 | |
| 135 | /* Find the AHCI PCI device and verify it's the right one. */ |
| 136 | ahci = qpci_device_find(pcibus, QPCI_DEVFN(0x1F, 0x02)); |
| 137 | g_assert(ahci != NULL); |
| 138 | |
| 139 | ahci_fingerprint = qpci_config_readl(ahci, PCI_VENDOR_ID); |
| 140 | |
| 141 | switch (ahci_fingerprint) { |
| 142 | case AHCI_INTEL_ICH9: |
| 143 | break; |
| 144 | default: |
| 145 | /* Unknown device. */ |
| 146 | g_assert_not_reached(); |
| 147 | } |
| 148 | |
| 149 | if (fingerprint) { |
| 150 | *fingerprint = ahci_fingerprint; |
| 151 | } |
| 152 | return ahci; |
| 153 | } |
| 154 | |
| 155 | void free_ahci_device(QPCIDevice *dev) |
| 156 | { |
| 157 | QPCIBus *pcibus = dev ? dev->bus : NULL; |
| 158 | |
| 159 | /* libqos doesn't have a function for this, so free it manually */ |
| 160 | g_free(dev); |
| 161 | qpci_free_pc(pcibus); |
| 162 | } |
| 163 | |
| 164 | /* Free all memory in-use by the AHCI device. */ |
| 165 | void ahci_clean_mem(AHCIQState *ahci) |
| 166 | { |
| 167 | uint8_t port, slot; |
| 168 | |
| 169 | for (port = 0; port < 32; ++port) { |
| 170 | if (ahci->port[port].fb) { |
| 171 | ahci_free(ahci, ahci->port[port].fb); |
| 172 | ahci->port[port].fb = 0; |
| 173 | } |
| 174 | if (ahci->port[port].clb) { |
| 175 | for (slot = 0; slot < 32; slot++) { |
| 176 | ahci_destroy_command(ahci, port, slot); |
| 177 | } |
| 178 | ahci_free(ahci, ahci->port[port].clb); |
| 179 | ahci->port[port].clb = 0; |
| 180 | } |
| 181 | } |
| 182 | } |
| 183 | |
| 184 | /*** Logical Device Initialization ***/ |
| 185 | |
| 186 | /** |
| 187 | * Start the PCI device and sanity-check default operation. |
| 188 | */ |
| 189 | void ahci_pci_enable(AHCIQState *ahci) |
| 190 | { |
| 191 | uint8_t reg; |
| 192 | |
| 193 | start_ahci_device(ahci); |
| 194 | |
| 195 | switch (ahci->fingerprint) { |
| 196 | case AHCI_INTEL_ICH9: |
| 197 | /* ICH9 has a register at PCI 0x92 that |
| 198 | * acts as a master port enabler mask. */ |
| 199 | reg = qpci_config_readb(ahci->dev, 0x92); |
| 200 | reg |= 0x3F; |
| 201 | qpci_config_writeb(ahci->dev, 0x92, reg); |
| 202 | /* 0...0111111b -- bit significant, ports 0-5 enabled. */ |
| 203 | ASSERT_BIT_SET(qpci_config_readb(ahci->dev, 0x92), 0x3F); |
| 204 | break; |
| 205 | } |
| 206 | |
| 207 | } |
| 208 | |
| 209 | /** |
| 210 | * Map BAR5/ABAR, and engage the PCI device. |
| 211 | */ |
| 212 | void start_ahci_device(AHCIQState *ahci) |
| 213 | { |
| 214 | /* Map AHCI's ABAR (BAR5) */ |
| 215 | ahci->hba_bar = qpci_iomap(ahci->dev, 5, &ahci->barsize); |
| 216 | |
| 217 | /* turns on pci.cmd.iose, pci.cmd.mse and pci.cmd.bme */ |
| 218 | qpci_device_enable(ahci->dev); |
| 219 | } |
| 220 | |
| 221 | /** |
| 222 | * Test and initialize the AHCI's HBA memory areas. |
| 223 | * Initialize and start any ports with devices attached. |
| 224 | * Bring the HBA into the idle state. |
| 225 | */ |
| 226 | void ahci_hba_enable(AHCIQState *ahci) |
| 227 | { |
| 228 | /* Bits of interest in this section: |
| 229 | * GHC.AE Global Host Control / AHCI Enable |
| 230 | * PxCMD.ST Port Command: Start |
| 231 | * PxCMD.SUD "Spin Up Device" |
| 232 | * PxCMD.POD "Power On Device" |
| 233 | * PxCMD.FRE "FIS Receive Enable" |
| 234 | * PxCMD.FR "FIS Receive Running" |
| 235 | * PxCMD.CR "Command List Running" |
| 236 | */ |
| 237 | uint32_t reg, ports_impl; |
| 238 | uint16_t i; |
| 239 | uint8_t num_cmd_slots; |
| 240 | |
| 241 | g_assert(ahci != NULL); |
| 242 | |
| 243 | /* Set GHC.AE to 1 */ |
| 244 | ahci_set(ahci, AHCI_GHC, AHCI_GHC_AE); |
| 245 | reg = ahci_rreg(ahci, AHCI_GHC); |
| 246 | ASSERT_BIT_SET(reg, AHCI_GHC_AE); |
| 247 | |
| 248 | /* Cache CAP and CAP2. */ |
| 249 | ahci->cap = ahci_rreg(ahci, AHCI_CAP); |
| 250 | ahci->cap2 = ahci_rreg(ahci, AHCI_CAP2); |
| 251 | |
| 252 | /* Read CAP.NCS, how many command slots do we have? */ |
| 253 | num_cmd_slots = ((ahci->cap & AHCI_CAP_NCS) >> ctzl(AHCI_CAP_NCS)) + 1; |
| 254 | g_test_message("Number of Command Slots: %u", num_cmd_slots); |
| 255 | |
| 256 | /* Determine which ports are implemented. */ |
| 257 | ports_impl = ahci_rreg(ahci, AHCI_PI); |
| 258 | |
| 259 | for (i = 0; ports_impl; ports_impl >>= 1, ++i) { |
| 260 | if (!(ports_impl & 0x01)) { |
| 261 | continue; |
| 262 | } |
| 263 | |
| 264 | g_test_message("Initializing port %u", i); |
| 265 | |
| 266 | reg = ahci_px_rreg(ahci, i, AHCI_PX_CMD); |
| 267 | if (BITCLR(reg, AHCI_PX_CMD_ST | AHCI_PX_CMD_CR | |
| 268 | AHCI_PX_CMD_FRE | AHCI_PX_CMD_FR)) { |
| 269 | g_test_message("port is idle"); |
| 270 | } else { |
| 271 | g_test_message("port needs to be idled"); |
| 272 | ahci_px_clr(ahci, i, AHCI_PX_CMD, |
| 273 | (AHCI_PX_CMD_ST | AHCI_PX_CMD_FRE)); |
| 274 | /* The port has 500ms to disengage. */ |
| 275 | usleep(500000); |
| 276 | reg = ahci_px_rreg(ahci, i, AHCI_PX_CMD); |
| 277 | ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_CR); |
| 278 | ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_FR); |
| 279 | g_test_message("port is now idle"); |
| 280 | /* The spec does allow for possibly needing a PORT RESET |
| 281 | * or HBA reset if we fail to idle the port. */ |
| 282 | } |
| 283 | |
| 284 | /* Allocate Memory for the Command List Buffer & FIS Buffer */ |
| 285 | /* PxCLB space ... 0x20 per command, as in 4.2.2 p 36 */ |
| 286 | ahci->port[i].clb = ahci_alloc(ahci, num_cmd_slots * 0x20); |
| 287 | qtest_memset(ahci->parent->qts, ahci->port[i].clb, 0x00, |
| 288 | num_cmd_slots * 0x20); |
| 289 | g_test_message("CLB: 0x%08" PRIx64, ahci->port[i].clb); |
| 290 | ahci_px_wreg(ahci, i, AHCI_PX_CLB, ahci->port[i].clb); |
| 291 | g_assert_cmphex(ahci->port[i].clb, ==, |
| 292 | ahci_px_rreg(ahci, i, AHCI_PX_CLB)); |
| 293 | |
| 294 | /* PxFB space ... 0x100, as in 4.2.1 p 35 */ |
| 295 | ahci->port[i].fb = ahci_alloc(ahci, 0x100); |
| 296 | qtest_memset(ahci->parent->qts, ahci->port[i].fb, 0x00, 0x100); |
| 297 | g_test_message("FB: 0x%08" PRIx64, ahci->port[i].fb); |
| 298 | ahci_px_wreg(ahci, i, AHCI_PX_FB, ahci->port[i].fb); |
| 299 | g_assert_cmphex(ahci->port[i].fb, ==, |
| 300 | ahci_px_rreg(ahci, i, AHCI_PX_FB)); |
| 301 | |
| 302 | /* Clear PxSERR, PxIS, then IS.IPS[x] by writing '1's. */ |
| 303 | ahci_px_wreg(ahci, i, AHCI_PX_SERR, 0xFFFFFFFF); |
| 304 | ahci_px_wreg(ahci, i, AHCI_PX_IS, 0xFFFFFFFF); |
| 305 | ahci_wreg(ahci, AHCI_IS, (1 << i)); |
| 306 | |
| 307 | /* Verify Interrupts Cleared */ |
| 308 | reg = ahci_px_rreg(ahci, i, AHCI_PX_SERR); |
| 309 | g_assert_cmphex(reg, ==, 0); |
| 310 | |
| 311 | reg = ahci_px_rreg(ahci, i, AHCI_PX_IS); |
| 312 | g_assert_cmphex(reg, ==, 0); |
| 313 | |
| 314 | reg = ahci_rreg(ahci, AHCI_IS); |
| 315 | ASSERT_BIT_CLEAR(reg, (1 << i)); |
| 316 | |
| 317 | /* Enable All Interrupts: */ |
| 318 | ahci_px_wreg(ahci, i, AHCI_PX_IE, 0xFFFFFFFF); |
| 319 | reg = ahci_px_rreg(ahci, i, AHCI_PX_IE); |
| 320 | g_assert_cmphex(reg, ==, ~((uint32_t)AHCI_PX_IE_RESERVED)); |
| 321 | |
| 322 | /* Enable the FIS Receive Engine. */ |
| 323 | ahci_px_set(ahci, i, AHCI_PX_CMD, AHCI_PX_CMD_FRE); |
| 324 | reg = ahci_px_rreg(ahci, i, AHCI_PX_CMD); |
| 325 | ASSERT_BIT_SET(reg, AHCI_PX_CMD_FR); |
| 326 | |
| 327 | /* AHCI 1.3 spec: if !STS.BSY, !STS.DRQ and PxSSTS.DET indicates |
| 328 | * physical presence, a device is present and may be started. However, |
| 329 | * PxSERR.DIAG.X /may/ need to be cleared a priori. */ |
| 330 | reg = ahci_px_rreg(ahci, i, AHCI_PX_SERR); |
| 331 | if (BITSET(reg, AHCI_PX_SERR_DIAG_X)) { |
| 332 | ahci_px_set(ahci, i, AHCI_PX_SERR, AHCI_PX_SERR_DIAG_X); |
| 333 | } |
| 334 | |
| 335 | reg = ahci_px_rreg(ahci, i, AHCI_PX_TFD); |
| 336 | if (BITCLR(reg, AHCI_PX_TFD_STS_BSY | AHCI_PX_TFD_STS_DRQ)) { |
| 337 | reg = ahci_px_rreg(ahci, i, AHCI_PX_SSTS); |
| 338 | if ((reg & AHCI_PX_SSTS_DET) == SSTS_DET_ESTABLISHED) { |
| 339 | /* Device Found: set PxCMD.ST := 1 */ |
| 340 | ahci_px_set(ahci, i, AHCI_PX_CMD, AHCI_PX_CMD_ST); |
| 341 | ASSERT_BIT_SET(ahci_px_rreg(ahci, i, AHCI_PX_CMD), |
| 342 | AHCI_PX_CMD_CR); |
| 343 | g_test_message("Started Device %u", i); |
| 344 | } else if ((reg & AHCI_PX_SSTS_DET)) { |
| 345 | /* Device present, but in some unknown state. */ |
| 346 | g_assert_not_reached(); |
| 347 | } |
| 348 | } |
| 349 | } |
| 350 | |
| 351 | /* Enable GHC.IE */ |
| 352 | ahci_set(ahci, AHCI_GHC, AHCI_GHC_IE); |
| 353 | reg = ahci_rreg(ahci, AHCI_GHC); |
| 354 | ASSERT_BIT_SET(reg, AHCI_GHC_IE); |
| 355 | |
| 356 | ahci->enabled = true; |
| 357 | /* TODO: The device should now be idling and waiting for commands. |
| 358 | * In the future, a small test-case to inspect the Register D2H FIS |
| 359 | * and clear the initial interrupts might be good. */ |
| 360 | } |
| 361 | |
| 362 | /** |
| 363 | * Pick the first implemented and running port |
| 364 | */ |
| 365 | unsigned ahci_port_select(AHCIQState *ahci) |
| 366 | { |
| 367 | uint32_t ports, reg; |
| 368 | unsigned i; |
| 369 | |
| 370 | ports = ahci_rreg(ahci, AHCI_PI); |
| 371 | for (i = 0; i < 32; ports >>= 1, ++i) { |
| 372 | if (ports == 0) { |
| 373 | i = 32; |
| 374 | } |
| 375 | |
| 376 | if (!(ports & 0x01)) { |
| 377 | continue; |
| 378 | } |
| 379 | |
| 380 | reg = ahci_px_rreg(ahci, i, AHCI_PX_CMD); |
| 381 | if (BITSET(reg, AHCI_PX_CMD_ST)) { |
| 382 | break; |
| 383 | } |
| 384 | } |
| 385 | g_assert(i < 32); |
| 386 | return i; |
| 387 | } |
| 388 | |
| 389 | /** |
| 390 | * Clear a port's interrupts and status information prior to a test. |
| 391 | */ |
| 392 | void ahci_port_clear(AHCIQState *ahci, uint8_t port) |
| 393 | { |
| 394 | uint32_t reg; |
| 395 | |
| 396 | /* Clear out this port's interrupts (ignore the init register d2h fis) */ |
| 397 | reg = ahci_px_rreg(ahci, port, AHCI_PX_IS); |
| 398 | ahci_px_wreg(ahci, port, AHCI_PX_IS, reg); |
| 399 | g_assert_cmphex(ahci_px_rreg(ahci, port, AHCI_PX_IS), ==, 0); |
| 400 | |
| 401 | /* Wipe the FIS-Receive Buffer */ |
| 402 | qtest_memset(ahci->parent->qts, ahci->port[port].fb, 0x00, 0x100); |
| 403 | } |
| 404 | |
| 405 | /** |
| 406 | * Check a port for errors. |
| 407 | */ |
| 408 | void ahci_port_check_error(AHCIQState *ahci, AHCICommand *cmd) |
| 409 | { |
| 410 | uint8_t port = cmd->port; |
| 411 | uint32_t reg; |
| 412 | |
| 413 | /* If expecting TF error, ensure that TFES is set. */ |
| 414 | if (cmd->errors) { |
| 415 | reg = ahci_px_rreg(ahci, port, AHCI_PX_IS); |
| 416 | ASSERT_BIT_SET(reg, AHCI_PX_IS_TFES); |
| 417 | } else { |
| 418 | /* The upper 9 bits of the IS register all indicate errors. */ |
| 419 | reg = ahci_px_rreg(ahci, port, AHCI_PX_IS); |
| 420 | reg &= ~cmd->interrupts; |
| 421 | reg >>= 23; |
| 422 | g_assert_cmphex(reg, ==, 0); |
| 423 | } |
| 424 | |
| 425 | /* The Sata Error Register should be empty, even when expecting TF error. */ |
| 426 | reg = ahci_px_rreg(ahci, port, AHCI_PX_SERR); |
| 427 | g_assert_cmphex(reg, ==, 0); |
| 428 | |
| 429 | /* If expecting TF error, and TFES was set, perform error recovery |
| 430 | * (see AHCI 1.3 section 6.2.2.1) such that we can send new commands. */ |
| 431 | if (cmd->errors) { |
| 432 | /* This will clear PxCI. */ |
| 433 | ahci_px_clr(ahci, port, AHCI_PX_CMD, AHCI_PX_CMD_ST); |
| 434 | |
| 435 | /* The port has 500ms to disengage. */ |
| 436 | usleep(500000); |
| 437 | reg = ahci_px_rreg(ahci, port, AHCI_PX_CMD); |
| 438 | ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_CR); |
| 439 | |
| 440 | /* Clear PxIS. */ |
| 441 | reg = ahci_px_rreg(ahci, port, AHCI_PX_IS); |
| 442 | ahci_px_wreg(ahci, port, AHCI_PX_IS, reg); |
| 443 | |
| 444 | /* Check if we need to perform a COMRESET. |
| 445 | * Not implemented right now, as there is no reason why our QEMU model |
| 446 | * should need a COMRESET when expecting TF error. */ |
| 447 | reg = ahci_px_rreg(ahci, port, AHCI_PX_TFD); |
| 448 | ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_STS_BSY | AHCI_PX_TFD_STS_DRQ); |
| 449 | |
| 450 | /* Enable issuing new commands. */ |
| 451 | ahci_px_set(ahci, port, AHCI_PX_CMD, AHCI_PX_CMD_ST); |
| 452 | } |
| 453 | |
| 454 | /* The TFD also has two error sections. */ |
| 455 | reg = ahci_px_rreg(ahci, port, AHCI_PX_TFD); |
| 456 | if (!cmd->errors) { |
| 457 | ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_STS_ERR); |
| 458 | } else { |
| 459 | ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_ERR); |
| 460 | } |
| 461 | ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_ERR & (~cmd->errors << 8)); |
| 462 | ASSERT_BIT_SET(reg, AHCI_PX_TFD_ERR & (cmd->errors << 8)); |
| 463 | } |
| 464 | |
| 465 | void ahci_port_check_interrupts(AHCIQState *ahci, AHCICommand *cmd) |
| 466 | { |
| 467 | uint8_t port = cmd->port; |
| 468 | uint32_t reg; |
| 469 | |
| 470 | /* If we expect errors, error handling in ahci_port_check_error() will |
| 471 | * already have cleared PxIS, so in that case this function cannot verify |
| 472 | * and clear expected interrupts. */ |
| 473 | if (cmd->errors) { |
| 474 | return; |
| 475 | } |
| 476 | |
| 477 | /* Check for expected interrupts */ |
| 478 | reg = ahci_px_rreg(ahci, port, AHCI_PX_IS); |
| 479 | ASSERT_BIT_SET(reg, cmd->interrupts); |
| 480 | |
| 481 | /* Clear expected interrupts and assert all interrupts now cleared. */ |
| 482 | ahci_px_wreg(ahci, port, AHCI_PX_IS, cmd->interrupts); |
| 483 | g_assert_cmphex(ahci_px_rreg(ahci, port, AHCI_PX_IS), ==, 0); |
| 484 | } |
| 485 | |
| 486 | void ahci_port_check_nonbusy(AHCIQState *ahci, AHCICommand *cmd) |
| 487 | { |
| 488 | uint8_t slot = cmd->slot; |
| 489 | uint8_t port = cmd->port; |
| 490 | uint32_t reg; |
| 491 | |
| 492 | /* For NCQ command with error PxSACT bit should still be set. |
| 493 | * For NCQ command without error, PxSACT bit should be cleared. |
| 494 | * For non-NCQ command, PxSACT bit should always be cleared. */ |
| 495 | reg = ahci_px_rreg(ahci, port, AHCI_PX_SACT); |
| 496 | if (cmd->props->ncq && cmd->errors) { |
| 497 | ASSERT_BIT_SET(reg, (1 << slot)); |
| 498 | } else { |
| 499 | ASSERT_BIT_CLEAR(reg, (1 << slot)); |
| 500 | } |
| 501 | |
| 502 | /* For non-NCQ command with error, PxCI bit should still be set. |
| 503 | * For non-NCQ command without error, PxCI bit should be cleared. |
| 504 | * For NCQ command without error, PxCI bit should be cleared. |
| 505 | * For NCQ command with error, PxCI bit may or may not be cleared. */ |
| 506 | reg = ahci_px_rreg(ahci, port, AHCI_PX_CI); |
| 507 | if (!cmd->props->ncq && cmd->errors) { |
| 508 | ASSERT_BIT_SET(reg, (1 << slot)); |
| 509 | } else if (!cmd->errors) { |
| 510 | ASSERT_BIT_CLEAR(reg, (1 << slot)); |
| 511 | } |
| 512 | |
| 513 | /* And assert that we are generally not busy. */ |
| 514 | reg = ahci_px_rreg(ahci, port, AHCI_PX_TFD); |
| 515 | ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_STS_BSY); |
| 516 | ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_STS_DRQ); |
| 517 | } |
| 518 | |
| 519 | void ahci_port_check_d2h_sanity(AHCIQState *ahci, uint8_t port, uint8_t slot) |
| 520 | { |
| 521 | RegD2HFIS *d2h = g_malloc0(0x20); |
| 522 | uint32_t reg; |
| 523 | |
| 524 | qtest_memread(ahci->parent->qts, ahci->port[port].fb + 0x40, d2h, 0x20); |
| 525 | g_assert_cmphex(d2h->fis_type, ==, 0x34); |
| 526 | |
| 527 | reg = ahci_px_rreg(ahci, port, AHCI_PX_TFD); |
| 528 | g_assert_cmphex((reg & AHCI_PX_TFD_ERR) >> 8, ==, d2h->error); |
| 529 | g_assert_cmphex((reg & AHCI_PX_TFD_STS), ==, d2h->status); |
| 530 | |
| 531 | g_free(d2h); |
| 532 | } |
| 533 | |
| 534 | void ahci_port_check_pio_sanity(AHCIQState *ahci, AHCICommand *cmd) |
| 535 | { |
| 536 | PIOSetupFIS *pio = g_malloc0(0x20); |
| 537 | uint8_t port = cmd->port; |
| 538 | |
| 539 | /* We cannot check the Status or E_Status registers, because |
| 540 | * the status may have again changed between the PIO Setup FIS |
| 541 | * and the conclusion of the command with the D2H Register FIS. */ |
| 542 | qtest_memread(ahci->parent->qts, ahci->port[port].fb + 0x20, pio, 0x20); |
| 543 | g_assert_cmphex(pio->fis_type, ==, 0x5f); |
| 544 | |
| 545 | /* Data transferred by PIO will either be: |
| 546 | * (1) 12 or 16 bytes for an ATAPI command packet (QEMU always uses 12), or |
| 547 | * (2) Actual data from the drive. |
| 548 | * If we do both, (2) winds up erasing any evidence of (1). |
| 549 | */ |
| 550 | if (cmd->props->atapi && (cmd->xbytes == 0 || cmd->props->dma)) { |
| 551 | g_assert(le16_to_cpu(pio->tx_count) == 12 || |
| 552 | le16_to_cpu(pio->tx_count) == 16); |
| 553 | } else { |
| 554 | /* The AHCI test suite here does not test any PIO command that specifies |
| 555 | * a DRQ block larger than one sector (like 0xC4), so this should always |
| 556 | * be one sector or less. */ |
| 557 | size_t pio_len = ((cmd->xbytes % cmd->sector_size) ? |
| 558 | (cmd->xbytes % cmd->sector_size) : cmd->sector_size); |
| 559 | g_assert_cmphex(le16_to_cpu(pio->tx_count), ==, pio_len); |
| 560 | } |
| 561 | g_free(pio); |
| 562 | } |
| 563 | |
| 564 | void ahci_port_check_cmd_sanity(AHCIQState *ahci, AHCICommand *cmd) |
| 565 | { |
| 566 | AHCICommandHeader cmdh; |
| 567 | |
| 568 | ahci_get_command_header(ahci, cmd->port, cmd->slot, &cmdh); |
| 569 | /* Physical Region Descriptor Byte Count is not required to work for NCQ. */ |
| 570 | if (!cmd->props->ncq) { |
| 571 | g_assert_cmphex(cmd->xbytes, ==, cmdh.prdbc); |
| 572 | } |
| 573 | } |
| 574 | |
| 575 | /* Get the command in #slot of port #port. */ |
| 576 | void ahci_get_command_header(AHCIQState *ahci, uint8_t port, |
| 577 | uint8_t slot, AHCICommandHeader *cmd) |
| 578 | { |
| 579 | uint64_t ba = ahci->port[port].clb; |
| 580 | ba += slot * sizeof(AHCICommandHeader); |
| 581 | qtest_memread(ahci->parent->qts, ba, cmd, sizeof(AHCICommandHeader)); |
| 582 | |
| 583 | cmd->flags = le16_to_cpu(cmd->flags); |
| 584 | cmd->prdtl = le16_to_cpu(cmd->prdtl); |
| 585 | cmd->prdbc = le32_to_cpu(cmd->prdbc); |
| 586 | cmd->ctba = le64_to_cpu(cmd->ctba); |
| 587 | } |
| 588 | |
| 589 | /* Set the command in #slot of port #port. */ |
| 590 | void ahci_set_command_header(AHCIQState *ahci, uint8_t port, |
| 591 | uint8_t slot, AHCICommandHeader *cmd) |
| 592 | { |
| 593 | AHCICommandHeader tmp = { .flags = 0 }; |
| 594 | uint64_t ba = ahci->port[port].clb; |
| 595 | ba += slot * sizeof(AHCICommandHeader); |
| 596 | |
| 597 | tmp.flags = cpu_to_le16(cmd->flags); |
| 598 | tmp.prdtl = cpu_to_le16(cmd->prdtl); |
| 599 | tmp.prdbc = cpu_to_le32(cmd->prdbc); |
| 600 | tmp.ctba = cpu_to_le64(cmd->ctba); |
| 601 | |
| 602 | qtest_memwrite(ahci->parent->qts, ba, &tmp, sizeof(AHCICommandHeader)); |
| 603 | } |
| 604 | |
| 605 | void ahci_destroy_command(AHCIQState *ahci, uint8_t port, uint8_t slot) |
| 606 | { |
| 607 | AHCICommandHeader cmd; |
| 608 | |
| 609 | /* Obtain the Nth Command Header */ |
| 610 | ahci_get_command_header(ahci, port, slot, &cmd); |
| 611 | if (cmd.ctba == 0) { |
| 612 | /* No address in it, so just return -- it's empty. */ |
| 613 | goto tidy; |
| 614 | } |
| 615 | |
| 616 | /* Free the Table */ |
| 617 | ahci_free(ahci, cmd.ctba); |
| 618 | |
| 619 | tidy: |
| 620 | /* NULL the header. */ |
| 621 | memset(&cmd, 0x00, sizeof(cmd)); |
| 622 | ahci_set_command_header(ahci, port, slot, &cmd); |
| 623 | ahci->port[port].ctba[slot] = 0; |
| 624 | ahci->port[port].prdtl[slot] = 0; |
| 625 | } |
| 626 | |
| 627 | void ahci_write_fis(AHCIQState *ahci, AHCICommand *cmd) |
| 628 | { |
| 629 | RegH2DFIS tmp = cmd->fis; |
| 630 | uint64_t addr = cmd->header.ctba; |
| 631 | |
| 632 | /* NCQ commands use exclusively 8 bit fields and needs no adjustment. |
| 633 | * Only the count field needs to be adjusted for non-NCQ commands. |
| 634 | * The auxiliary FIS fields are defined per-command and are not currently |
| 635 | * implemented in ahci.o, but may or may not need to be flipped. */ |
| 636 | if (!cmd->props->ncq) { |
| 637 | tmp.count = cpu_to_le16(tmp.count); |
| 638 | } |
| 639 | |
| 640 | qtest_memwrite(ahci->parent->qts, addr, &tmp, sizeof(tmp)); |
| 641 | } |
| 642 | |
| 643 | unsigned ahci_pick_cmd(AHCIQState *ahci, uint8_t port) |
| 644 | { |
| 645 | unsigned i; |
| 646 | unsigned j; |
| 647 | uint32_t reg; |
| 648 | |
| 649 | reg = ahci_px_rreg(ahci, port, AHCI_PX_CI); |
| 650 | |
| 651 | /* Pick the least recently used command slot that's available */ |
| 652 | for (i = 0; i < 32; ++i) { |
| 653 | j = ((ahci->port[port].next + i) % 32); |
| 654 | if (reg & (1 << j)) { |
| 655 | continue; |
| 656 | } |
| 657 | ahci_destroy_command(ahci, port, j); |
| 658 | ahci->port[port].next = (j + 1) % 32; |
| 659 | return j; |
| 660 | } |
| 661 | |
| 662 | g_test_message("All command slots were busy."); |
| 663 | g_assert_not_reached(); |
| 664 | } |
| 665 | |
| 666 | static unsigned size_to_prdtl(unsigned bytes, unsigned bytes_per_prd) |
| 667 | { |
| 668 | /* Each PRD can describe up to 4MiB */ |
| 669 | g_assert_cmphex(bytes_per_prd, <=, 4096 * 1024); |
| 670 | g_assert_cmphex(bytes_per_prd & 0x01, ==, 0x00); |
| 671 | return (bytes + bytes_per_prd - 1) / bytes_per_prd; |
| 672 | } |
| 673 | |
| 674 | const AHCIOpts default_opts = { .size = 0 }; |
| 675 | |
| 676 | /** |
| 677 | * ahci_exec: execute a given command on a specific |
| 678 | * AHCI port. |
| 679 | * |
| 680 | * @ahci: The device to send the command to |
| 681 | * @port: The port number of the SATA device we wish |
| 682 | * to have execute this command |
| 683 | * @op: The S/ATA command to execute, or if opts.atapi |
| 684 | * is true, the SCSI command code. |
| 685 | * @opts: Optional arguments to modify execution behavior. |
| 686 | */ |
| 687 | void ahci_exec(AHCIQState *ahci, uint8_t port, |
| 688 | uint8_t op, const AHCIOpts *opts_in) |
| 689 | { |
| 690 | AHCICommand *cmd; |
| 691 | int rc; |
| 692 | AHCIOpts *opts; |
| 693 | uint64_t buffer_in; |
| 694 | |
| 695 | opts = g_memdup2((opts_in == NULL ? &default_opts : opts_in), |
| 696 | sizeof(AHCIOpts)); |
| 697 | |
| 698 | buffer_in = opts->buffer; |
| 699 | |
| 700 | /* No guest buffer provided, create one. */ |
| 701 | if (opts->size && !opts->buffer) { |
| 702 | opts->buffer = ahci_alloc(ahci, opts->size); |
| 703 | g_assert(opts->buffer); |
| 704 | qtest_memset(ahci->parent->qts, opts->buffer, 0x00, opts->size); |
| 705 | } |
| 706 | |
| 707 | /* Command creation */ |
| 708 | if (opts->atapi) { |
| 709 | uint16_t bcl = opts->set_bcl ? opts->bcl : ATAPI_SECTOR_SIZE; |
| 710 | cmd = ahci_atapi_command_create(op, bcl, opts->atapi_dma); |
| 711 | if (opts->atapi_raw) { |
| 712 | /* request full 2352-byte raw sectors; sector_size must match */ |
| 713 | cmd->atapi_cmd[9] = 0xf8; |
| 714 | cmd->sector_size = ATAPI_RAW_SECTOR_SIZE; |
| 715 | } |
| 716 | } else { |
| 717 | cmd = ahci_command_create(op); |
| 718 | } |
| 719 | ahci_command_adjust(cmd, opts->lba, opts->buffer, |
| 720 | opts->size, opts->prd_size); |
| 721 | |
| 722 | if (opts->pre_cb) { |
| 723 | rc = opts->pre_cb(ahci, cmd, opts); |
| 724 | g_assert_cmpint(rc, ==, 0); |
| 725 | } |
| 726 | |
| 727 | /* Write command to memory and issue it */ |
| 728 | ahci_command_commit(ahci, cmd, port); |
| 729 | ahci_command_issue_async(ahci, cmd); |
| 730 | if (opts->error) { |
| 731 | qtest_qmp_eventwait(ahci->parent->qts, "STOP"); |
| 732 | } |
| 733 | if (opts->mid_cb) { |
| 734 | rc = opts->mid_cb(ahci, cmd, opts); |
| 735 | g_assert_cmpint(rc, ==, 0); |
| 736 | } |
| 737 | if (opts->error) { |
| 738 | qtest_qmp_send(ahci->parent->qts, "{'execute':'cont' }"); |
| 739 | qtest_qmp_eventwait(ahci->parent->qts, "RESUME"); |
| 740 | } |
| 741 | |
| 742 | /* Wait for command to complete and verify sanity */ |
| 743 | ahci_command_wait(ahci, cmd); |
| 744 | ahci_command_verify(ahci, cmd); |
| 745 | if (opts->post_cb) { |
| 746 | rc = opts->post_cb(ahci, cmd, opts); |
| 747 | g_assert_cmpint(rc, ==, 0); |
| 748 | } |
| 749 | ahci_command_free(cmd); |
| 750 | if (opts->buffer != buffer_in) { |
| 751 | ahci_free(ahci, opts->buffer); |
| 752 | } |
| 753 | g_free(opts); |
| 754 | } |
| 755 | |
| 756 | /* Issue a command, expecting it to fail and STOP the VM */ |
| 757 | AHCICommand *ahci_guest_io_halt(AHCIQState *ahci, uint8_t port, |
| 758 | uint8_t ide_cmd, uint64_t buffer, |
| 759 | size_t bufsize, uint64_t sector) |
| 760 | { |
| 761 | AHCICommand *cmd; |
| 762 | |
| 763 | cmd = ahci_command_create(ide_cmd); |
| 764 | ahci_command_adjust(cmd, sector, buffer, bufsize, 0); |
| 765 | ahci_command_commit(ahci, cmd, port); |
| 766 | ahci_command_issue_async(ahci, cmd); |
| 767 | qtest_qmp_eventwait(ahci->parent->qts, "STOP"); |
| 768 | |
| 769 | return cmd; |
| 770 | } |
| 771 | |
| 772 | /* Resume a previously failed command and verify/finalize */ |
| 773 | void ahci_guest_io_resume(AHCIQState *ahci, AHCICommand *cmd) |
| 774 | { |
| 775 | /* Complete the command */ |
| 776 | qtest_qmp_send(ahci->parent->qts, "{'execute':'cont' }"); |
| 777 | qtest_qmp_eventwait(ahci->parent->qts, "RESUME"); |
| 778 | ahci_command_wait(ahci, cmd); |
| 779 | ahci_command_verify(ahci, cmd); |
| 780 | ahci_command_free(cmd); |
| 781 | } |
| 782 | |
| 783 | /* Given a guest buffer address, perform an IO operation */ |
| 784 | void ahci_guest_io(AHCIQState *ahci, uint8_t port, uint8_t ide_cmd, |
| 785 | uint64_t buffer, size_t bufsize, uint64_t sector) |
| 786 | { |
| 787 | AHCICommand *cmd; |
| 788 | cmd = ahci_command_create(ide_cmd); |
| 789 | ahci_command_set_buffer(cmd, buffer); |
| 790 | ahci_command_set_size(cmd, bufsize); |
| 791 | if (sector) { |
| 792 | ahci_command_set_offset(cmd, sector); |
| 793 | } |
| 794 | ahci_command_commit(ahci, cmd, port); |
| 795 | ahci_command_issue(ahci, cmd); |
| 796 | ahci_command_verify(ahci, cmd); |
| 797 | ahci_command_free(cmd); |
| 798 | } |
| 799 | |
| 800 | static AHCICommandProp *ahci_command_find(uint8_t command_name) |
| 801 | { |
| 802 | int i; |
| 803 | |
| 804 | for (i = 0; i < ARRAY_SIZE(ahci_command_properties); i++) { |
| 805 | if (ahci_command_properties[i].cmd == command_name) { |
| 806 | return &ahci_command_properties[i]; |
| 807 | } |
| 808 | } |
| 809 | |
| 810 | return NULL; |
| 811 | } |
| 812 | |
| 813 | /* Given a HOST buffer, create a buffer address and perform an IO operation. */ |
| 814 | void ahci_io(AHCIQState *ahci, uint8_t port, uint8_t ide_cmd, |
| 815 | void *buffer, size_t bufsize, uint64_t sector) |
| 816 | { |
| 817 | uint64_t ptr; |
| 818 | AHCICommandProp *props; |
| 819 | |
| 820 | props = ahci_command_find(ide_cmd); |
| 821 | g_assert(props); |
| 822 | ptr = ahci_alloc(ahci, bufsize); |
| 823 | g_assert(!bufsize || ptr); |
| 824 | qtest_memset(ahci->parent->qts, ptr, 0x00, bufsize); |
| 825 | |
| 826 | if (bufsize && props->write) { |
| 827 | qtest_bufwrite(ahci->parent->qts, ptr, buffer, bufsize); |
| 828 | } |
| 829 | |
| 830 | ahci_guest_io(ahci, port, ide_cmd, ptr, bufsize, sector); |
| 831 | |
| 832 | if (bufsize && props->read) { |
| 833 | qtest_bufread(ahci->parent->qts, ptr, buffer, bufsize); |
| 834 | } |
| 835 | |
| 836 | ahci_free(ahci, ptr); |
| 837 | } |
| 838 | |
| 839 | /** |
| 840 | * Initializes a basic command header in memory. |
| 841 | * We assume that this is for an ATA command using RegH2DFIS. |
| 842 | */ |
| 843 | static void command_header_init(AHCICommand *cmd) |
| 844 | { |
| 845 | AHCICommandHeader *hdr = &cmd->header; |
| 846 | AHCICommandProp *props = cmd->props; |
| 847 | |
| 848 | hdr->flags = 5; /* RegH2DFIS is 5 DW long. Must be < 32 */ |
| 849 | hdr->flags |= CMDH_CLR_BSY; /* Clear the BSY bit when done */ |
| 850 | if (props->write) { |
| 851 | hdr->flags |= CMDH_WRITE; |
| 852 | } |
| 853 | if (props->atapi) { |
| 854 | hdr->flags |= CMDH_ATAPI; |
| 855 | } |
| 856 | /* Other flags: PREFETCH, RESET, and BIST */ |
| 857 | hdr->prdtl = size_to_prdtl(cmd->xbytes, cmd->prd_size); |
| 858 | hdr->prdbc = 0; |
| 859 | hdr->ctba = 0; |
| 860 | } |
| 861 | |
| 862 | static void command_table_init(AHCICommand *cmd) |
| 863 | { |
| 864 | RegH2DFIS *fis = &(cmd->fis); |
| 865 | uint16_t sect_count = (cmd->xbytes / cmd->sector_size); |
| 866 | |
| 867 | fis->fis_type = REG_H2D_FIS; |
| 868 | fis->flags = REG_H2D_FIS_CMD; /* "Command" bit */ |
| 869 | fis->command = cmd->name; |
| 870 | |
| 871 | if (cmd->props->ncq) { |
| 872 | NCQFIS *ncqfis = (NCQFIS *)fis; |
| 873 | /* NCQ is weird and re-uses FIS frames for unrelated data. |
| 874 | * See SATA 3.2, 13.6.4.1 READ FPDMA QUEUED for an example. */ |
| 875 | ncqfis->sector_low = sect_count & 0xFF; |
| 876 | ncqfis->sector_hi = (sect_count >> 8) & 0xFF; |
| 877 | ncqfis->device = NCQ_DEVICE_MAGIC; |
| 878 | /* Force Unit Access is bit 7 in the device register */ |
| 879 | ncqfis->tag = 0; /* bits 3-7 are the NCQ tag */ |
| 880 | ncqfis->prio = 0; /* bits 6,7 are a prio tag */ |
| 881 | /* RARC bit is bit 0 of TAG field */ |
| 882 | } else { |
| 883 | fis->feature_low = 0x00; |
| 884 | fis->feature_high = 0x00; |
| 885 | if (cmd->props->lba28 || cmd->props->lba48) { |
| 886 | fis->device = ATA_DEVICE_LBA; |
| 887 | } |
| 888 | fis->count = (cmd->xbytes / cmd->sector_size); |
| 889 | } |
| 890 | fis->icc = 0x00; |
| 891 | fis->control = 0x00; |
| 892 | memset(fis->aux, 0x00, ARRAY_SIZE(fis->aux)); |
| 893 | } |
| 894 | |
| 895 | void ahci_command_enable_atapi_dma(AHCICommand *cmd) |
| 896 | { |
| 897 | RegH2DFIS *fis = &(cmd->fis); |
| 898 | g_assert(cmd->props->atapi); |
| 899 | fis->feature_low |= 0x01; |
| 900 | /* PIO is still used to transfer the ATAPI command */ |
| 901 | g_assert(cmd->props->pio); |
| 902 | cmd->props->dma = true; |
| 903 | /* BUG: We expect the DMA Setup interrupt for DMA commands */ |
| 904 | /* cmd->interrupts |= AHCI_PX_IS_DSS; */ |
| 905 | } |
| 906 | |
| 907 | AHCICommand *ahci_command_create(uint8_t command_name) |
| 908 | { |
| 909 | AHCICommandProp *props = ahci_command_find(command_name); |
| 910 | AHCICommand *cmd; |
| 911 | |
| 912 | g_assert(props); |
| 913 | cmd = g_new0(AHCICommand, 1); |
| 914 | g_assert(!(props->dma && props->pio) || props->atapi); |
| 915 | g_assert(!(props->lba28 && props->lba48)); |
| 916 | g_assert(!(props->read && props->write)); |
| 917 | g_assert(!props->size || props->data); |
| 918 | g_assert(!props->ncq || props->lba48); |
| 919 | |
| 920 | /* Defaults and book-keeping */ |
| 921 | cmd->props = g_memdup2(props, sizeof(AHCICommandProp)); |
| 922 | cmd->name = command_name; |
| 923 | cmd->xbytes = props->size; |
| 924 | cmd->prd_size = 4096; |
| 925 | cmd->buffer = 0xabad1dea; |
| 926 | cmd->sector_size = props->atapi ? ATAPI_SECTOR_SIZE : AHCI_SECTOR_SIZE; |
| 927 | |
| 928 | if (!cmd->props->ncq) { |
| 929 | cmd->interrupts = AHCI_PX_IS_DHRS; |
| 930 | } |
| 931 | /* BUG: We expect the DPS interrupt for data commands */ |
| 932 | /* cmd->interrupts |= props->data ? AHCI_PX_IS_DPS : 0; */ |
| 933 | /* BUG: We expect the DMA Setup interrupt for DMA commands */ |
| 934 | /* cmd->interrupts |= props->dma ? AHCI_PX_IS_DSS : 0; */ |
| 935 | cmd->interrupts |= props->ncq ? AHCI_PX_IS_SDBS : 0; |
| 936 | |
| 937 | command_header_init(cmd); |
| 938 | command_table_init(cmd); |
| 939 | |
| 940 | return cmd; |
| 941 | } |
| 942 | |
| 943 | AHCICommand *ahci_atapi_command_create(uint8_t scsi_cmd, uint16_t bcl, bool dma) |
| 944 | { |
| 945 | AHCICommand *cmd = ahci_command_create(CMD_PACKET); |
| 946 | cmd->atapi_cmd = g_malloc0(16); |
| 947 | cmd->atapi_cmd[0] = scsi_cmd; |
| 948 | stw_le_p(&cmd->fis.lba_lo[1], bcl); |
| 949 | if (dma) { |
| 950 | ahci_command_enable_atapi_dma(cmd); |
| 951 | } else { |
| 952 | cmd->interrupts |= bcl ? AHCI_PX_IS_PSS : 0; |
| 953 | } |
| 954 | return cmd; |
| 955 | } |
| 956 | |
| 957 | void ahci_atapi_test_ready(AHCIQState *ahci, uint8_t port, |
| 958 | bool ready, uint8_t expected_sense) |
| 959 | { |
| 960 | AHCICommand *cmd = ahci_atapi_command_create(CMD_ATAPI_TEST_UNIT_READY, 0, false); |
| 961 | ahci_command_set_size(cmd, 0); |
| 962 | if (!ready) { |
| 963 | cmd->interrupts |= AHCI_PX_IS_TFES; |
| 964 | cmd->errors |= expected_sense << 4; |
| 965 | } |
| 966 | ahci_command_commit(ahci, cmd, port); |
| 967 | ahci_command_issue(ahci, cmd); |
| 968 | ahci_command_verify(ahci, cmd); |
| 969 | ahci_command_free(cmd); |
| 970 | } |
| 971 | |
| 972 | static int copy_buffer(AHCIQState *ahci, AHCICommand *cmd, |
| 973 | const AHCIOpts *opts) |
| 974 | { |
| 975 | unsigned char *rx = opts->opaque; |
| 976 | qtest_bufread(ahci->parent->qts, opts->buffer, rx, opts->size); |
| 977 | return 0; |
| 978 | } |
| 979 | |
| 980 | void ahci_atapi_get_sense(AHCIQState *ahci, uint8_t port, |
| 981 | uint8_t *sense, uint8_t *asc) |
| 982 | { |
| 983 | unsigned char *rx; |
| 984 | AHCIOpts opts = { |
| 985 | .size = 18, |
| 986 | .atapi = true, |
| 987 | .post_cb = copy_buffer, |
| 988 | }; |
| 989 | rx = g_malloc(18); |
| 990 | opts.opaque = rx; |
| 991 | |
| 992 | ahci_exec(ahci, port, CMD_ATAPI_REQUEST_SENSE, &opts); |
| 993 | |
| 994 | *sense = rx[2]; |
| 995 | *asc = rx[12]; |
| 996 | |
| 997 | g_free(rx); |
| 998 | } |
| 999 | |
| 1000 | void ahci_atapi_eject(AHCIQState *ahci, uint8_t port) |
| 1001 | { |
| 1002 | AHCICommand *cmd = ahci_atapi_command_create(CMD_ATAPI_START_STOP_UNIT, 0, false); |
| 1003 | ahci_command_set_size(cmd, 0); |
| 1004 | |
| 1005 | cmd->atapi_cmd[4] = 0x02; /* loej = true */ |
| 1006 | ahci_command_commit(ahci, cmd, port); |
| 1007 | ahci_command_issue(ahci, cmd); |
| 1008 | ahci_command_verify(ahci, cmd); |
| 1009 | ahci_command_free(cmd); |
| 1010 | } |
| 1011 | |
| 1012 | void ahci_atapi_load(AHCIQState *ahci, uint8_t port) |
| 1013 | { |
| 1014 | AHCICommand *cmd = ahci_atapi_command_create(CMD_ATAPI_START_STOP_UNIT, 0, false); |
| 1015 | ahci_command_set_size(cmd, 0); |
| 1016 | |
| 1017 | cmd->atapi_cmd[4] = 0x03; /* loej,start = true */ |
| 1018 | ahci_command_commit(ahci, cmd, port); |
| 1019 | ahci_command_issue(ahci, cmd); |
| 1020 | ahci_command_verify(ahci, cmd); |
| 1021 | ahci_command_free(cmd); |
| 1022 | } |
| 1023 | |
| 1024 | void ahci_command_free(AHCICommand *cmd) |
| 1025 | { |
| 1026 | g_free(cmd->atapi_cmd); |
| 1027 | g_free(cmd->props); |
| 1028 | g_free(cmd); |
| 1029 | } |
| 1030 | |
| 1031 | void ahci_command_set_flags(AHCICommand *cmd, uint16_t cmdh_flags) |
| 1032 | { |
| 1033 | cmd->header.flags |= cmdh_flags; |
| 1034 | } |
| 1035 | |
| 1036 | void ahci_command_clr_flags(AHCICommand *cmd, uint16_t cmdh_flags) |
| 1037 | { |
| 1038 | cmd->header.flags &= ~cmdh_flags; |
| 1039 | } |
| 1040 | |
| 1041 | static void ahci_atapi_command_set_offset(AHCICommand *cmd, uint64_t lba) |
| 1042 | { |
| 1043 | unsigned char *cbd = cmd->atapi_cmd; |
| 1044 | g_assert(cbd); |
| 1045 | |
| 1046 | switch (cbd[0]) { |
| 1047 | case CMD_ATAPI_READ_10: |
| 1048 | case CMD_ATAPI_READ_CD: |
| 1049 | g_assert_cmpuint(lba, <=, UINT32_MAX); |
| 1050 | stl_be_p(&cbd[2], lba); |
| 1051 | break; |
| 1052 | case CMD_ATAPI_REQUEST_SENSE: |
| 1053 | case CMD_ATAPI_TEST_UNIT_READY: |
| 1054 | case CMD_ATAPI_START_STOP_UNIT: |
| 1055 | g_assert_cmphex(lba, ==, 0x00); |
| 1056 | break; |
| 1057 | default: |
| 1058 | /* SCSI doesn't have uniform packet formats, |
| 1059 | * so you have to add support for it manually. Sorry! */ |
| 1060 | fprintf(stderr, "The Libqos AHCI driver does not support the " |
| 1061 | "set_offset operation for ATAPI command 0x%02x, " |
| 1062 | "please add support.\n", |
| 1063 | cbd[0]); |
| 1064 | g_assert_not_reached(); |
| 1065 | } |
| 1066 | } |
| 1067 | |
| 1068 | void ahci_command_set_offset(AHCICommand *cmd, uint64_t lba_sect) |
| 1069 | { |
| 1070 | RegH2DFIS *fis = &(cmd->fis); |
| 1071 | |
| 1072 | if (cmd->props->atapi) { |
| 1073 | ahci_atapi_command_set_offset(cmd, lba_sect); |
| 1074 | return; |
| 1075 | } else if (!cmd->props->data && !lba_sect) { |
| 1076 | /* Not meaningful, ignore. */ |
| 1077 | return; |
| 1078 | } else if (cmd->props->lba28) { |
| 1079 | g_assert_cmphex(lba_sect, <=, 0xFFFFFFF); |
| 1080 | } else if (cmd->props->lba48 || cmd->props->ncq) { |
| 1081 | g_assert_cmphex(lba_sect, <=, 0xFFFFFFFFFFFF); |
| 1082 | } else { |
| 1083 | /* Can't set offset if we don't know the format. */ |
| 1084 | g_assert_not_reached(); |
| 1085 | } |
| 1086 | |
| 1087 | /* LBA28 uses the low nibble of the device/control register for LBA24:27 */ |
| 1088 | fis->lba_lo[0] = (lba_sect & 0xFF); |
| 1089 | fis->lba_lo[1] = (lba_sect >> 8) & 0xFF; |
| 1090 | fis->lba_lo[2] = (lba_sect >> 16) & 0xFF; |
| 1091 | if (cmd->props->lba28) { |
| 1092 | fis->device = (fis->device & 0xF0) | ((lba_sect >> 24) & 0x0F); |
| 1093 | } |
| 1094 | fis->lba_hi[0] = (lba_sect >> 24) & 0xFF; |
| 1095 | fis->lba_hi[1] = (lba_sect >> 32) & 0xFF; |
| 1096 | fis->lba_hi[2] = (lba_sect >> 40) & 0xFF; |
| 1097 | } |
| 1098 | |
| 1099 | void ahci_command_set_buffer(AHCICommand *cmd, uint64_t buffer) |
| 1100 | { |
| 1101 | cmd->buffer = buffer; |
| 1102 | } |
| 1103 | |
| 1104 | static void ahci_atapi_set_size(AHCICommand *cmd, uint64_t xbytes) |
| 1105 | { |
| 1106 | unsigned char *cbd = cmd->atapi_cmd; |
| 1107 | uint64_t nsectors = xbytes / ATAPI_SECTOR_SIZE; |
| 1108 | uint32_t tmp; |
| 1109 | g_assert(cbd); |
| 1110 | |
| 1111 | switch (cbd[0]) { |
| 1112 | case CMD_ATAPI_READ_10: |
| 1113 | g_assert_cmpuint(nsectors, <=, UINT16_MAX); |
| 1114 | stw_be_p(&cbd[7], nsectors); |
| 1115 | break; |
| 1116 | case CMD_ATAPI_READ_CD: |
| 1117 | /* 24bit BE store */ |
| 1118 | g_assert_cmphex(nsectors, <, 1ULL << 24); |
| 1119 | tmp = nsectors; |
| 1120 | cbd[6] = (tmp & 0xFF0000) >> 16; |
| 1121 | cbd[7] = (tmp & 0xFF00) >> 8; |
| 1122 | cbd[8] = (tmp & 0xFF); |
| 1123 | break; |
| 1124 | case CMD_ATAPI_REQUEST_SENSE: |
| 1125 | g_assert_cmpuint(xbytes, <=, UINT8_MAX); |
| 1126 | cbd[4] = (uint8_t)xbytes; |
| 1127 | break; |
| 1128 | case CMD_ATAPI_TEST_UNIT_READY: |
| 1129 | case CMD_ATAPI_START_STOP_UNIT: |
| 1130 | g_assert_cmpuint(xbytes, ==, 0); |
| 1131 | break; |
| 1132 | default: |
| 1133 | /* SCSI doesn't have uniform packet formats, |
| 1134 | * so you have to add support for it manually. Sorry! */ |
| 1135 | fprintf(stderr, "The Libqos AHCI driver does not support the set_size " |
| 1136 | "operation for ATAPI command 0x%02x, please add support.\n", |
| 1137 | cbd[0]); |
| 1138 | g_assert_not_reached(); |
| 1139 | } |
| 1140 | } |
| 1141 | |
| 1142 | void ahci_command_set_sizes(AHCICommand *cmd, uint64_t xbytes, |
| 1143 | unsigned prd_size) |
| 1144 | { |
| 1145 | uint16_t sect_count; |
| 1146 | |
| 1147 | /* Each PRD can describe up to 4MiB, and must not be odd. */ |
| 1148 | g_assert_cmphex(prd_size, <=, 4096 * 1024); |
| 1149 | g_assert_cmphex(prd_size & 0x01, ==, 0x00); |
| 1150 | if (prd_size) { |
| 1151 | cmd->prd_size = prd_size; |
| 1152 | } |
| 1153 | cmd->xbytes = xbytes; |
| 1154 | sect_count = (cmd->xbytes / cmd->sector_size); |
| 1155 | |
| 1156 | if (cmd->props->ncq) { |
| 1157 | NCQFIS *nfis = (NCQFIS *)&(cmd->fis); |
| 1158 | nfis->sector_low = sect_count & 0xFF; |
| 1159 | nfis->sector_hi = (sect_count >> 8) & 0xFF; |
| 1160 | } else if (cmd->props->atapi) { |
| 1161 | ahci_atapi_set_size(cmd, xbytes); |
| 1162 | } else { |
| 1163 | /* For writes, the PIO Setup FIS interrupt only comes from DRQs |
| 1164 | * after the first. |
| 1165 | */ |
| 1166 | if (cmd->props->pio && sect_count > (cmd->props->read ? 0 : 1)) { |
| 1167 | cmd->interrupts |= AHCI_PX_IS_PSS; |
| 1168 | } |
| 1169 | cmd->fis.count = sect_count; |
| 1170 | } |
| 1171 | cmd->header.prdtl = size_to_prdtl(cmd->xbytes, cmd->prd_size); |
| 1172 | } |
| 1173 | |
| 1174 | void ahci_command_set_size(AHCICommand *cmd, uint64_t xbytes) |
| 1175 | { |
| 1176 | ahci_command_set_sizes(cmd, xbytes, cmd->prd_size); |
| 1177 | } |
| 1178 | |
| 1179 | void ahci_command_set_prd_size(AHCICommand *cmd, unsigned prd_size) |
| 1180 | { |
| 1181 | ahci_command_set_sizes(cmd, cmd->xbytes, prd_size); |
| 1182 | } |
| 1183 | |
| 1184 | /* For a no-data command, whose count carries an argument of its own */ |
| 1185 | void ahci_command_set_count(AHCICommand *cmd, uint16_t count) |
| 1186 | { |
| 1187 | g_assert(!cmd->props->data); |
| 1188 | cmd->fis.count = count; |
| 1189 | } |
| 1190 | |
| 1191 | void ahci_command_expect_error(AHCICommand *cmd, uint8_t err) |
| 1192 | { |
| 1193 | cmd->interrupts |= AHCI_PX_IS_TFES; |
| 1194 | cmd->errors |= err; |
| 1195 | } |
| 1196 | |
| 1197 | void ahci_command_adjust(AHCICommand *cmd, uint64_t offset, uint64_t buffer, |
| 1198 | uint64_t xbytes, unsigned prd_size) |
| 1199 | { |
| 1200 | ahci_command_set_sizes(cmd, xbytes, prd_size); |
| 1201 | ahci_command_set_buffer(cmd, buffer); |
| 1202 | ahci_command_set_offset(cmd, offset); |
| 1203 | } |
| 1204 | |
| 1205 | void ahci_command_commit(AHCIQState *ahci, AHCICommand *cmd, uint8_t port) |
| 1206 | { |
| 1207 | uint16_t i, prdtl; |
| 1208 | uint64_t table_size, table_ptr, remaining; |
| 1209 | PRD prd; |
| 1210 | |
| 1211 | /* This command is now tied to this port/command slot */ |
| 1212 | cmd->port = port; |
| 1213 | cmd->slot = ahci_pick_cmd(ahci, port); |
| 1214 | |
| 1215 | if (cmd->props->ncq) { |
| 1216 | NCQFIS *nfis = (NCQFIS *)&cmd->fis; |
| 1217 | nfis->tag = (cmd->slot << 3) & 0xFC; |
| 1218 | } |
| 1219 | |
| 1220 | /* Create a buffer for the command table */ |
| 1221 | prdtl = size_to_prdtl(cmd->xbytes, cmd->prd_size); |
| 1222 | table_size = CMD_TBL_SIZ(prdtl); |
| 1223 | table_ptr = ahci_alloc(ahci, table_size); |
| 1224 | g_assert(table_ptr); |
| 1225 | /* AHCI 1.3: Must be aligned to 0x80 */ |
| 1226 | g_assert((table_ptr & 0x7F) == 0x00); |
| 1227 | cmd->header.ctba = table_ptr; |
| 1228 | |
| 1229 | /* Commit the command header (part of the Command List Buffer) */ |
| 1230 | ahci_set_command_header(ahci, port, cmd->slot, &(cmd->header)); |
| 1231 | /* Now, write the command table (FIS, ACMD, and PRDT) -- FIS first, */ |
| 1232 | ahci_write_fis(ahci, cmd); |
| 1233 | /* Then ATAPI CMD, if needed */ |
| 1234 | if (cmd->props->atapi) { |
| 1235 | qtest_memwrite(ahci->parent->qts, table_ptr + 0x40, cmd->atapi_cmd, 16); |
| 1236 | } |
| 1237 | |
| 1238 | /* Construct and write the PRDs to the command table */ |
| 1239 | g_assert_cmphex(prdtl, ==, cmd->header.prdtl); |
| 1240 | remaining = cmd->xbytes; |
| 1241 | for (i = 0; i < prdtl; ++i) { |
| 1242 | prd.dba = cpu_to_le64(cmd->buffer + (cmd->prd_size * i)); |
| 1243 | prd.res = 0; |
| 1244 | if (remaining > cmd->prd_size) { |
| 1245 | /* Note that byte count is 0-based. */ |
| 1246 | prd.dbc = cpu_to_le32(cmd->prd_size - 1); |
| 1247 | remaining -= cmd->prd_size; |
| 1248 | } else { |
| 1249 | /* Again, dbc is 0-based. */ |
| 1250 | prd.dbc = cpu_to_le32(remaining - 1); |
| 1251 | remaining = 0; |
| 1252 | } |
| 1253 | prd.dbc |= cpu_to_le32(0x80000000); /* Request DPS Interrupt */ |
| 1254 | |
| 1255 | /* Commit the PRD entry to the Command Table */ |
| 1256 | qtest_memwrite(ahci->parent->qts, table_ptr + 0x80 + (i * sizeof(PRD)), |
| 1257 | &prd, sizeof(PRD)); |
| 1258 | } |
| 1259 | |
| 1260 | /* Bookmark the PRDTL and CTBA values */ |
| 1261 | ahci->port[port].ctba[cmd->slot] = table_ptr; |
| 1262 | ahci->port[port].prdtl[cmd->slot] = prdtl; |
| 1263 | } |
| 1264 | |
| 1265 | void ahci_command_issue_async(AHCIQState *ahci, AHCICommand *cmd) |
| 1266 | { |
| 1267 | if (cmd->props->ncq) { |
| 1268 | ahci_px_wreg(ahci, cmd->port, AHCI_PX_SACT, (1 << cmd->slot)); |
| 1269 | } |
| 1270 | |
| 1271 | ahci_px_wreg(ahci, cmd->port, AHCI_PX_CI, (1 << cmd->slot)); |
| 1272 | } |
| 1273 | |
| 1274 | void ahci_command_wait(AHCIQState *ahci, AHCICommand *cmd) |
| 1275 | { |
| 1276 | /* We can't rely on STS_BSY until the command has started processing. |
| 1277 | * Therefore, we also use the Command Issue bit as indication of |
| 1278 | * a command in-flight. */ |
| 1279 | |
| 1280 | #define RSET(REG, MASK) (BITSET(ahci_px_rreg(ahci, cmd->port, (REG)), (MASK))) |
| 1281 | |
| 1282 | while (!RSET(AHCI_PX_TFD, AHCI_PX_TFD_STS_ERR) && |
| 1283 | (RSET(AHCI_PX_TFD, AHCI_PX_TFD_STS_BSY) || |
| 1284 | RSET(AHCI_PX_CI, 1 << cmd->slot) || |
| 1285 | (cmd->props->ncq && RSET(AHCI_PX_SACT, 1 << cmd->slot)))) { |
| 1286 | usleep(50); |
| 1287 | } |
| 1288 | |
| 1289 | } |
| 1290 | |
| 1291 | void ahci_command_issue(AHCIQState *ahci, AHCICommand *cmd) |
| 1292 | { |
| 1293 | ahci_command_issue_async(ahci, cmd); |
| 1294 | ahci_command_wait(ahci, cmd); |
| 1295 | } |
| 1296 | |
| 1297 | void ahci_command_verify(AHCIQState *ahci, AHCICommand *cmd) |
| 1298 | { |
| 1299 | uint8_t slot = cmd->slot; |
| 1300 | uint8_t port = cmd->port; |
| 1301 | |
| 1302 | ahci_port_check_nonbusy(ahci, cmd); |
| 1303 | ahci_port_check_error(ahci, cmd); |
| 1304 | ahci_port_check_interrupts(ahci, cmd); |
| 1305 | ahci_port_check_cmd_sanity(ahci, cmd); |
| 1306 | if (cmd->interrupts & AHCI_PX_IS_DHRS) { |
| 1307 | ahci_port_check_d2h_sanity(ahci, port, slot); |
| 1308 | } |
| 1309 | if (cmd->props->pio) { |
| 1310 | ahci_port_check_pio_sanity(ahci, cmd); |
| 1311 | } |
| 1312 | } |
| 1313 | |
| 1314 | uint8_t ahci_command_slot(AHCICommand *cmd) |
| 1315 | { |
| 1316 | return cmd->slot; |
| 1317 | } |