@samitouri / QOSamiQemu
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1 /*
2 * libqos driver framework
3 *
4 * Copyright (c) 2022-2023 Red Hat, Inc.
5 * Copyright (c) 2018 Emanuele Giuseppe Esposito <e.emanuelegiuseppe@gmail.com>
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License version 2.1 as published by the Free Software Foundation.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>
18 */
19
20 #include "qemu/osdep.h"
21 #include "hw/net/igb_regs.h"
22 #include "hw/net/mii.h"
23 #include "hw/pci/pci_ids.h"
24 #include "../libqtest.h"
25 #include "pci-pc.h"
26 #include "qemu/sockets.h"
27 #include "qemu/iov.h"
28 #include "qemu/module.h"
29 #include "qemu/bitops.h"
30 #include "qemu/bswap.h"
31 #include "libqos-malloc.h"
32 #include "qgraph.h"
33 #include "e1000e.h"
34
35 #define IGB_IVAR_TEST_CFG \
36 ((E1000E_RX0_MSG_ID | E1000_IVAR_VALID) << (igb_ivar_entry_rx(0) * 8) | \
37 ((E1000E_TX0_MSG_ID | E1000_IVAR_VALID) << (igb_ivar_entry_tx(0) * 8)))
38
39 #define E1000E_RING_LEN (0x1000)
40
41 static void e1000e_foreach_callback(QPCIDevice *dev, int devfn, void *data)
42 {
43 QPCIDevice *res = data;
44 memcpy(res, dev, sizeof(QPCIDevice));
45 g_free(dev);
46 }
47
48 static void e1000e_pci_destructor(QOSGraphObject *obj)
49 {
50 QE1000E_PCI *epci = (QE1000E_PCI *) obj;
51 qpci_iounmap(&epci->pci_dev, epci->mac_regs);
52 qpci_msix_disable(&epci->pci_dev);
53 }
54
55 static void igb_pci_start_hw(QOSGraphObject *obj)
56 {
57 static const uint8_t address[] = E1000E_ADDRESS;
58 QE1000E_PCI *d = (QE1000E_PCI *) obj;
59 uint32_t val;
60
61 /* Enable the device */
62 qpci_device_enable(&d->pci_dev);
63
64 /* Reset the device */
65 val = e1000e_macreg_read(&d->e1000e, E1000_CTRL);
66 e1000e_macreg_write(&d->e1000e, E1000_CTRL, val | E1000_CTRL_RST | E1000_CTRL_SLU);
67
68 /* Setup link */
69 e1000e_macreg_write(&d->e1000e, E1000_MDIC,
70 MII_BMCR_AUTOEN | MII_BMCR_ANRESTART |
71 (MII_BMCR << E1000_MDIC_REG_SHIFT) |
72 (1 << E1000_MDIC_PHY_SHIFT) |
73 E1000_MDIC_OP_WRITE);
74
75 qtest_clock_step(d->pci_dev.bus->qts, 900000000);
76
77 /* Enable and configure MSI-X */
78 qpci_msix_enable(&d->pci_dev);
79 e1000e_macreg_write(&d->e1000e, E1000_IVAR0, IGB_IVAR_TEST_CFG);
80
81 /* Check the device link status */
82 val = e1000e_macreg_read(&d->e1000e, E1000_STATUS);
83 g_assert_cmphex(val & E1000_STATUS_LU, ==, E1000_STATUS_LU);
84
85 /* Initialize TX/RX logic */
86 e1000e_macreg_write(&d->e1000e, E1000_RCTL, 0);
87 e1000e_macreg_write(&d->e1000e, E1000_TCTL, 0);
88
89 e1000e_macreg_write(&d->e1000e, E1000_TDBAL(0),
90 (uint32_t) d->e1000e.tx_ring);
91 e1000e_macreg_write(&d->e1000e, E1000_TDBAH(0),
92 (uint32_t) (d->e1000e.tx_ring >> 32));
93 e1000e_macreg_write(&d->e1000e, E1000_TDLEN(0), E1000E_RING_LEN);
94 e1000e_macreg_write(&d->e1000e, E1000_TDT(0), 0);
95 e1000e_macreg_write(&d->e1000e, E1000_TDH(0), 0);
96
97 /* Enable transmit */
98 e1000e_macreg_write(&d->e1000e, E1000_TCTL, E1000_TCTL_EN);
99
100 e1000e_macreg_write(&d->e1000e, E1000_RDBAL(0),
101 (uint32_t)d->e1000e.rx_ring);
102 e1000e_macreg_write(&d->e1000e, E1000_RDBAH(0),
103 (uint32_t)(d->e1000e.rx_ring >> 32));
104 e1000e_macreg_write(&d->e1000e, E1000_RDLEN(0), E1000E_RING_LEN);
105 e1000e_macreg_write(&d->e1000e, E1000_RDT(0), 0);
106 e1000e_macreg_write(&d->e1000e, E1000_RDH(0), 0);
107 e1000e_macreg_write(&d->e1000e, E1000_RA,
108 ldl_le_p(address));
109 e1000e_macreg_write(&d->e1000e, E1000_RA + 4,
110 E1000_RAH_AV | E1000_RAH_POOL_1 |
111 lduw_le_p(address + 4));
112
113 /* Set supported receive descriptor mode */
114 e1000e_macreg_write(&d->e1000e,
115 E1000_SRRCTL(0),
116 E1000_SRRCTL_DESCTYPE_ADV_ONEBUF);
117
118 /* Enable receive */
119 e1000e_macreg_write(&d->e1000e, E1000_RFCTL, E1000_RFCTL_EXTEN);
120 e1000e_macreg_write(&d->e1000e, E1000_RCTL, E1000_RCTL_EN);
121
122 /* Enable all interrupts */
123 e1000e_macreg_write(&d->e1000e, E1000_GPIE, E1000_GPIE_MSIX_MODE);
124 e1000e_macreg_write(&d->e1000e, E1000_IMS, 0xFFFFFFFF);
125 e1000e_macreg_write(&d->e1000e, E1000_EIMS, 0xFFFFFFFF);
126
127 }
128
129 static void *igb_pci_get_driver(void *obj, const char *interface)
130 {
131 QE1000E_PCI *epci = obj;
132 if (!g_strcmp0(interface, "igb-if")) {
133 return &epci->e1000e;
134 }
135
136 /* implicit contains */
137 if (!g_strcmp0(interface, "pci-device")) {
138 return &epci->pci_dev;
139 }
140
141 fprintf(stderr, "%s not present in igb\n", interface);
142 g_assert_not_reached();
143 }
144
145 static void *igb_pci_create(void *pci_bus, QGuestAllocator *alloc, void *addr)
146 {
147 QE1000E_PCI *d = g_new0(QE1000E_PCI, 1);
148 QPCIBus *bus = pci_bus;
149 QPCIAddress *address = addr;
150
151 qpci_device_foreach(bus, address->vendor_id, address->device_id,
152 e1000e_foreach_callback, &d->pci_dev);
153
154 /* Map BAR0 (mac registers) */
155 d->mac_regs = qpci_iomap(&d->pci_dev, 0, NULL);
156
157 /* Allocate and setup TX ring */
158 d->e1000e.tx_ring = guest_alloc(alloc, E1000E_RING_LEN);
159 g_assert(d->e1000e.tx_ring != 0);
160
161 /* Allocate and setup RX ring */
162 d->e1000e.rx_ring = guest_alloc(alloc, E1000E_RING_LEN);
163 g_assert(d->e1000e.rx_ring != 0);
164
165 d->obj.get_driver = igb_pci_get_driver;
166 d->obj.start_hw = igb_pci_start_hw;
167 d->obj.destructor = e1000e_pci_destructor;
168
169 return &d->obj;
170 }
171
172 static void igb_register_nodes(void)
173 {
174 QPCIAddress addr = {
175 .vendor_id = PCI_VENDOR_ID_INTEL,
176 .device_id = E1000_DEV_ID_82576,
177 };
178
179 /*
180 * FIXME: every test using this node needs to setup a -netdev socket,id=hs0
181 * otherwise QEMU is not going to start
182 */
183 QOSGraphEdgeOptions opts = {
184 .extra_device_opts = "netdev=hs0",
185 };
186 add_qpci_address(&opts, &addr);
187
188 qos_node_create_driver("igb", igb_pci_create);
189 qos_node_consumes("igb", "pci-bus", &opts);
190 }
191
192 libqos_init(igb_register_nodes);