| 1 | /* |
| 2 | * libqos driver riscv-iommu-pci framework |
| 3 | * |
| 4 | * Copyright (c) 2024 Ventana Micro Systems Inc. |
| 5 | * |
| 6 | * This work is licensed under the terms of the GNU GPL, version 2 or (at your |
| 7 | * option) any later version. See the COPYING file in the top-level directory. |
| 8 | * |
| 9 | */ |
| 10 | |
| 11 | #ifndef TESTS_LIBQOS_RISCV_IOMMU_H |
| 12 | #define TESTS_LIBQOS_RISCV_IOMMU_H |
| 13 | |
| 14 | #include "qgraph.h" |
| 15 | #include "pci.h" |
| 16 | #include "qemu/bitops.h" |
| 17 | |
| 18 | #ifndef GENMASK_ULL |
| 19 | #define GENMASK_ULL(h, l) (((~0ULL) >> (63 - (h) + (l))) << (l)) |
| 20 | #endif |
| 21 | |
| 22 | /* |
| 23 | * RISC-V IOMMU uses PCI_VENDOR_ID_REDHAT 0x1b36 and |
| 24 | * PCI_DEVICE_ID_REDHAT_RISCV_IOMMU 0x0014. |
| 25 | */ |
| 26 | #define RISCV_IOMMU_PCI_VENDOR_ID 0x1b36 |
| 27 | #define RISCV_IOMMU_PCI_DEVICE_ID 0x0014 |
| 28 | #define RISCV_IOMMU_PCI_DEVICE_CLASS 0x0806 |
| 29 | |
| 30 | /* Common field positions */ |
| 31 | #define RISCV_IOMMU_QUEUE_ENABLE BIT(0) |
| 32 | #define RISCV_IOMMU_QUEUE_INTR_ENABLE BIT(1) |
| 33 | #define RISCV_IOMMU_QUEUE_MEM_FAULT BIT(8) |
| 34 | #define RISCV_IOMMU_QUEUE_ACTIVE BIT(16) |
| 35 | #define RISCV_IOMMU_QUEUE_BUSY BIT(17) |
| 36 | |
| 37 | #define RISCV_IOMMU_REG_CAP 0x0000 |
| 38 | #define RISCV_IOMMU_CAP_VERSION GENMASK_ULL(7, 0) |
| 39 | |
| 40 | #define RISCV_IOMMU_REG_DDTP 0x0010 |
| 41 | #define RISCV_IOMMU_DDTP_BUSY BIT_ULL(4) |
| 42 | #define RISCV_IOMMU_DDTP_MODE GENMASK_ULL(3, 0) |
| 43 | #define RISCV_IOMMU_DDTP_MODE_OFF 0 |
| 44 | |
| 45 | #define RISCV_IOMMU_REG_CQCSR 0x0048 |
| 46 | #define RISCV_IOMMU_CQCSR_CQEN RISCV_IOMMU_QUEUE_ENABLE |
| 47 | #define RISCV_IOMMU_CQCSR_CIE RISCV_IOMMU_QUEUE_INTR_ENABLE |
| 48 | #define RISCV_IOMMU_CQCSR_CQON RISCV_IOMMU_QUEUE_ACTIVE |
| 49 | #define RISCV_IOMMU_CQCSR_BUSY RISCV_IOMMU_QUEUE_BUSY |
| 50 | |
| 51 | #define RISCV_IOMMU_REG_FQCSR 0x004C |
| 52 | #define RISCV_IOMMU_FQCSR_FQEN RISCV_IOMMU_QUEUE_ENABLE |
| 53 | #define RISCV_IOMMU_FQCSR_FIE RISCV_IOMMU_QUEUE_INTR_ENABLE |
| 54 | #define RISCV_IOMMU_FQCSR_FQON RISCV_IOMMU_QUEUE_ACTIVE |
| 55 | #define RISCV_IOMMU_FQCSR_BUSY RISCV_IOMMU_QUEUE_BUSY |
| 56 | |
| 57 | #define RISCV_IOMMU_REG_PQCSR 0x0050 |
| 58 | #define RISCV_IOMMU_PQCSR_PQEN RISCV_IOMMU_QUEUE_ENABLE |
| 59 | #define RISCV_IOMMU_PQCSR_PIE RISCV_IOMMU_QUEUE_INTR_ENABLE |
| 60 | #define RISCV_IOMMU_PQCSR_PQON RISCV_IOMMU_QUEUE_ACTIVE |
| 61 | #define RISCV_IOMMU_PQCSR_BUSY RISCV_IOMMU_QUEUE_BUSY |
| 62 | |
| 63 | #define RISCV_IOMMU_REG_IPSR 0x0054 |
| 64 | |
| 65 | #define RISCV_IOMMU_REG_IVEC 0x02F8 |
| 66 | #define RISCV_IOMMU_REG_IVEC_CIV GENMASK_ULL(3, 0) |
| 67 | #define RISCV_IOMMU_REG_IVEC_FIV GENMASK_ULL(7, 4) |
| 68 | #define RISCV_IOMMU_REG_IVEC_PMIV GENMASK_ULL(11, 8) |
| 69 | #define RISCV_IOMMU_REG_IVEC_PIV GENMASK_ULL(15, 12) |
| 70 | |
| 71 | #define RISCV_IOMMU_REG_CQB 0x0018 |
| 72 | #define RISCV_IOMMU_CQB_PPN_START 10 |
| 73 | #define RISCV_IOMMU_CQB_PPN_LEN 44 |
| 74 | #define RISCV_IOMMU_CQB_LOG2SZ_START 0 |
| 75 | #define RISCV_IOMMU_CQB_LOG2SZ_LEN 5 |
| 76 | |
| 77 | #define RISCV_IOMMU_REG_CQT 0x0024 |
| 78 | |
| 79 | #define RISCV_IOMMU_REG_FQB 0x0028 |
| 80 | #define RISCV_IOMMU_FQB_PPN_START 10 |
| 81 | #define RISCV_IOMMU_FQB_PPN_LEN 44 |
| 82 | #define RISCV_IOMMU_FQB_LOG2SZ_START 0 |
| 83 | #define RISCV_IOMMU_FQB_LOG2SZ_LEN 5 |
| 84 | |
| 85 | #define RISCV_IOMMU_REG_FQT 0x0034 |
| 86 | |
| 87 | #define RISCV_IOMMU_REG_PQB 0x0038 |
| 88 | #define RISCV_IOMMU_PQB_PPN_START 10 |
| 89 | #define RISCV_IOMMU_PQB_PPN_LEN 44 |
| 90 | #define RISCV_IOMMU_PQB_LOG2SZ_START 0 |
| 91 | #define RISCV_IOMMU_PQB_LOG2SZ_LEN 5 |
| 92 | |
| 93 | #define RISCV_IOMMU_REG_PQT 0x0044 |
| 94 | |
| 95 | typedef struct QRISCVIOMMU { |
| 96 | QOSGraphObject obj; |
| 97 | QPCIDevice dev; |
| 98 | QPCIBar reg_bar; |
| 99 | } QRISCVIOMMU; |
| 100 | |
| 101 | #endif |