| 1 | /* |
| 2 | * QTests for Nuvoton NPCM7xx EMC Modules. |
| 3 | * |
| 4 | * Copyright 2020 Google LLC |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify it |
| 7 | * under the terms of the GNU General Public License as published by the |
| 8 | * Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
| 14 | * for more details. |
| 15 | */ |
| 16 | |
| 17 | #include "qemu/osdep.h" |
| 18 | #include "libqos/libqos.h" |
| 19 | #include "qobject/qdict.h" |
| 20 | #include "qobject/qnum.h" |
| 21 | #include "qemu/bitops.h" |
| 22 | #include "qemu/bswap.h" |
| 23 | #include "qemu/iov.h" |
| 24 | |
| 25 | /* Name of the emc device. */ |
| 26 | #define TYPE_NPCM7XX_EMC "npcm7xx-emc" |
| 27 | |
| 28 | /* Timeout for various operations, in seconds. */ |
| 29 | #define TIMEOUT_SECONDS 10 |
| 30 | |
| 31 | /* Address in memory of the descriptor. */ |
| 32 | #define DESC_ADDR (1 << 20) /* 1 MiB */ |
| 33 | |
| 34 | /* Address in memory of the data packet. */ |
| 35 | #define DATA_ADDR (DESC_ADDR + 4096) |
| 36 | |
| 37 | #define CRC_LENGTH 4 |
| 38 | |
| 39 | #define NUM_TX_DESCRIPTORS 3 |
| 40 | #define NUM_RX_DESCRIPTORS 2 |
| 41 | |
| 42 | /* Size of tx,rx test buffers. */ |
| 43 | #define TX_DATA_LEN 64 |
| 44 | #define RX_DATA_LEN 64 |
| 45 | |
| 46 | #define TX_STEP_COUNT 10000 |
| 47 | #define RX_STEP_COUNT 10000 |
| 48 | |
| 49 | /* 32-bit register indices. */ |
| 50 | typedef enum NPCM7xxPWMRegister { |
| 51 | /* Control registers. */ |
| 52 | REG_CAMCMR, |
| 53 | REG_CAMEN, |
| 54 | |
| 55 | /* There are 16 CAMn[ML] registers. */ |
| 56 | REG_CAMM_BASE, |
| 57 | REG_CAML_BASE, |
| 58 | |
| 59 | REG_TXDLSA = 0x22, |
| 60 | REG_RXDLSA, |
| 61 | REG_MCMDR, |
| 62 | REG_MIID, |
| 63 | REG_MIIDA, |
| 64 | REG_FFTCR, |
| 65 | REG_TSDR, |
| 66 | REG_RSDR, |
| 67 | REG_DMARFC, |
| 68 | REG_MIEN, |
| 69 | |
| 70 | /* Status registers. */ |
| 71 | REG_MISTA, |
| 72 | REG_MGSTA, |
| 73 | REG_MPCNT, |
| 74 | REG_MRPC, |
| 75 | REG_MRPCC, |
| 76 | REG_MREPC, |
| 77 | REG_DMARFS, |
| 78 | REG_CTXDSA, |
| 79 | REG_CTXBSA, |
| 80 | REG_CRXDSA, |
| 81 | REG_CRXBSA, |
| 82 | |
| 83 | NPCM7XX_NUM_EMC_REGS, |
| 84 | } NPCM7xxPWMRegister; |
| 85 | |
| 86 | enum { NUM_CAMML_REGS = 16 }; |
| 87 | |
| 88 | /* REG_CAMCMR fields */ |
| 89 | /* Enable CAM Compare */ |
| 90 | #define REG_CAMCMR_ECMP (1 << 4) |
| 91 | /* Accept Unicast Packet */ |
| 92 | #define REG_CAMCMR_AUP (1 << 0) |
| 93 | |
| 94 | /* REG_MCMDR fields */ |
| 95 | /* Software Reset */ |
| 96 | #define REG_MCMDR_SWR (1 << 24) |
| 97 | /* Frame Transmission On */ |
| 98 | #define REG_MCMDR_TXON (1 << 8) |
| 99 | /* Accept Long Packet */ |
| 100 | #define REG_MCMDR_ALP (1 << 1) |
| 101 | /* Frame Reception On */ |
| 102 | #define REG_MCMDR_RXON (1 << 0) |
| 103 | |
| 104 | /* REG_MIEN fields */ |
| 105 | /* Enable Transmit Completion Interrupt */ |
| 106 | #define REG_MIEN_ENTXCP (1 << 18) |
| 107 | /* Enable Transmit Interrupt */ |
| 108 | #define REG_MIEN_ENTXINTR (1 << 16) |
| 109 | /* Enable Receive Good Interrupt */ |
| 110 | #define REG_MIEN_ENRXGD (1 << 4) |
| 111 | /* ENable Receive Interrupt */ |
| 112 | #define REG_MIEN_ENRXINTR (1 << 0) |
| 113 | |
| 114 | /* REG_MISTA fields */ |
| 115 | /* Transmit Bus Error Interrupt */ |
| 116 | #define REG_MISTA_TXBERR (1 << 24) |
| 117 | /* Transmit Descriptor Unavailable Interrupt */ |
| 118 | #define REG_MISTA_TDU (1 << 23) |
| 119 | /* Transmit Completion Interrupt */ |
| 120 | #define REG_MISTA_TXCP (1 << 18) |
| 121 | /* Transmit Interrupt */ |
| 122 | #define REG_MISTA_TXINTR (1 << 16) |
| 123 | /* Receive Bus Error Interrupt */ |
| 124 | #define REG_MISTA_RXBERR (1 << 11) |
| 125 | /* Receive Descriptor Unavailable Interrupt */ |
| 126 | #define REG_MISTA_RDU (1 << 10) |
| 127 | /* DMA Early Notification Interrupt */ |
| 128 | #define REG_MISTA_DENI (1 << 9) |
| 129 | /* Maximum Frame Length Interrupt */ |
| 130 | #define REG_MISTA_DFOI (1 << 8) |
| 131 | /* Receive Good Interrupt */ |
| 132 | #define REG_MISTA_RXGD (1 << 4) |
| 133 | /* Packet Too Long Interrupt */ |
| 134 | #define REG_MISTA_PTLE (1 << 3) |
| 135 | /* Receive Interrupt */ |
| 136 | #define REG_MISTA_RXINTR (1 << 0) |
| 137 | |
| 138 | typedef struct NPCM7xxEMCTxDesc NPCM7xxEMCTxDesc; |
| 139 | typedef struct NPCM7xxEMCRxDesc NPCM7xxEMCRxDesc; |
| 140 | |
| 141 | struct NPCM7xxEMCTxDesc { |
| 142 | uint32_t flags; |
| 143 | uint32_t txbsa; |
| 144 | uint32_t status_and_length; |
| 145 | uint32_t ntxdsa; |
| 146 | }; |
| 147 | |
| 148 | struct NPCM7xxEMCRxDesc { |
| 149 | uint32_t status_and_length; |
| 150 | uint32_t rxbsa; |
| 151 | uint32_t reserved; |
| 152 | uint32_t nrxdsa; |
| 153 | }; |
| 154 | |
| 155 | /* NPCM7xxEMCTxDesc.flags values */ |
| 156 | /* Owner: 0 = cpu, 1 = emc */ |
| 157 | #define TX_DESC_FLAG_OWNER_MASK (1 << 31) |
| 158 | /* Transmit interrupt enable */ |
| 159 | #define TX_DESC_FLAG_INTEN (1 << 2) |
| 160 | |
| 161 | /* NPCM7xxEMCTxDesc.status_and_length values */ |
| 162 | /* Transmission complete */ |
| 163 | #define TX_DESC_STATUS_TXCP (1 << 19) |
| 164 | /* Transmit interrupt */ |
| 165 | #define TX_DESC_STATUS_TXINTR (1 << 16) |
| 166 | |
| 167 | /* NPCM7xxEMCRxDesc.status_and_length values */ |
| 168 | /* Owner: 0b00 = cpu, 0b10 = emc */ |
| 169 | #define RX_DESC_STATUS_OWNER_SHIFT 30 |
| 170 | #define RX_DESC_STATUS_OWNER_MASK 0xc0000000 |
| 171 | /* Frame Reception Complete */ |
| 172 | #define RX_DESC_STATUS_RXGD (1 << 20) |
| 173 | /* Packet too long */ |
| 174 | #define RX_DESC_STATUS_PTLE (1 << 19) |
| 175 | /* Receive Interrupt */ |
| 176 | #define RX_DESC_STATUS_RXINTR (1 << 16) |
| 177 | |
| 178 | #define RX_DESC_PKT_LEN(word) ((uint32_t) (word) & 0xffff) |
| 179 | |
| 180 | typedef struct EMCModule { |
| 181 | int rx_irq; |
| 182 | int tx_irq; |
| 183 | uint64_t base_addr; |
| 184 | } EMCModule; |
| 185 | |
| 186 | typedef struct TestData { |
| 187 | const EMCModule *module; |
| 188 | } TestData; |
| 189 | |
| 190 | static const EMCModule emc_module_list[] = { |
| 191 | { |
| 192 | .rx_irq = 15, |
| 193 | .tx_irq = 16, |
| 194 | .base_addr = 0xf0825000 |
| 195 | }, |
| 196 | { |
| 197 | .rx_irq = 114, |
| 198 | .tx_irq = 115, |
| 199 | .base_addr = 0xf0826000 |
| 200 | } |
| 201 | }; |
| 202 | |
| 203 | /* Returns the index of the EMC module. */ |
| 204 | static int emc_module_index(const EMCModule *mod) |
| 205 | { |
| 206 | ptrdiff_t diff = mod - emc_module_list; |
| 207 | |
| 208 | g_assert_true(diff >= 0 && diff < ARRAY_SIZE(emc_module_list)); |
| 209 | |
| 210 | return diff; |
| 211 | } |
| 212 | |
| 213 | #ifndef _WIN32 |
| 214 | static void packet_test_clear(void *sockets) |
| 215 | { |
| 216 | int *test_sockets = sockets; |
| 217 | |
| 218 | close(test_sockets[0]); |
| 219 | g_free(test_sockets); |
| 220 | } |
| 221 | |
| 222 | static int *packet_test_init(int module_num, GString *cmd_line) |
| 223 | { |
| 224 | int *test_sockets = g_new(int, 2); |
| 225 | int ret = socketpair(PF_UNIX, SOCK_STREAM, 0, test_sockets); |
| 226 | g_assert_cmpint(ret, != , -1); |
| 227 | |
| 228 | /* |
| 229 | * KISS and use -nic. The driver accepts 'emc0' and 'emc1' as aliases |
| 230 | * in the 'model' field to specify the device to match. |
| 231 | */ |
| 232 | g_string_append_printf(cmd_line, " -nic socket,fd=%d,model=emc%d " |
| 233 | "-nic user,model=npcm7xx-emc " |
| 234 | "-nic user,model=npcm-gmac " |
| 235 | "-nic user,model=npcm-gmac", |
| 236 | test_sockets[1], module_num); |
| 237 | |
| 238 | g_test_queue_destroy(packet_test_clear, test_sockets); |
| 239 | return test_sockets; |
| 240 | } |
| 241 | #endif /* _WIN32 */ |
| 242 | |
| 243 | static uint32_t emc_read(QTestState *qts, const EMCModule *mod, |
| 244 | NPCM7xxPWMRegister regno) |
| 245 | { |
| 246 | return qtest_readl(qts, mod->base_addr + regno * sizeof(uint32_t)); |
| 247 | } |
| 248 | |
| 249 | #ifndef _WIN32 |
| 250 | static void emc_write(QTestState *qts, const EMCModule *mod, |
| 251 | NPCM7xxPWMRegister regno, uint32_t value) |
| 252 | { |
| 253 | qtest_writel(qts, mod->base_addr + regno * sizeof(uint32_t), value); |
| 254 | } |
| 255 | |
| 256 | static void emc_read_tx_desc(QTestState *qts, uint32_t addr, |
| 257 | NPCM7xxEMCTxDesc *desc) |
| 258 | { |
| 259 | qtest_memread(qts, addr, desc, sizeof(*desc)); |
| 260 | desc->flags = le32_to_cpu(desc->flags); |
| 261 | desc->txbsa = le32_to_cpu(desc->txbsa); |
| 262 | desc->status_and_length = le32_to_cpu(desc->status_and_length); |
| 263 | desc->ntxdsa = le32_to_cpu(desc->ntxdsa); |
| 264 | } |
| 265 | |
| 266 | static void emc_write_tx_desc(QTestState *qts, const NPCM7xxEMCTxDesc *desc, |
| 267 | uint32_t addr) |
| 268 | { |
| 269 | NPCM7xxEMCTxDesc le_desc; |
| 270 | |
| 271 | le_desc.flags = cpu_to_le32(desc->flags); |
| 272 | le_desc.txbsa = cpu_to_le32(desc->txbsa); |
| 273 | le_desc.status_and_length = cpu_to_le32(desc->status_and_length); |
| 274 | le_desc.ntxdsa = cpu_to_le32(desc->ntxdsa); |
| 275 | qtest_memwrite(qts, addr, &le_desc, sizeof(le_desc)); |
| 276 | } |
| 277 | |
| 278 | static void emc_read_rx_desc(QTestState *qts, uint32_t addr, |
| 279 | NPCM7xxEMCRxDesc *desc) |
| 280 | { |
| 281 | qtest_memread(qts, addr, desc, sizeof(*desc)); |
| 282 | desc->status_and_length = le32_to_cpu(desc->status_and_length); |
| 283 | desc->rxbsa = le32_to_cpu(desc->rxbsa); |
| 284 | desc->reserved = le32_to_cpu(desc->reserved); |
| 285 | desc->nrxdsa = le32_to_cpu(desc->nrxdsa); |
| 286 | } |
| 287 | |
| 288 | static void emc_write_rx_desc(QTestState *qts, const NPCM7xxEMCRxDesc *desc, |
| 289 | uint32_t addr) |
| 290 | { |
| 291 | NPCM7xxEMCRxDesc le_desc; |
| 292 | |
| 293 | le_desc.status_and_length = cpu_to_le32(desc->status_and_length); |
| 294 | le_desc.rxbsa = cpu_to_le32(desc->rxbsa); |
| 295 | le_desc.reserved = cpu_to_le32(desc->reserved); |
| 296 | le_desc.nrxdsa = cpu_to_le32(desc->nrxdsa); |
| 297 | qtest_memwrite(qts, addr, &le_desc, sizeof(le_desc)); |
| 298 | } |
| 299 | |
| 300 | /* |
| 301 | * Reset the EMC module. |
| 302 | * The module must be reset before, e.g., TXDLSA,RXDLSA are changed. |
| 303 | */ |
| 304 | static bool emc_soft_reset(QTestState *qts, const EMCModule *mod) |
| 305 | { |
| 306 | uint32_t val; |
| 307 | uint64_t end_time; |
| 308 | |
| 309 | emc_write(qts, mod, REG_MCMDR, REG_MCMDR_SWR); |
| 310 | |
| 311 | /* |
| 312 | * Wait for device to reset as the linux driver does. |
| 313 | * During reset the AHB reads 0 for all registers. So first wait for |
| 314 | * something that resets to non-zero, and then wait for SWR becoming 0. |
| 315 | */ |
| 316 | end_time = g_get_monotonic_time() + TIMEOUT_SECONDS * G_TIME_SPAN_SECOND; |
| 317 | |
| 318 | do { |
| 319 | qtest_clock_step(qts, 100); |
| 320 | val = emc_read(qts, mod, REG_FFTCR); |
| 321 | } while (val == 0 && g_get_monotonic_time() < end_time); |
| 322 | if (val != 0) { |
| 323 | do { |
| 324 | qtest_clock_step(qts, 100); |
| 325 | val = emc_read(qts, mod, REG_MCMDR); |
| 326 | if ((val & REG_MCMDR_SWR) == 0) { |
| 327 | /* |
| 328 | * N.B. The CAMs have been reset here, so macaddr matching of |
| 329 | * incoming packets will not work. |
| 330 | */ |
| 331 | return true; |
| 332 | } |
| 333 | } while (g_get_monotonic_time() < end_time); |
| 334 | } |
| 335 | |
| 336 | g_message("%s: Timeout expired", __func__); |
| 337 | return false; |
| 338 | } |
| 339 | #endif /* _WIN32 */ |
| 340 | |
| 341 | /* Check emc registers are reset to default value. */ |
| 342 | static void test_init(gconstpointer test_data) |
| 343 | { |
| 344 | const TestData *td = test_data; |
| 345 | const EMCModule *mod = td->module; |
| 346 | QTestState *qts = qtest_init("-machine quanta-gsj"); |
| 347 | int i; |
| 348 | |
| 349 | #define CHECK_REG(regno, value) \ |
| 350 | do { \ |
| 351 | g_assert_cmphex(emc_read(qts, mod, (regno)), ==, (value)); \ |
| 352 | } while (0) |
| 353 | |
| 354 | CHECK_REG(REG_CAMCMR, 0); |
| 355 | CHECK_REG(REG_CAMEN, 0); |
| 356 | CHECK_REG(REG_TXDLSA, 0xfffffffc); |
| 357 | CHECK_REG(REG_RXDLSA, 0xfffffffc); |
| 358 | CHECK_REG(REG_MCMDR, 0); |
| 359 | CHECK_REG(REG_MIID, 0); |
| 360 | CHECK_REG(REG_MIIDA, 0x00900000); |
| 361 | CHECK_REG(REG_FFTCR, 0x0101); |
| 362 | CHECK_REG(REG_DMARFC, 0x0800); |
| 363 | CHECK_REG(REG_MIEN, 0); |
| 364 | CHECK_REG(REG_MISTA, 0); |
| 365 | CHECK_REG(REG_MGSTA, 0); |
| 366 | CHECK_REG(REG_MPCNT, 0x7fff); |
| 367 | CHECK_REG(REG_MRPC, 0); |
| 368 | CHECK_REG(REG_MRPCC, 0); |
| 369 | CHECK_REG(REG_MREPC, 0); |
| 370 | CHECK_REG(REG_DMARFS, 0); |
| 371 | CHECK_REG(REG_CTXDSA, 0); |
| 372 | CHECK_REG(REG_CTXBSA, 0); |
| 373 | CHECK_REG(REG_CRXDSA, 0); |
| 374 | CHECK_REG(REG_CRXBSA, 0); |
| 375 | |
| 376 | #undef CHECK_REG |
| 377 | |
| 378 | /* Skip over the MAC address registers, which is BASE+0 */ |
| 379 | for (i = 1; i < NUM_CAMML_REGS; ++i) { |
| 380 | g_assert_cmpuint(emc_read(qts, mod, REG_CAMM_BASE + i * 2), ==, |
| 381 | 0); |
| 382 | g_assert_cmpuint(emc_read(qts, mod, REG_CAML_BASE + i * 2), ==, |
| 383 | 0); |
| 384 | } |
| 385 | |
| 386 | qtest_quit(qts); |
| 387 | } |
| 388 | |
| 389 | #ifndef _WIN32 |
| 390 | static bool emc_wait_irq(QTestState *qts, const EMCModule *mod, int step, |
| 391 | bool is_tx) |
| 392 | { |
| 393 | uint64_t end_time = |
| 394 | g_get_monotonic_time() + TIMEOUT_SECONDS * G_TIME_SPAN_SECOND; |
| 395 | |
| 396 | do { |
| 397 | if (qtest_get_irq(qts, is_tx ? mod->tx_irq : mod->rx_irq)) { |
| 398 | return true; |
| 399 | } |
| 400 | qtest_clock_step(qts, step); |
| 401 | } while (g_get_monotonic_time() < end_time); |
| 402 | |
| 403 | g_message("%s: Timeout expired", __func__); |
| 404 | return false; |
| 405 | } |
| 406 | |
| 407 | static bool emc_wait_mista(QTestState *qts, const EMCModule *mod, int step, |
| 408 | uint32_t flag) |
| 409 | { |
| 410 | uint64_t end_time = |
| 411 | g_get_monotonic_time() + TIMEOUT_SECONDS * G_TIME_SPAN_SECOND; |
| 412 | |
| 413 | do { |
| 414 | uint32_t mista = emc_read(qts, mod, REG_MISTA); |
| 415 | if (mista & flag) { |
| 416 | return true; |
| 417 | } |
| 418 | qtest_clock_step(qts, step); |
| 419 | } while (g_get_monotonic_time() < end_time); |
| 420 | |
| 421 | g_message("%s: Timeout expired", __func__); |
| 422 | return false; |
| 423 | } |
| 424 | |
| 425 | static bool wait_socket_readable(int fd) |
| 426 | { |
| 427 | fd_set read_fds; |
| 428 | struct timeval tv; |
| 429 | int rv; |
| 430 | |
| 431 | FD_ZERO(&read_fds); |
| 432 | FD_SET(fd, &read_fds); |
| 433 | tv.tv_sec = TIMEOUT_SECONDS; |
| 434 | tv.tv_usec = 0; |
| 435 | rv = select(fd + 1, &read_fds, NULL, NULL, &tv); |
| 436 | if (rv == -1) { |
| 437 | perror("select"); |
| 438 | } else if (rv == 0) { |
| 439 | g_message("%s: Timeout expired", __func__); |
| 440 | } |
| 441 | return rv == 1; |
| 442 | } |
| 443 | |
| 444 | /* Initialize *desc (in host endian format). */ |
| 445 | static void init_tx_desc(NPCM7xxEMCTxDesc *desc, size_t count, |
| 446 | uint32_t desc_addr) |
| 447 | { |
| 448 | g_assert(count >= 2); |
| 449 | memset(&desc[0], 0, sizeof(*desc) * count); |
| 450 | /* Leave the last one alone, owned by the cpu -> stops transmission. */ |
| 451 | for (size_t i = 0; i < count - 1; ++i) { |
| 452 | desc[i].flags = |
| 453 | (TX_DESC_FLAG_OWNER_MASK | /* owner = 1: emc */ |
| 454 | TX_DESC_FLAG_INTEN | |
| 455 | 0 | /* crc append = 0 */ |
| 456 | 0 /* padding enable = 0 */); |
| 457 | desc[i].status_and_length = |
| 458 | (0 | /* collision count = 0 */ |
| 459 | 0 | /* SQE = 0 */ |
| 460 | 0 | /* PAU = 0 */ |
| 461 | 0 | /* TXHA = 0 */ |
| 462 | 0 | /* LC = 0 */ |
| 463 | 0 | /* TXABT = 0 */ |
| 464 | 0 | /* NCS = 0 */ |
| 465 | 0 | /* EXDEF = 0 */ |
| 466 | 0 | /* TXCP = 0 */ |
| 467 | 0 | /* DEF = 0 */ |
| 468 | 0 | /* TXINTR = 0 */ |
| 469 | 0 /* length filled in later */); |
| 470 | desc[i].ntxdsa = desc_addr + (i + 1) * sizeof(*desc); |
| 471 | } |
| 472 | } |
| 473 | |
| 474 | static void enable_tx(QTestState *qts, const EMCModule *mod, |
| 475 | const NPCM7xxEMCTxDesc *desc, size_t count, |
| 476 | uint32_t desc_addr, uint32_t mien_flags) |
| 477 | { |
| 478 | /* Write the descriptors to guest memory. */ |
| 479 | for (size_t i = 0; i < count; ++i) { |
| 480 | emc_write_tx_desc(qts, desc + i, desc_addr + i * sizeof(*desc)); |
| 481 | } |
| 482 | |
| 483 | /* Trigger sending the packet. */ |
| 484 | /* The module must be reset before changing TXDLSA. */ |
| 485 | g_assert(emc_soft_reset(qts, mod)); |
| 486 | emc_write(qts, mod, REG_TXDLSA, desc_addr); |
| 487 | emc_write(qts, mod, REG_CTXDSA, ~0); |
| 488 | emc_write(qts, mod, REG_MIEN, REG_MIEN_ENTXCP | mien_flags); |
| 489 | { |
| 490 | uint32_t mcmdr = emc_read(qts, mod, REG_MCMDR); |
| 491 | mcmdr |= REG_MCMDR_TXON; |
| 492 | emc_write(qts, mod, REG_MCMDR, mcmdr); |
| 493 | } |
| 494 | } |
| 495 | |
| 496 | static void emc_send_verify1(QTestState *qts, const EMCModule *mod, int fd, |
| 497 | bool with_irq, uint32_t desc_addr, |
| 498 | uint32_t next_desc_addr, |
| 499 | const char *test_data, int test_size) |
| 500 | { |
| 501 | NPCM7xxEMCTxDesc result_desc; |
| 502 | uint32_t expected_mask, expected_value, recv_len; |
| 503 | int ret; |
| 504 | char buffer[TX_DATA_LEN]; |
| 505 | |
| 506 | g_assert(wait_socket_readable(fd)); |
| 507 | |
| 508 | /* Read the descriptor back. */ |
| 509 | emc_read_tx_desc(qts, desc_addr, &result_desc); |
| 510 | /* Descriptor should be owned by cpu now. */ |
| 511 | g_assert((result_desc.flags & TX_DESC_FLAG_OWNER_MASK) == 0); |
| 512 | /* Test the status bits, ignoring the length field. */ |
| 513 | expected_mask = 0xffff << 16; |
| 514 | expected_value = TX_DESC_STATUS_TXCP; |
| 515 | if (with_irq) { |
| 516 | expected_value |= TX_DESC_STATUS_TXINTR; |
| 517 | } |
| 518 | g_assert_cmphex((result_desc.status_and_length & expected_mask), ==, |
| 519 | expected_value); |
| 520 | |
| 521 | /* Check data sent to the backend. */ |
| 522 | recv_len = ~0; |
| 523 | ret = recv(fd, &recv_len, sizeof(recv_len), MSG_DONTWAIT); |
| 524 | g_assert_cmpint(ret, == , sizeof(recv_len)); |
| 525 | |
| 526 | g_assert(wait_socket_readable(fd)); |
| 527 | memset(buffer, 0xff, sizeof(buffer)); |
| 528 | ret = recv(fd, buffer, test_size, MSG_DONTWAIT); |
| 529 | g_assert_cmpmem(buffer, ret, test_data, test_size); |
| 530 | } |
| 531 | |
| 532 | static void emc_send_verify(QTestState *qts, const EMCModule *mod, int fd, |
| 533 | bool with_irq) |
| 534 | { |
| 535 | NPCM7xxEMCTxDesc desc[NUM_TX_DESCRIPTORS]; |
| 536 | uint32_t desc_addr = DESC_ADDR; |
| 537 | static const char test1_data[] = "TEST1"; |
| 538 | static const char test2_data[] = "Testing 1 2 3 ..."; |
| 539 | uint32_t data1_addr = DATA_ADDR; |
| 540 | uint32_t data2_addr = data1_addr + sizeof(test1_data); |
| 541 | bool got_tdu; |
| 542 | uint32_t end_desc_addr; |
| 543 | |
| 544 | /* Prepare test data buffer. */ |
| 545 | qtest_memwrite(qts, data1_addr, test1_data, sizeof(test1_data)); |
| 546 | qtest_memwrite(qts, data2_addr, test2_data, sizeof(test2_data)); |
| 547 | |
| 548 | init_tx_desc(&desc[0], NUM_TX_DESCRIPTORS, desc_addr); |
| 549 | desc[0].txbsa = data1_addr; |
| 550 | desc[0].status_and_length |= sizeof(test1_data); |
| 551 | desc[1].txbsa = data2_addr; |
| 552 | desc[1].status_and_length |= sizeof(test2_data); |
| 553 | |
| 554 | enable_tx(qts, mod, &desc[0], NUM_TX_DESCRIPTORS, desc_addr, |
| 555 | with_irq ? REG_MIEN_ENTXINTR : 0); |
| 556 | |
| 557 | /* Prod the device to send the packet. */ |
| 558 | emc_write(qts, mod, REG_TSDR, 1); |
| 559 | |
| 560 | /* |
| 561 | * It's problematic to observe the interrupt for each packet. |
| 562 | * Instead just wait until all the packets go out. |
| 563 | */ |
| 564 | got_tdu = false; |
| 565 | while (!got_tdu) { |
| 566 | if (with_irq) { |
| 567 | g_assert_true(emc_wait_irq(qts, mod, TX_STEP_COUNT, |
| 568 | /*is_tx=*/true)); |
| 569 | } else { |
| 570 | g_assert_true(emc_wait_mista(qts, mod, TX_STEP_COUNT, |
| 571 | REG_MISTA_TXINTR)); |
| 572 | } |
| 573 | got_tdu = !!(emc_read(qts, mod, REG_MISTA) & REG_MISTA_TDU); |
| 574 | /* If we don't have TDU yet, reset the interrupt. */ |
| 575 | if (!got_tdu) { |
| 576 | emc_write(qts, mod, REG_MISTA, |
| 577 | emc_read(qts, mod, REG_MISTA) & 0xffff0000); |
| 578 | } |
| 579 | } |
| 580 | |
| 581 | end_desc_addr = desc_addr + 2 * sizeof(desc[0]); |
| 582 | g_assert_cmphex(emc_read(qts, mod, REG_CTXDSA), ==, end_desc_addr); |
| 583 | g_assert_cmphex(emc_read(qts, mod, REG_MISTA), ==, |
| 584 | REG_MISTA_TXCP | REG_MISTA_TXINTR | REG_MISTA_TDU); |
| 585 | |
| 586 | emc_send_verify1(qts, mod, fd, with_irq, |
| 587 | desc_addr, end_desc_addr, |
| 588 | test1_data, sizeof(test1_data)); |
| 589 | emc_send_verify1(qts, mod, fd, with_irq, |
| 590 | desc_addr + sizeof(desc[0]), end_desc_addr, |
| 591 | test2_data, sizeof(test2_data)); |
| 592 | } |
| 593 | |
| 594 | /* Initialize *desc (in host endian format). */ |
| 595 | static void init_rx_desc(NPCM7xxEMCRxDesc *desc, size_t count, |
| 596 | uint32_t desc_addr, uint32_t data_addr) |
| 597 | { |
| 598 | g_assert_true(count >= 2); |
| 599 | memset(desc, 0, sizeof(*desc) * count); |
| 600 | desc[0].rxbsa = data_addr; |
| 601 | desc[0].status_and_length = |
| 602 | (0b10 << RX_DESC_STATUS_OWNER_SHIFT | /* owner = 10: emc */ |
| 603 | 0 | /* RP = 0 */ |
| 604 | 0 | /* ALIE = 0 */ |
| 605 | 0 | /* RXGD = 0 */ |
| 606 | 0 | /* PTLE = 0 */ |
| 607 | 0 | /* CRCE = 0 */ |
| 608 | 0 | /* RXINTR = 0 */ |
| 609 | 0 /* length (filled in later) */); |
| 610 | /* Leave the last one alone, owned by the cpu -> stops transmission. */ |
| 611 | desc[0].nrxdsa = desc_addr + sizeof(*desc); |
| 612 | } |
| 613 | |
| 614 | static void enable_rx(QTestState *qts, const EMCModule *mod, |
| 615 | const NPCM7xxEMCRxDesc *desc, size_t count, |
| 616 | uint32_t desc_addr, uint32_t mien_flags, |
| 617 | uint32_t mcmdr_flags) |
| 618 | { |
| 619 | /* |
| 620 | * Write the descriptor to guest memory. |
| 621 | * FWIW, IWBN if the docs said the buffer needs to be at least DMARFC |
| 622 | * bytes. |
| 623 | */ |
| 624 | for (size_t i = 0; i < count; ++i) { |
| 625 | emc_write_rx_desc(qts, desc + i, desc_addr + i * sizeof(*desc)); |
| 626 | } |
| 627 | |
| 628 | /* Trigger receiving the packet. */ |
| 629 | /* The module must be reset before changing RXDLSA. */ |
| 630 | g_assert(emc_soft_reset(qts, mod)); |
| 631 | emc_write(qts, mod, REG_RXDLSA, desc_addr); |
| 632 | emc_write(qts, mod, REG_MIEN, REG_MIEN_ENRXGD | mien_flags); |
| 633 | |
| 634 | /* |
| 635 | * We don't know what the device's macaddr is, so just accept all |
| 636 | * unicast packets (AUP). |
| 637 | */ |
| 638 | emc_write(qts, mod, REG_CAMCMR, REG_CAMCMR_AUP); |
| 639 | emc_write(qts, mod, REG_CAMEN, 1 << 0); |
| 640 | { |
| 641 | uint32_t mcmdr = emc_read(qts, mod, REG_MCMDR); |
| 642 | mcmdr |= REG_MCMDR_RXON | mcmdr_flags; |
| 643 | emc_write(qts, mod, REG_MCMDR, mcmdr); |
| 644 | } |
| 645 | } |
| 646 | |
| 647 | static void emc_recv_verify(QTestState *qts, const EMCModule *mod, int fd, |
| 648 | bool with_irq, bool pump_rsdr) |
| 649 | { |
| 650 | NPCM7xxEMCRxDesc desc[NUM_RX_DESCRIPTORS]; |
| 651 | uint32_t desc_addr = DESC_ADDR; |
| 652 | uint32_t data_addr = DATA_ADDR; |
| 653 | int ret; |
| 654 | uint32_t expected_mask, expected_value; |
| 655 | NPCM7xxEMCRxDesc result_desc; |
| 656 | |
| 657 | /* Prepare test data buffer. */ |
| 658 | const char test[RX_DATA_LEN] = "TEST"; |
| 659 | int len = htonl(sizeof(test)); |
| 660 | const struct iovec iov[] = { |
| 661 | { |
| 662 | .iov_base = &len, |
| 663 | .iov_len = sizeof(len), |
| 664 | },{ |
| 665 | .iov_base = (char *) test, |
| 666 | .iov_len = sizeof(test), |
| 667 | }, |
| 668 | }; |
| 669 | |
| 670 | /* |
| 671 | * Reset the device BEFORE sending a test packet, otherwise the packet |
| 672 | * may get swallowed by an active device of an earlier test. |
| 673 | */ |
| 674 | init_rx_desc(&desc[0], NUM_RX_DESCRIPTORS, desc_addr, data_addr); |
| 675 | enable_rx(qts, mod, &desc[0], NUM_RX_DESCRIPTORS, desc_addr, |
| 676 | with_irq ? REG_MIEN_ENRXINTR : 0, 0); |
| 677 | |
| 678 | /* |
| 679 | * If requested, prod the device to accept a packet. |
| 680 | * This isn't necessary, the linux driver doesn't do this. |
| 681 | * Test doing/not-doing this for robustness. |
| 682 | */ |
| 683 | if (pump_rsdr) { |
| 684 | emc_write(qts, mod, REG_RSDR, 1); |
| 685 | } |
| 686 | |
| 687 | /* Send test packet to device's socket. */ |
| 688 | ret = iov_send(fd, iov, 2, 0, sizeof(len) + sizeof(test)); |
| 689 | g_assert_cmpint(ret, == , sizeof(test) + sizeof(len)); |
| 690 | |
| 691 | /* Wait for RX interrupt. */ |
| 692 | if (with_irq) { |
| 693 | g_assert_true(emc_wait_irq(qts, mod, RX_STEP_COUNT, /*is_tx=*/false)); |
| 694 | } else { |
| 695 | g_assert_true(emc_wait_mista(qts, mod, RX_STEP_COUNT, REG_MISTA_RXGD)); |
| 696 | } |
| 697 | |
| 698 | g_assert_cmphex(emc_read(qts, mod, REG_CRXDSA), ==, |
| 699 | desc_addr + sizeof(desc[0])); |
| 700 | |
| 701 | expected_mask = 0xffff; |
| 702 | expected_value = (REG_MISTA_DENI | |
| 703 | REG_MISTA_RXGD | |
| 704 | REG_MISTA_RXINTR); |
| 705 | g_assert_cmphex((emc_read(qts, mod, REG_MISTA) & expected_mask), |
| 706 | ==, expected_value); |
| 707 | |
| 708 | /* Read the descriptor back. */ |
| 709 | emc_read_rx_desc(qts, desc_addr, &result_desc); |
| 710 | /* Descriptor should be owned by cpu now. */ |
| 711 | g_assert((result_desc.status_and_length & RX_DESC_STATUS_OWNER_MASK) == 0); |
| 712 | /* Test the status bits, ignoring the length field. */ |
| 713 | expected_mask = 0xffff << 16; |
| 714 | expected_value = RX_DESC_STATUS_RXGD; |
| 715 | if (with_irq) { |
| 716 | expected_value |= RX_DESC_STATUS_RXINTR; |
| 717 | } |
| 718 | g_assert_cmphex((result_desc.status_and_length & expected_mask), ==, |
| 719 | expected_value); |
| 720 | g_assert_cmpint(RX_DESC_PKT_LEN(result_desc.status_and_length), ==, |
| 721 | RX_DATA_LEN + CRC_LENGTH); |
| 722 | |
| 723 | { |
| 724 | char buffer[RX_DATA_LEN]; |
| 725 | qtest_memread(qts, data_addr, buffer, sizeof(buffer)); |
| 726 | g_assert_cmpstr(buffer, == , "TEST"); |
| 727 | } |
| 728 | } |
| 729 | |
| 730 | static void emc_test_ptle(QTestState *qts, const EMCModule *mod, int fd) |
| 731 | { |
| 732 | NPCM7xxEMCRxDesc desc[NUM_RX_DESCRIPTORS]; |
| 733 | uint32_t desc_addr = DESC_ADDR; |
| 734 | uint32_t data_addr = DATA_ADDR; |
| 735 | int ret; |
| 736 | NPCM7xxEMCRxDesc result_desc; |
| 737 | uint32_t expected_mask, expected_value; |
| 738 | |
| 739 | /* Prepare test data buffer. */ |
| 740 | #define PTLE_DATA_LEN 1600 |
| 741 | char test_data[PTLE_DATA_LEN]; |
| 742 | int len = htonl(sizeof(test_data)); |
| 743 | const struct iovec iov[] = { |
| 744 | { |
| 745 | .iov_base = &len, |
| 746 | .iov_len = sizeof(len), |
| 747 | },{ |
| 748 | .iov_base = (char *) test_data, |
| 749 | .iov_len = sizeof(test_data), |
| 750 | }, |
| 751 | }; |
| 752 | memset(test_data, 42, sizeof(test_data)); |
| 753 | |
| 754 | /* |
| 755 | * Reset the device BEFORE sending a test packet, otherwise the packet |
| 756 | * may get swallowed by an active device of an earlier test. |
| 757 | */ |
| 758 | init_rx_desc(&desc[0], NUM_RX_DESCRIPTORS, desc_addr, data_addr); |
| 759 | enable_rx(qts, mod, &desc[0], NUM_RX_DESCRIPTORS, desc_addr, |
| 760 | REG_MIEN_ENRXINTR, REG_MCMDR_ALP); |
| 761 | |
| 762 | /* Send test packet to device's socket. */ |
| 763 | ret = iov_send(fd, iov, 2, 0, sizeof(len) + sizeof(test_data)); |
| 764 | g_assert_cmpint(ret, == , sizeof(test_data) + sizeof(len)); |
| 765 | |
| 766 | /* Wait for RX interrupt. */ |
| 767 | g_assert_true(emc_wait_irq(qts, mod, RX_STEP_COUNT, /*is_tx=*/false)); |
| 768 | |
| 769 | /* Read the descriptor back. */ |
| 770 | emc_read_rx_desc(qts, desc_addr, &result_desc); |
| 771 | /* Descriptor should be owned by cpu now. */ |
| 772 | g_assert((result_desc.status_and_length & RX_DESC_STATUS_OWNER_MASK) == 0); |
| 773 | /* Test the status bits, ignoring the length field. */ |
| 774 | expected_mask = 0xffff << 16; |
| 775 | expected_value = (RX_DESC_STATUS_RXGD | |
| 776 | RX_DESC_STATUS_PTLE | |
| 777 | RX_DESC_STATUS_RXINTR); |
| 778 | g_assert_cmphex((result_desc.status_and_length & expected_mask), ==, |
| 779 | expected_value); |
| 780 | g_assert_cmpint(RX_DESC_PKT_LEN(result_desc.status_and_length), ==, |
| 781 | PTLE_DATA_LEN + CRC_LENGTH); |
| 782 | |
| 783 | { |
| 784 | char buffer[PTLE_DATA_LEN]; |
| 785 | qtest_memread(qts, data_addr, buffer, sizeof(buffer)); |
| 786 | g_assert(memcmp(buffer, test_data, PTLE_DATA_LEN) == 0); |
| 787 | } |
| 788 | } |
| 789 | |
| 790 | static void test_tx(gconstpointer test_data) |
| 791 | { |
| 792 | const TestData *td = test_data; |
| 793 | g_autoptr(GString) cmd_line = g_string_new("-machine quanta-gsj"); |
| 794 | int *test_sockets = packet_test_init(emc_module_index(td->module), |
| 795 | cmd_line); |
| 796 | QTestState *qts = qtest_init(cmd_line->str); |
| 797 | |
| 798 | /* |
| 799 | * TODO: For pedantic correctness test_sockets[0] should be closed after |
| 800 | * the fork and before the exec, but that will require some harness |
| 801 | * improvements. |
| 802 | */ |
| 803 | close(test_sockets[1]); |
| 804 | /* Defensive programming */ |
| 805 | test_sockets[1] = -1; |
| 806 | |
| 807 | qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic"); |
| 808 | |
| 809 | emc_send_verify(qts, td->module, test_sockets[0], /*with_irq=*/false); |
| 810 | emc_send_verify(qts, td->module, test_sockets[0], /*with_irq=*/true); |
| 811 | |
| 812 | qtest_quit(qts); |
| 813 | } |
| 814 | |
| 815 | static void test_rx(gconstpointer test_data) |
| 816 | { |
| 817 | const TestData *td = test_data; |
| 818 | g_autoptr(GString) cmd_line = g_string_new("-machine quanta-gsj"); |
| 819 | int *test_sockets = packet_test_init(emc_module_index(td->module), |
| 820 | cmd_line); |
| 821 | QTestState *qts = qtest_init(cmd_line->str); |
| 822 | |
| 823 | /* |
| 824 | * TODO: For pedantic correctness test_sockets[0] should be closed after |
| 825 | * the fork and before the exec, but that will require some harness |
| 826 | * improvements. |
| 827 | */ |
| 828 | close(test_sockets[1]); |
| 829 | /* Defensive programming */ |
| 830 | test_sockets[1] = -1; |
| 831 | |
| 832 | qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic"); |
| 833 | |
| 834 | emc_recv_verify(qts, td->module, test_sockets[0], /*with_irq=*/false, |
| 835 | /*pump_rsdr=*/false); |
| 836 | emc_recv_verify(qts, td->module, test_sockets[0], /*with_irq=*/false, |
| 837 | /*pump_rsdr=*/true); |
| 838 | emc_recv_verify(qts, td->module, test_sockets[0], /*with_irq=*/true, |
| 839 | /*pump_rsdr=*/false); |
| 840 | emc_recv_verify(qts, td->module, test_sockets[0], /*with_irq=*/true, |
| 841 | /*pump_rsdr=*/true); |
| 842 | emc_test_ptle(qts, td->module, test_sockets[0]); |
| 843 | |
| 844 | qtest_quit(qts); |
| 845 | } |
| 846 | #endif /* _WIN32 */ |
| 847 | |
| 848 | static void emc_add_test(const char *name, const TestData* td, |
| 849 | GTestDataFunc fn) |
| 850 | { |
| 851 | g_autofree char *full_name = g_strdup_printf( |
| 852 | "npcm7xx_emc/emc[%d]/%s", emc_module_index(td->module), name); |
| 853 | qtest_add_data_func(full_name, td, fn); |
| 854 | } |
| 855 | #define add_test(name, td) emc_add_test(#name, td, test_##name) |
| 856 | |
| 857 | int main(int argc, char **argv) |
| 858 | { |
| 859 | TestData test_data_list[ARRAY_SIZE(emc_module_list)]; |
| 860 | |
| 861 | g_test_init(&argc, &argv, NULL); |
| 862 | |
| 863 | for (int i = 0; i < ARRAY_SIZE(emc_module_list); ++i) { |
| 864 | TestData *td = &test_data_list[i]; |
| 865 | |
| 866 | td->module = &emc_module_list[i]; |
| 867 | |
| 868 | add_test(init, td); |
| 869 | #ifndef _WIN32 |
| 870 | add_test(tx, td); |
| 871 | add_test(rx, td); |
| 872 | #endif |
| 873 | } |
| 874 | |
| 875 | return g_test_run(); |
| 876 | } |