@samitouri / QOSamiQemu
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1 /*
2 * QTest testcase for PowerNV 10 Seeprom Communications
3 *
4 * Copyright (c) 2024, IBM Corporation.
5 *
6 * SPDX-License-Identifier: GPL-2.0-or-later
7 */
8 #include "qemu/osdep.h"
9 #include "libqtest.h"
10 #include "hw/ssi/pnv_spi_regs.h"
11 #include "pnv-xscom.h"
12
13 #define FLASH_SIZE (512 * 1024)
14 #define SPIC2_XSCOM_BASE 0xc0040
15
16 /* To transmit READ opcode and address */
17 #define READ_OP_TDR_DATA 0x0300010000000000
18 /*
19 * N1 shift - tx 4 bytes (transmit opcode and address)
20 * N2 shift - tx and rx 8 bytes.
21 */
22 #define READ_OP_COUNTER_CONFIG 0x2040000000002b00
23 /* SEQ_OP_SELECT_RESPONDER - N1 Shift - N2 Shift * 5 - SEQ_OP_STOP */
24 #define READ_OP_SEQUENCER 0x1130404040404010
25
26 /* To transmit WREN(Set Write Enable Latch in status0 register) opcode */
27 #define WRITE_OP_WREN 0x0600000000000000
28 /* To transmit WRITE opcode, address and data */
29 #define WRITE_OP_TDR_DATA 0x0300010012345678
30 /* N1 shift - tx 8 bytes (transmit opcode, address and data) */
31 #define WRITE_OP_COUNTER_CONFIG 0x4000000000002000
32 /* SEQ_OP_SELECT_RESPONDER - N1 Shift - SEQ_OP_STOP */
33 #define WRITE_OP_SEQUENCER 0x1130100000000000
34
35 static void pnv_spi_xscom_write(QTestState *qts, const PnvChip *chip,
36 uint32_t reg, uint64_t val)
37 {
38 uint32_t pcba = SPIC2_XSCOM_BASE + reg;
39 qtest_writeq(qts, pnv_xscom_addr(chip, pcba), val);
40 }
41
42 static uint64_t pnv_spi_xscom_read(QTestState *qts, const PnvChip *chip,
43 uint32_t reg)
44 {
45 uint32_t pcba = SPIC2_XSCOM_BASE + reg;
46 return qtest_readq(qts, pnv_xscom_addr(chip, pcba));
47 }
48
49 static void spi_seeprom_transaction(QTestState *qts, const PnvChip *chip)
50 {
51 /* SPI transactions to SEEPROM to read from SEEPROM image */
52 pnv_spi_xscom_write(qts, chip, SPI_CTR_CFG_REG, READ_OP_COUNTER_CONFIG);
53 pnv_spi_xscom_write(qts, chip, SPI_SEQ_OP_REG, READ_OP_SEQUENCER);
54 pnv_spi_xscom_write(qts, chip, SPI_XMIT_DATA_REG, READ_OP_TDR_DATA);
55 pnv_spi_xscom_write(qts, chip, SPI_XMIT_DATA_REG, 0);
56 /* Read 5*8 bytes from SEEPROM at 0x100 */
57 uint64_t rdr_val = pnv_spi_xscom_read(qts, chip, SPI_RCV_DATA_REG);
58 g_test_message("RDR READ = 0x%" PRIx64, rdr_val);
59 rdr_val = pnv_spi_xscom_read(qts, chip, SPI_RCV_DATA_REG);
60 rdr_val = pnv_spi_xscom_read(qts, chip, SPI_RCV_DATA_REG);
61 rdr_val = pnv_spi_xscom_read(qts, chip, SPI_RCV_DATA_REG);
62 rdr_val = pnv_spi_xscom_read(qts, chip, SPI_RCV_DATA_REG);
63 g_test_message("RDR READ = 0x%" PRIx64, rdr_val);
64
65 /* SPI transactions to SEEPROM to write to SEEPROM image */
66 pnv_spi_xscom_write(qts, chip, SPI_CTR_CFG_REG, WRITE_OP_COUNTER_CONFIG);
67 /* Set Write Enable Latch bit of status0 register */
68 pnv_spi_xscom_write(qts, chip, SPI_SEQ_OP_REG, WRITE_OP_SEQUENCER);
69 pnv_spi_xscom_write(qts, chip, SPI_XMIT_DATA_REG, WRITE_OP_WREN);
70 /* write 8 bytes to SEEPROM at 0x100 */
71 pnv_spi_xscom_write(qts, chip, SPI_SEQ_OP_REG, WRITE_OP_SEQUENCER);
72 pnv_spi_xscom_write(qts, chip, SPI_XMIT_DATA_REG, WRITE_OP_TDR_DATA);
73 }
74
75 static void test_spi_seeprom(const void *data)
76 {
77 const PnvChip *chip = data;
78 QTestState *qts = NULL;
79 g_autofree char *tmp_path = NULL;
80 const char *machine = pnv_get_machine_type(chip->chip_type);
81 int ret;
82 int fd;
83
84 /* Create a temporary raw image */
85 fd = g_file_open_tmp("qtest-seeprom-XXXXXX", &tmp_path, NULL);
86 g_assert(fd >= 0);
87 ret = ftruncate(fd, FLASH_SIZE);
88 g_assert(ret == 0);
89 close(fd);
90
91 qts = qtest_initf("-machine %s -smp 2,cores=2,"
92 "threads=1 -accel tcg,thread=single -nographic "
93 "-blockdev node-name=pib_spic2,driver=file,"
94 "filename=%s -device 25csm04,bus=chip0.spi.2,cs=0,"
95 "drive=pib_spic2", machine, tmp_path);
96 spi_seeprom_transaction(qts, chip);
97 qtest_quit(qts);
98 unlink(tmp_path);
99 }
100
101 int main(int argc, char **argv)
102 {
103 g_test_init(&argc, &argv, NULL);
104
105 for (int i = 0; i < ARRAY_SIZE(pnv_chips); i++) {
106 /* TYPE_PNV_SPI is not instantiated for older Power8/9 machines */
107 if (pnv_chips[i].chip_type < PNV_CHIP_POWER10) {
108 continue;
109 }
110
111 g_autofree char *tname = g_strdup_printf("pnv-xscom/spi-seeprom/%s",
112 pnv_chips[i].cpu_model);
113 qtest_add_data_func(tname, &pnv_chips[i], test_spi_seeprom);
114 }
115 return g_test_run();
116 }