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1 /*
2 * QTest testcase for PowerNV 10 interrupt controller (xive2)
3 *
4 * Copyright (c) 2024, IBM Corporation.
5 *
6 * SPDX-License-Identifier: GPL-2.0-or-later
7 */
8
9 #ifndef TEST_PNV_XIVE2_COMMON_H
10 #define TEST_PNV_XIVE2_COMMON_H
11
12 #define PPC_BIT(bit) (0x8000000000000000ULL >> (bit))
13 #define PPC_BIT32(bit) (0x80000000 >> (bit))
14 #define PPC_BIT8(bit) (0x80 >> (bit))
15 #define PPC_BITMASK(bs, be) ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
16 #define PPC_BITMASK32(bs, be) ((PPC_BIT32(bs) - PPC_BIT32(be)) | \
17 PPC_BIT32(bs))
18 #include "hw/intc/pnv_xive2_regs.h"
19 #include "hw/ppc/xive_regs.h"
20 #include "hw/ppc/xive2_regs.h"
21
22 /*
23 * sizing:
24 * 128 interrupts
25 * => ESB BAR range: 16M
26 * 256 ENDs
27 * => END BAR range: 16M
28 * 256 VPs
29 * => NVPG,NVC BAR range: 32M
30 */
31 #define MAX_IRQS 128
32 #define MAX_ENDS 256
33 #define MAX_VPS 256
34
35 #define XIVE_PAGE_SHIFT 16
36
37 #define XIVE_TRIGGER_PAGE 0
38 #define XIVE_EOI_PAGE 1
39
40 #define XIVE_IC_ADDR 0x0006030200000000ull
41 #define XIVE_IC_TM_INDIRECT (XIVE_IC_ADDR + (256 << XIVE_PAGE_SHIFT))
42 #define XIVE_IC_BAR ((0x3ull << 62) | XIVE_IC_ADDR)
43 #define XIVE_TM_BAR 0xc006030203180000ull
44 #define XIVE_ESB_ADDR 0x0006050000000000ull
45 #define XIVE_ESB_BAR ((0x3ull << 62) | XIVE_ESB_ADDR)
46 #define XIVE_END_BAR 0xc006060000000000ull
47 #define XIVE_NVPG_ADDR 0x0006040000000000ull
48 #define XIVE_NVPG_BAR ((0x3ull << 62) | XIVE_NVPG_ADDR)
49 #define XIVE_NVC_ADDR 0x0006030208000000ull
50 #define XIVE_NVC_BAR ((0x3ull << 62) | XIVE_NVC_ADDR)
51
52 /*
53 * Memory layout
54 * A check is done when a table is configured to ensure that the max
55 * size of the resource fits in the table.
56 */
57 #define XIVE_VST_SIZE 0x10000ull /* must be at least 4k */
58
59 #define XIVE_MEM_START 0x10000000ull
60 #define XIVE_ESB_MEM XIVE_MEM_START
61 #define XIVE_EAS_MEM (XIVE_ESB_MEM + XIVE_VST_SIZE)
62 #define XIVE_END_MEM (XIVE_EAS_MEM + XIVE_VST_SIZE)
63 #define XIVE_NVP_MEM (XIVE_END_MEM + XIVE_VST_SIZE)
64 #define XIVE_NVG_MEM (XIVE_NVP_MEM + XIVE_VST_SIZE)
65 #define XIVE_NVC_MEM (XIVE_NVG_MEM + XIVE_VST_SIZE)
66 #define XIVE_SYNC_MEM (XIVE_NVC_MEM + XIVE_VST_SIZE)
67 #define XIVE_QUEUE_MEM (XIVE_SYNC_MEM + XIVE_VST_SIZE)
68 #define XIVE_QUEUE_SIZE 4096 /* per End */
69 #define XIVE_REPORT_MEM (XIVE_QUEUE_MEM + XIVE_QUEUE_SIZE * MAX_VPS)
70 #define XIVE_REPORT_SIZE 256 /* two cache lines per NVP */
71 #define XIVE_MEM_END (XIVE_REPORT_MEM + XIVE_REPORT_SIZE * MAX_VPS)
72
73 #define P10_XSCOM_BASE 0x000603fc00000000ull
74 #define XIVE_XSCOM 0x2010800ull
75
76 #define XIVE_ESB_RESET 0b00
77 #define XIVE_ESB_OFF 0b01
78 #define XIVE_ESB_PENDING 0b10
79 #define XIVE_ESB_QUEUED 0b11
80
81 #define XIVE_ESB_GET 0x800
82 #define XIVE_ESB_SET_PQ_00 0xc00 /* Load */
83 #define XIVE_ESB_SET_PQ_01 0xd00 /* Load */
84 #define XIVE_ESB_SET_PQ_10 0xe00 /* Load */
85 #define XIVE_ESB_SET_PQ_11 0xf00 /* Load */
86
87 #define XIVE_ESB_STORE_EOI 0x400 /* Store */
88
89
90 extern uint64_t pnv_xive_xscom_read(QTestState *qts, uint32_t reg);
91 extern void pnv_xive_xscom_write(QTestState *qts, uint32_t reg, uint64_t val);
92 extern uint64_t xive_get_queue_addr(uint32_t end_index);
93 extern uint8_t get_esb(QTestState *qts, uint32_t index, uint8_t page,
94 uint32_t offset);
95 extern void set_esb(QTestState *qts, uint32_t index, uint8_t page,
96 uint32_t offset, uint32_t val);
97 extern void get_nvp(QTestState *qts, uint32_t index, Xive2Nvp* nvp);
98 extern void set_nvp(QTestState *qts, uint32_t index, uint8_t first);
99 extern void get_cl_pair(QTestState *qts, Xive2Nvp *nvp, uint8_t *cl_pair);
100 extern void set_cl_pair(QTestState *qts, Xive2Nvp *nvp, uint8_t *cl_pair);
101 extern void set_nvg(QTestState *qts, uint32_t index, uint8_t next);
102 extern void set_eas(QTestState *qts, uint32_t index, uint32_t end_index,
103 uint32_t data);
104 extern void set_end(QTestState *qts, uint32_t index, uint32_t nvp_index,
105 uint8_t priority, bool i);
106
107
108 void test_flush_sync_inject(QTestState *qts);
109 void test_nvpg_bar(QTestState *qts);
110
111 #endif /* TEST_PNV_XIVE2_COMMON_H */