| 1 | /* |
| 2 | * QTest testcase for PowerNV XSCOM bus |
| 3 | * |
| 4 | * Copyright (c) 2016, IBM Corporation. |
| 5 | * |
| 6 | * This work is licensed under the terms of the GNU GPL, version 2 or |
| 7 | * later. See the COPYING file in the top-level directory. |
| 8 | */ |
| 9 | #include "qemu/osdep.h" |
| 10 | |
| 11 | #include "libqtest.h" |
| 12 | |
| 13 | #include "pnv-xscom.h" |
| 14 | |
| 15 | static uint64_t pnv_xscom_read(QTestState *qts, const PnvChip *chip, |
| 16 | uint32_t pcba) |
| 17 | { |
| 18 | return qtest_readq(qts, pnv_xscom_addr(chip, pcba)); |
| 19 | } |
| 20 | |
| 21 | static void test_xscom_cfam_id(QTestState *qts, const PnvChip *chip) |
| 22 | { |
| 23 | uint64_t f000f = pnv_xscom_read(qts, chip, 0xf000f); |
| 24 | |
| 25 | g_assert_cmphex(f000f, ==, chip->cfam_id); |
| 26 | } |
| 27 | |
| 28 | static void test_cfam_id(const void *data) |
| 29 | { |
| 30 | const PnvChip *chip = data; |
| 31 | const char *machine = pnv_get_machine_type(chip->chip_type); |
| 32 | QTestState *qts; |
| 33 | |
| 34 | qts = qtest_initf("-M %s -accel tcg -cpu %s", |
| 35 | machine, chip->cpu_model); |
| 36 | test_xscom_cfam_id(qts, chip); |
| 37 | qtest_quit(qts); |
| 38 | } |
| 39 | |
| 40 | |
| 41 | #define PNV_XSCOM_EX_CORE_BASE 0x10000000ull |
| 42 | #define PNV_XSCOM_EX_BASE(core) \ |
| 43 | (PNV_XSCOM_EX_CORE_BASE | ((uint64_t)(core) << 24)) |
| 44 | #define PNV_XSCOM_P9_EC_BASE(core) \ |
| 45 | ((uint64_t)(((core) & 0x1F) + 0x20) << 24) |
| 46 | #define PNV_XSCOM_P10_EC_BASE(core) \ |
| 47 | ((uint64_t)((((core) & ~0x3) + 0x20) << 24) + 0x20000 + \ |
| 48 | (0x1000 << (3 - (core & 0x3)))) |
| 49 | |
| 50 | #define PNV_XSCOM_EX_DTS_RESULT0 0x50000 |
| 51 | |
| 52 | static void test_xscom_core(QTestState *qts, const PnvChip *chip) |
| 53 | { |
| 54 | if ((chip->chip_type == PNV_CHIP_POWER10) || |
| 55 | (chip->chip_type == PNV_CHIP_POWER11)) { |
| 56 | uint32_t first_core_thread_state = |
| 57 | PNV_XSCOM_P10_EC_BASE(chip->first_core) + 0x412; |
| 58 | uint64_t thread_state; |
| 59 | |
| 60 | thread_state = pnv_xscom_read(qts, chip, first_core_thread_state); |
| 61 | |
| 62 | g_assert_cmphex(thread_state, ==, 0); |
| 63 | } else { |
| 64 | uint32_t first_core_dts0 = PNV_XSCOM_EX_DTS_RESULT0; |
| 65 | uint64_t dts0; |
| 66 | |
| 67 | if (chip->chip_type == PNV_CHIP_POWER9) { |
| 68 | first_core_dts0 |= PNV_XSCOM_P9_EC_BASE(chip->first_core); |
| 69 | } else { /* POWER8 */ |
| 70 | first_core_dts0 |= PNV_XSCOM_EX_BASE(chip->first_core); |
| 71 | } |
| 72 | |
| 73 | dts0 = pnv_xscom_read(qts, chip, first_core_dts0); |
| 74 | |
| 75 | g_assert_cmphex(dts0, ==, 0x26f024f023f0000ull); |
| 76 | } |
| 77 | } |
| 78 | |
| 79 | static void test_core(const void *data) |
| 80 | { |
| 81 | const PnvChip *chip = data; |
| 82 | const char *machine = pnv_get_machine_type(chip->chip_type); |
| 83 | QTestState *qts; |
| 84 | |
| 85 | qts = qtest_initf("-M %s -accel tcg -cpu %s", |
| 86 | machine, chip->cpu_model); |
| 87 | test_xscom_core(qts, chip); |
| 88 | qtest_quit(qts); |
| 89 | } |
| 90 | |
| 91 | static void add_test(const char *name, void (*test)(const void *data)) |
| 92 | { |
| 93 | int i; |
| 94 | |
| 95 | for (i = 0; i < ARRAY_SIZE(pnv_chips); i++) { |
| 96 | g_autofree char *tname = g_strdup_printf("pnv-xscom/%s/%s", name, |
| 97 | pnv_chips[i].cpu_model); |
| 98 | qtest_add_data_func(tname, &pnv_chips[i], test); |
| 99 | } |
| 100 | } |
| 101 | |
| 102 | int main(int argc, char **argv) |
| 103 | { |
| 104 | g_test_init(&argc, &argv, NULL); |
| 105 | |
| 106 | add_test("cfam_id", test_cfam_id); |
| 107 | add_test("core", test_core); |
| 108 | return g_test_run(); |
| 109 | } |